|-------------+----------------+----------------------------------------------------------------------------------|
| tdc\_v2.2* | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. |
|-------------+----------------+----------------------------------------------------------------------------------|
+| tdc\_v2.1.5 | 22.06.2015 | Extra coarse counter reset register for higher frequency. |
+|-------------+----------------+----------------------------------------------------------------------------------|
| tdc\_v2.1.4 | 17.06.2015 | Several bug fixes for the stretcher option. |
|-------------+----------------+----------------------------------------------------------------------------------|
| tdc\_v2.1.2 | 28.01.2015 | In case of a missing reference time a header error bit is set and DAQ keeps running. |
|-------------+----------------+----------------------------------------------------------------------------------|
| tdc\_v0.5 | 22.10.2012 | Hit counter registers and LVDS receiver output level can be reached via slow control. |
|-------------+----------------+----------------------------------------------------------------------------------|
-| | | * Design under construction... |
+| | | * Design under construction... |
|-------------+----------------+----------------------------------------------------------------------------------|