signal ram_addr_i : std_logic_vector(3 downto 0);
signal spi_ram_addr_i : std_logic_vector(3 downto 0);
- signal enable_cfg_flash : std_logic;
+ signal enable_cfg_flash : std_logic_vector(2 downto 0);
signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
signal memreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
signal burst_counter : std_logic_vector(3 downto 0);
flash_page(12 downto 0) <= spi_flash_page(12 downto 0);
flash_page(15 downto 13) <= "000";
select_cfg <= '1';
- if (spi_flash_page(12 downto 10) = "111" or enable_cfg_flash = '0') then
+ if (spi_flash_page(12 downto 10) = "111" or enable_cfg_flash(0) = '0') then
select_cfg <= '0';
flash_page(12 downto 10) <= "000";
end if;
select_cfg <= '0';
else
flash_page <= spi_flash_page;
- select_cfg <= enable_cfg_flash;
+ select_cfg <= enable_cfg_flash(0);
end if;
end if;
end process;
readback_reg <= SPI_DATA_IN(15 downto 8);
elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then
reg_LOC_WRITE_OUT <= '0';
- enable_cfg_flash <= SPI_DATA_IN(0);
+ if SPI_DATA_IN(0) = '0' then
+ enable_cfg_flash(2 downto 0) <= "000";
+ elsif SPI_DATA_IN(2 downto 0) = "011" and enable_cfg_flash(2 downto 0) = "000" then --stage1
+ enable_cfg_flash(2 downto 0) <= "010";
+ elsif SPI_DATA_IN(2 downto 0) = "101" and enable_cfg_flash(2 downto 0) = "010" then --stage2
+ enable_cfg_flash(2 downto 0) <= "100";
+ elsif SPI_DATA_IN(2 downto 0) = "001" and enable_cfg_flash(2 downto 0) = "100" then --stage3
+ enable_cfg_flash(2 downto 0) <= "001";
+ else
+ enable_cfg_flash(2 downto 0) <= "000";
+ end if;
--flash_mode <= SPI_DATA_IN(8); --XXX
elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then
reg_LOC_WRITE_OUT <= '0';
reg_LOC_WRITE_OUT <= '0';
if (flash_mode = '0' and USE_OLD_13BIT_MODE = c_YES) then
spi_flash_command <= SPI_DATA_IN(15 downto 13);
- if (enable_cfg_flash = '1') then
+ if (enable_cfg_flash(0) = '1') then
spi_flash_page <= "000" & SPI_DATA_IN(12 downto 0);
else
spi_flash_page <= "000111" & SPI_DATA_IN(9 downto 0);
reg_LOC_READ_OUT <= '0';
reg_SPI_READY_OUT <= '1';
reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
- reg_SPI_DATA_OUT(15 downto 0) <= x"0" & "000" & flash_mode & '0' & auto_reset & "00" & '0' & flash_busy & flash_err & enable_cfg_flash;
+ reg_SPI_DATA_OUT(15 downto 0) <= x"0" & "000" & flash_mode & '0' & auto_reset & "00" & '0' & flash_busy & flash_err & enable_cfg_flash(0);
elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then
reg_LOC_READ_OUT <= '0';
reg_SPI_READY_OUT <= '1';