use work.version.all;
entity trb_net16_gbe_buf is
-generic(
- DO_SIMULATION : integer range 0 to 1 := 1
+generic(
+ DO_SIMULATION : integer range c_NO to c_YES := c_NO
);
port(
CLK : in std_logic;
-- Interface between IPU channel and packet constructor
component trb_net16_ipu2gbe is
-port(
+port(
CLK : in std_logic;
RESET : in std_logic;
--Event information coming from CTS
DBG_SF_AEMPTY_OUT : out std_logic;
DBG_SF_FULL_OUT : out std_logic;
DBG_SF_AFULL_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(31 downto 0)
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end component;
component ip_configurator is
-port(
+port(
CLK : in std_logic;
RESET : in std_logic;
-- configuration interface
START_CONFIG_IN : in std_logic; -- start configuration run
- BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank
+ BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank
CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used
MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for
MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory
tx_sndpaustim : in std_logic_vector(15 downto 0);
tx_sndpausreq : in std_logic;
tx_fifoctrl : in std_logic;
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
rx_fifo_full : in std_logic;
ignore_pkt : in std_logic;
-------------------- Output signals from the GMII -----------------------
- txd : out std_logic_vector(7 downto 0);
+ txd : out std_logic_vector(7 downto 0);
tx_en : out std_logic;
tx_er : out std_logic;
-------------------- Output signals from the CPU I/F -------------------
hdataout_en_n : out std_logic;
hready_n : out std_logic;
cpu_if_gbit_en : out std_logic;
- ---------------- Output signals from the Tx MAC FIFO I/F ---------------
+ ---------------- Output signals from the Tx MAC FIFO I/F ---------------
tx_macread : out std_logic;
tx_discfrm : out std_logic;
tx_staten : out std_logic;
tx_done : out std_logic;
tx_statvec : out std_logic_vector(30 downto 0);
- ---------------- Output signals from the Rx MAC FIFO I/F ---------------
+ ---------------- Output signals from the Rx MAC FIFO I/F ---------------
rx_fifo_error : out std_logic;
rx_stat_vector : out std_logic_vector(31 downto 0);
rx_dbout : out std_logic_vector(7 downto 0);
rx_eof : out std_logic;
rx_error : out std_logic
);
-end component;
+end component;
component mb_mac_sim is
port (
--------------- Receive FIFO interface -----------------------------------
RX_DBOUT : out std_logic_vector(7 downto 0);
RX_FIFO_FULL : in std_logic;
- IGNORE_PKT : in std_logic;
+ IGNORE_PKT : in std_logic;
RX_FIFO_ERROR : out std_logic;
RX_STAT_VECTOR : out std_logic_vector(31 downto 0);
RX_STAT_EN : out std_logic;
MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0);
MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0);
MR_AN_PAGE_RX_OUT : out std_logic;
- MR_AN_COMPLETE_OUT : out std_logic;
+ MR_AN_COMPLETE_OUT : out std_logic;
MR_AN_ENABLE_IN : in std_logic;
MR_RESTART_AN_IN : in std_logic;
-- Status and control port
end component;
component slv_mac_memory is
-port(
+port(
CLK : in std_logic;
RESET : in std_logic;
BUSY_IN : in std_logic;
signal pcs_an_complete : std_logic;
signal pcs_an_page_rx : std_logic;
-signal pcs_stat_debug : std_logic_vector(63 downto 0);
+signal pcs_stat_debug : std_logic_vector(63 downto 0);
signal stage_stat_regs : std_logic_vector(31 downto 0);
signal stage_ctrl_regs : std_logic_vector(31 downto 0);
-- IP configurator: allows IP config to change for each event builder
THE_IP_CONFIGURATOR: ip_configurator
-port map(
+port map(
CLK => CLK,
RESET => RESET,
-- configuration interface
-- gk 27.03.01
MB_IP_CONFIG: slv_mac_memory
-port map(
+port map(
CLK => CLK, -- clk_100,
RESET => RESET, --reset_i,
BUSY_IN => '0',
-- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
THE_IPU_INTERFACE: trb_net16_ipu2gbe
-port map(
+port map(
CLK => CLK,
RESET => RESET,
--Event information coming from CTS
DBG_REM_CTR_OUT => ig_rem_ctr,
DBG_SF_WCNT_OUT => ig_wcnt,
DBG_SF_RCNT_OUT => ig_rcnt,
- DBG_SF_DATA_OUT => ig_data,
+ DBG_SF_DATA_OUT => ig_data,
DBG_SF_RD_EN_OUT => ig_rd_en,
DBG_SF_WR_EN_OUT => ig_wr_en,
DBG_SF_EMPTY_OUT => ig_empty,
DBG_SF_FULL_OUT => ig_full,
DBG_SF_AFULL_OUT => ig_afull,
DEBUG_OUT => ig_debug
-);
+);
-- Second stage: Packet constructor
PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
-port map(
+port map(
-- ports for user logic
RESET => RESET,
CLK => CLK,
DBG_ACT_QUEUE_SIZE => pc_act_queue_size,
DEBUG_OUT => open
);
-
+
-- Third stage: Frame Constructor
FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
-port map(
+port map(
-- ports for user logic
RESET => RESET,
CLK => CLK,
BSM_CONSTR_OUT => fc_bsm_constr,
BSM_TRANS_OUT => fc_bsm_trans,
DEBUG_OUT => open
-);
-
+);
+
FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
-port map(
+port map(
CLK => CLK,
RESET => RESET,
TX_MAC_CLK => serdes_clk_125,
DBG_INIT_DONE_OUT => open,
DBG_ENABLED_OUT => open,
DEBUG_OUT => open
-);
+);
-- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
imp_gen: if (DO_SIMULATION = 0) generate
-- Implementation
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
-
+
-- MAC part
MAC: tsmac3
port map(
tx_sndpaustim => x"0000",
tx_sndpausreq => '0',
tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
rx_fifo_full => '0',
ignore_pkt => '0',
---------------- Output signals from the GMII -----------------------
hdataout_en_n => mac_hdata_en,
hready_n => mac_hready,
cpu_if_gbit_en => open,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
+ ------------- Output signals from the Tx MAC FIFO I/F ---------------
tx_macread => mac_tx_read,
tx_discfrm => open,
tx_staten => open,
tx_statvec => open,
tx_done => mac_tx_done,
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
+ ------------- Output signals from the Rx MAC FIFO I/F ---------------
rx_fifo_error => open,
rx_stat_vector => open,
rx_dbout => open,
);
stage_stat_regs(31 downto 28) <= x"d";
- stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status
+ stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status
stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm
stage_stat_regs(19 downto 18) <= (others => '0');
stage_stat_regs(17) <= pcs_an_complete;
--------------- Receive FIFO interface -----------------------------------
RX_DBOUT => open,
RX_FIFO_FULL => '0',
- IGNORE_PKT => '0',
+ IGNORE_PKT => '0',
RX_FIFO_ERROR => open,
RX_STAT_VECTOR => open,
RX_STAT_EN => open,
pcs_an_complete <= '1';
mac_tx_clk_en <= '1';
mac_rx_clk_en <= '1';
-
+
stage_stat_regs(31 downto 0) <= (others => '0');
pcs_stat_debug(63 downto 0) <= (others => '0');
-#####################################################################
-# Basic constraints
-#####################################################################
- COMMERCIAL ;
- BLOCK RESETPATHS ;
- BLOCK ASYNCPATHS ;
- BLOCK RD_DURING_WR_PATHS ;
-
- FREQUENCY PORT CLK_100_IN 100.000000 MHz ;
- FREQUENCY PORT CLK_125_IN 125.000000 MHz ;
-
- FREQUENCY PORT "ADCCLK_OUT_7" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_8" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_9" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_10" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_11" 20.000000 MHz ;
- FREQUENCY PORT "ADCCLK_OUT_12" 20.000000 MHz ;
-
- FREQUENCY PORT "DCO_IN_7" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_8" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_9" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_10" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_11" 100.000000 MHz ;
- FREQUENCY PORT "DCO_IN_12" 100.000000 MHz ;
-
signal flag_half_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
signal flag_almost_full_combined : std_logic;
signal flag_half_full_combined : std_logic;
-
+
begin
assert DATA_BUFFER_FULL_THRESH < 2**DATA_BUFFER_DEPTH-2 report "Data buffer threshold too high" severity error;
assert HEADER_BUFFER_FULL_THRESH < 2**HEADER_BUFFER_DEPTH-2 report "Header buffer threshold too high" severity error;
-
+
---------------------------------------------------------------------------
-- FEE & IPU I/O
---------------------------------------------------------------------------
when WAIT_BUSY =>
lvl1_state_bits <= "010";
- if LVL1_TRG_DATA_VALID_IN = '1' and or_all(got_busy_release) = '1' then
+ if LVL1_TRG_DATA_VALID_IN = '1' and and_all(got_busy_release) = '1' then
current_lvl1_state <= BUSY_RELEASE;
end if;
proc_filllevel_flag : process(CLOCK)
begin
if rising_edge(CLOCK) then
- if data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)) >= buffer_half_threshold then
+ if unsigned(data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)))
+ >= buffer_half_threshold then
flag_half_full(i) <= '1';
else
flag_half_full(i) <= '0';
end if;
- if data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)) >= buffer_end_threshold then
+ if unsigned(data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)))
+ >= buffer_end_threshold then
flag_almost_full(i) <= '1';
else
flag_almost_full(i) <= '0';
end generate;
flag_half_full_combined <= or_all(flag_half_full);
- flag_almost_full_combined <= or_alll(flag_almost_full);
-
+ flag_almost_full_combined <= or_all(flag_almost_full);
+
---------------------------------------------------------------------------
-- Generate Statusbits
---------------------------------------------------------------------------
IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
--Debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
+ STATUS_OUT : out std_logic_vector(31 downto 0)
);
end entity;
end if;
when WAIT_FOR_LENGTH =>
- if or_all(DAT_DATA_EMPTY_IN) = '1' or DAT_HDR_DATA_EMPTY_IN = '1' then
+ if DAT_HDR_DATA_EMPTY_IN = '1' then
next_state <= WAITING_FOR_EVENT;
else
next_state <= GOT_LENGTH;
else x"5" when current_state = END_READOUT
else x"F";
- DEBUG_OUT( 3 downto 0) <= state_bits;
- DEBUG_OUT(11 downto 4) <= (others => '0');
- DEBUG_OUT(12) <= error_not_found;
- DEBUG_OUT(13) <= error_missing;
- DEBUG_OUT(14) <= error_sync;
- DEBUG_OUT(15) <= error_not_configured;
-
+ STATUS_OUT( 3 downto 0) <= state_bits;
+ STATUS_OUT(11 downto 4) <= (others => '0');
+ STATUS_OUT(12) <= error_not_found;
+ STATUS_OUT(13) <= error_missing;
+ STATUS_OUT(14) <= error_sync;
+ STATUS_OUT(15) <= error_not_configured;
+ STATUS_OUT(31 downto 16) <= (others => '0');
end architecture;
\ No newline at end of file
--data buffer threshold has to be set to fifo_depth - max_event_size - 2 when TRG_RELEASE_AFTER_DATA_FINISH = c_YES or
--fifo_depth - 2*max_event_size - 2 when TRG_RELEASE_AFTER_DATA_FINISH = c_NO
+--STATUS_OUT(0): release status
+--STATUS_OUT(1): data handler debug
+--STATUS_OUT(2): ipu handler status
architecture handler_trigger_and_data_arch of handler_trigger_and_data is
signal fee_trg_release : std_logic_vector(DATA_INTERFACE_NUMBER downto 0);
signal buf_lvl1_trg_release : std_logic;
+ signal status_ipu_handler_i : std_logic_vector(31 downto 0);
+ signal debug_data_handler_i : std_logic_vector(31 downto 0);
begin
STAT_DATA_BUFFER_LEVEL => STAT_DATA_BUFFER_LEVEL,
STAT_HEADER_BUFFER_LEVEL => STAT_HEADER_BUFFER_LEVEL,
--Debug
- DEBUG_OUT => DEBUG_DATA_HANDLER_OUT
+ DEBUG_OUT => debug_data_handler_i
);
IPU_LENGTH_OUT => IPU_LENGTH_OUT,
IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,
--Debug
- DEBUG_OUT => DEBUG_IPU_HANDLER_OUT
+ STATUS_OUT => status_ipu_handler_i
);
buf_lvl1_trg_release <= and_all(fee_trg_release);
LVL1_ERROR_PATTERN_OUT <= fee_trg_statusbits;
+ DEBUG_IPU_HANDLER_OUT <= status_ipu_handler_i;
+
+-----------------------------------------------------------------------
+-- Debug
+-----------------------------------------------------------------------
+
+ STATUS_OUT(DATA_INTERFACE_NUMBER downto 0) <= fee_trg_release;
+ STATUS_OUT(31 downto DATA_INTERFACE_NUMBER+1) <= (others => '1');
+
+ STATUS_OUT(63 downto 32) <= debug_data_handler_i;
+ STATUS_OUT(95 downto 64) <= status_ipu_handler_i;
+ STATUS_OUT(127 downto 96) <= (others => '0');
end architecture;
\ No newline at end of file
signal tbuf_dataready : std_logic;
signal tbuf_read_enable : std_logic;
- signal dummy : std_logic_vector(95 downto 0);
+ signal dummy : std_logic_vector(255 downto 0);
+ signal write_enable : std_logic_vector(5 downto 0);
+ signal read_enable : std_logic_vector(5 downto 0);
+ signal last_write_enable : std_logic_vector(5 downto 0);
+ signal last_read_enable : std_logic_vector(5 downto 0);
begin
---------------------------------------------------------------------------
THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", others => x"0000"),
- PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, others => 0)
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, others => 0)
)
port map(
CLK => CLK,
BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,
BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,
BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,
+ BUS_READ_ENABLE_OUT(3) => read_enable(3),
+ BUS_READ_ENABLE_OUT(4) => read_enable(4),
+ BUS_READ_ENABLE_OUT(5) => read_enable(5),
BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,
BUS_WRITE_ENABLE_OUT(1) => dummy(0),
- BUS_WRITE_ENABLE_OUT(2) => dummy(1),
+ BUS_WRITE_ENABLE_OUT(2) => write_enable(2),
+ BUS_WRITE_ENABLE_OUT(3) => write_enable(3),
+ BUS_WRITE_ENABLE_OUT(4) => write_enable(4),
+ BUS_WRITE_ENABLE_OUT(5) => write_enable(5),
BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,
BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),
BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),
+ BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96),
BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,
BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),
BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),
+ BUS_ADDR_OUT(95 downto 48) => dummy(241 downto 194),
BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,
BUS_TIMEOUT_OUT(1) => dummy(94),
BUS_TIMEOUT_OUT(2) => dummy(95),
+ BUS_TIMEOUT_OUT(3) => dummy(192),
+ BUS_TIMEOUT_OUT(4) => dummy(193),
+ BUS_TIMEOUT_OUT(5) => dummy(194),
BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,
BUS_DATA_IN(63 downto 32) => dbuf_data_in,
BUS_DATA_IN(95 downto 64) => stat_header_buffer_level,
+ BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0),
BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,
BUS_DATAREADY_IN(1) => dbuf_dataready,
BUS_DATAREADY_IN(2) => tbuf_dataready,
+ BUS_DATAREADY_IN(3) => last_read_enable(3),
+ BUS_DATAREADY_IN(4) => last_read_enable(4),
+ BUS_DATAREADY_IN(5) => last_read_enable(5),
BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,
BUS_WRITE_ACK_IN(1) => '0',
BUS_WRITE_ACK_IN(2) => '0',
+ BUS_WRITE_ACK_IN(3) => '0',
+ BUS_WRITE_ACK_IN(4) => '0',
+ BUS_WRITE_ACK_IN(5) => '0',
BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,
BUS_NO_MORE_DATA_IN(1) => '0',
BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_NO_MORE_DATA_IN(5) => '0',
BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,
BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,
- BUS_UNKNOWN_ADDR_IN(2) => '0'
+ BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2),
+ BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3),
+ BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4),
+ BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5)
);
+ proc_ack_strobes : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_write_enable <= write_enable;
+ last_read_enable <= read_enable;
+ end if;
+ end process;
+
+
---------------------------------------------------------------------------
-- Data and IPU Handler
---------------------------------------------------------------------------
component trb_net16_gbe_buf is
- generic(
- DO_SIMULATION : integer range 0 to 1 := 0
+ generic(
+ DO_SIMULATION : integer range c_NO to c_YES := c_NO
);
port(
CLK : in std_logic;
IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
--Debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
+ STATUS_OUT : out std_logic_vector(31 downto 0)
);
end component;
component slv_mac_memory is
- port(
+ port(
CLK : in std_logic;
RESET : in std_logic;
BUSY_IN : in std_logic;
jspc29 / trbnet.git / commitdiff