working DLMs in both direction

diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd
index 22bd896fdd1f03a738868394f34df0191da48d7b..27d1af1506e24c41c30c7948435c838c300d87f3 100644 (file)
--- a/gbe_trb/base/inserter.vhd
+++ b/gbe_trb/base/inserter.vhd
@@ -68,6 +68,8 @@ architecture inserter_arch of inserter is
 \r
   signal ins_cnt          : unsigned(2 downto 0);\r
   \r
+  signal payload          : std_logic_vector(7 downto 0);\r
+  \r
 begin\r
 \r
   DEBUG_OUT(0)   <= drop_req_x;\r
@@ -100,7 +102,7 @@ begin
     end if;\r
   end process THE_SYNC_PROC;\r
 \r
-  -- we have an /I/ candidate for dropping (in the input and first stage)\r
+  -- we have an /I/ candidate for dropping (in the input and in the first stage)\r
   idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and\r
                       (PHY_D_IN = x"50")            and (PHY_K_IN = '0')   and (PHY_CD_IN = '0')) \r
              else '0';\r
@@ -119,6 +121,18 @@ begin
     end if;\r
   end process THE_INSERT_COUNTER_PROC;\r
 \r
+  -- store the payload\r
+  THE_PAYLOAD_PROC: process( CLK )\r
+  begin\r
+    if( rising_edge(CLK) ) then\r
+      if   ( RESET = '1' ) then\r
+        payload <= (others => '0');\r
+      elsif( DLM_INJECT_IN = '1' ) then\r
+        payload <= DLM_DATA_IN;\r
+      end if;\r
+    end if;\r
+  end process THE_PAYLOAD_PROC;\r
+  \r
   -- we need to drop at least one /I/\r
   drop_req_x <= '1' when (ins_cnt /= b"000") else '0';\r
 \r
@@ -156,7 +170,7 @@ begin
                '0' when inject_d = '1' else\r
                tx_k_int;\r
   TX_D_OUT  <= x"dc" when inject_k = '1' else\r
-               DLM_DATA_IN when inject_d = '1' else -- payload is here\r
+               payload when inject_d = '1' else -- payload is here\r
                tx_d_int;\r
 \r
 \r

diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd
index dcda515bb716a33445b5954b620773bfdae8edeb..d598e07596669fae71ae2caea95dc11c8510714f 100644 (file)
--- a/gbe_trb/base/remover.vhd
+++ b/gbe_trb/base/remover.vhd
@@ -74,7 +74,7 @@ begin
 \r
   dlm_found   <= dlm_found_x when rising_edge(CLK);\r
 \r
-  DLM_FOUND_OUT <= dlm_found;\r
+  DLM_FOUND_OUT <= dlm_found when rising_edge(CLK); -- needed to have valid data\r
 \r
   THE_STORE_PROC: process( CLK )\r
   begin\r

diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd
index 7643a50ebd81649e8beaa8cdf180eff2b64747a9..3d589cbc0c451f33dc076eb16ac95555aa142f6a 100644 (file)
--- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd
@@ -22,7 +22,8 @@ use work.med_sync_define_RS.all;
 
 entity gbe_med_fifo is
   generic(
-    SERDES_NUM            : integer range 0 to 3        := 0
+    SERDES_NUM            : integer range 0 to 3  := 0;
+    INCLUDE_DLM           : integer range 0 to 1  := 1
   );
   port (
     RESET                 : in  std_logic;
@@ -57,13 +58,13 @@ entity gbe_med_fifo is
     LINK_ACTIVE_OUT       : out std_logic; -- for internal SCTRL
     TICK_MS_IN            : in  std_logic;
     -- DLM
-    DLM_INJECT_IN         : in  std_logic;
-    DLM_DATA_IN           : in  std_logic_vector(7 downto 0);
+    DLM_INJECT_IN         : in  std_logic                    := '0';
+    DLM_DATA_IN           : in  std_logic_vector(7 downto 0) := (others => '0');
     DLM_FOUND_OUT         : out std_logic;
     DLM_DATA_OUT          : out std_logic_vector(7 downto 0);
     -- Debug
     STATUS_OUT            : out std_logic_vector(7 downto 0);
-    DEBUG_OUT             : out std_logic_vector(63 downto 0)          
+    DEBUG_OUT             : out std_logic_vector(63 downto 0)
   );
 end entity gbe_med_fifo;
 
@@ -263,10 +264,10 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is
   
   signal fifo_full_i                              : std_logic;
 
-  signal rx_bsm                                   : std_logic_vector(3 downto 0);
+--  signal rx_bsm                                   : std_logic_vector(3 downto 0);
   
-  signal remover_dbg                              : std_logic_vector(15 downto 0);
-  signal inserter_dbg                             : std_logic_vector(15 downto 0);
+--  signal remover_dbg                              : std_logic_vector(15 downto 0);
+--  signal inserter_dbg                             : std_logic_vector(15 downto 0);
   
 --  -- just a check to see if something goes wrong....
 --  attribute HGROUP : string;
@@ -498,7 +499,7 @@ begin
     RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based
     RX_PCS_RST_OUT    => rx_pcs_rst, -- CLK_REF based
     LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based
-    STATE_OUT         => rx_bsm --open
+    STATE_OUT         => open --rx_bsm
   );
 
   -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
@@ -514,92 +515,58 @@ begin
     D_OUT(1) => rx_serdes_rst_q
   );
 
---  -- RX PATH
---  -- "Good" debugging pins
---  debug(7 downto 0)  <= sd_rx_data_src;
---  debug(15 downto 8) <= sd_rx_data_dst;
---  debug(16)          <= sd_rx_kcntl_src(0);
---  debug(17)          <= sd_rx_kcntl_dst(0);
---  debug(18)          <= sd_rx_disp_error(0);
---  debug(19)          <= sd_rx_cv_error(0);
---  -- "Bad" debugging pins
---  debug(20) <= remover_dbg(0);
---  debug(21) <= remover_dbg(1);
---  debug(22) <= remover_dbg(2);
---  debug(23) <= remover_dbg(3);
---  debug(24) <= remover_dbg(4);
---  debug(25) <= remover_dbg(5);
---  debug(26) <= pcs_rx_en;
---  debug(27) <= pcs_rx_er;
---  debug(28) <= mac_rx_wr;
---  debug(29) <= mac_rx_eof;
---  debug(30) <= mac_rx_err;
---  debug(31) <= '0';
---  debug(32) <= sd_rx_clk;
---  debug(33) <= CLK_125;
-
-  -- TX PATH
-  -- "Good" debugging pins
-  debug(7 downto 0)  <= sd_tx_data_src;
-  debug(15 downto 8) <= sd_tx_data_dst;
-  debug(16)          <= sd_tx_kcntl_src(0);
-  debug(17)          <= sd_tx_kcntl_dst(0);
-  debug(18)          <= sd_tx_correct_disp_src(0);
-  debug(19)          <= sd_tx_correct_disp_dst(0);
-  -- "Bad" debugging pins
-  debug(20) <= inserter_dbg(0);
-  debug(21) <= inserter_dbg(1);
-  debug(22) <= inserter_dbg(2);
-  debug(23) <= inserter_dbg(3);
-  debug(24) <= inserter_dbg(4);
-  debug(25) <= inserter_dbg(5);
-  debug(26) <= inserter_dbg(6);
-  debug(27) <= inserter_dbg(7);
-  debug(28) <= inserter_dbg(8);
-  debug(29) <= pcs_tx_en;
-  debug(30) <= '0';
-  debug(31) <= '0';
-  debug(32) <= sd_rx_clk;
-  debug(33) <= CLK_125;
-
   ------------------------------------------------------------  
   --- Trudy and Eve ------------------------------------------
   ------------------------------------------------------------  
-  THE_TRUDY: entity inserter
-  port map(
-    CLK           => CLK_125,
-    RESET         => CLEAR,
-    -- PHY output
-    PHY_D_IN      => sd_tx_data_src,
-    PHY_K_IN      => sd_tx_kcntl_src(0),
-    PHY_CD_IN     => sd_tx_correct_disp_src(0),
-    -- SerDes input
-    TX_D_OUT      => sd_tx_data_dst,
-    TX_K_OUT      => sd_tx_kcntl_dst(0),
-    TX_CD_OUT     => sd_tx_correct_disp_dst(0),
-    -- DLM stuff
-    DLM_DATA_IN   => DLM_DATA_IN,
-    DLM_INJECT_IN => DLM_INJECT_IN,
-    --
-    DEBUG_OUT     => inserter_dbg
-  );
   
-  THE_EVE: entity remover
-  port map(
-    CLK           => sd_rx_clk,
-    RESET         => CLEAR,
-    -- SerDes output
-    RX_D_IN       => sd_rx_data_src,
-    RX_K_IN       => sd_rx_kcntl_src(0),
-    -- PHY input
-    PHY_D_OUT     => sd_rx_data_dst,
-    PHY_K_OUT     => sd_rx_kcntl_dst(0),
-    -- DLM stuff
-    DLM_DATA_OUT  => DLM_DATA_OUT,
-    DLM_FOUND_OUT => DLM_FOUND_OUT,
-    --
-    DEBUG_OUT     => remover_dbg
-  );
+  TRUDY_AND_EVE: if INCLUDE_DLM = 1 generate 
+    THE_TRUDY: entity inserter
+    port map(
+      CLK           => CLK_125,
+      RESET         => CLEAR,
+      -- PHY output
+      PHY_D_IN      => sd_tx_data_src,
+      PHY_K_IN      => sd_tx_kcntl_src(0),
+      PHY_CD_IN     => sd_tx_correct_disp_src(0),
+      -- SerDes input
+      TX_D_OUT      => sd_tx_data_dst,
+      TX_K_OUT      => sd_tx_kcntl_dst(0),
+      TX_CD_OUT     => sd_tx_correct_disp_dst(0),
+      -- DLM stuff
+      DLM_DATA_IN   => DLM_DATA_IN,
+      DLM_INJECT_IN => DLM_INJECT_IN,
+      --
+      DEBUG_OUT     => open --inserter_dbg
+    );
+  
+    THE_EVE: entity remover
+    port map(
+      CLK           => sd_rx_clk,
+      RESET         => CLEAR,
+      -- SerDes output
+      RX_D_IN       => sd_rx_data_src,
+      RX_K_IN       => sd_rx_kcntl_src(0),
+      -- PHY input
+      PHY_D_OUT     => sd_rx_data_dst,
+      PHY_K_OUT     => sd_rx_kcntl_dst(0),
+      -- DLM stuff
+      DLM_DATA_OUT  => DLM_DATA_OUT,
+      DLM_FOUND_OUT => DLM_FOUND_OUT,
+      --
+      DEBUG_OUT     => open --remover_dbg
+    );
+  end generate TRUDY_AND_EVE;
+  
+  NO_TRUDY_AND_EVE: if INCLUDE_DLM = 0 generate
+    sd_tx_data_dst            <= sd_tx_data_src;
+    sd_tx_kcntl_dst(0)        <= sd_tx_kcntl_src(0);
+    sd_tx_correct_disp_dst(0) <= sd_tx_correct_disp_src(0);
+    sd_rx_data_dst            <= sd_rx_data_src;
+    sd_rx_kcntl_dst(0)        <= sd_rx_kcntl_src(0);
+    DLM_DATA_OUT              <= (others => '0');
+    DLM_FOUND_OUT             <= '0';
+  end generate NO_TRUDY_AND_EVE;
+  
   ------------------------------------------------------------  
   ------------------------------------------------------------  
   ------------------------------------------------------------  
@@ -937,4 +904,52 @@ begin
 --  debug(32) <= '0';
 --  debug(33) <= CLK_125;
 
+--  -- RX PATH
+--  -- "Good" debugging pins
+--  debug(7 downto 0)  <= sd_rx_data_src;
+--  debug(15 downto 8) <= sd_rx_data_dst;
+--  debug(16)          <= sd_rx_kcntl_src(0);
+--  debug(17)          <= sd_rx_kcntl_dst(0);
+--  debug(18)          <= sd_rx_disp_error(0);
+--  debug(19)          <= sd_rx_cv_error(0);
+--  -- "Bad" debugging pins
+--  debug(20) <= remover_dbg(0);
+--  debug(21) <= remover_dbg(1);
+--  debug(22) <= remover_dbg(2);
+--  debug(23) <= remover_dbg(3);
+--  debug(24) <= remover_dbg(4);
+--  debug(25) <= remover_dbg(5);
+--  debug(26) <= pcs_rx_en;
+--  debug(27) <= pcs_rx_er;
+--  debug(28) <= mac_rx_wr;
+--  debug(29) <= mac_rx_eof;
+--  debug(30) <= mac_rx_err;
+--  debug(31) <= '0';
+--  debug(32) <= sd_rx_clk;
+--  debug(33) <= CLK_125;
+
+--  -- TX PATH
+--  -- "Good" debugging pins
+--  debug(7 downto 0)  <= sd_tx_data_src;
+--  debug(15 downto 8) <= sd_tx_data_dst;
+--  debug(16)          <= sd_tx_kcntl_src(0);
+--  debug(17)          <= sd_tx_kcntl_dst(0);
+--  debug(18)          <= sd_tx_correct_disp_src(0);
+--  debug(19)          <= sd_tx_correct_disp_dst(0);
+--  -- "Bad" debugging pins
+--  debug(20) <= inserter_dbg(0);
+--  debug(21) <= inserter_dbg(1);
+--  debug(22) <= inserter_dbg(2);
+--  debug(23) <= inserter_dbg(3);
+--  debug(24) <= inserter_dbg(4);
+--  debug(25) <= inserter_dbg(5);
+--  debug(26) <= inserter_dbg(6);
+--  debug(27) <= inserter_dbg(7);
+--  debug(28) <= inserter_dbg(8);
+--  debug(29) <= pcs_tx_en;
+--  debug(30) <= '0';
+--  debug(31) <= '0';
+--  debug(32) <= sd_rx_clk;
+--  debug(33) <= CLK_125;
+
 end architecture gbe_med_fifo_arch;