added resync to med_tlk

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index 3e70ffafac3103718ab4f9ba299c51d5ee0f8125..abf7201fb8e020a36812a622146fee3c59151538 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -665,7 +665,7 @@ begin
           when sa_WRONG_ADDR =>
             fifo_to_apl_read <= not fifo_to_apl_empty;
             throw_away <= '1';
-            if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" then
+            if saved_fifo_to_apl_packet_type = TYPE_TRM and fifo_to_apl_PACKET_NUM_OUT = "11" then
               next_state_to_apl <= sa_INACTIVE;
               slave_end <= '1';
             end if;

diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd
index 51cee8357c6d3ac9af6f8306e70b821cab3c55bc..45cb877d704e92541a8ec5eee9e13f6d85fa1017 100644 (file)
--- a/trb_net16_endpoint_0_trg_1_api.vhd
+++ b/trb_net16_endpoint_0_trg_1_api.vhd
@@ -46,7 +46,8 @@ entity trb_net16_endpoint_0_trg_1_api is
     MED_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
     MED_READ_OUT:      out std_logic; -- buffer reads a word from media
     MED_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits
-
+    MED_STAT_OP      : in  std_logic_vector (15 downto 0);
+    MED_CTRL_OP      : out std_logic_vector (15 downto 0);
     
     -- APL Transmitter port
     APL_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
@@ -145,9 +146,7 @@ component trb_net16_iobuf is
     INT_INIT_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
     INT_INIT_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
     INT_INIT_READ_OUT:      out std_logic;
-    
-    INT_REPLY_HEADER_IN:     in  std_logic; -- Concentrator kindly asks to resend the last
-                                      -- header (only for the reply path)
+
     INT_REPLY_DATAREADY_OUT: out std_logic;
     INT_REPLY_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
     INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
@@ -363,6 +362,9 @@ signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31
 
 begin
 
+  MED_CTRL_OP(15) <= MED_STAT_OP(15);
+  MED_CTRL_OP(14 downto 0) <= (others => '0');
+
   --Connections for data channel
     genmuxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
       gendat: if i = DAT_CHANNEL generate
@@ -600,8 +602,7 @@ IOBUF: trb_net16_iobuf
     INT_INIT_DATA_IN       => apl_to_buf_INIT_DATA,
     INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
     INT_INIT_READ_OUT      => apl_to_buf_INIT_READ,
-    
-    INT_REPLY_HEADER_IN     => '0',
+
     INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
     INT_REPLY_DATA_OUT      => buf_to_apl_REPLY_DATA,
     INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 6d8a98fea094837694581c8d605ccc7371262f77..2235e0a71e81265528b909a433b0de7f6cc1ef9b 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -48,6 +48,8 @@ entity trb_net16_hub_base is
     MED_PACKET_NUM_IN : in  std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
     MED_READ_OUT      : out std_logic_vector (MII_NUMBER-1 downto 0); -- buffer reads a word from media
     MED_ERROR_IN      : in  std_logic_vector (MII_NUMBER*3-1 downto 0);
+    MED_STAT_OP       : in  std_logic_vector (MII_NUMBER*16-1 downto 0);
+    MED_CTRL_OP       : out std_logic_vector (MII_NUMBER*16-1 downto 0);
     --API: interfaces
     APL_DATA_IN       : in  std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
     APL_PACKET_NUM_IN : in  std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
@@ -166,7 +168,10 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal IOBUF_IBUF_BUFFER            :  std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
   signal IOBUF_CTRL_GEN               :  std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
   signal IOBUF_CTRL_IBUF_BUFFER       :  std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
-
+  signal resync : std_logic_vector(MII_NUMBER-1 downto 0);
+  signal combined_resync : std_logic;
+  signal reg_resync : std_logic;
+  signal resync_counter : std_logic_vector(7 downto 0);
 
   component trb_net16_hub_logic is
   generic (
@@ -280,7 +285,6 @@ end component;
       INT_INIT_DATA_IN:       in  std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
       INT_INIT_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
       INT_INIT_READ_OUT:      out std_logic;
-      INT_REPLY_HEADER_IN:     in  std_logic;
       INT_REPLY_DATAREADY_OUT: out std_logic;
       INT_REPLY_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
       INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
@@ -467,12 +471,35 @@ end component;
       MED_REPLY_READ_OUT:          out std_logic
       );
   end component;
-  
+
 begin
 
---set unused signals
-  
 
+--generate media resync
+  gen_resync : for i in 0 to MII_NUMBER-1 generate
+    resync(i) <= MED_STAT_OP(i*16+15);
+    MED_CTRL_OP(15+i*16) <= reg_resync;
+  end generate;
+  combined_resync <= or_all(resync);
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          resync_counter <= (others => '0');
+          reg_resync <= '0';
+        else
+          if combined_resync = '1' then
+            reg_resync <= '1';
+          elsif resync_counter = x"FE" then
+            reg_resync <= '0';
+          end if;
+          if reg_resync = '1' then
+            resync_counter <= resync_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
 
 
 --generate multiplexers
@@ -558,8 +585,7 @@ begin
             INT_INIT_DATA_IN       => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
             INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
             INT_INIT_READ_OUT      => hub_to_buf_INIT_READ(i),
-            
-            INT_REPLY_HEADER_IN     => buf_to_hub_REPLY_SEND_HEADER(i),
+
             INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
             INT_REPLY_DATA_OUT      => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
             INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),

diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd
index bc4093e63176d95287018274029f16df44bcf0f4..6dbf20f3503883449db61d20454c63fddd013fe5 100644 (file)
--- a/trb_net16_hub_logic.vhd
+++ b/trb_net16_hub_logic.vhd
@@ -84,7 +84,22 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
       CTRL:  in  STD_LOGIC_VECTOR (31 downto 0)
       );
   end component;
-  
+
+  component trb_net_ram is
+    generic(
+      depth : integer := 4;
+      width : integer := 16
+      );
+    port(
+      CLK    : in std_logic;
+      wr     : in std_logic;
+      ain    : in std_logic_vector(depth-1 downto 0);
+      din    : in std_logic_vector(width-1 downto 0);
+      aout   : in std_logic_vector(depth-1 downto 0);
+      dout   : out std_logic_vector(width-1 downto 0)
+      );
+  end component;
+
 --signals init_pool
   signal INIT_POOL_DATAREADY                 : std_logic;
   signal INIT_POOL_READ                      : std_logic;
@@ -107,6 +122,13 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
   signal REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1  downto 0);
   signal REPLY_MUX_real_reading                : std_logic;
   signal real_activepoints                     : std_logic_vector(POINT_NUMBER-1 downto 0);
+  
+  signal REPLY_reading_hdr                     : std_logic_vector(POINT_NUMBER-1  downto 0);
+  signal next_REPLY_reading_hdr                : std_logic_vector(POINT_NUMBER-1  downto 0);
+  signal current_REPLY_reading_hdr             : std_logic_vector(POINT_NUMBER-1  downto 0);
+  signal last_header_addr : std_logic_vector(1 downto 0);
+  signal last_header_data : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0);
+  signal reading_last_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
 
 --general signals
   signal locked, next_locked                 : std_logic;
@@ -346,6 +368,50 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
       end if;
     end process;
 
+--REPLY reading and saving HDR
+----------------------------------
+  gen_reading_hdr : for i in 0 to POINT_NUMBER-1 generate
+    process(REPLY_reading_hdr, REPLY_PACKET_NUM_IN, REPLY_DATA_IN)
+      begin
+        next_REPLY_reading_hdr(i) <= REPLY_reading_hdr(i);
+        if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "11" then
+          next_REPLY_reading_hdr(i) <= '0';
+        elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_HDR
+            and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "00" then
+          next_REPLY_reading_hdr(i) <= '1';
+        end if;
+      end process;
+  end generate;
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if  RESET = '1' then
+          REPLY_reading_hdr <= (others => '0');
+        else
+          REPLY_reading_hdr <= next_REPLY_reading_hdr;
+        end if;
+      end if;
+    end process;
+  current_REPLY_reading_hdr <= next_REPLY_reading_hdr or REPLY_reading_hdr;
+
+  gen_saving_hdr : for i in 0 to POINT_NUMBER-1 generate
+    last_HDR_RAM : trb_net_ram
+      generic map(
+        depth => 2,
+        width => 16
+        )
+      port map(
+        CLK    => CLK,
+        wr     => REPLY_reading_hdr(i),
+        ain    => REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+        din    => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+        aout   => last_header_addr(1 downto 0),
+        dout   => last_header_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
+        );
+  end generate;
+  last_header_addr <= packet_counter;
+
 
 
 --REPLY reading and merging TRM
@@ -491,6 +557,11 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
 
   -- we have to care to read multiples of four packets from every point
   -- release is currently done after first packet of TRM
+  -- when switching from one point to another some data was already read from, we have
+  -- to set reading_last_hdr instead of reading_from_point
+
+reading_last_hdr <= (others => '0');
+  
   gen_reply_point_lock : process(reply_point_lock, reading_from_point, comb_REPLY_muxed_PACKET_NUM, REPLY_MUX_reading,
                                  REPLY_DATAREADY_IN, comb_REPLY_muxed_DATA)
     begin
@@ -532,7 +603,8 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
       begin
         tmp_data := '0';
         gen_data_mux : for j in 0 to POINT_NUMBER-1 loop
-          tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j));
+          tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j))
+                               or (last_header_data(j*c_DATA_WIDTH+i) and reading_last_hdr(j));
         end loop;
         comb_REPLY_muxed_DATA(i) <= tmp_data;
       end process;

diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd
index 493eee508e075fe10016ffe18928187719c9f4a4..9a6db0f11304172abdee3d6be2534dc23341c0e0 100644 (file)
--- a/trb_net16_ibuf.vhd
+++ b/trb_net16_ibuf.vhd
@@ -38,7 +38,6 @@ entity trb_net16_ibuf is
     INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
     INT_REPLY_DATAREADY_OUT : out std_logic;
     INT_REPLY_READ_IN       : in  std_logic;
-    INT_REPLY_HEADER_IN     : in  std_logic;    
     INT_ERROR_OUT           : out std_logic_vector (2 downto 0);
     -- Status and control port
     STAT_BUFFER             : out std_logic_vector (31 downto 0)
@@ -93,26 +92,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is
       );
   end component;
 
-  component trb_net_ram is
-    generic(
-      depth : integer := 4;
-      width : integer := 16
-      );
-    port(
-      CLK    : in std_logic;
-      wr     : in std_logic;
-      ain    : in std_logic_vector(depth-1 downto 0);
-      din    : in std_logic_vector(width-1 downto 0);
-      aout   : in std_logic_vector(depth-1 downto 0);
-      dout   : out std_logic_vector(width-1 downto 0)
-      );
-  end component;  
+
   
-  signal last_header_addr : std_logic_vector(1 downto 0);
-  signal reg_last_header_addr :  std_logic_vector(1 downto 0);
-  signal last_header_data : std_logic_vector(15 downto 0); 
-  signal reg_INT_REPLY_HEADER_IN, next_reg_INT_REPLY_HEADER_IN : std_logic;
-  signal sending_last_header, next_sending_last_header : std_logic;
   signal fifo_data_in          : std_logic_vector(c_DATA_WIDTH-1 downto 0);
   signal fifo_data_out         : std_logic_vector(c_DATA_WIDTH-1 downto 0);
   signal fifo_packet_num_in    : std_logic_vector(c_NUM_WIDTH-1  downto 0);
@@ -297,7 +278,7 @@ begin
         SYN_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
         SYN_READ_IN => INT_REPLY_READ_IN
         );
-        
+
     process(CLK)
       begin
         if rising_edge(CLK) then
@@ -320,9 +301,7 @@ begin
 
   process(fifo_data_out, fifo_packet_num_out, sbuf_init_free, 
           fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type,
-          fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, 
-                        sending_last_header, last_header_addr, reg_INT_REPLY_HEADER_IN, 
-                        INT_REPLY_HEADER_IN, last_header_data, reg_last_header_addr)
+          fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN)
     begin
       tmp_INT_DATA_OUT <= fifo_data_out;
       tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out;
@@ -331,36 +310,17 @@ begin
       got_eob_init_out <= '0';
       got_eob_reply_out <= '0';
       throw_away <= '0';
-      next_sending_last_header <= sending_last_header;
-      next_reg_INT_REPLY_HEADER_IN <= reg_INT_REPLY_HEADER_IN or INT_REPLY_HEADER_IN;
+
 
       fifo_read <= not fifo_empty and not (fifo_read_before and not 
                       ((INT_INIT_READ_IN and not current_fifo_packet_type(3)) 
                       or (INT_REPLY_READ_IN and current_fifo_packet_type(3)) or throw_away));
 
-      if reg_INT_REPLY_HEADER_IN = '1' and fifo_packet_num_out = "11" then
-                   next_reg_INT_REPLY_HEADER_IN <= '0';
-        fifo_read <= '0';
-        next_sending_last_header <= '1';
-      end if;
-
-      
       if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then
         tmp_INT_INIT_DATAREADY_OUT <=  sbuf_init_free and not current_fifo_packet_type(3);
         tmp_INT_REPLY_DATAREADY_OUT <=  sbuf_reply_free and current_fifo_packet_type(3);
       end if;
 
-      if sending_last_header = '1' then
-        tmp_INT_REPLY_DATAREADY_OUT <= '1';
-        tmp_INT_DATA_OUT <= last_header_data;
-        tmp_INT_PACKET_NUM_OUT <= reg_last_header_addr;
-        if tmp_INT_REPLY_DATAREADY_OUT = '1' and sbuf_REPLY_free = '1' then
-          if last_header_addr = "11" then
-            next_sending_last_header <= '0';
-          end if;
-        end if;
-      end if;
-      
       if last_fifo_read = '1' then
         if current_fifo_packet_type(2 downto 0) = TYPE_EOB then
           throw_away <= '1';
@@ -385,35 +345,7 @@ begin
         end if;
       end if;
     end process;
-    
-   process(CLK)
-    begin
-      if rising_edge(CLK) then
-        if RESET = '1' then
-          last_header_addr <= "00";
-        elsif sending_last_header = '1' and sbuf_REPLY_free = '1' then
-          last_header_addr <= last_header_addr + 1;
-        end if;
-      end if;
-    end process;
-    
-   process(CLK)
-    begin
-      if rising_edge(CLK) then
-        if RESET = '1' then
-          reg_INT_REPLY_HEADER_IN <= '0';
-          reg_last_header_addr <= "00";
---          last_header_addr <= "00";
-                        sending_last_header <= '0';
-        else
-          reg_INT_REPLY_HEADER_IN <= next_reg_INT_REPLY_HEADER_IN;
-          reg_last_header_addr <= last_header_addr;
---          last_header_addr <= next_last_header_addr;
-                        sending_last_header <= next_sending_last_header;
-        end if;
-      end if;
-    end process;
-    
+
    process(CLK)
     begin
       if rising_edge(CLK) then
@@ -430,7 +362,6 @@ begin
       end if;
     end process;
 
-
   gen_ack1 : if USE_ACKNOWLEDGE = 1 generate
     reg_locked: process(CLK)
       begin
@@ -446,22 +377,7 @@ begin
       end process;
   end generate;
 
---saving last HDR
-  last_HDR_RAM : trb_net_ram
-    generic map(
-      depth => 2,
-      width => 16
-      )
-    port map(
-      CLK    => CLK,
-      wr     => reading_header,
-      ain    => fifo_packet_num_out,
-      din    => fifo_data_out,
-      aout   => last_header_addr,
-      dout   => last_header_data
-      );
 
-  reading_header <= '1' when (current_fifo_packet_type = TYPE_HDR and fifo_empty = '0') else '0';
 
 
   

diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd
index 8147820c5b336a430e8d9d89d41a97ad496499e0..1cdfa88bced6621ced54090faadcb39f2fc2bdc6 100644 (file)
--- a/trb_net16_iobuf.vhd
+++ b/trb_net16_iobuf.vhd
@@ -58,8 +58,6 @@ entity trb_net16_iobuf is
     INT_INIT_PACKET_NUM_IN: in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
     INT_INIT_READ_OUT:      out std_logic;
 
-    INT_REPLY_HEADER_IN:     in  std_logic; -- Concentrator kindly asks to resend the last
-                                      -- header (only for the reply path)
     INT_REPLY_DATAREADY_OUT: out std_logic;
     INT_REPLY_DATA_OUT:      out std_logic_vector (c_DATA_WIDTH-1 downto 0);
     INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1  downto 0);
@@ -153,7 +151,6 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is
       INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
       INT_REPLY_DATAREADY_OUT : out std_logic;
       INT_REPLY_READ_IN       : in  std_logic;
-      INT_REPLY_HEADER_IN     : in  std_logic;
       INT_ERROR_OUT           : out std_logic_vector (2 downto 0);
       -- Status and control port
       STAT_BUFFER             : out std_logic_vector (31 downto 0)
@@ -227,7 +224,6 @@ begin
         INT_REPLY_DATA_OUT => INT_REPLY_DATA_OUT,
         INT_REPLY_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
         INT_REPLY_READ_IN => INT_REPLY_READ_IN,
-        INT_REPLY_HEADER_IN => INT_REPLY_HEADER_IN,
         INT_ERROR_OUT => IBUF_error,
         STAT_BUFFER(31 downto 0) => IBUF_stat_buffer
         );

diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index fc79df1e8250b81db27387f36343b5ba8e28f9e1..22ad1ad529cf96b7175a1d11e88283647bd10cd5 100644 (file)
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -35,7 +35,9 @@ entity trb_net16_med_tlk is
     MED_DATA_OUT        : out std_logic_vector (15 downto 0);
     MED_PACKET_NUM_OUT  : out std_logic_vector (1 downto 0);
     MED_ERROR_OUT       : out std_logic_vector (2 downto 0);
-    STAT                : out std_logic_vector (63 downto 0)
+    STAT                : out std_logic_vector (63 downto 0);
+    STAT_OP             : out std_logic_vector (15 downto 0);
+    CTRL_OP             : in  std_logic_vector (15 downto 0)
                         --connect STAT(0) to LED
     );
 end trb_net16_med_tlk;
@@ -57,9 +59,7 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
       full_out:        OUT std_logic;
       empty_out:       OUT std_logic;
       fifostatus_out:  OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo
-      valid_read_out:  OUT std_logic;
-      almost_empty_out:OUT std_logic;
-      underflow_out:   OUT std_logic
+      valid_read_out:  OUT std_logic
       );
   end component trb_net_fifo_16bit_bram_dualport;
 
@@ -112,6 +112,9 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
   signal state_bits : std_logic_vector(2 downto 0);
   signal counter_reset : std_logic;
 
+  signal resync_counter : std_logic_vector(1 downto 0);
+  signal buf_STAT_OP : std_logic_vector(15 downto 0);
+  signal send_resync : std_logic;
 begin
 
   TLK_ENABLE  <= not RESET;
@@ -142,9 +145,7 @@ begin
       full_out        => fifo_full_a,
       empty_out       => fifo_empty_a,
       fifostatus_out  => fifo_status_a,
-      almost_empty_out=> fifo_almost_empty_a,
-      valid_read_out  => fifo_valid_read_a,
-      underflow_out   => fifo_underflow_a
+      valid_read_out  => fifo_valid_read_a
       );
 
   fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow;
@@ -155,23 +156,19 @@ begin
 --   fifo_rd_en_a <= not fifo_almost_empty_a and rx_allow;
 
 
-  buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a  and rx_allow;
+  buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and rx_allow;
   MED_ERROR_OUT <= buf_MED_ERROR_OUT;
+  buf_STAT_OP(2 downto 0) <= buf_MED_ERROR_OUT;
+  STAT_OP <= buf_STAT_OP;
   fifo_reset <= internal_reset;
-  fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
+  fifo_din_a <= '0' & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
 
   process(CLK)
     begin
       if rising_edge(CLK) then
-        if internal_reset = '1' then
-          MED_PACKET_NUM_OUT <= "00";
-          MED_DATAREADY_OUT  <= '0';
-          MED_DATA_OUT       <= (others => '0');
-        else
-          MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
-          MED_DATAREADY_OUT  <= buf_MED_DATAREADY_OUT;
-          MED_DATA_OUT       <= fifo_dout_a(15 downto 0);
-        end if;
+        MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
+        MED_DATAREADY_OUT  <= buf_MED_DATAREADY_OUT;
+        MED_DATA_OUT       <= fifo_dout_a(15 downto 0);
       end if;
     end process;
 
@@ -187,8 +184,6 @@ begin
   STAT(9) <= fifo_full_m;
 --  STAT(10)<= last_fifo_rd_en_m;
 --  STAT(11)<= last_fifo_rd_en_a;
-  STAT(12)<= fifo_almost_empty_m;
-  STAT(13)<= fifo_almost_empty_a;
   STAT(14) <= reg_RX_DV;
   STAT(15) <= reg_RX_ER;
   STAT(31 downto 16) <= reg_RXD;
@@ -201,8 +196,6 @@ begin
   STAT(50 downto 49) <= fifo_dout_m(17 downto 16);
   STAT(54 downto 51) <= fifo_din_a(3 downto 0);
   STAT(56 downto 55) <= fifo_din_a(17 downto 16);
-  STAT(57) <= fifo_underflow_a;
-  STAT(58) <= fifo_underflow_m;
   STAT(59) <= TLK_CLK_neg;
   STAT(60) <= fifo_wr_en_m;
   --STAT(63 downto 57) <= (others => '0');
@@ -211,15 +204,9 @@ begin
   process(TLK_RX_CLK)
     begin
       if rising_edge(TLK_RX_CLK) then
-        if internal_reset = '1' then
-          reg_RXD   <= (others => '0');
-          reg_RX_DV <= '0';
-          reg_RX_ER <= '0';
-        else
-          reg_RXD   <= TLK_RXD;
-          reg_RX_DV <= TLK_RX_DV;
-          reg_RX_ER <= TLK_RX_ER;
-        end if;
+        reg_RXD   <= TLK_RXD;
+        reg_RX_DV <= TLK_RX_DV;
+        reg_RX_ER <= TLK_RX_ER;
       end if;
     end process;
 
@@ -234,9 +221,26 @@ begin
       end if;
     end process;
 
---common network packet number reset
-  reset_packet_num <= '0';
-
+--Detect resync
+---------------
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        buf_STAT_OP(15) <= '0';
+        reset_packet_num <= '0';
+        if fifo_valid_read_a = '1' then
+          if fifo_dout_a(7 downto 0) = x"7F" then
+            resync_counter <= resync_counter + 1;
+          else
+            resync_counter <= "00";
+          end if;
+        end if;
+        if resync_counter = "11" then
+          buf_STAT_OP(15) <= '1';
+          reset_packet_num <= '1';
+        end if;
+      end if;
+    end process;
 
 -------------
 --Sender
@@ -280,11 +284,9 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
       write_data_in   => fifo_din_m,
       read_data_out   => fifo_dout_m,
       valid_read_out  => fifo_valid_read_m,
-      almost_empty_out=> fifo_almost_empty_m,
       full_out        => fifo_full_m,
       empty_out       => fifo_empty_m,
-      fifostatus_out  => fifo_status_m,
-      underflow_out   => fifo_underflow_m
+      fifostatus_out  => fifo_status_m
       );
 
   TLK_TX_ER   <= '0';
@@ -294,13 +296,8 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
   process(CLK)
     begin
       if rising_edge(CLK) then
-        if internal_reset = '1' then
-          fifo_wr_en_m  <= '0';
-          fifo_din_m    <= (others => '0');
-        else
-          fifo_wr_en_m  <= (MED_DATAREADY_IN and buf_MED_READ_OUT);-- or fifo_almost_empty_m;
-          fifo_din_m    <= fifo_almost_empty_m & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN;
-        end if;
+        fifo_wr_en_m  <= (MED_DATAREADY_IN and buf_MED_READ_OUT);-- or fifo_almost_empty_m;
+        fifo_din_m    <= '0' & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN;
       end if;
     end process;
 
@@ -309,16 +306,22 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
   process(TLK_CLK_neg)
     begin
       if rising_edge(TLK_CLK_neg) then
-        if internal_reset = '1' then
-          reg_TX_EN <= '0';
-          reg_TXD   <= (others => '0');
-        else
+        if send_resync = '0' then
           reg_TXD   <= fifo_dout_m(15 downto 0);
-          reg_TX_EN <= fifo_valid_read_m and fifo_dout_m(16) and not fifo_underflow_m; --last_fifo_rd_en_m;
+        else
+          reg_TXD   <= x"007F";
         end if;
+        reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or send_resync; --last_fifo_rd_en_m;
       end if;
     end process;
 
+--   process(TLK_CLK_neg)
+--     begin
+--       if rising_edge(TLK_CLK_neg) then
+--         
+--       end if;
+--     end process;
+
 -------------
 --Medium states
 -------------
@@ -339,7 +342,7 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
           next_MED_ERROR_OUT <= ERROR_NC;
           next_internal_reset <= '1';
           counter_reset <= '0';
-          if counter(16) = '1' then  --16
+          if counter(16) = '1' then
             counter_reset <= '1';
             next_state <= WAIT_FOR_RX_LOCK;
             next_internal_reset <= '0';
@@ -352,7 +355,7 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
           end if;
         when WAIT_FOR_TX_ALLOW =>
           next_MED_ERROR_OUT <= ERROR_WAIT;
-          if counter(27) = '1' then --20
+          if counter(27) = '1' then
             next_tx_allow <= '1';
             next_state <= WORKING;
           end if;
@@ -383,20 +386,15 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
   states_reg : process(CLK)
     begin
       if rising_edge(CLK) then
-        if internal_reset = '1' then
-          tx_allow <= '0';
-          rx_allow <= '0';
-        else
-          tx_allow <= next_tx_allow;
-          rx_allow <= next_rx_allow;
-        end if;
+        tx_allow <= next_tx_allow;
+        rx_allow <= next_rx_allow;
       end if;
     end process;
 
   states_reg_counter : process(CLK)
     begin
       if rising_edge(CLK) then
-        if RESET = '1' or counter_reset = '1' then
+        if counter_reset = '1' then
           counter <= (others => '0');
         else
           counter <= next_counter;

diff --git a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd
index 7a6ae8ad0faf7e43a14c430102a8cd2eeae1b957..90cdcd3757bb90dcc7afb8ab57b593307cc5358d 100644 (file)
--- a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd
+++ b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd
@@ -54,9 +54,7 @@ entity trb_net_fifo_16bit_bram_dualport is
      full_out:        OUT std_logic;
      empty_out:       OUT std_logic;
      fifostatus_out:  OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo
-     valid_read_out:  OUT std_logic;
-     almost_empty_out:OUT std_logic;
-     underflow_out :  OUT std_logic
+     valid_read_out:  OUT std_logic
     );
 end entity trb_net_fifo_16bit_bram_dualport;
 
@@ -145,9 +143,7 @@ architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_du
       dout: OUT std_logic_VECTOR(17 downto 0);
       empty: OUT std_logic;
       full: OUT std_logic;
-      prog_empty: OUT std_logic;
-      valid: OUT std_logic;
-      underflow: OUT std_logic);
+      valid: OUT std_logic);
   end component;
 --       read_clock_in:   IN  std_logic;
 --      write_clock_in:  IN  std_logic;
@@ -171,9 +167,7 @@ FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k
       dout => read_data_out,
       empty => empty_out,
       full => full_out,
-      prog_empty => almost_empty_out,
-      valid => valid_read_out,
-      underflow => underflow_out
+      valid => valid_read_out
       );
 
 --    read_enable <= read_enable_in;

diff --git a/xilinx/virtex4/xilinx_fifo_dualport_18x1k.ngc b/xilinx/virtex4/xilinx_fifo_dualport_18x1k.ngc
deleted file mode 100644 (file)
index e38660e..0000000
--- a/xilinx/virtex4/xilinx_fifo_dualport_18x1k.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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\ No newline at end of file

diff --git a/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco b/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco
index 4954c115f154820770922cbb9e3a4b26209b9b98..f20d1df18ab5a1b769a07f8d7390fd8f5d54244b 100644 (file)
--- a/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco
+++ b/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco
@@ -56,14 +56,14 @@ CSET output_depth=1024
 CSET overflow_flag=false
 CSET overflow_sense=Active_High
 CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
 CSET programmable_full_type=No_Programmable_Full_Threshold
 CSET read_clock_frequency=100
 CSET read_data_count=false
 CSET read_data_count_width=10
 CSET reset_pin=true
 CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=true
+CSET underflow_flag=false
 CSET underflow_sense=Active_High
 CSET use_dout_reset=false
 CSET use_embedded_registers=false