--- /dev/null
+../scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--design options: backplane or front SFP
+ constant USE_BACKPLANE : integer := c_NO;
+
+--We want an ECP3
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO; -- DEPRECIATED
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"D00F";
+
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+ type intlist_t is array(0 to 7) of integer;
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0);
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := std_logic_vector(to_unsigned(62,8));
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+ t(22 downto 16) := "0100111"; --sctrl via GbE
+ t(23 downto 23) := "1"; -- GbE included
+ t(27 downto 24) := "0000"; --num SFPs with TrbNet
+ t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1));
+ t(40 downto 40) := "0"; -- LCD
+ t(42 downto 42) := "0"; -- SPU
+ t(43 downto 43) := "0"; -- UART
+ t(44 downto 44) := "0"; -- STATISTICS
+ t(51 downto 48) := "0000"; -- TRIGGER_LOGIC
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := "0"; -- RX_CLOCK
+ t(54 downto 54) := "1"; -- EXTERNAL_CLOCK
+ t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
mapper_options => '-u -retime -split_node',
include_TDC => 0,
-include_GBE => 0,
+include_GBE => 1,
firefox_open => 0,
twr_number_of_errors => 20,
--- /dev/null
+# locate the PCS blocks
+LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
+LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSC";
+
+FREQUENCY NET "CLK_CORE_PCLK_c" 200.0 MHz;
+FREQUENCY NET "CLK_SUPPL_PCLK_c" 125.0 MHz;
+FREQUENCY NET "clk_sys" 100.0 MHz;
+FREQUENCY NET "GBE/clk_125_rx_from_pcs[0]" 125.0 MHz;
+
+# primary nets
+#USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]";
+
+# secondary nets
+#USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[1]";
add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../TOMcat/code/tomcat_tools.vhd"
add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+#add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire2.vhd"
+
#SlowControl files
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd"
#Hub
add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd"
#GbE
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_single.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_raw.vhd"
+
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
-
-
-
-add_file -vhdl -lib work "./trb3sc_hub.vhd"
-#add_file -fpga_constraint "./synplify.fdc"
+add_file -vhdl -lib work "./trb3sc_gbe_hub.vhd"
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define_RS.all;
+
+entity trb3sc_gbe_hub is
+ port(
+ CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
+ CLK_CORE_PCLK : in std_logic; --Main Oscillator
+ CLK_EXT_PLL_LEFT : in std_logic; --External Clock
+ --Additional IO
+ HDR_IO : inout std_logic_vector(10 downto 1);
+ BACK_LVDS : inout std_logic_vector( 1 downto 0);
+ BACK_GPIO : inout std_logic_vector( 3 downto 0);
+ --LED
+ LED_GREEN : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector( 1 downto 0);
+ LED_RJ_RED : out std_logic_vector( 1 downto 0);
+ LED_WHITE : out std_logic_vector( 1 downto 0);
+ LED_SFP_GREEN : out std_logic_vector( 1 downto 0);
+ LED_SFP_RED : out std_logic_vector( 1 downto 0);
+ --SFP
+ SFP_LOS : in std_logic_vector( 1 downto 0);
+ SFP_MOD0 : in std_logic_vector( 1 downto 0);
+ SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+ SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+ SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
+ LED_HUB_LINKOK : out std_logic_vector(8 downto 1);
+ LED_HUB_RX : out std_logic_vector(8 downto 1);
+ LED_HUB_TX : out std_logic_vector(8 downto 1);
+ HUB_MOD0 : in std_logic_vector(8 downto 1);
+ HUB_MOD1 : inout std_logic_vector(8 downto 1);
+ HUB_MOD2 : inout std_logic_vector(8 downto 1);
+ HUB_TXDIS : out std_logic_vector(8 downto 1);
+ HUB_LOS : in std_logic_vector(8 downto 1);
+ --Serdes switch
+ PCSSW_ENSMB : out std_logic;
+ PCSSW_EQ : out std_logic_vector( 3 downto 0);
+ PCSSW_PE : out std_logic_vector( 3 downto 0);
+ PCSSW : out std_logic_vector( 7 downto 0);
+ --ADC
+ ADC_CLK : out std_logic;
+ ADC_CS : out std_logic;
+ ADC_DIN : out std_logic;
+ ADC_DOUT : in std_logic;
+ --Flash, 1-wire, Reload
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_IN : out std_logic;
+ FLASH_OUT : in std_logic;
+ PROGRAMN : out std_logic;
+ ENPIRION_CLOCK : out std_logic;
+ TEMPSENS : inout std_logic;
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_IN : signal is true;
+ attribute syn_useioff of FLASH_OUT : signal is true;
+
+end entity;
+
+architecture trb3sc_arch of trb3sc_gbe_hub is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys : std_logic;
+ signal clk_full : std_logic;
+ signal clk_full_osc : std_logic;
+ signal GSR_N : std_logic;
+ signal clear : std_logic;
+ signal reset_i : std_logic;
+ signal do_reboot_i : std_logic;
+ signal reset_via_gbe : std_logic;
+ signal reboot_from_gbe : std_logic;
+
+ signal ctrlbus_rx, bustools_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
+
+ signal bus_master_active : std_logic;
+
+ signal flash_ncs_i : std_logic;
+ signal flash_sclk_i : std_logic;
+ signal flash_miso_i : std_logic;
+ signal flash_mosi_i : std_logic;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal timer : TIMERS;
+ signal additional_reg : std_logic_vector(31 downto 0);
+
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_read : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+
+ signal status : std_logic_vector(15 downto 0);
+
+ ----------------------------------------------------------------
+-- signal tx_pll_lol_i : std_logic;
+-- signal tx_clk_avail_i : std_logic;
+-- signal tx_pcs_rst_i : std_logic;
+-- signal sync_tx_quad_i : std_logic;
+-- signal link_tx_ready_i : std_logic;
+-- signal link_rx_ready_i : std_logic_vector(3 downto 0);
+-- signal status_raw : std_logic_vector(31 downto 0);
+
+
+-- component gbe_med_raw is
+-- generic(
+-- LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"
+-- );
+-- port(
+-- RESET : in std_logic;
+-- GSR_N : in std_logic;
+-- CLK_SYS : in std_logic;
+-- CLK_125 : in std_logic;
+-- CLK_125_RX : out std_logic_vector(3 downto 0);
+-- -- MAC status and config
+-- MAC_READY_CONF_OUT : out std_logic_vector(3 downto 0);
+-- MAC_RECONF_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- MAC_AN_READY_OUT : out std_logic_vector(3 downto 0);
+-- -- MAC data interface
+-- MAC_FIFOAVAIL_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- MAC_FIFOEOF_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- MAC_FIFOEMPTY_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- MAC_RX_FIFOFULL_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- -- MAC TX interface
+-- MAC_TX_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0) := (others => '0');
+-- MAC_TX_READ_OUT : out std_logic_vector(3 downto 0);
+-- MAC_TX_DISCRFRM_OUT : out std_logic_vector(3 downto 0);
+-- MAC_TX_STAT_EN_OUT : out std_logic_vector(3 downto 0);
+-- MAC_TX_STATS_OUT : out std_logic_vector(4 * 31 - 1 downto 0);
+-- MAC_TX_DONE_OUT : out std_logic_vector(3 downto 0);
+-- -- MAC RX interface
+-- MAC_RX_FIFO_ERR_OUT : out std_logic_vector(3 downto 0);
+-- MAC_RX_STATS_OUT : out std_logic_vector(4 * 32 - 1 downto 0);
+-- MAC_RX_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
+-- MAC_RX_WRITE_OUT : out std_logic_vector(3 downto 0);
+-- MAC_RX_STAT_EN_OUT : out std_logic_vector(3 downto 0);
+-- MAC_RX_EOF_OUT : out std_logic_vector(3 downto 0);
+-- MAC_RX_ERROR_OUT : out std_logic_vector(3 downto 0);
+-- -- SFP Connection
+-- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- SD_LOS_IN : in std_logic_vector(3 downto 0) := (others => '0');
+-- SD_TXDIS_OUT : out std_logic_vector(3 downto 0);
+-- -- SerDes control
+-- TX_PLOL_LOL_OUT : out std_logic;
+-- TX_PCS_RST_IN : in std_logic;
+-- RX_LINK_READY_OUT : out std_logic_vector(3 downto 0);
+-- TX_LINK_READY_IN : in std_logic;
+-- -- Debug
+-- STATUS_OUT : out std_logic_vector(4 + 8 - 1 downto 0);
+-- DEBUG_OUT : out std_logic_vector(63 downto 0)
+-- );
+-- end component gbe_med_raw;
+
+-- attribute syn_noprune : boolean;
+-- attribute syn_noprune of gbe_med_raw : component is true;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ GLOBAL_RESET_IN => '0',
+ RESET_FROM_NET_IN => '0',
+ RESET_OUT => reset_i,
+ CLEAR_OUT => open,
+ GSR_OUT => GSR_N,
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => open
+ );
+
+ clear <= not GSR_N;
+
+-- SerDes usage:
+-- backplane: A0 uplink on backplane, (A1, A2, A3 unused)MOD1
+-- B0, B1, B2, B3 downlink on hub addon
+-- C0, C1, C2, C3 downlink on hub addon
+-- D0, D1 downlink on TRB3sc, (D2, D3 unused)
+-- needs PCSSW = 11100100
+--
+-- SFP: D0 uplink, (D1, D2, D3 unused)
+-- A0, A1, A2, A3 downlink on backplane
+-- B3 downlink on TRB3sc, (B0, B1, B2 unused)
+-- C0, C1, C2, C3 unused
+-- needs PCSS" = 01001110
+
+---------------------------------------------------------------------------
+-- Serdes Select
+---------------------------------------------------------------------------
+ PCSSW_ENSMB <= '0';
+ PCSSW_EQ <= x"0";
+ PCSSW_PE <= x"F";
+-- PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3
+ PCSSW <= "01001110"; -- SFP2 on TX_LINK_READY_INB3, AddOn on D1
+
+---------------------------------------------------------------------------
+-- PCSD as test point (SFP2)
+---------------------------------------------------------------------------
+ GBE : entity work.gbe_wrapper_single
+ generic map(
+ DO_SIMULATION => 0,
+ INCLUDE_DEBUG => 0,
+ USE_INTERNAL_TRBNET_DUMMY => 0,
+ USE_EXTERNAL_TRBNET_DUMMY => 0,
+ RX_PATH_ENABLE => 1,
+ FIXED_SIZE_MODE => 1,
+ INCREMENTAL_MODE => 1,
+ FIXED_SIZE => 100,
+ FIXED_DELAY_MODE => 1,
+ UP_DOWN_MODE => 0,
+ UP_DOWN_LIMIT => 100,
+ FIXED_DELAY => 100,
+
+ NUMBER_OF_GBE_LINKS => 4,
+ LINKS_ACTIVE => "0001",
+
+ LINK_HAS_READOUT => "0000",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001",
+ LINK_HAS_FWD => "0000"
+ )
+ port map(
+ CLK_SYS_IN => clk_sys,
+ CLK_125_IN => CLK_SUPPL_PCLK,
+ RESET => reset_i,
+ GSR_N => GSR_N,
+ -- Trigger
+ TRIGGER_IN => '0',
+ -- SFP
+ SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_LOS_IN(0) => SFP_LOS(0),
+ SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+ -- unique adresses
+ MC_UNIQUE_ID_IN => timer.uid,
+ MY_TRBNET_ADDRESS_IN => timer.network_address,
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+ -- slow control by GbE
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+ -- readout
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+ -- reset
+ MAKE_RESET_OUT => reset_via_gbe,
+ -- debug
+ STATUS_OUT => status,
+ DEBUG_OUT => open
+ );
+
+-------------------------------------------------------------------------------
+-- SCTRL endpoint for GbE standalone
+-------------------------------------------------------------------------------
+ THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
+ generic map(
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ APL_WRITE_ALL_WORDS => c_NO,
+ INIT_ADDRESS => INIT_ADDRESS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
+ REGIO_USE_1WIRE_INTERFACE => c_YES
+ )
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+ --Port to GbE
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+ GBE_MAKE_RESET_IN => reset_via_gbe,
+ --Slow Control Port
+ --common registers 0x00-0x2F
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_COMMON_STAT_STROBE_OUT => open,
+ REGIO_COMMON_CTRL_STROBE_OUT => open,
+ --internal data port
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ --Data port - external master (e.g. Flash or Debug)
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ --Sensors & ID
+ ONEWIRE_INOUT => TEMPSENS,
+ I2C_SCL => open,
+ I2C_SDA => open,
+ -- Generic stuff
+ TIMERS_OUT => timer,
+ MY_ADDRESS_OUT => open -- BUG?
+ );
+
+ common_stat_reg <= (others => '0');
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 8, 2 => 8, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ --
+ BUS_RX(0) => bustools_rx, -- Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => busgbeip_rx,
+ BUS_RX(2) => busgbereg_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => busgbeip_tx,
+ BUS_TX(2) => busgbereg_tx,
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.tomcat_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --Flash & Reload
+ FLASH_CS => flash_ncs_i,
+ FLASH_CLK => flash_sclk_i,
+ FLASH_IN => flash_miso_i,
+ FLASH_OUT => flash_mosi_i,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => do_reboot_i,
+ -- I2C
+ SDA_INOUT => open, --I2C_SDA,
+ SCL_INOUT => open, --SI2C_SCL,
+ -- Additional register
+ ADDITIONAL_REG => additional_reg,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+ FLASH_CS <= flash_ncs_i;
+ FLASH_CLK <= flash_sclk_i;
+ FLASH_IN <= flash_mosi_i;
+ flash_miso_i <= FLASH_OUT;
+
+ do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+ LED_GREEN <= not status(0); --'0';
+ LED_ORANGE <= not status(1); --'0';
+ LED_RED <= not status(2); --'0';
+ LED_YELLOW <= not status(5); --'0';
+
+GEN_HUB_LEDS : for i in 0 to 6 generate
+ LED_HUB_LINKOK(i+1) <= not '1';
+ LED_HUB_TX(i+1) <= not '0';
+ LED_HUB_RX(i+1) <= not '0';
+end generate;
+
+ LED_HUB_LINKOK(8) <= not '1';
+ LED_HUB_TX(8) <= not '0';
+ LED_HUB_RX(8) <= not '0';
+ LED_SFP_GREEN(0) <= not '0';
+ LED_SFP_RED(0) <= not '0';
+
+ LED_SFP_GREEN(1) <= not '0';
+ LED_SFP_RED(1) <= not '0';
+
+ LED_WHITE(1) <= not additional_reg(31); --'0';
+ LED_WHITE(0) <= not status(8); --'0';
+
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- THE_GBE_MED_RAW: gbe_med_raw
+-- generic map(
+-- LINKS_ACTIVE => "1111"
+-- )
+-- port map(
+-- RESET => reset_i,
+-- GSR_N => GSR_N,
+-- CLK_SYS => clk_sys,
+-- CLK_125 => CLK_SUPPL_PCLK,
+-- CLK_125_RX => open,
+-- -- MAC status and config
+-- MAC_READY_CONF_OUT => open,
+-- MAC_RECONF_IN => (others => '0'),
+-- MAC_AN_READY_OUT => open,
+-- -- MAC data interface
+-- MAC_FIFOAVAIL_IN => (others => '0'),
+-- MAC_FIFOEOF_IN => (others => '0'),
+-- MAC_FIFOEMPTY_IN => (others => '0'),
+-- MAC_RX_FIFOFULL_IN => (others => '0'),
+-- -- MAC TX interface
+-- MAC_TX_DATA_IN => (others => '0'),
+-- MAC_TX_READ_OUT => open,
+-- MAC_TX_DISCRFRM_OUT => open,
+-- MAC_TX_STAT_EN_OUT => open,
+-- MAC_TX_STATS_OUT => open,
+-- MAC_TX_DONE_OUT => open,
+-- -- MAC RX interface
+-- MAC_RX_FIFO_ERR_OUT => open,
+-- MAC_RX_STATS_OUT => open,
+-- MAC_RX_DATA_OUT => open,
+-- MAC_RX_WRITE_OUT => open,
+-- MAC_RX_STAT_EN_OUT => open,
+-- MAC_RX_EOF_OUT => open,
+-- MAC_RX_ERROR_OUT => open,
+-- -- SFP Connection
+-- SD_PRSNT_N_IN => HUB_MOD0(4 downto 1), --(others => '0'),
+-- SD_LOS_IN => HUB_LOS(4 downto 1), --(others => '0'),
+-- SD_TXDIS_OUT => HUB_TXDIS(4 downto 1), --open,
+-- -- SerDes control
+-- TX_PLOL_LOL_OUT => tx_pll_lol_i,
+-- TX_PCS_RST_IN => tx_pcs_rst_i,
+-- RX_LINK_READY_OUT => link_rx_ready_i,
+-- TX_LINK_READY_IN => link_tx_ready_i,
+-- -- Debug
+-- STATUS_OUT => status_raw, --open,
+-- DEBUG_OUT => open
+-- );
+
+-- LED_HUB_LINKOK(1) <= not status_raw(0 * 8 + 2);
+-- LED_HUB_RX(1) <= not status_raw(0 * 8 + 1);
+-- LED_HUB_TX(1) <= not status_raw(0 * 8 + 0);
+
+-- LED_HUB_LINKOK(2) <= not status_raw(1 * 8 + 2);
+-- LED_HUB_RX(2) <= not status_raw(1 * 8 + 1);
+-- LED_HUB_TX(2) <= not status_raw(1 * 8 + 0);
+
+-- LED_HUB_LINKOK(3) <= not status_raw(2 * 8 + 2);
+-- LED_HUB_RX(3) <= not status_raw(2 * 8 + 1);
+-- LED_HUB_TX(3) <= not status_raw(2 * 8 + 0);
+
+-- LED_HUB_LINKOK(4) <= not status_raw(3 * 8 + 2);
+-- LED_HUB_RX(4) <= not status_raw(3 * 8 + 1);
+-- LED_HUB_TX(4) <= not status_raw(3 * 8 + 0);
+
+-- -- RSL for TX of SerDes, based on extRSL logic
+-- THE_MAIN_TX_RST: main_tx_reset_RS
+-- port map (
+-- CLEAR => clear,
+-- CLK_REF => CLK_SUPPL_PCLK,
+-- TX_PLL_LOL_IN => tx_pll_lol_i,
+-- TX_CLOCK_AVAIL_IN => '1', -- not needed here
+-- TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
+-- SYNC_TX_QUAD_OUT => open, --not needed here
+-- LINK_TX_READY_OUT => link_tx_ready_i,
+-- STATE_OUT => open
+-- );
+
+end architecture;
+++ /dev/null
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-use ieee.numeric_std.all;
-use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
-
-package config is
-
-
-------------------------------------------------------------------------------
---Begin of design configuration
-------------------------------------------------------------------------------
-
---design options: backplane or front SFP, with or without GBE
- constant USE_BACKPLANE : integer := c_YES;
- constant INCLUDE_GBE : integer := c_NO;
-
---We want an ECP3
- constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
-
--- Link speed
- constant LINK_SPEED : integer := 125; -- 125: 1.25Gbps, 200: 2.00Gbps
-
---Runs with 120 MHz instead of 100 MHz
- constant USE_120_MHZ : integer := c_NO;
- constant USE_200MHZOSCILLATOR : integer := c_YES;
- constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
- constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
-
---Use sync mode, RX clock for all parts of the FPGA
- constant USE_RXCLOCK : integer := c_NO; -- DEPRECIATED
-
---Address settings
- constant INIT_ADDRESS : std_logic_vector := x"d00f";
-
- constant INCLUDE_UART : integer := c_YES;
- constant INCLUDE_SPI : integer := c_YES;
- constant INCLUDE_LCD : integer := c_NO;
- constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
-
- --input monitor and trigger generation logic
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
- constant INCLUDE_STATISTICS : integer := c_NO;
- constant TRIG_GEN_INPUT_NUM : integer := 0;
- constant TRIG_GEN_OUTPUT_NUM : integer := 0;
- constant MONITOR_INPUT_NUM : integer := 0;
-
-------------------------------------------------------------------------------
---End of design configuration
-------------------------------------------------------------------------------
-
- type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
- constant LCD_DATA : data_t := (
- x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
- x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
-
- x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a",
- x"0a",
- x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
- x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
- x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
- others => x"00");
-
-
-
---With GbE:
--- for MII_NUMBER=5 (4 downlinks, 1 uplink):
--- port 0,1,2,3: downlinks to other FPGA
--- port MII-1: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL
--- port MII: SCTRL channel on uplink to CTS
--- port MII+1: SCTRL channel from GbE interface
-
---With no GbE:
--- for MII_NUMBER=5 (4 downlinks, 1 uplink):
--- port 0,1,2,3: downlinks to other FPGA
--- port 4: uplink
--- port 5: internal endpoint on SCTRL
-
-
- type hub_mii_t is array(0 to 3) of integer;
- type hub_ct is array(0 to 16) of integer;
- type hub_cfg_t is array(0 to 3) of hub_ct;
- type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0);
- type intlist_t is array(0 to 7) of integer;
-
-
- --order: no backplane, no GBE 8x AddOn, SFP downlink, SFP uplink
- -- backplane, no GBE 8x AddOn, 2x SFP downlink, backplane uplink
- -- no backplane, GBE 7x AddOn, 1x SFP uplink, GBE sctrl
- -- backplane, GBE 8x AddOn, backplane uplink, GBE sctrl
-
- constant INTERFACE_NUM_ARR : hub_mii_t := (10,11,8,9);
--- 0 1 2 3 4 5 6 7 8 9 a b c d e f
- constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0));
- constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0,0),
- (1,1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0),
- (1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0),
- (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0));
- constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0));
-
- constant INTERFACE_NUM : integer;
- constant IS_UPLINK : hub_ct;
- constant IS_DOWNLINK : hub_ct;
- constant IS_UPLINK_ONLY : hub_ct;
-
-------------------------------------------------------------------------------
---Select settings by configuration
-------------------------------------------------------------------------------
-
- constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000";
-
- constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
- constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
-
- --declare constants, filled in body
- constant HARDWARE_INFO : std_logic_vector(31 downto 0);
- constant CLOCK_FREQUENCY : integer;
- constant MEDIA_FREQUENCY : integer;
- constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
- constant BROADCAST_SPECIAL_ADDR : std_logic_vector;
-
-end;
-
-package body config is
---compute correct configuration mode
-
- constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
- HW_INFO_BASE );
- constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
- constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
-
- constant CFG_MODE : integer := INCLUDE_GBE*2 + USE_BACKPLANE;
-
- constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
- constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
- constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
- constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
- constant BROADCAST_SPECIAL_ADDR : std_logic_vector := std_logic_vector(to_unsigned(100+CFG_MODE,8));
-
-
-function generateIncludedFeatures return std_logic_vector is
- variable t : std_logic_vector(63 downto 0);
- begin
- t := (others => '0');
- t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
- if INCLUDE_GBE = c_YES then
- t(22 downto 16) := "0100111"; --sctrl via GbE
- end if;
- t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
- t(27 downto 24) := std_logic_vector(to_unsigned(INTERFACE_NUM-USE_BACKPLANE,4)); --num SFPs with TrbNet
- t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1));
- t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
- t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
- t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
- t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
- t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
- t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
- t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
- t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
- t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
- return t;
- end function;
-
- constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
-
-end package body;
+++ /dev/null
-# locate the PCS blocks
-LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSA";
-LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST" SITE "PCSC";
-LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSD";
-LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
-
-# locate the media interfaces inside fabric
-REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB
-REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC
-LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_RIGHT";
-LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT";
-LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT";
-LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_RIGHT";
-LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_LEFT";
-
-# primary nets
-USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]";
-USE PRIMARY NET "THE_MEDIA_4_PCSC/clk_rx_full[0]";
-USE PRIMARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[0]";
-
-# secondary nets
-USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[1]";
-USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[2]";
-USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[3]";
-USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[1]";
-USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[2]";
-USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[3]";
-USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]";
-
-# read from SCI can be delayed due to long read strobe
-# write strobe can be delayed due to A/D being stable after access
-MULTICYCLE FROM ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-MULTICYCLE FROM ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-MULTICYCLE FROM ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIWSTN 15 ns;
-MULTICYCLE FROM ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-
-################################
-
-FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
-FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.version.all;
-use work.config.all;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.trb_net16_hub_func.all;
-use work.version.all;
-use work.trb_net_gbe_components.all;
-use work.med_sync_define_RS.all;
-
-entity trb3sc_gbe_hub is
- port(
- CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
- CLK_CORE_PCLK : in std_logic; --Main Oscillator
- CLK_EXT_PLL_LEFT : in std_logic; --External Clock
- --Additional IO
--- HDR_IO : inout std_logic_vector(10 downto 1);
- BACK_LVDS : inout std_logic_vector( 1 downto 0);
- BACK_GPIO : inout std_logic_vector( 3 downto 0);
- --LED
- LED_GREEN : out std_logic;
- LED_YELLOW : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_RJ_GREEN : out std_logic_vector( 1 downto 0);
- LED_RJ_RED : out std_logic_vector( 1 downto 0);
- LED_WHITE : out std_logic_vector( 1 downto 0);
- LED_SFP_GREEN : out std_logic_vector( 1 downto 0);
- LED_SFP_RED : out std_logic_vector( 1 downto 0);
- --SFP
- SFP_LOS : in std_logic_vector( 1 downto 0);
- SFP_MOD0 : in std_logic_vector( 1 downto 0);
- SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
- SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
- SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
- LED_HUB_LINKOK : out std_logic_vector(8 downto 1);
- LED_HUB_RX : out std_logic_vector(8 downto 1);
- LED_HUB_TX : out std_logic_vector(8 downto 1);
- HUB_MOD0 : in std_logic_vector(8 downto 1);
- HUB_MOD1 : inout std_logic_vector(8 downto 1);
- HUB_MOD2 : inout std_logic_vector(8 downto 1);
- HUB_TXDIS : out std_logic_vector(8 downto 1);
- HUB_LOS : in std_logic_vector(8 downto 1);
- --Serdes switch
- PCSSW_ENSMB : out std_logic;
- PCSSW_EQ : out std_logic_vector( 3 downto 0);
- PCSSW_PE : out std_logic_vector( 3 downto 0);
- PCSSW : out std_logic_vector( 7 downto 0);
- --ADC
- ADC_CLK : out std_logic;
- ADC_CS : out std_logic;
- ADC_DIN : out std_logic;
- ADC_DOUT : in std_logic;
- --Flash, 1-wire, Reload
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_IN : out std_logic;
- FLASH_OUT : in std_logic;
- PROGRAMN : out std_logic;
- ENPIRION_CLOCK : out std_logic;
- TEMPSENS : inout std_logic
- --Test Connectors
--- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_IN : signal is true;
- attribute syn_useioff of FLASH_OUT : signal is true;
-
-end entity;
-
-architecture trb3sc_arch of trb3sc_gbe_hub is
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- signal clk_sys, clk_full, clk_full_osc : std_logic;
- signal GSR_N : std_logic;
- signal reset_i : std_logic;
- signal do_reboot_i, reboot_from_gbe : std_logic;
- signal external_reset_i : std_logic;
-
- signal time_counter : unsigned(31 downto 0) := (others => '0');
- signal led : std_logic_vector(1 downto 0);
- signal debug_clock_reset : std_logic_vector(31 downto 0);
-
- --Media Interface
- signal med2int : med2int_array_t(0 to 10);
- signal int2med : int2med_array_t(0 to 10);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
-
- signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx,
- bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx,
- bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
-
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-
- signal sed_error_i : std_logic;
- signal bus_master_active : std_logic;
-
- signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
- signal uart_tx, uart_rx : std_logic;
-
- signal timer : TIMERS;
- signal lcd_data : std_logic_vector(511 downto 0);
-
- signal cts_number : std_logic_vector(15 downto 0);
- signal cts_code : std_logic_vector(7 downto 0);
- signal cts_information : std_logic_vector(7 downto 0);
- signal cts_start_readout : std_logic;
- signal cts_readout_type : std_logic_vector(3 downto 0);
- signal cts_data : std_logic_vector(31 downto 0);
- signal cts_dataready : std_logic;
- signal cts_readout_finished : std_logic;
- signal cts_read : std_logic;
- signal cts_length : std_logic_vector(15 downto 0);
- signal cts_status_bits : std_logic_vector(31 downto 0);
- signal fee_data : std_logic_vector(15 downto 0);
- signal fee_dataready : std_logic;
- signal fee_read : std_logic;
- signal fee_status_bits : std_logic_vector(31 downto 0);
- signal fee_busy : std_logic;
- signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
- signal gsc_init_read, gsc_reply_read : std_logic;
- signal gsc_init_dataready, gsc_reply_dataready : std_logic;
- signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
- signal gsc_busy : std_logic;
- signal my_address : std_logic_vector(15 downto 0);
- signal mc_unique_id : std_logic_vector(63 downto 0);
- signal reset_via_gbe : std_logic := '0';
-
- signal med_dataready_out : std_logic_vector (11-1 downto 0);
- signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0);
- signal med_read_in : std_logic_vector (11-1 downto 0);
- signal med_dataready_in : std_logic_vector (11-1 downto 0);
- signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0);
- signal med_read_out : std_logic_vector (11-1 downto 0);
- signal med_stat_op : std_logic_vector (11*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (11*16-1 downto 0);
- signal rdack, wrack : std_logic;
-
- signal trig_gen_out_i : std_logic_vector(3 downto 0);
- signal monitor_inputs_i : std_logic_vector(17 downto 0);
-
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- attribute syn_keep of bussci1_rx : signal is true;
- attribute syn_preserve of bussci1_rx : signal is true;
- attribute syn_keep of bustools_rx : signal is true;
- attribute syn_preserve of bustools_rx : signal is true;
- attribute syn_keep of bustc_rx : signal is true;
- attribute syn_preserve of bustc_rx : signal is true;
-
- signal word_sync_i : std_logic;
- signal master_clk_i : std_logic;
- signal global_reset_i : std_logic;
- signal tx_pll_lol_qd_a_i : std_logic;
- signal tx_pll_lol_qd_b_i : std_logic;
- signal tx_pll_lol_qd_c_i : std_logic;
- signal tx_pll_lol_qd_d_i : std_logic;
- signal tx_clk_avail_i : std_logic;
- signal tx_pcs_rst_i : std_logic;
- signal sync_tx_quad_i : std_logic;
- signal link_tx_ready_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_reset_state : std_logic_vector(3 downto 0);
- signal debug_i : std_logic_vector(31 downto 0);
-
- signal send_rst_i : std_logic;
- signal send_rst_word_i : std_logic_vector(7 downto 0);
- signal send_dlm_word_i : std_logic_vector(7 downto 0);
-
- signal init_quad : std_logic;
- signal link_clock : std_logic;
-
-begin
----------------------------------------------------------------------------
--- Clock & Reset Handling
----------------------------------------------------------------------------
-THE_CLOCK_RESET : entity work.clock_reset_handler
- port map(
- INT_CLK_IN => CLK_CORE_PCLK,
- EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full,
- NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half,
- GLOBAL_RESET_IN => global_reset_i,
- RESET_FROM_NET_IN => '0',
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
- RESET_OUT => reset_i,
- CLEAR_OUT => open,
- GSR_OUT => GSR_N,
- FULL_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- REF_CLK_OUT => clk_full_osc,
- ENPIRION_CLOCK => ENPIRION_CLOCK,
- LED_RED_OUT => LED_RJ_RED,
- LED_GREEN_OUT => LED_RJ_GREEN,
- DEBUG_OUT => debug_clock_reset
- );
-
- init_quad <= not GSR_N;
-
- -- select link speed, wrong values are catched in media interface
- link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else
- clk_full_osc when (LINK_SPEED = 200) else
- '0';
-
----------------------------------------------------------------------------
--- PCSA: Uplink when backplane is used
----------------------------------------------------------------------------
-gen_PCSA : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS
- generic map(
- IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED)
- )
- port map(
- -- Clocks and reset
- CLK_REF_FULL => CLK_SUPPL_PCLK,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => init_quad,
- -- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(INTERFACE_NUM-1),
- MEDIA_MED2INT(1 to 3) => open,
- MEDIA_INT2MED(0) => int2med(INTERFACE_NUM-1),
- MEDIA_INT2MED(1 to 3) => open,
- -- komma operation
- RX_DLM_OUT(3 downto 1) => open,
- RX_DLM_OUT(0) => rx_dlm_i,
- RX_DLM_WORD_OUT(31 downto 8) => open,
- RX_DLM_WORD_OUT(7 downto 0) => send_dlm_word_i,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => send_rst_i,
- RX_RST_WORD_OUT => send_rst_word_i,
- TX_RST_IN => '0',
- TX_RST_WORD_IN => x"00",
- -- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => master_clk_i,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => global_reset_i,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
- --SFP Connection
- SD_PRSNT_N_IN(0) => BACK_GPIO(1),
- SD_PRSNT_N_IN(3 downto 1) => (others => '1'),
- SD_LOS_IN(0) => BACK_GPIO(1),
- SD_LOS_IN(3 downto 1) => (others => '1'),
- SD_TXDIS_OUT(0) => BACK_GPIO(0),
- SD_TXDIS_OUT(3 downto 1) => open,
- --Control Interface
- BUS_RX => bussci1_rx,
- BUS_TX => bussci1_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
- );
-end generate;
-
----------------------------------------------------------------------------
--- PCSB: TrbNet downlinks (backplane)
----------------------------------------------------------------------------
-gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
- generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER)
- )
- port map(
- -- Clocks and reset
- CLK_REF_FULL => link_clock,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => init_quad,
- -- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
- -- komma operation
- RX_DLM_OUT(0) => open,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => open,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => open,
- RX_RST_WORD_OUT => open,
- TX_RST_IN => send_rst_i,
- TX_RST_WORD_IN => send_rst_word_i,
- -- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => open,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => open,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => open,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
- TX_CLK_AVAIL_OUT => open,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
- --SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
- --Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => open
- );
-end generate;
-
----------------------------------------------------------------------------
--- PCSB: TrbNet one uplink and three downlinks (no backplane)
----------------------------------------------------------------------------
-gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
- generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE)
- )
- port map(
- -- Clocks and reset
- CLK_REF_FULL => link_clock,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => init_quad,
- -- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
- -- komma operation
- RX_DLM_OUT(0) => open,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => rx_dlm_i,
- RX_DLM_WORD_OUT(23 downto 0) => open,
- RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => send_rst_i,
- RX_RST_WORD_OUT => send_rst_word_i,
- TX_RST_IN => send_rst_i,
- TX_RST_WORD_IN => send_rst_word_i,
- -- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => master_clk_i,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => global_reset_i,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
- --SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
- --Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => open
- );
-
- tx_pll_lol_qd_a_i <= '0';
-
-end generate;
-
- THE_MAIN_TX_RST: main_tx_reset_RS
- port map (
- CLEAR => init_quad,
- CLK_REF => link_clock,
- TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i,
- TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
- TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i,
- TX_PLL_LOL_QD_D_IN => tx_pll_lol_qd_d_i,
- TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
- TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
- SYNC_TX_QUAD_OUT => sync_tx_quad_i,
- LINK_TX_READY_OUT => link_tx_ready_i,
- STATE_OUT => tx_reset_state
- );
-
----------------------------------------------------------------------------
--- PCSC: 4 downlinks
----------------------------------------------------------------------------
- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS
- generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER)
- )
- port map(
- -- Clocks and reset
- CLK_REF_FULL => link_clock,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => init_quad,
- -- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(2),
- MEDIA_MED2INT(1) => med2int(3),
- MEDIA_MED2INT(2) => med2int(0),
- MEDIA_MED2INT(3) => med2int(1),
- MEDIA_INT2MED(0) => int2med(2),
- MEDIA_INT2MED(1) => int2med(3),
- MEDIA_INT2MED(2) => int2med(0),
- MEDIA_INT2MED(3) => int2med(1),
- -- komma operation
- RX_DLM_OUT => open,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => open,
- RX_RST_WORD_OUT => open,
- TX_RST_IN => send_rst_i,
- TX_RST_WORD_IN => send_rst_word_i,
- -- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => open,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => open,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => open,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i,
- TX_CLK_AVAIL_OUT => open,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
- --SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(3),
- SD_PRSNT_N_IN(1) => HUB_MOD0(4),
- SD_PRSNT_N_IN(2) => HUB_MOD0(1),
- SD_PRSNT_N_IN(3) => HUB_MOD0(2),
- SD_LOS_IN(0) => HUB_LOS(3),
- SD_LOS_IN(1) => HUB_LOS(4),
- SD_LOS_IN(2) => HUB_LOS(1),
- SD_LOS_IN(3) => HUB_LOS(2),
- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
- --Control Interface
- BUS_RX => bussci3_rx,
- BUS_TX => bussci3_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => open
- );
-
----------------------------------------------------------------------------
--- PCSD: 2 downlinks (no GbE)
----------------------------------------------------------------------------
-gen_PCSD : if INCLUDE_GBE = c_NO generate
- THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS
- generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED)
- )
- port map(
- -- Clocks and reset
- CLK_REF_FULL => link_clock,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => init_quad,
- -- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(8),
- MEDIA_MED2INT(1) => med2int(7),
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => open,
- MEDIA_INT2MED(0) => int2med(8),
- MEDIA_INT2MED(1) => int2med(7),
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => open,
- -- komma operation
- RX_DLM_OUT => open,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => open,
- RX_RST_WORD_OUT => open,
- TX_RST_IN => send_rst_i,
- TX_RST_WORD_IN => send_rst_word_i,
- -- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => open,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => open,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => open,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i,
- TX_CLK_AVAIL_OUT => open,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
- --SFP Connection
- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
- SD_PRSNT_N_IN(1) => HUB_MOD0(8),
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => '1',
- SD_LOS_IN(0) => SFP_LOS(0),
- SD_LOS_IN(1) => HUB_LOS(8),
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
- SD_TXDIS_OUT(1) => HUB_TXDIS(8),
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
- --Control Interface
- BUS_RX => bussci4_rx,
- BUS_TX => bussci4_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => open
- );
-end generate;
-
----------------------------------------------------------------------------
--- GbE
----------------------------------------------------------------------------
-gen_noGBE : if INCLUDE_GBE = c_NO generate
- gsc_reply_read <= '1';
- gsc_init_dataready <= '0';
- busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write;
- busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write;
-end generate;
-
----------------------------------------------------------------------------
--- PCSD: GbE
----------------------------------------------------------------------------
-gen_GBE : if INCLUDE_GBE = c_YES generate
- GBE : entity work.gbe_wrapper
- generic map(
- DO_SIMULATION => 0,
- INCLUDE_DEBUG => 0,
- USE_INTERNAL_TRBNET_DUMMY => 0,
- USE_EXTERNAL_TRBNET_DUMMY => 0,
- RX_PATH_ENABLE => 1,
- FIXED_SIZE_MODE => 1,
- INCREMENTAL_MODE => 1,
- FIXED_SIZE => 100,
- FIXED_DELAY_MODE => 1,
- UP_DOWN_MODE => 0,
- UP_DOWN_LIMIT => 100,
- FIXED_DELAY => 100,
-
- NUMBER_OF_GBE_LINKS => 4,
- LINKS_ACTIVE => "0001",
-
- LINK_HAS_READOUT => "0001",
- LINK_HAS_SLOWCTRL => "0001",
- LINK_HAS_DHCP => "0001",
- LINK_HAS_ARP => "0001",
- LINK_HAS_PING => "0001"
- )
- port map(
- CLK_SYS_IN => clk_sys,
- CLK_125_IN => CLK_SUPPL_PCLK,
- RESET => reset_i,
- GSR_N => GSR_N,
- --
- TRIGGER_IN => '0',
- --
- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
- SD_PRSNT_N_IN(3 downto 1) => "111",
- SD_LOS_IN(0) => SFP_LOS(0),
- SD_LOS_IN(3 downto 1) => "111",
- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
- --
- CTS_NUMBER_IN => cts_number,
- CTS_CODE_IN => cts_code,
- CTS_INFORMATION_IN => cts_information,
- CTS_READOUT_TYPE_IN => cts_readout_type,
- CTS_START_READOUT_IN => cts_start_readout,
- CTS_DATA_OUT => cts_data,
- CTS_DATAREADY_OUT => cts_dataready,
- CTS_READOUT_FINISHED_OUT => cts_readout_finished,
- CTS_READ_IN => cts_read,
- CTS_LENGTH_OUT => cts_length,
- CTS_ERROR_PATTERN_OUT => cts_status_bits,
- --
- FEE_DATA_IN => fee_data,
- FEE_DATAREADY_IN => fee_dataready,
- FEE_READ_OUT => fee_read,
- FEE_STATUS_BITS_IN => fee_status_bits,
- FEE_BUSY_IN => fee_busy,
- --
- MC_UNIQUE_ID_IN => mc_unique_id,
- MY_TRBNET_ADDRESS_IN => my_address,
- ISSUE_REBOOT_OUT => reboot_from_gbe,
- --
- GSC_CLK_IN => clk_sys,
- GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
- GSC_INIT_DATA_OUT => gsc_init_data,
- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
- GSC_INIT_READ_IN => gsc_init_read,
- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
- GSC_REPLY_DATA_IN => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
- GSC_REPLY_READ_OUT => gsc_reply_read,
- GSC_BUSY_IN => gsc_busy,
- --
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
- --
- MAKE_RESET_OUT => reset_via_gbe,
- --
- DEBUG_OUT => open
- );
-end generate;
-
----------------------------------------------------------------------------
--- Hub
----------------------------------------------------------------------------
-gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate
- THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
- generic map(
- HUB_USED_CHANNELS => (1,1,0,1),
- INIT_ADDRESS => INIT_ADDRESS,
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => IS_UPLINK,
- MII_IS_DOWNLINK => IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
- USE_ONEWIRE => c_YES,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- INIT_ENDPOINT_ID => x"0001",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
- )
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
- --Media interfacces
- MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1),
- MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1),
- --Event information coming from CTSCTS_READOUT_TYPE_OUT
- CTS_NUMBER_OUT => cts_number,
- CTS_CODE_OUT => cts_code,
- CTS_INFORMATION_OUT => cts_information,
- CTS_READOUT_TYPE_OUT => cts_readout_type,
- CTS_START_READOUT_OUT => cts_start_readout,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN => cts_data,
- CTS_DATAREADY_IN => cts_dataready,
- CTS_READOUT_FINISHED_IN => cts_readout_finished,
- CTS_READ_OUT => cts_read,
- CTS_LENGTH_IN => cts_length,
- CTS_STATUS_BITS_IN => cts_status_bits,
- -- Data from Frontends
- FEE_DATA_OUT => fee_data,
- FEE_DATAREADY_OUT => fee_dataready,
- FEE_READ_IN => fee_read,
- FEE_STATUS_BITS_OUT => fee_status_bits,
- FEE_BUSY_OUT => fee_busy,
- MY_ADDRESS_IN => my_address,
- COMMON_STAT_REGS => common_stat_reg, --open,
- COMMON_CTRL_REGS => common_ctrl_reg, --open,
- ONEWIRE => TEMPSENS,
- MY_ADDRESS_OUT => my_address,
- UNIQUE_ID_OUT => mc_unique_id,
- EXTERNAL_SEND_RESET => external_reset_i,
- --
- BUS_RX => ctrlbus_rx,
- BUS_TX => ctrlbus_tx,
- TIMER => timer,
- --Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
- --status and control ports
- HUB_STAT_CHANNEL => open,
- HUB_STAT_GEN => open,
- MPLEX_CTRL => (others => '0'),
- MPLEX_STAT => open,
- STAT_REGS => open,
- STAT_CTRL_REGS => open,
- --Fixed status and control ports
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
- external_reset_i <= reset_via_gbe;
-end generate;
-
-
-gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate
- THE_HUB : trb_net16_hub_base
- generic map(
- HUB_USED_CHANNELS => (1,1,0,1),
- INIT_ADDRESS => INIT_ADDRESS,
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => IS_UPLINK,
- MII_IS_DOWNLINK => IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
- USE_ONEWIRE => c_YES,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- INIT_ENDPOINT_ID => x"0001",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
- )
- port map (
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0),
- MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0),
- MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0),
- MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0),
- MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0),
- MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0),
- MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0),
- MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0),
- MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0),
- MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0),
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => my_address,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => ctrlbus_rx.addr,
- REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
- REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
- REGIO_DATA_OUT => ctrlbus_rx.data,
- REGIO_DATA_IN => ctrlbus_tx.data,
- REGIO_DATAREADY_IN => rdack,
- REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
- REGIO_WRITE_ACK_IN => wrack,
- REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
- REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
-
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
-
- gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
- med_data_in(i*16+15 downto i*16) <= med2int(i).data;
- med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num;
- med_dataready_in(i) <= med2int(i).dataready;
- med_read_in(i) <= med2int(i).tx_read;
- med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op;
-
- int2med(i).data <= med_data_out(i*16+15 downto i*16);
- int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3);
- int2med(i).dataready <= med_dataready_out(i);
- int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16);
- end generate;
-
- rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;
- wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;
-
-end generate;
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
- generic map(
- PORT_NUMBER => 8,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"8100", 7 => x"8300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 8, 7 => 8, others => 0),
- PORT_MASK_ENABLE => 1
- )
- port map(
- CLK => clk_sys,
- RESET => reset_i,
-
- REGIO_RX => handlerbus_rx,
- REGIO_TX => ctrlbus_tx,
-
- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bustc_rx, --Clock switch
- BUS_RX(2) => bussci1_rx, --SCI Serdes
- BUS_RX(3) => bussci2_rx,
- BUS_RX(4) => bussci3_rx,
- BUS_RX(5) => bussci4_rx,
- BUS_RX(6) => busgbeip_rx,
- BUS_RX(7) => busgbereg_rx,
- BUS_TX(0) => bustools_tx,
- BUS_TX(1) => bustc_tx,
- BUS_TX(2) => bussci1_tx,
- BUS_TX(3) => bussci2_tx,
- BUS_TX(4) => bussci3_tx,
- BUS_TX(5) => bussci4_tx,
- BUS_TX(6) => busgbeip_tx,
- BUS_TX(7) => busgbereg_tx,
- STAT_DEBUG => open
- );
-
- handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
-
----------------------------------------------------------------------------
--- Control Tools
----------------------------------------------------------------------------
- THE_TOOLS: entity work.trb3sc_tools
- port map(
- CLK => clk_sys,
- RESET => reset_i,
-
- --Flash & Reload
- FLASH_CS => FLASH_CS,
- FLASH_CLK => FLASH_CLK,
- FLASH_IN => FLASH_OUT,
- FLASH_OUT => FLASH_IN,
- PROGRAMN => PROGRAMN,
- REBOOT_IN => do_reboot_i,
- --SPI
- SPI_CS_OUT => spi_cs,
- SPI_MOSI_OUT=> spi_mosi,
- SPI_MISO_IN => spi_miso,
- SPI_CLK_OUT => spi_clk,
- --Header
- HEADER_IO => open, --HDR_IO,
- --LCD
- LCD_DATA_IN => open,
- --ADC
- ADC_CS => ADC_CS,
- ADC_MOSI => ADC_DIN,
- ADC_MISO => ADC_DOUT,
- ADC_CLK => ADC_CLK,
- --Trigger & Monitor
- MONITOR_INPUTS => open,
- TRIG_GEN_INPUTS => open,
- TRIG_GEN_OUTPUTS => open,
- --SED
- SED_ERROR_OUT => sed_error_i,
- --Slowcontrol
- BUS_RX => bustools_rx,
- BUS_TX => bustools_tx,
- --Control master for default settings
- BUS_MASTER_IN => ctrlbus_tx,
- BUS_MASTER_OUT => bus_master_out,
- BUS_MASTER_ACTIVE => bus_master_active,
- DEBUG_OUT => open
- );
-
-gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate
- do_reboot_i <= common_ctrl_reg(15);
-end generate;
-gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate
- do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
-end generate;
-
-
----------------------------------------------------------------------------
--- Switchesadding signal probes
----------------------------------------------------------------------------
---Serdes Select
- PCSSW_ENSMB <= '0';
- PCSSW_EQ <= x"0";
- PCSSW_PE <= x"F";
- PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
- LED_GREEN <= not debug_i(0 + 3); -- LFD --debug_clock_reset(0);
- LED_ORANGE <= not debug_i(0 + 2); -- LHD --debug_clock_reset(1);
- LED_RED <= not debug_i(0 + 1); -- LRR --not sed_error_i;
- LED_YELLOW <= not debug_i(0 + 0); -- LTR --debug_clock_reset(2);
-
-gen_hub_leds : for i in 0 to 6 generate
- LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9);
- LED_HUB_TX(i+1) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9));
- LED_HUB_RX(i+1) <= not (med2int(i).stat_op(11));
-end generate;
-
- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = c_NO else
- '1';
- LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = c_NO else
- '1';
- LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = c_NO else
- '1';
- LED_SFP_GREEN(0) <= not med2int(8).stat_op(9) when INCLUDE_GBE = c_NO else
- '1';
- LED_SFP_RED(0) <= not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = c_NO else
- '1';
-
- LED_SFP_GREEN(1) <= not med2int(9).stat_op(9) when INCLUDE_GBE = c_NO else
- not med2int(7).stat_op(9);
- LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9)) when INCLUDE_GBE = c_NO else
- not (med2int(7).stat_op(10) or med2int(7).stat_op(11) or not med2int(7).stat_op(9));
-
- LED_WHITE(1) <= not send_dlm_word_i(7);
- LED_WHITE(0) <= not send_rst_word_i(0);
-
-end architecture;
-
-
-
jspc29 / trb3sc.git / commitdiff