trb_slv_clock => clk,
fast_clk => fast_clk,
reset => reset,
- hitbus => hbus_from_mupix_fast_sync,
- szintillator_trigger => szintilator_fast_sync,
+ hitbus => hbus_from_mupix_sync,
+ hitbus_fast => hbus_from_mupix_fast_sync,
+ szintillator_trigger => szintilator_sync,
+ szintillator_trigger_fast => szintilator_fast_sync,
SLV_READ_IN => slv_read(8),
SLV_WRITE_IN => slv_write(8),
SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),
clk : in std_logic;
reset : in std_logic;
hitbus : in std_logic;
- hitbus_timeout : in std_logic_vector(31 downto 0);
+ hitbus_timeout : in std_logic_vector(15 downto 0);
szintillator_trigger : in std_logic;
readyToWrite : in std_logic;
measurementFinished : out std_logic;
signal_synchro: process (clk) is
begin -- process clk
if rising_edge(clk) then
- hitbus_edge <= hitbus_edge(0) & hitbus_delayed;
- szintillator_trigger_buffer <= szintillator_trigger;
- szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer;
+ if reset = '1' then
+ hitbus_edge <= (others => '0');
+ szintillator_trigger_edge <= (others => '0');
+ else
+ hitbus_edge <= hitbus_edge(0) & hitbus_delayed;
+ szintillator_trigger_buffer <= szintillator_trigger;
+ szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer;
+ end if;
end if;
end process signal_synchro;
TimeWalk_Measurement : process (clk) is
begin -- process TimeWalk_Measurement
if rising_edge(clk) then
- measurementFinished <= '0';
- measurementData <= (others => '0');
- case timewalk_fsm is
- when idle =>
- latencycounter <= (others => '0');
- hitbuscounter <= (others => '0');
- if szintillator_trigger_edge = "01" then
- timewalk_fsm <= waitforhitbus;
- end if;
- when waitforhitbus =>
- latencycounter <= latencycounter + 1;
- if latencycounter = unsigned(hitbus_timeout(15 downto 0)) then
- timewalk_fsm <= idle;
- elsif hitbus_edge = "01" then
- timewalk_fsm <= measurehitbus;
- else
- timewalk_fsm <= waitforhitbus;
- end if;
- when measurehitbus =>
- if hitbus_edge = "00" then
- timewalk_fsm <= measurement_done;
- else
- hitbuscounter <= hitbuscounter + 1;
- timewalk_fsm <= measurehitbus;
- end if;
- when measurement_done =>
- timewalk_fsm <= idle;
- if readyToWrite = '1' then
- measurementData <= std_logic_vector(latencycounter & hitbuscounter);
- measurementFinished <= '1';
- end if;
- end case;
+ if reset = '1' then
+ timewalk_fsm <= idle;
+ else
+ measurementFinished <= '0';
+ measurementData <= (others => '0');
+ case timewalk_fsm is
+ when idle =>
+ latencycounter <= (others => '0');
+ hitbuscounter <= (others => '0');
+ if szintillator_trigger_edge = "01" then
+ timewalk_fsm <= waitforhitbus;
+ else
+ timewalk_fsm <= idle;
+ end if;
+ when waitforhitbus =>
+ latencycounter <= latencycounter + 1;
+ if hitbus_edge = "01" then
+ timewalk_fsm <= measurehitbus;
+ elsif latencycounter = unsigned(hitbus_timeout) then
+ timewalk_fsm <= idle;
+ else
+ timewalk_fsm <= waitforhitbus;
+ end if;
+ when measurehitbus =>
+ hitbuscounter <= hitbuscounter + 1;
+ if hitbus_edge = "10" then
+ timewalk_fsm <= measurement_done;
+ else
+ timewalk_fsm <= measurehitbus;
+ end if;
+ when measurement_done =>
+ timewalk_fsm <= idle;
+ if readyToWrite = '1' then
+ measurementData <= std_logic_vector(latencycounter & hitbuscounter);
+ measurementFinished <= '1';
+ end if;
+ end case;
+ end if;
end if;
end process TimeWalk_Measurement;
fast_clk : in std_logic; -- fast clock samples hitbus and szintilator
reset : in std_logic;
hitbus : in std_logic;
+ hitbus_fast : in std_logic;
szintillator_trigger : in std_logic;
+ szintillator_trigger_fast : in std_logic;
-- trb slowcontrol
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
architecture TimeWalk_arch of TimeWalkWithFiFo is
constant bitsBeforeWriteCounter : integer := 2;
- signal hitbus_timeout : std_logic_vector(31 downto 0) := x"00000024";
+ signal hitbus_timeout : std_logic_vector(15 downto 0) := x"0024";
signal resetcounters : std_logic := '0';
signal hitbusEdgeCounter : unsigned(31 downto 0) := (others => '0');
signal szintilatorEdgeCounter : unsigned(31 downto 0) := (others => '0');
signal hitbusRisingEdge : std_logic_vector(1 downto 0) := (others => '0');
signal szintilatorRisingEdge : std_logic_vector(1 downto 0) := (others => '0');
- signal hitbus_buffer : std_logic := '0';
- signal szintilator_trigger_buffer : std_logic := '0';
signal FiFo_Wren : std_logic := '0';
signal FiFo_data_in : std_logic_vector(31 downto 0) := (others => '0');
port map (
clk => fast_clk,
reset => reset,
- hitbus => hitbus,
+ hitbus => hitbus_fast,
hitbus_timeout => hitbus_timeout,
- szintillator_trigger => szintillator_trigger,
+ szintillator_trigger => szintillator_trigger_fast,
readyToWrite => not FiFo_full,
measurementFinished => FiFo_Wren,
measurementData => FiFo_data_in);
edge_counter: process (trb_slv_clock) is
begin -- process edge_counter
if rising_edge(trb_slv_clock) then
- hitbus_buffer <= hitbus;
- szintilator_trigger_buffer <= szintillator_trigger;
- hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus_buffer;
- szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintilator_trigger_buffer;
+ hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus;
+ szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintillator_trigger;
if resetcounters = '1' then
szintilatorEdgeCounter <= (others => '0');
hitbusEdgeCounter <= (others => '0');
elsif slv_write_in = '1' then
case SLV_ADDR_IN is
when x"0403" =>
- hitbus_timeout <= slv_data_in;
+ hitbus_timeout <= slv_data_in(15 downto 0);
slv_ack_out <= '1';
when x"0406" =>
resetcounters <= slv_data_in(0);
fifo_start_read <= '1';
fifo_reading_s <= '1';
when x"0403" =>
- slv_data_out <= hitbus_timeout;
+ slv_data_out(15 downto 0) <= hitbus_timeout;
slv_ack_out <= '1';
when x"0404" =>
slv_data_out <= szintilatorEdgeCounter;
component TimeWalkWithFiFo is
port (
trb_slv_clock : in std_logic;
- fast_clk : in std_logic;
+ fast_clk : in std_logic; -- fast clock samples hitbus and szintilator
reset : in std_logic;
hitbus : in std_logic;
+ hitbus_fast : in std_logic;
szintillator_trigger : in std_logic;
+ szintillator_trigger_fast : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
clk : in std_logic;
reset : in std_logic;
hitbus : in std_logic;
- hitbus_timeout : in std_logic_vector(31 downto 0);
+ hitbus_timeout : in std_logic_vector(15 downto 0);
szintillator_trigger : in std_logic;
readyToWrite : in std_logic;
measurementFinished : out std_logic;
jspc29 / trb3.git / commitdiff