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-\subsection{Memory Map}
+%\subsection{Memory Map}
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-\subsubsection{Trigger Control Registers, Trigger Logic}
+\subsubsection{CTS Control Registers}
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For all registers described in this subsection refer to the Fig.\ref{cts_logic}
-To enable trigger box logic which is described in this subsection (Fig.\ref{cts_logic})
-it is necessary to set register A0C5 to 40000000.
+
\begin{description}
- \item [0xA089: Debug] Trigger logic debug out
- \item [0xA09B -- 0xA0BA: Scaler] Scalers out
- \item [0xA0CC: Input enable] Individual bits are enabling inputs
- \item [0xA0CD -- 0xA0CE: Downscale] Downscales the input signals, each input signal is downscaled by $2^{value}$
- \item [0xA0D1 -- 0xA0D4: Delay] Delay input signals, each nibble corresponds to one input e.g. 0xA0D1(3 to 0) corresponds to first input of the start part (Start 0). Delay value = 4 bit value * clock period (5ns)
- \item [0xA0D6 -- 0xA0D8] Set width = value*clock period
- \item [0xA0D9] Bits 12 downto 0 - TS gating disable
- \item [0xA0DA: Trigger output] Bits 14 downto 0 - trigger out enable
- \item [0xA0DB: Output select] Bits 6 downto 0 is selecting multiplexer output for ADO TTL(1) line and 14 down to 8 for ADO TTL(2):
- \begin{description}
- \item [31 -- 0] delayed signals
- \item [46 -- 32] pti $and$ gts out
- \item [47] lvl1 trigger
- \item [48] Start and Veto antycoincidence
- \item [49] Veto set width out
- \item [50] Start downscaled in
- \item [51] LVL1 busy
- \item [52] OR out
- \item [53] Start downscaled out
- \item [54] Veto downscaled out
- \item [63 - 55] Multiplicity out
- \end{description}
- \item [0xA0DC] Different settings:
+ \item [0xA0C0] LVL1 trigger settings:
\begin{description}
\item[Bit 4 -- 0] If (4)=0 then standard trigger selection else trigger code = (3 downto 0)
\item[Bit 5] MDC calibration trigger enable
\item[Bit 6] Force update Shower pedestals trigger (write ..1..0)
\item[Bit 7] Disable Shower pedestals update (generated once during each spill off)
- \item[Bit 11 -- 8] Select frequency for internally generated trigger - $781.25kHz/(2^{value})$.
- \item[Bit 12] Enable Shower calibration trigger
- \item[Bit 13] Enable trigger from internal generator
- \item[Bit 28 -- 24] MDC delay trigger. $Delay = Value * 40 ns + 30ns$
- \item[Bit 31] Enable trigger lines test - only for debuging trigger distribution
+ \item[Bit 8] Enable Shower calibration trigger
+ \end{description}
+ \item [0xA0C1] LVL1/LVL2 trigger settings:
+ \begin{description}
+ \item[Bit 7 -- 0] How many lvl1 events wait to send lvl2 trigger
+ \item[Bit 16 -- 12] Delay of MDCB trigger = value * 40 ns
+ \item[Bit 21 -- 17] Delay of MDCA trigger = value * 40 ns
+ \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 120 + Value*10 ns else width = Value*10ns
+ \end{description}
+ \item [0xA0C2] Multiplexers output select:
+ \begin{description}
+ \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the Fig.\ref{cts_logic})
+ \begin{description}
+ \item 31 - 0 After one clok
+ \item 63 - 32 After delay
+ \item 95 - 64 After downscale
+ \item 127 - 96 After set width
+
+ \end{description}
+ \item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4))
+ \item[Bit 23 -- 16] Data version set into the data stream from the CTS (see CTS data structure chapter)
+ \end{description}
+ \item [0xA0C4 -- 0xA0C3] Enable inputs (order as on the Fig.\ref{cts_logic})
+ \item [0xA0C6 -- 0xA0C5] TS gating disable
+ \item [0xA0C8 -- 0xA0C7] Enable outputs
+ \item [0xA0D0 -- 0xA0C9] Downscale registers
+ \item [0xA0D8 -- 0xA0D1] Delay registers
+ \item [0xA0E0 -- 0xA0D9] Width registers
+ \item [0xA0E1] LVL2 EB IP table
+ \begin{description}
+ \item[Bit 15 -- 0] When writing to this register EB is chosen to be a reciver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected
+ \end{description}
+ \item [0xA0E2] LVL2 - events per EB
+ \begin{description}
+ \item[Bit 23 -- 0] Number of events per EB
+ \end{description}
+ \item [0xA0E3] LVL2 - events per EB
+ \begin{description}
+ \item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $
\end{description}
- \item [0xA099] Trigger logic debug
- \item[Bit 3 -- 0] State machine debug: 0x1 - Idle; 0x2 - Waiting for readout start; 3 - sending latches; 4 - sending scalers; 5 - readout finished
- \item[Bit 4] Beam inhibit in
\end{description}
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-\subsubsection{CTS Control and Status Registers}
+\subsubsection{CTS Status Registers}
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-When Trigger Logic is not used (A0C5 bit 30 = 0 ) the configuration of the used logic is simple (just accepting the input triggers see address A0C5).
-In this case when calibration trigger is set (0xA0C7;A0C5 bit 30 = 0) still the reference time/hold signal is send. When Trigger Logic is enabled and register 0xA0DC is used to overwrite trigger code. In this case if calibration trigger is send there is no reference time/hold signal.
-It is recommended to start system ether with simple or trigger logic and do not switch between them when it is running.
+
+
\begin{description}
- \item[0xA091: LVL1 information] Busy flags and current trigger number and type on LVL1 channel
+
+ \item [0xA000] Trigger logic debug out
+ \begin{description}
+ \item[Bit 15 -- 0] LVL1 trigger number
+ \item[Bit 16] trigger buffer fifo full
+ \item[Bit 17] trigger buffer fifo empty
+ \item[Bit 18] event rate bit 13
+ \item[Bit 19] event rate bit 15
+ \item[Bit 20] lvl1 trigger buffer busy
+ \item[Bit 21] lvl1 TrbNet busy
+ \item[Bit 22] lvl1 local busy
+ \item[Bit 31 -- 24] lvl1 trigger rnd code
+ \end{description}
+
+ \item[0xA001: LVL1 information] Busy flags and current trigger number and type on LVL1 channel
\begin{description}
- \item[Bit 15 -- 0] LVL1 trigger number
- \item[Bit 19 -- 16] LVL1 trigger type
- \item[Bit 20] LVL1 CTS busy
- \item[Bit 21] LVL1 TrbNet busy
- \item[Bit 22] LVL1 Local busy
- \item[Bit 23] LVL1 trigger box busy
- \item[Bit 31 -- 24] LVL1 trigger random code
+ \item[Bit 19 -- 0] Accepted event rate
+ \item[Bit 20] LVL2 CTS busy
+ \item[Bit 21] LVL2 TrbNet busy
+ \item[Bit 22] LVL2 local busy
+ \item[Bit 23] 0
+ \item[Bit 31 -- 24] LVL1 and LVL2 difference
\end{description}
- \item[0xA092: Mixed information] LVL1 trigger rate, further busy flags for LVL1 and IPU channel
+ \item[0xA002: Mixed information] LVL1 trigger rate, further busy flags for LVL1 and IPU channel
\begin{description}
- \item[Bit 19 -- 0] LVL1 trigger rate (accepted triggers per second)
- \item[Bit 20] RICH APV double pulse busy
- \item[Bit 21] LVL1 self trigger
- \item[Bit 25 -- 22] Bits 7, 9, 11 and 13 of trigger rate counter (ignore on slow control)
- \item[Bit 26] IPU channel CTS busy
- \item[Bit 27] IPU channel TrbNet busy
- \item[Bit 28] IPU channel local busy
+ \item[Bit 15 -- 0] LVL2 trigger number
+ \item[Bit 19 -- 16] Trigger fifo data counter lower 4 bits
+ \item[Bit 23 -- 20] LVL1 internal readout state machine :
+ \begin{description}
+ \item[0x0] Not allowed
+ \item[0x1] IDLE
+ \item[0x2] Waiting for token in
+ \item[0x3] Data preperation
+ \item[0x4] Data sending
+ \item[0x5] Data finished send
+ \end{description}
+ \item[Bit 24] Beam inhibit in
\end{description}
- \item[0xA093: IPU status] Status bits for event fifo, fill level and current IPU trigger number
- \begin{description}
- \item[Bit 0] CTS event random number fifo full
- \item[Bit 1] CTS event random number fifo empty
- \item[Bit 2] CTS event number / type fifo full
- \item[Bit 3] CTS event number / type fifo empty
- \item[Bit 11 -- 4] Difference between LVL1 and IPU event counters
- \item[Bit 23 -- 12] IPU event number
- \item[Bit 31 -- 24] CTS fifo data counter
- \end{description}
-
- \item[0xA0C3: Etrax control] Etrax readout control register
+ \item[0xA004 : CTS readout to TrbNet]
+ \begin{description}
+ \item[Bit 15 -- 0] words in event
+ \item[Bit 16] header fifo full
+ \item[Bit 17] header fifo empty
+ \item[Bit 18] data fifo full
+ \item[Bit 19] data fifo empty
+ \item[Bit 20] lvl2(second state machine runs directly after the first "lvl1") busy - in the state machine
+ \item[Bit 21] lvl1 memory busy
+ \item[Bit 22] lvl1 busy - in the state machine
+ \item[Bit 27 -- 24] first state machine debug
+ \begin{description}
+ \item[0x0] Not allowed
+ \item[0x1] IDLE
+ \item[0x2] Send and wait for token
+ \item[0x3] Save data marker
+ \item[0x4] Save header
+ \item[0x5] Save header
+ \item[0x6] Save header marker
+ \item[0x7] Wait for emptying buffers
+ \end{description}
+ \item[Bit 31 -- 28] second state machine debug
+ \begin{description}
+ \item[0x0] Not allowed
+ \item[0x1] IDLE
+ \item[0x2] Wait for TrbNet ready
+ \item[0x3] Readout header marker 1
+ \item[0x4] Readout header marker 2,3
+ \item[0x5] Send headers and data
+ \item[0x6] Readout data marker 1
+ \item[0x7] Readout data marker 2,3
+ \item[0x8] Send data
+ \end{description}
+ \end{description}
+ \item[0xA005: CTS readout information] Busy flags and current trigger number and type on LVL1 channel
\begin{description}
- \item[Bit 4] Disable readout on Etrax
+ \item[Bit 13 -- 0] Data word counter
+ \item[Bit 29 -- 16] Header word counter
\end{description}
-For the time being "old" logic of the CTS is not removed.
-\item[0xA0C5 old CTS trigger selection] Trigger source selection
+ \item[0xA006: CTS readout information]
\begin{description}
- \item[Bit 4 -- 0] enable trigger input on LVDS(4 downto 0) - corresponds to ADO LV(9 downto 0) on the trbv2 schematics
- \item[Bit 9 -- 5] enable trigger input on LVTTL(20 downto 16) - corresponds to ADO TTL(20 downto 16) on the trbv2 schematics
- \item[Bit 10] trigger form fast reference trigger - corresponds to Vir Trig on the trbv2 schematics
- \item[Bit 11] self triggering (internal generator)
- \item[Bit 12] enable LVDS(0) and LVDS(1) coincidence
- \item[Bit 13] Trigger from C5(28) register
- \item[Bit 14] enable LVTTL(16) and LVTTL(17) coincidence
- \item[Bit 15] enable LVTTL(18) and LVTTL(19)
- \item[Bit 17 -- 16] Change source of LVL2 trigger: "00" - auto (defaoult, generated after LVL1 trigger),"01" - LVDS lines,"10"- local source
- \item[Bit 27 -- 20] Number of how many LVL1 trigger has to pass to send LVL2 trigger
- \item[Bit 28] Making trigger on rising edge (0...1...0)
- \item[Bit 29] not used
- \item[Bit 30] Enable LVL1 trigger source te be trigger logic (see Fig.\ref{cts_logic})
- \item[Bit 31] Make double APV pulse (0...1...0)
+ \item[Bit 7 -- 0] counter how many times first state machine started
+ \item[Bit 15 -- 8] counter how many times first state machine finished
+ \item[Bit 23 -- 16] counter how many times second state machine started
+ \item[Bit 31 -- 24] counter how many times second state machine finished
\end{description}
-\item[0xA0C6] LVL1 and IPU mixed
+ \item[0xA007: R/W registers debug information]
\begin{description}
- \item[Bit 7 -- 0] IPU downscale - not used in current scheme.
- \item[Bit 27 -- 8] Frequency of self triggering : 50MHz/value
- \item[Bit 31 -- 28] Length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
+ \item[Bit 15 -- 0] saved data for the registers
+ \item[Bit 23 -- 16] saved address for the registers
+ \item[Bit 24] R/W mode: 0 write ,1 read
+ \item[Bit 25] unknown address set
\end{description}
-\item[0xA0C7] LVL1 trigger type selection
- \begin{description}
- \item[Bit 4 -- 0] If c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger logic
- \end{description}
+ \item[0xA028 -- 0xA008 ] Input scalers
+ \item[0xA037 -- 0xA029 ] Scalers after downscaling
+ \item[0xA046 -- 0xA038 ] Scalers after trigger accepted
-\item[0xA0C8] LVL1 trigger information
- \begin{description}
- \item[Bit 13 -- 0] LVL1 trigger information 13 downto 0
\end{description}
-\item[0xA0C9] Selects how many times should be sent data to the EB with current ID (which corresponds to the EB IP number), when 0 does not swith between IDs
-\item[0xA0CA] Tables of 8 EB IDs (each ID has four bits), the IDs are switched form CA(3 down to 0) to CA(7 down to 4) ... CB(31 down to 28)
-\item[0xA0CB] Tables of 8 EB IDs (each ID has four bits)
-
-\end{description}
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