add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
-add_file -vhdl -lib work "../../trbnet/xilinx/xcku/trb_net_xdna.vhd"
-add_file -vhdl -lib work "../../trbnet/xilinx/xcku/read_dna_address.vhd"
+#add_file -vhdl -lib work "../../trbnet/xilinx/xcku/trb_net_xdna.vhd"
+#add_file -vhdl -lib work "../../trbnet/xilinx/xcku/read_dna_address.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
FEE_DATA_FINISHED_OUT => cts_rdo_finished
);
- cts_addon_triggers_in(1 downto 0) <= '0' & mbs_trigger when rising_edge(clk_sys);
+ --cts_addon_triggers_in(1 downto 0) <= '0' & mbs_trigger when rising_edge(clk_sys);
buscts_tx.nack <= '0';
buscts_tx.ack <= '0';
THE_LOCAL_MBS_CREATE : process
variable cnt : unsigned(16 downto 0) := (others => '0');
begin
- wait until rising_edge(clk_sys);
+-- wait until rising_edge(clk_sys);
+ wait until rising_edge(med2int(INTERFACE_NUM).clk_half);
mbs_local_trigger_in <= '0';
if (reset_i = '1') then
cnt := 0;
mbs_local_trigger_num_in <= (others => '0');
else
cnt := cnt + 1;
- if (cnt = 100000) then
+ if (cnt = 10240) then
mbs_local_trigger_in <= '1';
mbs_local_trigger_num_in <= std_logic_vector(unsigned(mbs_local_trigger_num_in) + 1);
cnt := 0;
THE_MBS_REC : entity work.mbs_recv
+ generic map(
+ USE_40MHz => c_NO
+ )
port map (
CLK => clk_sys,
RESET_IN => reset_i,
---------------------------------------------------------------------------
--TRIGGER_TO_CTS <= trig_gen_out_i(1);
- --RJ45_SIG_4 <= trig_gen_out_i(0);
+ RJ45_SIG_4 <= cts_trigger_out;--trig_gen_out_i(0);
+ RJ45_SIG_5 <= mbs_trigger;
+ TRIGGER_TO_CTS <= mbs_local_trigger_in;
+
--TRIGGER_OUT <= RJ45_SIG_1;
--cts_ext_trigger <= TRIGGER_IN; --
TRIGGER_OUT <= cts_trigger_out; -- trigger from internal CTS to DiRICH/Power