signal number_of_subs : std_logic_vector(15 downto 0);
signal size_check_ctr : integer range 0 to 7;
signal sf_data_q, sf_data_qq, sf_data_qqq, sf_data_qqqq, sf_data_qqqqq, sf_data_qqqqqq : std_logic_vector(15 downto 0);
- signal sf_wr_lock : std_logic;
+ signal sf_wr_lock, sf_wr_en_and_lock : std_logic;
signal too_large_dropped : std_logic_vector(31 downto 0);
signal previous_ttype, previous_bank : std_logic_vector(3 downto 0);
signal sf_cnt : std_logic_vector(15 downto 0);
if (save_current_state = IDLE) then
sf_wr_lock <= '1';
- elsif (save_current_state = PRE_SAVE_DATA and size_check_ctr = 3 and FEE_DATAREADY_IN = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward
+ elsif (save_current_state = PRE_SAVE_DATA and size_check_ctr = 4 and fee_dataready = '1' and (sf_data_q & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward
sf_wr_lock <= '0';
else
sf_wr_lock <= sf_wr_lock;
end if;
end process;
- process(RESET, CLK_IPU)
+ process(CLK_IPU)
begin
- if (RESET = '1') then
- too_large_dropped <= (others => '0');
- elsif rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then
- too_large_dropped <= too_large_dropped + x"1";
+ if rising_edge(CLK_IPU) then
+
+ if (RESET = '1') then
+ too_large_dropped <= (others => '0');
else
- too_large_dropped <= too_large_dropped;
+ if (save_current_state = SAVE_PRE_DATA and size_check_ctr = 0 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then
+ too_large_dropped <= too_large_dropped + x"1";
+ else
+ too_large_dropped <= too_large_dropped;
+ end if;
end if;
end if;
end process;
+
+
SAVED_EVENTS_CTR_PROC : process(RESET, CLK_IPU)
begin
if (RESET = '1') then
saved_events_ctr <= (others => '0');
elsif rising_edge(CLK_IPU) then
- if (save_current_state = SEND_TERM_PULSE and DATA_GBE_ENABLE_IN = '1') then
+ if (save_current_state = SEND_TERM_PULSE and DATA_GBE_ENABLE_IN = '1' and sf_wr_lock = '0') then
saved_events_ctr <= saved_events_ctr + x"1";
else
saved_events_ctr <= saved_events_ctr;
Data(17) => save_eod,
WrClock => CLK_IPU,
RdClock => CLK_GBE,
- WrEn => sf_wr_en,
+ WrEn => sf_wr_en_and_lock,
RdEn => sf_rd_en,
Reset => sf_reset,
RPReset => sf_reset,
sf_reset <= RESET;
+ sf_wr_en_and_lock <= sf_wr_en and not sf_wr_lock;
+
bytes_ctr_gen : if DO_SIMULATION = 1 generate
process(CLK_IPU)
begin