###################################################################################
#Settings for this project
my $TOPNAME = "padiwa_amps"; #Name of top-level entity
-my $lattice_path = '/opt/lattice/diamond/2.2_x64';
+my $lattice_path = '/opt/lattice/diamond/3.6_x64';
my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
-my $synplify_path = '/opt/synplicity/F-2012.03-SP1';
+my $synplify_path = '/opt/synplicity/K-2015.09';
my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de';
my $lm_license_file_for_par = '1702@hadeb05.gsi.de';
###################################################################################
<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="1.3" title="padiwa_amps" device="LCMXO2-4000HC-6FTG256C" default_implementation="padiwa_amps">
+<BaliProject version="3.2" title="padiwa_amps" device="LCMXO2-4000HC-6FTG256C" default_implementation="padiwa_amps">
<Options/>
<Implementation title="padiwa_amps" dir="padiwa_amps" description="padiwa_amps" default_strategy="Strategy1">
- <Options top="padiwa_amps"/>
+ <Options deftop="padiwa_amps" top="padiwa_amps"/>
<Source name="padiwa_amps.vhd" type="VHDL" type_short="VHDL">
<Options top_module="padiwa_amps"/>
</Source>
- <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/source/spi_slave.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/spi_slave.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
<Source name="version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/cores/oddr16.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/pwm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../cores/efb_define_def.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../cores/UFM_WB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
- <Source name="../wasa/source/pwm.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../cores/pll.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/cores/efb_define_def.v" type="Verilog" type_short="Verilog">
+ <Source name="../cores/flashram.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/cores/UFM_WB_top.v" type="Verilog" type_short="Verilog">
+ <Source name="../cores/flash.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/cores/pll.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../pinout/padiwa_amps.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="../wasa/cores/flashram.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/Stretcher.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../wasa/cores/flash.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/Stretcher_A.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../base/padiwa_amps.lpf" type="Logic Preference" type_short="LPF">
+ <Source name="../source/Stretcher_B.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- </Implementation>
+ </Implementation>
<Strategy name="Strategy1" file="Strategy1.sty"/>
</BaliProject>
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "../source/spi_slave.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_sctrl.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_recv.vhd"
+###add_file -vhdl -lib work "../../trbnet/special/uart_sctrl.vhd"
+###add_file -vhdl -lib work "../../trbnet/special/uart_recv.vhd"
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../source/pwm.vhd"
add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
add_file -verilog -lib work "../cores/efb_define_def.v"
add_file -verilog -lib work "../cores/UFM_WB.v"
+add_file -vhdl -lib work "../source/Stretcher.vhd"
+add_file -vhdl -lib work "../source/Stretcher_A.vhd"
+add_file -vhdl -lib work "../source/Stretcher_B.vhd"
add_file -vhdl -lib work "padiwa_amps.vhd"
component PUR port(PUR : in std_logic); end component;
component GSR port(GSR : in std_logic); end component;
-
+constant DELAYDEPTH : integer := 16;
attribute NOM_FREQ : string;
attribute NOM_FREQ of clk_source : label is "133.00";
signal flash_err : std_logic;
signal inp_select : integer range 0 to 31 := 0;
-signal inp_invert : std_logic_vector(15 downto 0);
+signal inp_invert : std_logic_vector(15 downto 0) := (others => '1');
signal input_enable : std_logic_vector(15 downto 0);
signal inp_status : std_logic_vector(15 downto 0);
signal led_status : std_logic_vector(8 downto 0) := "100000000";
signal ffarr_data : std_logic_vector(15 downto 0);
signal ffarr_read : std_logic;
-
+signal delayed_inputs : std_logic_vector(127 downto 0);
+signal selected_delay : std_logic_vector(8 downto 1);
+signal delayselect : integer range 0 to 15;
begin
when x"8" => spi_reg20_i <= x"00" & discharge_override;
when x"9" => spi_reg20_i <= x"00" & discharge_highz;
when x"a" => spi_reg20_i <= x"00" & delay_invert;
+ when x"b" => spi_reg20_i <= x"00" & std_logic_vector(to_unsigned(delayselect,8));
when x"f" => spi_reg20_i <= ffarr_data;
when others => null;
end case;
when x"8" => discharge_override <= spi_data_i(7 downto 0);
when x"9" => discharge_highz <= spi_data_i(7 downto 0);
when x"a" => delay_invert <= spi_data_i(7 downto 0);
+ when x"b" => delayselect <= to_integer(unsigned(spi_data_i(7 downto 0)));
when others => null;
end case;
end if;
---------------------------------------------------------------------------
--- Delay generation
+-- Stretcher
---------------------------------------------------------------------------
+THE_STRETCHER : entity work.Stretcher
+ generic map(
+ CHANNEL => 8,
+ DEPTH => DELAYDEPTH
+ )
+ port map(
+ PULSE_IN => fast_input,
+ PULSE_OUT => delayed_inputs
+ );
+---------------------------------------------------------------------------
+-- Delay generation
+---------------------------------------------------------------------------
+--git delay
+------------
+--gen_discharge : for i in 1 to 8 generate
+--DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else
+-- (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else
+-- discharge_override(i) when discharge_disable(i) = '1';
+--
+--DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i);
+--end generate;
+
+--delay intern: standard latch
+-------------------------
gen_discharge : for i in 1 to 8 generate
-DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else
- (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else
- discharge_override(i) when discharge_disable(i) = '1';
-
-DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i);
+process (slow_input, selected_delay)
+begin
+ if (slow_input(i)='0') then
+ DISCHARGE(i)<='0';
+ elsif (selected_delay(i)='1') then
+ DISCHARGE(i)<='1';
+ end if;
+end process;
+
+-- delayed_inputs(i) <= selected_delay(i);
+selected_delay(i) <= delayed_inputs(i*DELAYDEPTH-1-delayselect);
end generate;
-
+
+
+
fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0);
slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1);
last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
-TEST_LINE <= (others => '0');
-
+-- TEST_LINE <= (others => '0');
+--TEST_LINE(7 downto 0) <= delayed_inputs(7 downto 0);
+--TEST_LINE(8) <= fast_input(1);
+--TEST_LINE(13 downto 9) <= (others => '0');
+TEST_LINE(7 downto 0) <= selected_delay;
gen_leds : for i in 1 to 8 generate
LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1);
\r
DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_*_IN*" ;\r
IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ;\r
+\r
+UGROUP "StretchA" BBOX 8 2\r
+ BLKNAME THE_STRETCHER/Stretcher_A_1\r
+ ;\r
+LOCATE UGROUP "StretchA" SITE "R2C2D"; \r
+ \r
+UGROUP "StretchB" BBOX 8 2\r
+ BLKNAME THE_STRETCHER/Stretcher_B_1\r
+ ;\r
+LOCATE UGROUP "StretchB" SITE "R2C30D"; \r
+ \r
+\r
+
\ No newline at end of file
jspc29 / padiwa.git / commitdiff