use work.trb3_components.all;
use work.StdTypes.all;
+use wirk.Constants.all;
entity MupixBoard8 is
port(
generic(
g_mupix_links : natural := 4;
g_cyc_mem_address_width : integer := 13;
- g_datawidth : integer := 32
+ g_datawidthfifo : integer := 40;
+ g_datawidthtrb : integer := 32
);
port(
clk : in std_logic;
component FrameGeneratorMux
generic(
- fpga_clk_speed : integer;
- spi_clk_speed : integer;
FIFODEPTH : positive;
DATAWIDTH : natural
);
end component MupixDataLink;
constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos
- constant DATA_WIDTH : natural := 32; --width of datawords
- signal mux_fifo_data : std_logic_vector(127 downto 0);
- signal mux_fifo_full : std_logic_vector(3 downto 0);
- signal mux_fifo_empty : std_logic_vector(3 downto 0);
- signal mux_fifo_rden : std_logic_vector(3 downto 0);
+ signal mux_fifo_data : std_logic_vector(c_mupixhitsize*c_links downto 0);
+ signal mux_fifo_full : std_logic_vector(c_links - 1 downto 0);
+ signal mux_fifo_empty : std_logic_vector(c_links - 1 downto 0);
+ signal mux_fifo_rden : std_logic_vector(c_links - 1 downto 0);
--signal declarations
-- Bus Handler
signal mupixdata_i : std_logic_vector(31 downto 0);
--connections between mupix data fifos and mupix board
- signal fifo_rden_serdes_i : std_logic_vector(3 downto 0);
- signal fifo_empty_serdes_i : std_logic_vector(3 downto 0);
- signal fifo_full_serdes_i : std_logic_vector(3 downto 0);
- signal fifo_data_serdes_i : std_logic_vector(127 downto 0);
+ signal fifo_rden_serdes_i : std_logic_vector(c_links - 1 downto 0);
+ signal fifo_empty_serdes_i : std_logic_vector(c_links - 1 downto 0);
+ signal fifo_full_serdes_i : std_logic_vector(c_links - 1 downto 0);
+ signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links downto 0);
begin -- Behavioral
STAT_DEBUG => open
);
- mupixboardinterface_1 : component MupixBoardInterface
+ mupixboardinterface_1 : entity work.MupixBoardInterface
port map(
clk_in => clk,
fast_clk_in => fast_clk,
hit_sync => hit_sync
);
- hitbushistogram_1 : component HitbusHistogram
+ hitbushistogram_1 : entity work.HitbusHistogram
generic map(
HistogramRange => 10,
PostOscillationWaitCycles => 5
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0)
);
- pixelcontrol_1 : component PixelControl
+ pixelcontrol_1 : entity work.PixelControl
generic map(
fpga_clk_speed => fpga_clk_speed,
spi_clk_speed => mupix_spi_clk_speed
ctrl_rb <= mupixslctrl_i.rb;
- boardcontrol_1 : component MupixBoardDAC
+ boardcontrol_1 : entity work.MupixBoardDAC
port map(
clk => clk,
reset => reset,
generic map(
g_mupix_links => 4,
g_cyc_mem_address_width => 12,
- g_datawidth => 32
+ g_datawidthfifo => c_mupixhitsize,
+ g_datawidthtrb => 32
)
port map(
clk => clk,
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4)
);
- hitgenerator_1: component FrameGeneratorMux
+ hitgenerator_1: entity work.FrameGeneratorMux
generic map(
- fpga_clk_speed => fpga_clk_speed,
- spi_clk_speed => mupix_spi_clk_speed,
FIFODEPTH => FIFO_DEPTH,
- DATAWIDTH => DATA_WIDTH
+ DATAWIDTH => c_mupixhitsize
)
port map(
clk => clk,
use ieee.numeric_std.all;
entity MupixTRBReadout is
- generic(g_mupix_links : natural := 4; -- number of input data channels from mupix
+ generic(g_mupix_links : natural := 4; -- number of input data channels from mupix
g_cyc_mem_address_width : integer := 13; -- memory depth of circular buffer
- g_datawidth : integer := 32 -- width of data words
+ g_datawidthfifo : integer := 40; -- width of data words from fifos
+ g_datawidthtrb : integer := 32 -- trb data width
);
port(
clk : in std_logic; -- clock input
-- input fifo signals (maybe we need word width conversion somewhere ?)
fifo_empty : in std_logic_vector(g_mupix_links - 1 downto 0);
fifo_full : in std_logic_vector(g_mupix_links - 1 downto 0);
- fifo_datain : in std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0);
+ fifo_datain : in std_logic_vector(g_mupix_links*g_datawidthfifo - 1 downto 0);
fifo_rden : out std_logic_vector(g_mupix_links - 1 downto 0);
-- readout and trigger
trb_trigger : in std_logic; -- signal from trb to start readout
- dataout : out std_logic_vector(g_datawidth - 1 downto 0); -- data to TRB data channel
+ dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0); -- data to TRB data channel
data_valid : out std_logic; -- output data is valid
busy : out std_logic; -- readout controller is busy
-- TRB slow Control channel
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
- data_in : in std_logic_vector(g_datawidth - 1 downto 0);
+ data_in : in std_logic_vector(g_datawidthtrb - 1 downto 0);
rd_en : in std_logic;
offset_en : in std_logic;
offset : in std_logic_vector(g_addresswidth - 1 downto 0);
- data_out : out std_logic_vector(g_datawidth - 1 downto 0);
+ data_out : out std_logic_vector(g_datawidthtrb - 1 downto 0);
empty : out std_logic;
full : out std_logic;
almost_empty : out std_logic;
);
end component CircularMemory;
- component FiFoDataMux
+ component FiFoDataMuxWithConversion
generic(
- g_datawidth : integer := 32;
+ g_datawidthfifo : integer := 40;
+ g_datawidthtrb : integer := 32;
g_inputs : integer := 4;
g_clockspeed : integer := 1e8
);
rst : in std_logic;
fifo_empty : in std_logic_vector(g_inputs - 1 downto 0);
fifo_full : in std_logic_vector(g_inputs - 1 downto 0);
- fifo_datain : in std_logic_vector(g_inputs*g_datawidth - 1 downto 0);
+ fifo_datain : in std_logic_vector(g_inputs*g_datawidthfifo - 1 downto 0);
fifo_mask : in std_logic_vector(g_inputs - 1 downto 0);
fifo_rden : out std_logic_vector(g_inputs - 1 downto 0);
buff_wren : out std_logic;
- dataout : out std_logic_vector(g_datawidth - 1 downto 0);
+ dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0);
wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0);
fifo_full_o : out std_logic
);
- end component FiFoDataMux;
+ end component FiFoDataMuxWithConversion;
component ReadoutController
generic(
signal cycl_almost_empty : std_logic;
signal fifo_mux_wren : std_logic;
- signal fifo_mux_data_out : std_logic_vector(g_datawidth - 1 downto 0);
+ signal fifo_mux_data_out : std_logic_vector(g_datawidthtrb - 1 downto 0);
signal start_readout_slow_to_buffer : std_logic := '0';
signal start_readout : std_logic := '0';
- signal readout_controller_data_in : std_logic_vector(g_datawidth - 1 downto 0);
- signal readout_controller_data_out : std_logic_vector(g_datawidth - 1 downto 0);
+ signal readout_controller_data_in : std_logic_vector(g_datawidthtrb - 1 downto 0);
+ signal readout_controller_data_out : std_logic_vector(g_datawidthtrb - 1 downto 0);
signal readout_controller_busy : std_logic;
signal readout_controller_offset_en : std_logic;
signal readout_controller_rd_en : std_logic;
type slow_readout_fsm_type is (idle, waitstate);
signal slow_readout_fsm : slow_readout_fsm_type := idle;
- signal slow_data : std_logic_vector(g_datawidth - 1 downto 0) := (others => '0');
+ signal slow_data : std_logic_vector(g_datawidthtrb - 1 downto 0) := (others => '0');
signal start_slow_read : std_logic := '0';
signal slow_read_busy : std_logic := '0';
signal slow_read_done : std_logic := '0';
start_readout <= start_readout_slow_to_buffer or trb_trigger;
- data_mux_1 : entity work.FiFoDataMux
+ data_mux_1 : entity work.FiFoDataMuxWithConversion
generic map(
- g_datawidth => g_datawidth,
+ g_datawidthfifo => g_datawidthfifo,
+ g_datawidthtrb => g_datawidthtrb,
g_inputs => g_mupix_links,
g_clockspeed => 1e8
)
cycl_buffer_1 : entity work.CircularMemory
generic map(
- g_datawidth => g_datawidth,
+ g_datawidth => g_datawidthtrb,
g_addresswidth => g_cyc_mem_address_width,
g_clockspeed => 1e8,
g_boundedbuf => false
readout_controller_1 : entity work.ReadoutController
generic map(
- g_datawidth => g_datawidth,
+ g_datawidth => g_datawidthtrb,
g_addresswidth => g_cyc_mem_address_width
)
port map(
jspc29 / trb3.git / commitdiff