typos...

diff --git a/gbe/tomcat_gbe.prj b/gbe/tomcat_gbe.prj
index 68a21d7f9247417ea2a70c10489149589d3fc992..9c6dbd22fbc73d5bb752647b4ac14de81d0fdbd3 100644 (file)
--- a/gbe/tomcat_gbe.prj
+++ b/gbe/tomcat_gbe.prj
@@ -104,18 +104,26 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
 
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../TOMcat/cores/serdes_gbe.vhd"
+add_file -verilog -lib work "../../TOMcat/cores/pcs_gbe_softlogic.v"
+add_file -verilog -lib work "../../TOMcat/cores/sgmii_core_bb.v"
+
+# tsmac
+# serdes_gbe
+
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
@@ -123,10 +131,6 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
 
-# sgmii_core
-# tsmac
-# serdes_gbe
-
 #Fifos
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
@@ -164,6 +168,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../TOMcat/code/tomcat_tools.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
@@ -184,14 +189,14 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 
 #Media interface
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
 
 
 
@@ -262,35 +267,35 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
 
 
-add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
-add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-add_file -vhdl -lib work "tdc_release/Channel.vhd"
-add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
-add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
-add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
-add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
-add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
+#add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+#add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+#add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+#add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+#add_file -vhdl -lib work "tdc_release/Channel.vhd"
+#add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+#add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+#add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+#add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+#add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+#add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
+#add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+#add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+#add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+#add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+#add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+#add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+#add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
 add_file -vhdl -lib work "./tomcat_gbe.vhd"

diff --git a/gbe/tomcat_gbe.vhd b/gbe/tomcat_gbe.vhd
index f8eaa9c1cf78858739565db8026457d4b26198d1..ec948cabe3e2729bc627486984cfdfc31f0a506b 100644 (file)
--- a/gbe/tomcat_gbe.vhd
+++ b/gbe/tomcat_gbe.vhd
@@ -61,9 +61,6 @@ architecture arch of tomcat_gbe is
   attribute syn_keep                : boolean;
   attribute syn_preserve            : boolean;
 
-  attribute syn_keep of GSR_N       : signal is true;
-  attribute syn_preserve of GSR_N   : signal is true;  
-
   signal clk_sys                    : std_logic;
   signal clk_full                   : std_logic;
   signal clk_full_osc               : std_logic;
@@ -85,6 +82,12 @@ architecture arch of tomcat_gbe is
   signal gsc_reply_packet_num       : std_logic_vector(2 downto 0);
   signal gsc_busy                   : std_logic;
 
+  signal reboot_from_gbe            : std_logic;
+  signal reset_via_gbe              : std_logic;
+  
+  attribute syn_keep of GSR_N       : signal is true;
+  attribute syn_preserve of GSR_N   : signal is true;  
+
   ----------------------------------------------------------------------------
   
 
@@ -222,7 +225,7 @@ begin
       CTS_CODE_IN              => (others => '0'), --gbe_cts_code,            
       CTS_INFORMATION_IN       => (others => '0'), --gbe_cts_information,     
       CTS_READOUT_TYPE_IN      => (others => '0'), --gbe_cts_readout_type,    
-      CTS_START_READOUT_IN     => (others => '0'), --gbe_cts_start_readout,   
+      CTS_START_READOUT_IN     => '0', --gbe_cts_start_readout,   
       CTS_DATA_OUT             => open,                    
       CTS_DATAREADY_OUT        => open,                    
       CTS_READOUT_FINISHED_OUT => open, --gbe_cts_readout_finished,
@@ -238,7 +241,7 @@ begin
       -- unique adresses
       MC_UNIQUE_ID_IN          => uuid_i, --timer.uid,
       MY_TRBNET_ADDRESS_IN     => x"c000", --timer.network_address,
-      ISSUE_REBOOT_OUT         => open, --reboot_from_gbe, -- reboot by GbE
+      ISSUE_REBOOT_OUT         => reboot_from_gbe, -- reboot by GbE
       -- slow control by GbE
       GSC_CLK_IN               => clk_sys,            
       GSC_INIT_DATAREADY_OUT   => gsc_init_dataready,   
@@ -256,18 +259,17 @@ begin
       BUS_REG_RX               => open, --busgbereg_rx,
       BUS_REG_TX               => open, --busgbereg_tx,
       -- reset
-      MAKE_RESET_OUT           => open, --reset_via_gbe, -- reset by GbE
+      MAKE_RESET_OUT           => reset_via_gbe, -- reset by GbE
       -- debug
       DEBUG_OUT                => open
     );
-
-
+    
 -------------------------------------------------------------------------------
 -- Outputs
 -------------------------------------------------------------------------------
-  INTCOM(19 downto 0) <= (others => '0');
---  INTCOM(19)          <= '0';
---  INTCOM(18)          <= '0';
+  INTCOM(17 downto 0) <= (others => '0');
+  INTCOM(19)          <= reboot_from_gbe; --'0';
+  INTCOM(18)          <= reset_via_gbe; --'0';
 --  INTCOM(17)          <= '0';
 --  INTCOM(16)          <= '0';
 --  INTCOM(15)          <= '0';