--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_240_0" module="serdes_sync_240_0" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 09 22 09:47:17.857" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="serdes_sync_240_0.lpc" type="lpc" modified="2020 09 22 09:47:15.000"/>
+ <File name="serdes_sync_240_0.pp" type="pp" modified="2020 09 22 09:47:15.000"/>
+ <File name="serdes_sync_240_0.sym" type="sym" modified="2020 09 22 09:47:16.000"/>
+ <File name="serdes_sync_240_0.tft" type="tft" modified="2020 09 22 09:47:15.000"/>
+ <File name="serdes_sync_240_0.txt" type="pcs_module" modified="2020 09 22 09:47:15.000"/>
+ <File name="serdes_sync_240_0.vhd" type="top_level_vhdl" modified="2020 09 22 09:47:15.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN1156C
+SpeedGrade=6
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=serdes_sync_240_0
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/22/2020
+Time=09:47:15
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXTX
+_mode1=DISABLED
+_mode2=DISABLED
+_mode3=DISABLED
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2.4
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=240.0
+_tx_protocol0=G8B10B
+_tx_protocol1=DISABLED
+_tx_protocol2=DISABLED
+_tx_protocol3=DISABLED
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=240.0
+_tx_ficlk_rate1=240.0
+_tx_ficlk_rate2=240.0
+_tx_ficlk_rate3=240.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=EXTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=EXTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2.4
+_rx_datarange1=2.5
+_rx_datarange2=2.5
+_rx_datarange3=2
+_rx_protocol0=G8B10B
+_rx_protocol1=DISABLED
+_rx_protocol2=DISABLED
+_rx_protocol3=DISABLED
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=240.0
+_rxrefclk_rate1=250.0
+_rxrefclk_rate2=250.0
+_rxrefclk_rate3=200
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=DISABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=240.0
+_rx_ficlk_rate1=250.0
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=200
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=00
+_k02=00
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00000000
+_byten02=00000000
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_240_0.pp=pp
+serdes_sync_240_0.tft=tft
+serdes_sync_240_0.txt=pcs_module
+serdes_sync_240_0.sym=sym
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL "G8B10B"
+CH0_MODE "RXTX"
+CH1_MODE "DISABLED"
+CH2_MODE "DISABLED"
+CH3_MODE "DISABLED"
+CH0_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDHIGH"
+CH0_RX_DATARATE_RANGE "MEDHIGH"
+REFCK_MULT "10X"
+#REFCLK_RATE 240.0
+CH0_RX_DATA_RATE "FULL"
+CH0_TX_DATA_RATE "FULL"
+CH0_TX_DATA_WIDTH "8"
+CH0_RX_DATA_WIDTH "8"
+CH0_TX_FIFO "DISABLED"
+CH0_RX_FIFO "DISABLED"
+CH0_TDRV "0"
+#CH0_TX_FICLK_RATE 240.0
+#CH0_RXREFCLK_RATE "240.0"
+#CH0_RX_FICLK_RATE 240.0
+CH0_TX_PRE "DISABLED"
+CH0_RTERM_TX "50"
+CH0_RX_EQ "DISABLED"
+CH0_RTERM_RX "50"
+CH0_RX_DCC "DC"
+CH0_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH0_TX_SB "DISABLED"
+CH0_RX_SB "DISABLED"
+CH0_TX_8B10B "ENABLED"
+CH0_RX_8B10B "ENABLED"
+CH0_COMMA_A "1100000101"
+CH0_COMMA_B "0011111010"
+CH0_COMMA_M "1111111100"
+CH0_RXWA "ENABLED"
+CH0_ILSM "ENABLED"
+CH0_CTC "DISABLED"
+CH0_CC_MATCH4 "0100011100"
+CH0_CC_MATCH_MODE "1"
+CH0_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH0_SSLB "DISABLED"
+CH0_SPLBPORTS "DISABLED"
+CH0_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
+
+
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "serdes_sync_240_0.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_EXT";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_240_0 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_240_0.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ tx_force_disp_ch0 : in std_logic;
+ tx_disp_sel_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end serdes_sync_240_0;
+
+
+architecture serdes_sync_240_0_arch of serdes_sync_240_0 is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH0_CDR_SRC: string;
+ attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "120.000";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch0_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH0_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => hdoutp_ch0,
+ HDOUTN0 => hdoutn_ch0,
+ HDINP0 => hdinp_ch0,
+ HDINN0 => hdinn_ch0,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => sci_sel_ch0,
+ SCIENCH0 => fpsc_vhi,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => txiclk_ch0,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => rx_full_clk_ch0,
+ FF_RX_H_CLK_0 => rx_half_clk_ch0,
+ FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+ FF_TX_H_CLK_0 => tx_half_clk_ch0,
+ FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+ FF_TX_D_0_0 => txdata_ch0(0),
+ FF_TX_D_0_1 => txdata_ch0(1),
+ FF_TX_D_0_2 => txdata_ch0(2),
+ FF_TX_D_0_3 => txdata_ch0(3),
+ FF_TX_D_0_4 => txdata_ch0(4),
+ FF_TX_D_0_5 => txdata_ch0(5),
+ FF_TX_D_0_6 => txdata_ch0(6),
+ FF_TX_D_0_7 => txdata_ch0(7),
+ FF_TX_D_0_8 => tx_k_ch0,
+ FF_TX_D_0_9 => tx_force_disp_ch0,
+ FF_TX_D_0_10 => tx_disp_sel_ch0,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => rxdata_ch0(0),
+ FF_RX_D_0_1 => rxdata_ch0(1),
+ FF_RX_D_0_2 => rxdata_ch0(2),
+ FF_RX_D_0_3 => rxdata_ch0(3),
+ FF_RX_D_0_4 => rxdata_ch0(4),
+ FF_RX_D_0_5 => rxdata_ch0(5),
+ FF_RX_D_0_6 => rxdata_ch0(6),
+ FF_RX_D_0_7 => rxdata_ch0(7),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+ FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+ FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+ FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => open,
+ FF_RX_H_CLK_1 => open,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpsc_vlo,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => open,
+ FF_RX_D_1_1 => open,
+ FF_RX_D_1_2 => open,
+ FF_RX_D_1_3 => open,
+ FF_RX_D_1_4 => open,
+ FF_RX_D_1_5 => open,
+ FF_RX_D_1_6 => open,
+ FF_RX_D_1_7 => open,
+ FF_RX_D_1_8 => open,
+ FF_RX_D_1_9 => open,
+ FF_RX_D_1_10 => open,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => fpsc_vlo,
+ FFC_RXPWDNB_1 => fpsc_vlo,
+ FFS_RLOS_LO_1 => open,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => open,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => fpsc_vlo,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => open,
+ FF_RX_H_CLK_3 => open,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpsc_vlo,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => open,
+ FF_RX_D_3_1 => open,
+ FF_RX_D_3_2 => open,
+ FF_RX_D_3_3 => open,
+ FF_RX_D_3_4 => open,
+ FF_RX_D_3_5 => open,
+ FF_RX_D_3_6 => open,
+ FF_RX_D_3_7 => open,
+ FF_RX_D_3_8 => open,
+ FF_RX_D_3_9 => open,
+ FF_RX_D_3_10 => open,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => fpsc_vlo,
+ FFC_RXPWDNB_3 => fpsc_vlo,
+ FFS_RLOS_LO_3 => open,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => open,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => open,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => fpsc_vlo,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_240_0_arch ;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_240_3" module="serdes_sync_240_3" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 09 22 09:48:09.960" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="serdes_sync_240_3.lpc" type="lpc" modified="2020 09 22 09:48:07.000"/>
+ <File name="serdes_sync_240_3.pp" type="pp" modified="2020 09 22 09:48:07.000"/>
+ <File name="serdes_sync_240_3.sym" type="sym" modified="2020 09 22 09:48:08.000"/>
+ <File name="serdes_sync_240_3.tft" type="tft" modified="2020 09 22 09:48:07.000"/>
+ <File name="serdes_sync_240_3.txt" type="pcs_module" modified="2020 09 22 09:48:07.000"/>
+ <File name="serdes_sync_240_3.vhd" type="top_level_vhdl" modified="2020 09 22 09:48:07.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=serdes_sync_240_3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/22/2020
+Time=09:48:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=DISABLED
+_mode2=DISABLED
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2.4
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=240.0
+_tx_protocol0=DISABLED
+_tx_protocol1=DISABLED
+_tx_protocol2=DISABLED
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=240.0
+_tx_ficlk_rate1=240.0
+_tx_ficlk_rate2=240.0
+_tx_ficlk_rate3=240.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=EXTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2
+_rx_datarange1=2.5
+_rx_datarange2=2.5
+_rx_datarange3=2.4
+_rx_protocol0=DISABLED
+_rx_protocol1=DISABLED
+_rx_protocol2=DISABLED
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=200
+_rxrefclk_rate1=250.0
+_rxrefclk_rate2=250.0
+_rxrefclk_rate3=240.0
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=200
+_rx_ficlk_rate1=250.0
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=240.0
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=00
+_k02=00
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00000000
+_byten02=00000000
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=module
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_240_3.pp=pp
+serdes_sync_240_3.tft=tft
+serdes_sync_240_3.txt=pcs_module
+serdes_sync_240_3.sym=sym
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH3_PROTOCOL "G8B10B"
+CH0_MODE "DISABLED"
+CH1_MODE "DISABLED"
+CH2_MODE "DISABLED"
+CH3_MODE "RXTX"
+CH3_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDHIGH"
+CH3_RX_DATARATE_RANGE "MEDHIGH"
+REFCK_MULT "10X"
+#REFCLK_RATE 240.0
+CH3_RX_DATA_RATE "FULL"
+CH3_TX_DATA_RATE "FULL"
+CH3_TX_DATA_WIDTH "8"
+CH3_RX_DATA_WIDTH "8"
+CH3_TX_FIFO "ENABLED"
+CH3_RX_FIFO "DISABLED"
+CH3_TDRV "0"
+#CH3_TX_FICLK_RATE 240.0
+#CH3_RXREFCLK_RATE "240.0"
+#CH3_RX_FICLK_RATE 240.0
+CH3_TX_PRE "DISABLED"
+CH3_RTERM_TX "50"
+CH3_RX_EQ "DISABLED"
+CH3_RTERM_RX "50"
+CH3_RX_DCC "DC"
+CH3_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH3_TX_SB "DISABLED"
+CH3_RX_SB "DISABLED"
+CH3_TX_8B10B "ENABLED"
+CH3_RX_8B10B "ENABLED"
+CH3_COMMA_A "1100000101"
+CH3_COMMA_B "0011111010"
+CH3_COMMA_M "1111111100"
+CH3_RXWA "ENABLED"
+CH3_ILSM "ENABLED"
+CH3_CTC "DISABLED"
+CH3_CC_MATCH4 "0100011100"
+CH3_CC_MATCH_MODE "1"
+CH3_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH3_SSLB "DISABLED"
+CH3_SPLBPORTS "DISABLED"
+CH3_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
+
+
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "serdes_sync_240_3.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_EXT";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_240_3 is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_240_3.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+-- CH2 --
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end serdes_sync_240_3;
+
+
+architecture serdes_sync_240_3_arch of serdes_sync_240_3 is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "240.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "120.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "120.000";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch3_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => open,
+ FF_RX_H_CLK_1 => open,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpsc_vlo,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => open,
+ FF_RX_D_1_1 => open,
+ FF_RX_D_1_2 => open,
+ FF_RX_D_1_3 => open,
+ FF_RX_D_1_4 => open,
+ FF_RX_D_1_5 => open,
+ FF_RX_D_1_6 => open,
+ FF_RX_D_1_7 => open,
+ FF_RX_D_1_8 => open,
+ FF_RX_D_1_9 => open,
+ FF_RX_D_1_10 => open,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => fpsc_vlo,
+ FFC_RXPWDNB_1 => fpsc_vlo,
+ FFS_RLOS_LO_1 => open,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => open,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => fpsc_vlo,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => fpsc_vlo,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_240_3_arch ;
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2.4GHz
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity med_ecp3_sfp_sync_240 is
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO --select slave mode
+ );
+ port(
+ CLK_REF_FULL : in std_logic; -- 240 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 240 MHz, always on
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MEDIA_MED2INT : out MED2INT;
+ MEDIA_INT2MED : in INT2MED;
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+
+ --SFP Connection
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ -- Status and control port
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+end entity;
+
+
+architecture med_ecp3_sfp_sync_240_arch of med_ecp3_sfp_sync_240 is
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of med_ecp3_sfp_sync_240_arch : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of med_ecp3_sfp_sync_240_arch : architecture is "off";
+ attribute syn_hier : string;
+ attribute syn_hier of med_ecp3_sfp_sync_240_arch : architecture is "hard";
+
+-- signal clk_200_i : std_logic;
+signal clk_rx_full, clk_rx_half : std_logic;
+signal clk_tx_full, clk_tx_half : std_logic;
+
+signal tx_data : std_logic_vector(7 downto 0);
+signal tx_k : std_logic;
+signal rx_data : std_logic_vector(7 downto 0);
+signal rx_k : std_logic;
+signal rx_error : std_logic;
+
+signal rst_n : std_logic;
+signal rx_serdes_rst : std_logic;
+signal tx_serdes_rst : std_logic;
+signal tx_pcs_rst : std_logic;
+signal rx_pcs_rst : std_logic;
+signal rst_qd : std_logic;
+signal serdes_rst_qd : std_logic;
+
+signal rx_los_low : std_logic;
+signal lsm_status : std_logic;
+signal rx_cdr_lol : std_logic;
+signal tx_pll_lol : std_logic;
+
+signal sci_ch_i : std_logic_vector(4 downto 0);
+signal sci_addr_i : std_logic_vector(5 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+
+signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
+signal wa_position_sel : std_logic_vector(3 downto 0);
+
+signal stat_rx_control_i : std_logic_vector(31 downto 0);
+signal stat_tx_control_i : std_logic_vector(31 downto 0);
+signal debug_rx_control_i : std_logic_vector(31 downto 0);
+signal debug_tx_control_i : std_logic_vector(31 downto 0);
+signal stat_fsm_reset_i : std_logic_vector(31 downto 0);
+
+signal hdinp, hdinn, hdoutp, hdoutn : std_logic;
+attribute nopad : string;
+attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
+
+
+begin
+
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+
+-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+-- clk_200_i <= clk_rx_full;
+-- end generate;
+--
+-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+-- clk_200_i <= clk_200_internal;
+-- end generate;
+
+
+-------------------------------------------------
+-- Serdes
+-------------------------------------------------
+gen_pcs0 : if SERDES_NUM = 0 generate
+ THE_SERDES : entity work.serdes_sync_240_0
+ port map(
+ hdinp_ch0 => hdinp,
+ hdinn_ch0 => hdinn,
+ hdoutp_ch0 => hdoutp,
+ hdoutn_ch0 => hdoutn,
+ txiclk_ch0 => CLK_REF_FULL,
+ rx_full_clk_ch0 => clk_rx_full,
+ rx_half_clk_ch0 => clk_rx_half,
+ tx_full_clk_ch0 => clk_tx_full,
+ tx_half_clk_ch0 => clk_tx_half,
+ fpga_rxrefclk_ch0 => CLK_INTERNAL_FULL,
+ txdata_ch0 => tx_data,
+ tx_k_ch0 => tx_k,
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data,
+ rx_k_ch0 => rx_k,
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error,
+ rx_serdes_rst_ch0_c => rx_serdes_rst,
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst,
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst,
+ rx_pwrup_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low,
+ lsm_status_ch0_s => lsm_status,
+ rx_cdr_lol_ch0_s => rx_cdr_lol,
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL_QUAD => sci_ch_i(4),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => CLK_REF_FULL,
+ tx_serdes_rst_c => '0',
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => '0'
+
+ );
+end generate;
+
+gen_pcs3 : if SERDES_NUM = 3 generate
+ THE_SERDES : entity work.serdes_sync_240_3
+ port map(
+ hdinp_ch3 => hdinp,
+ hdinn_ch3 => hdinn,
+ hdoutp_ch3 => hdoutp,
+ hdoutn_ch3 => hdoutn,
+ txiclk_ch3 => CLK_REF_FULL, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706
+ rx_full_clk_ch3 => clk_rx_full,
+ rx_half_clk_ch3 => clk_rx_half,
+ tx_full_clk_ch3 => clk_tx_full,
+ tx_half_clk_ch3 => clk_tx_half,
+ fpga_rxrefclk_ch3 => CLK_INTERNAL_FULL,
+ txdata_ch3 => tx_data,
+ tx_k_ch3 => tx_k,
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data,
+ rx_k_ch3 => rx_k,
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error,
+ rx_serdes_rst_ch3_c => rx_serdes_rst,
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst,
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low,
+ lsm_status_ch3_s => lsm_status,
+ rx_cdr_lol_ch3_s => rx_cdr_lol,
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL_QUAD => sci_ch_i(4),
+ SCI_SEL_CH3 => sci_ch_i(3),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => CLK_REF_FULL,
+ tx_serdes_rst_c => '0',
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => '0'
+
+ );
+end generate;
+
+
+ tx_serdes_rst <= '0'; --no function
+ serdes_rst_qd <= '0'; --included in rst_qd
+ wa_position_sel <= x"0";
+-- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
+-- else wa_position(15 downto 12) when SERDES_NUM = 3;
+
+THE_MED_CONTROL : entity work.med_sync_control
+ generic map(
+ IS_SYNC_SLAVE => IS_SYNC_SLAVE,
+ IS_TX_RESET => 1
+ )
+ port map(
+ CLK_SYS => SYSCLK,
+ CLK_RXI => clk_rx_full, --clk_rx_full,
+ CLK_RXHALF => clk_rx_half,
+ CLK_TXI => CLK_REF_FULL, --clk_200_internal, --clk_tx_full, JM150706
+ CLK_REF => CLK_INTERNAL_FULL,
+ RESET => RESET,
+ CLEAR => CLEAR,
+
+ SFP_LOS => SD_LOS_IN,
+ TX_LOL => tx_pll_lol,
+ RX_CDR_LOL => rx_cdr_lol,
+ RX_LOS => rx_los_low,
+ WA_POSITION => wa_position_sel,
+
+ RX_SERDES_RST => rx_serdes_rst,
+ RX_PCS_RST => rx_pcs_rst,
+ QUAD_RST => rst_qd,
+ TX_PCS_RST => tx_pcs_rst,
+
+ MEDIA_MED2INT => MEDIA_MED2INT,
+ MEDIA_INT2MED => MEDIA_INT2MED,
+
+ TX_DATA => tx_data,
+ TX_K => tx_k,
+ RX_DATA => rx_data,
+ RX_K => rx_k,
+
+ TX_DLM_WORD => TX_DLM_WORD,
+ TX_DLM => TX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+ RX_DLM => RX_DLM,
+
+ STAT_TX_CONTROL => stat_tx_control_i,
+ STAT_RX_CONTROL => stat_rx_control_i,
+ DEBUG_TX_CONTROL => debug_tx_control_i,
+ DEBUG_RX_CONTROL => debug_rx_control_i,
+ STAT_RESET => stat_fsm_reset_i
+ );
+
+THE_SCI_READER : entity work.sci_reader
+ port map(
+ CLK => SYSCLK,
+ RESET => RESET,
+
+ --SCI
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL => sci_ch_i,
+ SCI_RD => sci_read_i,
+ SCI_WR => sci_write_i,
+
+ WA_POS_OUT => wa_position,
+
+ --Slowcontrol
+ BUS_RX => BUS_RX,
+ BUS_TX => BUS_TX,
+
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
+ MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
+ DEBUG_OUT => open
+ );
+
+-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0);
+-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8);
+-- STAT_DEBUG(7) <= '0';
+-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0);
+-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
+STAT_DEBUG(15 downto 0) <= debug_rx_control_i(15 downto 0);
+
+end architecture;
+
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