update stalled MDC analog project

author Maps <maps@ikf>

Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)

committer Maps <maps@ikf>

Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)
author Maps <maps@ikf>
Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)
committer Maps <maps@ikf>
Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)
diff --git a/MdcFeeUtil/MdcAnalogWK/Analog.SchDoc b/MdcFeeUtil/MdcAnalogWK/Analog.SchDoc

index c3d6b9036a842ee79cef8f4123fd30f661e4baca..0c6f9bb193e9fd287a9927a567a2b01a191cbcda 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/Analog.SchDoc and b/MdcFeeUtil/MdcAnalogWK/Analog.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/FPGA.SchDoc b/MdcFeeUtil/MdcAnalogWK/FPGA.SchDoc

index 382c0c03d3b0e506e1705f7b448c1728049d07ef..87eb45d82e9e6440dee0a87737f8f6c90e58ad0d 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/FPGA.SchDoc and b/MdcFeeUtil/MdcAnalogWK/FPGA.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/FPGA2.SchDoc b/MdcFeeUtil/MdcAnalogWK/FPGA2.SchDoc

index 8d0fa4f2e61333cbf2b1268a69b10e57a518ed4e..fadda641551736ea6e749d6401d19c4ebf3fc865 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/FPGA2.SchDoc and b/MdcFeeUtil/MdcAnalogWK/FPGA2.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/FPGA_Power.SchDoc b/MdcFeeUtil/MdcAnalogWK/FPGA_Power.SchDoc

index ea6087742d7f26277780b8e757898891c15723d6..8545b8431b0d0f90823b935cd13c327ecf89ddfe 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/FPGA_Power.SchDoc and b/MdcFeeUtil/MdcAnalogWK/FPGA_Power.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/Filter.SchDoc b/MdcFeeUtil/MdcAnalogWK/Filter.SchDoc

index a63e26f5c64ec914b8374c63be4482c962ae81c2..baf11cd59d131960aa95827a6fc4d32bfad77649 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/Filter.SchDoc and b/MdcFeeUtil/MdcAnalogWK/Filter.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/Inputs.SchDoc b/MdcFeeUtil/MdcAnalogWK/Inputs.SchDoc

index a639c5dfc25600e783c334da54e60c8f045ff8d0..4250fd960cbd18c2527d14d5c14bf6ca330be381 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/Inputs.SchDoc and b/MdcFeeUtil/MdcAnalogWK/Inputs.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/Inputs2.SchDoc b/MdcFeeUtil/MdcAnalogWK/Inputs2.SchDoc

index cd68557b3e3b8710da2a6f2af481f63652f46f14..f8f0dcc98cc0457ef04f1e41374c21a8d8ec84be 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/Inputs2.SchDoc and b/MdcFeeUtil/MdcAnalogWK/Inputs2.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/Main.SchDoc b/MdcFeeUtil/MdcAnalogWK/Main.SchDoc

index 3209fd799057bbaa9c0157df706fc68a8ffb65f1..abb3b56a13b2111bfec79d8539e334044fe9db24 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/Main.SchDoc and b/MdcFeeUtil/MdcAnalogWK/Main.SchDoc differ
diff --git a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.Annotation b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.Annotation

index 2f4237354e272aab280521c1813d34715459c9a3..31eda0991b981154452fffd8ce7e8f4c4e5580af 100755 (executable)
--- a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.Annotation
+++ b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.Annotation
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+PhysicalDesignator632=R61\r
+PhysicalDesignatorLocked632=0\r
+LogicalDesignator633=R64\r
+LogicalPartID633=1\r
+DocumentName633=FPGA.SchDoc\r
+ChannelName633=DBO\r
+UniqueID633=\RXOWUMFV\LTUMMRRE\r
+PhysicalDesignator633=R64\r
+PhysicalDesignatorLocked633=0\r
+LogicalDesignator634=U1\r
+LogicalPartID634=4\r
+DocumentName634=FPGA.SchDoc\r
+ChannelName634=DBO\r
+UniqueID634=\RXOWUMFV\NRJFDVLA\r
+PhysicalDesignator634=U1\r
+PhysicalDesignatorLocked634=0\r
+LogicalDesignator635=R11\r
+LogicalPartID635=1\r
+DocumentName635=FPGA.SchDoc\r
+ChannelName635=DBO\r
+UniqueID635=\RXOWUMFV\OCEJIQIJ\r
+PhysicalDesignator635=R11\r
+PhysicalDesignatorLocked635=0\r
+LogicalDesignator636=R27\r
+LogicalPartID636=1\r
+DocumentName636=FPGA.SchDoc\r
+ChannelName636=DBO\r
+UniqueID636=\RXOWUMFV\OMSUVBAN\r
+PhysicalDesignator636=R27\r
+PhysicalDesignatorLocked636=0\r
+LogicalDesignator637=R6\r
+LogicalPartID637=1\r
+DocumentName637=FPGA.SchDoc\r
+ChannelName637=DBO\r
+UniqueID637=\RXOWUMFV\PUGPAVBO\r
+PhysicalDesignator637=R6\r
+PhysicalDesignatorLocked637=0\r
+LogicalDesignator638=U1\r
+LogicalPartID638=5\r
+DocumentName638=FPGA.SchDoc\r
+ChannelName638=DBO\r
+UniqueID638=\RXOWUMFV\QFTAWUMV\r
+PhysicalDesignator638=U1\r
+PhysicalDesignatorLocked638=0\r
+LogicalDesignator639=P6\r
+LogicalPartID639=1\r
+DocumentName639=FPGA.SchDoc\r
+ChannelName639=DBO\r
+UniqueID639=\RXOWUMFV\QTGKRCRL\r
+PhysicalDesignator639=P6\r
+PhysicalDesignatorLocked639=0\r
+LogicalDesignator640=R18\r
+LogicalPartID640=1\r
+DocumentName640=FPGA.SchDoc\r
+ChannelName640=DBO\r
+UniqueID640=\RXOWUMFV\SAPMVLWX\r
+PhysicalDesignator640=R18\r
+PhysicalDesignatorLocked640=0\r
+LogicalDesignator641=U1\r
+LogicalPartID641=3\r
+DocumentName641=FPGA.SchDoc\r
+ChannelName641=DBO\r
+UniqueID641=\RXOWUMFV\TDGGHUPN\r
+PhysicalDesignator641=U1\r
+PhysicalDesignatorLocked641=0\r
+LogicalDesignator642=R67\r
+LogicalPartID642=1\r
+DocumentName642=FPGA.SchDoc\r
+ChannelName642=DBO\r
+UniqueID642=\RXOWUMFV\TIWJPHKB\r
+PhysicalDesignator642=R67\r
+PhysicalDesignatorLocked642=0\r
+LogicalDesignator643=U1\r
+LogicalPartID643=6\r
+DocumentName643=FPGA.SchDoc\r
+ChannelName643=DBO\r
+UniqueID643=\RXOWUMFV\UEVOKYNK\r
+PhysicalDesignator643=U1\r
+PhysicalDesignatorLocked643=0\r
+LogicalDesignator644=X1\r
+LogicalPartID644=1\r
+DocumentName644=FPGA.SchDoc\r
+ChannelName644=DBO\r
+UniqueID644=\RXOWUMFV\UHXVQDEV\r
+PhysicalDesignator644=X1\r
+PhysicalDesignatorLocked644=0\r
+LogicalDesignator645=R21\r
+LogicalPartID645=1\r
+DocumentName645=FPGA.SchDoc\r
+ChannelName645=DBO\r
+UniqueID645=\RXOWUMFV\VMLPTKDC\r
+PhysicalDesignator645=R21\r
+PhysicalDesignatorLocked645=0\r
+LogicalDesignator646=R15\r
+LogicalPartID646=1\r
+DocumentName646=FPGA.SchDoc\r
+ChannelName646=DBO\r
+UniqueID646=\RXOWUMFV\WEUQOJWH\r
+PhysicalDesignator646=R15\r
+PhysicalDesignatorLocked646=0\r
+LogicalDesignator647=R12\r
+LogicalPartID647=1\r
+DocumentName647=FPGA.SchDoc\r
+ChannelName647=DBO\r
+UniqueID647=\RXOWUMFV\XUEVBIFN\r
+PhysicalDesignator647=R12\r
+PhysicalDesignatorLocked647=0\r
+LogicalDesignator648=U1\r
+LogicalPartID648=2\r
+DocumentName648=FPGA.SchDoc\r
+ChannelName648=DBO\r
+UniqueID648=\RXOWUMFV\YDWIYQAR\r
+PhysicalDesignator648=U1\r
+PhysicalDesignatorLocked648=0\r
+LogicalDesignator649=R5\r
+LogicalPartID649=1\r
+DocumentName649=FPGA.SchDoc\r
+ChannelName649=DBO\r
+UniqueID649=\RXOWUMFV\YMTBFXDR\r
+PhysicalDesignator649=R5\r
+PhysicalDesignatorLocked649=0\r
+LogicalDesignator650=U1\r
+LogicalPartID650=1\r
+DocumentName650=FPGA.SchDoc\r
+ChannelName650=DBO\r
+UniqueID650=\RXOWUMFV\YSEIWBOF\r
+PhysicalDesignator650=U1\r
+PhysicalDesignatorLocked650=0\r
+LogicalDesignator651=C41\r
+LogicalPartID651=1\r
+DocumentName651=Main.SchDoc\r
+ChannelName651=Main\r
+UniqueID651=\SJDVJVDA\r
+PhysicalDesignator651=C41\r
+PhysicalDesignatorLocked651=0\r
+LogicalDesignator652=R25\r
+LogicalPartID652=1\r
+DocumentName652=Main.SchDoc\r
+ChannelName652=Main\r
+UniqueID652=\SKHFWAXH\r
+PhysicalDesignator652=R25\r
+PhysicalDesignatorLocked652=0\r
+LogicalDesignator653=TP1\r
+LogicalPartID653=1\r
+DocumentName653=Main.SchDoc\r
+ChannelName653=Main\r
+UniqueID653=\TGNPFKRP\r
+PhysicalDesignator653=TP1\r
+PhysicalDesignatorLocked653=0\r
+LogicalDesignator654=R29\r
+LogicalPartID654=1\r
+DocumentName654=Main.SchDoc\r
+ChannelName654=Main\r
+UniqueID654=\TQNWEGTM\r
+PhysicalDesignator654=R29\r
+PhysicalDesignatorLocked654=0\r
+LogicalDesignator655=L10\r
+LogicalPartID655=1\r
+DocumentName655=Main.SchDoc\r
+ChannelName655=Main\r
+UniqueID655=\UASLLVKH\r
+PhysicalDesignator655=L10\r
+PhysicalDesignatorLocked655=0\r
+LogicalDesignator656=C61\r
+LogicalPartID656=1\r
+DocumentName656=Main.SchDoc\r
+ChannelName656=Main\r
+UniqueID656=\UCNXXPXM\r
+PhysicalDesignator656=C61\r
+PhysicalDesignatorLocked656=0\r
+LogicalDesignator657=L7\r
+LogicalPartID657=1\r
+DocumentName657=Main.SchDoc\r
+ChannelName657=Main\r
+UniqueID657=\UFPTNWHC\r
+PhysicalDesignator657=L7\r
+PhysicalDesignatorLocked657=0\r
+LogicalDesignator658=Goethe1\r
+LogicalPartID658=1\r
+DocumentName658=Main.SchDoc\r
+ChannelName658=Main\r
+UniqueID658=\UJQCMLTG\r
+PhysicalDesignator658=Goethe1\r
+PhysicalDesignatorLocked658=0\r
+LogicalDesignator659=P5\r
+LogicalPartID659=1\r
+DocumentName659=Main.SchDoc\r
+ChannelName659=Main\r
+UniqueID659=\UTEYIWWA\r
+PhysicalDesignator659=P5\r
+PhysicalDesignatorLocked659=0\r
+LogicalDesignator660=Z1\r
+LogicalPartID660=1\r
+DocumentName660=Main.SchDoc\r
+ChannelName660=Main\r
+UniqueID660=\UXQKSVYU\r
+PhysicalDesignator660=Z1\r
+PhysicalDesignatorLocked660=0\r
+LogicalDesignator661=T201\r
+LogicalPartID661=1\r
+DocumentName661=Main.SchDoc\r
+ChannelName661=Main\r
+UniqueID661=\VVHDFXRU\r
+PhysicalDesignator661=T201\r
+PhysicalDesignatorLocked661=0\r
+LogicalDesignator662=C60\r
+LogicalPartID662=1\r
+DocumentName662=Main.SchDoc\r
+ChannelName662=Main\r
+UniqueID662=\WMLTPPMO\r
+PhysicalDesignator662=C60\r
+PhysicalDesignatorLocked662=0\r
+LogicalDesignator663=C33\r
+LogicalPartID663=1\r
+DocumentName663=Main.SchDoc\r
+ChannelName663=Main\r
+UniqueID663=\XSEVOWTC\r
+PhysicalDesignator663=C33\r
+PhysicalDesignatorLocked663=0\r
+LogicalDesignator664=L9\r
+LogicalPartID664=1\r
+DocumentName664=Main.SchDoc\r
+ChannelName664=Main\r
+UniqueID664=\XWSKBKDM\r
+PhysicalDesignator664=L9\r
+PhysicalDesignatorLocked664=0\r
+LogicalDesignator665=C32\r
+LogicalPartID665=1\r
+DocumentName665=Main.SchDoc\r
+ChannelName665=Main\r
+UniqueID665=\YDPDISNO\r
+PhysicalDesignator665=C32\r
+PhysicalDesignatorLocked665=0\r
+LogicalDesignator666=C62\r
+LogicalPartID666=1\r
+DocumentName666=Main.SchDoc\r
+ChannelName666=Main\r
+UniqueID666=\YGKBHTLX\r
+PhysicalDesignator666=C62\r
+PhysicalDesignatorLocked666=0\r
+LogicalDesignator667=C43\r
+LogicalPartID667=1\r
+DocumentName667=Main.SchDoc\r
+ChannelName667=Main\r
+UniqueID667=\YYFNBTIS\r
+PhysicalDesignator667=C43\r
+PhysicalDesignatorLocked667=0\r
  \r
  [SheetNumberManager]\r
  SheetNumberOrder=Display Order\r
diff --git a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcb b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcb

index 80edeb392d134a4d380c07ab6eda30a44bf83f0d..c06aeff7cf9b5753292a01a70cce0171ddfa0be8 100755 (executable)
--- a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcb
+++ b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcb
@@ -13,7 +13,7 @@ TimestampOutput=0
  SeparateFolders=0\r
  TemplateLocationPath=\r
  PinSwapBy_Netlabel=1\r
-PinSwapBy_Pin=1\r
+PinSwapBy_Pin=0\r
  AllowPortNetNames=0\r
  AllowSheetEntryNetNames=1\r
  AppendSheetNumberToLocalNets=0\r
@@ -23,14 +23,14 @@ UserID=0xFFFFFFFF
  DefaultPcbProtel=1\r
  DefaultPcbPcad=0\r
  ReorderDocumentsOnCompile=1\r
-NameNetsHierarchically=0\r
+NameNetsHierarchically=1\r
  PowerPortNamesTakePriority=0\r
  PushECOToAnnotationFile=1\r
  DItemRevisionGUID=\r
  ReportSuppressedErrorsInMessages=0\r
  FSMCodingStyle=eFMSDropDownList_OneProcess\r
  FSMEncodingStyle=eFMSDropDownList_OneHot\r
-OutputPath=Project Outputs for MdcAnalogWK\r
+OutputPath=\r
  LogFolderPath=\r
  ManagedProjectGUID=\r
  \r
@@ -66,7 +66,7 @@ AnnotateOrder=1
  DoLibraryUpdate=1\r
  DoDatabaseUpdate=1\r
  ClassGenCCAutoEnabled=1\r
-ClassGenCCAutoRoomEnabled=1\r
+ClassGenCCAutoRoomEnabled=0\r
  ClassGenNCAutoScope=None\r
  DItemRevisionGUID=\r
  GenerateClassCluster=0\r
@@ -259,6 +259,57 @@ DItemRevisionGUID=
  GenerateClassCluster=0\r
  DocumentUniqueId=\r
  \r
+[Document14]\r
+DocumentPath=Main.Harness\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
+AnnotateOrder=-1\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+DocumentUniqueId=\r
+\r
+[Document15]\r
+DocumentPath=FPGA.Harness\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
+AnnotateOrder=-1\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+DocumentUniqueId=\r
+\r
+[Document16]\r
+DocumentPath=AnalogIntegrator.SchDoc\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
+AnnotateOrder=9\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+DocumentUniqueId=BJHBVEFH\r
+\r
  [GeneratedDocument1]\r
  DocumentPath=Project Outputs for MdcAnalogWK\Design Rule Check - PCB.html\r
  DItemRevisionGUID=\r
@@ -274,7 +325,7 @@ GenerateBOM=1
  OutputJobsCount=0\r
  \r
  [Generic_EDE]\r
-OutputDir=Project Outputs for MdcAnalogWK\r
+OutputDir=\r
  \r
  [OutputGroup1]\r
  Name=Netlist Outputs\r
@@ -415,6 +466,12 @@ OutputDocumentPath17=
  OutputVariantName17=\r
  OutputDefault17=0\r
  PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1\r
+OutputType18=PDF3D\r
+OutputName18=PDF3D\r
+OutputDocumentPath18=\r
+OutputVariantName18=\r
+OutputDefault18=0\r
+PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1\r
  \r
  [OutputGroup4]\r
  Name=Assembly Outputs\r
@@ -791,11 +848,6 @@ OutputName4=Export STEP
  OutputDocumentPath4=\r
  OutputVariantName4=[No Variations]\r
  OutputDefault4=0\r
-OutputType5=PDF3D\r
-OutputName5=Export PDF3D\r
-OutputDocumentPath5=\r
-OutputVariantName5=\r
-OutputDefault5=0\r
  \r
  [Modification Levels]\r
  Type1=1\r
@@ -882,14 +934,14 @@ Type1=1
  Type2=1\r
  Type3=1\r
  Type4=1\r
-Type5=0\r
+Type5=1\r
  Type6=1\r
  Type7=1\r
  Type8=1\r
  Type9=1\r
  Type10=1\r
  Type11=1\r
-Type12=0\r
+Type12=1\r
  Type13=1\r
  Type14=1\r
  Type15=1\r
@@ -936,7 +988,7 @@ Type10=1
  Type11=2\r
  Type12=2\r
  Type13=2\r
-Type14=1\r
+Type14=0\r
  Type15=1\r
  Type16=1\r
  Type17=1\r
@@ -1037,19 +1089,19 @@ Type111=1
  \r
  [ERC Connection Matrix]\r
  L1=NNNNNNNNNNNWNNNWW\r
-L2=NNWNNNNWWWNWNWNWN\r
-L3=NWEENEEEENEWNEEWN\r
+L2=NNNNNNNWNNNWNNNWN\r
+L3=NNEENEEEENEWNEEWN\r
  L4=NNENNNWEENNWNENWN\r
  L5=NNNNNNNNNNNNNNNNN\r
  L6=NNENNNNEENNWNENWN\r
  L7=NNEWNNWEENNWNENWN\r
  L8=NWEENEENEEENNEENN\r
-L9=NWEENEEEENEWNEEWW\r
-L10=NWNNNNNENNEWNNEWN\r
+L9=NNEENEEEENEWNEEWW\r
+L10=NNNNNNNENNEWNNEWN\r
  L11=NNENNNNEEENWNENWN\r
  L12=WWWWNWWNWWWNWWWNN\r
  L13=NNNNNNNNNNNWNNNWW\r
-L14=NWEENEEEENEWNEEWW\r
+L14=NNEENEEEENEWNEEWW\r
  L15=NNENNNNEEENWNENWW\r
  L16=WWWWNWWNWWWNWWWNW\r
  L17=WNNNNNNNWNNNWWWWN\r
@@ -1061,7 +1113,7 @@ MatchParameter1=Comment
  MatchStrictly1=1\r
  MatchParameter2=Library Reference\r
  MatchStrictly2=1\r
-PhysicalNamingFormat=$Component_$RoomName\r
+PhysicalNamingFormat=$ComponentPrefix$ComponentIndex.$ChannelIndex\r
  GlobalIndexSortOrder=3\r
  GlobalIndexSortLocation=0\r
  UniqueIDPath0=\RXOWUMFV\AIURFWGK\HEJLNHFB\r
@@ -1192,310 +1244,438 @@ Order15=16
  IndexEnabled15=0\r
  IndexStartValue15=1\r
  Suffix15=\r
-UniqueIDPath16=\RXOWUMFV\GXDGLFQC\PSQGWTYE\r
-DocumentName16=Filter.SchDoc\r
+UniqueIDPath16=\RXOWUMFV\AIURFWGK\INQQIHGO\r
+DocumentName16=AnalogIntegrator.SchDoc\r
  IsEnabled16=1\r
  SelectionScope16=All\r
-Order16=17\r
+Order16=56\r
  IndexEnabled16=0\r
  IndexStartValue16=1\r
  Suffix16=\r
-UniqueIDPath17=\RXOWUMFV\GXDGLFQC\POUMECCN\r
-DocumentName17=Filter.SchDoc\r
+UniqueIDPath17=\RXOWUMFV\AIURFWGK\DISBAYYT\r
+DocumentName17=AnalogIntegrator.SchDoc\r
  IsEnabled17=1\r
  SelectionScope17=All\r
-Order17=18\r
+Order17=57\r
  IndexEnabled17=0\r
  IndexStartValue17=1\r
  Suffix17=\r
-UniqueIDPath18=\RXOWUMFV\GXDGLFQC\YBPBFBNS\r
-DocumentName18=Filter.SchDoc\r
+UniqueIDPath18=\RXOWUMFV\AIURFWGK\HLBRGEOD\r
+DocumentName18=AnalogIntegrator.SchDoc\r
  IsEnabled18=1\r
  SelectionScope18=All\r
-Order18=19\r
+Order18=58\r
  IndexEnabled18=0\r
  IndexStartValue18=1\r
  Suffix18=\r
-UniqueIDPath19=\RXOWUMFV\GXDGLFQC\CWGAJXLQ\r
-DocumentName19=Filter.SchDoc\r
+UniqueIDPath19=\RXOWUMFV\AIURFWGK\CWFCUVXP\r
+DocumentName19=AnalogIntegrator.SchDoc\r
  IsEnabled19=1\r
  SelectionScope19=All\r
-Order19=20\r
+Order19=59\r
  IndexEnabled19=0\r
  IndexStartValue19=1\r
  Suffix19=\r
-UniqueIDPath20=\RXOWUMFV\GXDGLFQC\RHOCFEYV\r
-DocumentName20=Filter.SchDoc\r
+UniqueIDPath20=\RXOWUMFV\AIURFWGK\WFOGAPDF\r
+DocumentName20=AnalogIntegrator.SchDoc\r
  IsEnabled20=1\r
  SelectionScope20=All\r
-Order20=21\r
+Order20=60\r
  IndexEnabled20=0\r
  IndexStartValue20=1\r
  Suffix20=\r
-UniqueIDPath21=\RXOWUMFV\GXDGLFQC\FNCJSMMD\r
-DocumentName21=Filter.SchDoc\r
+UniqueIDPath21=\RXOWUMFV\AIURFWGK\OPBYEWKR\r
+DocumentName21=AnalogIntegrator.SchDoc\r
  IsEnabled21=1\r
  SelectionScope21=All\r
-Order21=22\r
+Order21=61\r
  IndexEnabled21=0\r
  IndexStartValue21=1\r
  Suffix21=\r
-UniqueIDPath22=\RXOWUMFV\GXDGLFQC\ACMKAJLX\r
-DocumentName22=Filter.SchDoc\r
+UniqueIDPath22=\RXOWUMFV\AIURFWGK\NMMYYIKD\r
+DocumentName22=AnalogIntegrator.SchDoc\r
  IsEnabled22=1\r
  SelectionScope22=All\r
-Order22=23\r
+Order22=62\r
  IndexEnabled22=0\r
  IndexStartValue22=1\r
  Suffix22=\r
-UniqueIDPath23=\RXOWUMFV\GXDGLFQC\WGMKQNUJ\r
-DocumentName23=Filter.SchDoc\r
+UniqueIDPath23=\RXOWUMFV\AIURFWGK\AHBWYGBG\r
+DocumentName23=AnalogIntegrator.SchDoc\r
  IsEnabled23=1\r
  SelectionScope23=All\r
-Order23=24\r
+Order23=63\r
  IndexEnabled23=0\r
  IndexStartValue23=1\r
  Suffix23=\r
-UniqueIDPath24=\RXOWUMFV\GXDGLFQC\JONELCDF\r
-DocumentName24=Filter.SchDoc\r
+UniqueIDPath24=\RXOWUMFV\DXLQOYHU\BMJLPHOO\r
+DocumentName24=AnalogIntegrator.SchDoc\r
  IsEnabled24=1\r
  SelectionScope24=All\r
-Order24=25\r
+Order24=64\r
  IndexEnabled24=0\r
  IndexStartValue24=1\r
  Suffix24=\r
-UniqueIDPath25=\RXOWUMFV\GXDGLFQC\MAWUASYQ\r
-DocumentName25=Filter.SchDoc\r
+UniqueIDPath25=\RXOWUMFV\DXLQOYHU\TJORWAFY\r
+DocumentName25=AnalogIntegrator.SchDoc\r
  IsEnabled25=1\r
  SelectionScope25=All\r
-Order25=26\r
+Order25=65\r
  IndexEnabled25=0\r
  IndexStartValue25=1\r
  Suffix25=\r
-UniqueIDPath26=\RXOWUMFV\GXDGLFQC\VJKFLNCY\r
-DocumentName26=Filter.SchDoc\r
+UniqueIDPath26=\RXOWUMFV\DXLQOYHU\QLIDGKBJ\r
+DocumentName26=AnalogIntegrator.SchDoc\r
  IsEnabled26=1\r
  SelectionScope26=All\r
-Order26=27\r
+Order26=66\r
  IndexEnabled26=0\r
  IndexStartValue26=1\r
  Suffix26=\r
-UniqueIDPath27=\RXOWUMFV\GXDGLFQC\XTUMGQER\r
-DocumentName27=Filter.SchDoc\r
+UniqueIDPath27=\RXOWUMFV\DXLQOYHU\VNTLMFYB\r
+DocumentName27=AnalogIntegrator.SchDoc\r
  IsEnabled27=1\r
  SelectionScope27=All\r
-Order27=28\r
+Order27=67\r
  IndexEnabled27=0\r
  IndexStartValue27=1\r
  Suffix27=\r
-UniqueIDPath28=\RXOWUMFV\GXDGLFQC\CRKGBWXC\r
-DocumentName28=Filter.SchDoc\r
+UniqueIDPath28=\RXOWUMFV\DXLQOYHU\LNUTOIID\r
+DocumentName28=AnalogIntegrator.SchDoc\r
  IsEnabled28=1\r
  SelectionScope28=All\r
-Order28=29\r
+Order28=68\r
  IndexEnabled28=0\r
  IndexStartValue28=1\r
  Suffix28=\r
-UniqueIDPath29=\RXOWUMFV\GXDGLFQC\XJPHOWBY\r
-DocumentName29=Filter.SchDoc\r
+UniqueIDPath29=\RXOWUMFV\DXLQOYHU\YEILXQKN\r
+DocumentName29=AnalogIntegrator.SchDoc\r
  IsEnabled29=1\r
  SelectionScope29=All\r
-Order29=30\r
+Order29=69\r
  IndexEnabled29=0\r
  IndexStartValue29=1\r
  Suffix29=\r
-UniqueIDPath30=\RXOWUMFV\GXDGLFQC\REUQQFKP\r
-DocumentName30=Filter.SchDoc\r
+UniqueIDPath30=\RXOWUMFV\DXLQOYHU\AYQAGKWF\r
+DocumentName30=AnalogIntegrator.SchDoc\r
  IsEnabled30=1\r
  SelectionScope30=All\r
-Order30=31\r
+Order30=70\r
  IndexEnabled30=0\r
  IndexStartValue30=1\r
  Suffix30=\r
-UniqueIDPath31=\RXOWUMFV\GXDGLFQC\HPXCEQEG\r
-DocumentName31=Filter.SchDoc\r
+UniqueIDPath31=\RXOWUMFV\DXLQOYHU\CUPXDJXY\r
+DocumentName31=AnalogIntegrator.SchDoc\r
  IsEnabled31=1\r
  SelectionScope31=All\r
-Order31=32\r
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  IndexEnabled31=0\r
  IndexStartValue31=1\r
  Suffix31=\r
-UniqueIDPath32=\RXOWUMFV\GXDGLFQC\HQQOGJET\r
+UniqueIDPath32=\RXOWUMFV\GXDGLFQC\PSQGWTYE\r
  DocumentName32=Filter.SchDoc\r
  IsEnabled32=1\r
  SelectionScope32=All\r
-Order32=33\r
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  IndexEnabled32=0\r
  IndexStartValue32=1\r
  Suffix32=\r
-UniqueIDPath33=\RXOWUMFV\GXDGLFQC\WCRMJAYV\r
+UniqueIDPath33=\RXOWUMFV\GXDGLFQC\POUMECCN\r
  DocumentName33=Filter.SchDoc\r
  IsEnabled33=1\r
  SelectionScope33=All\r
-Order33=34\r
+Order33=18\r
  IndexEnabled33=0\r
  IndexStartValue33=1\r
  Suffix33=\r
-UniqueIDPath34=\RXOWUMFV\GXDGLFQC\ULMPOTMY\r
+UniqueIDPath34=\RXOWUMFV\GXDGLFQC\YBPBFBNS\r
  DocumentName34=Filter.SchDoc\r
  IsEnabled34=1\r
  SelectionScope34=All\r
-Order34=35\r
+Order34=19\r
  IndexEnabled34=0\r
  IndexStartValue34=1\r
  Suffix34=\r
-UniqueIDPath35=\RXOWUMFV\GXDGLFQC\WEOBTSFJ\r
+UniqueIDPath35=\RXOWUMFV\GXDGLFQC\CWGAJXLQ\r
  DocumentName35=Filter.SchDoc\r
  IsEnabled35=1\r
  SelectionScope35=All\r
-Order35=36\r
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  IndexEnabled35=0\r
  IndexStartValue35=1\r
  Suffix35=\r
-UniqueIDPath36=\RXOWUMFV\GXDGLFQC\QABAFRVT\r
+UniqueIDPath36=\RXOWUMFV\GXDGLFQC\RHOCFEYV\r
  DocumentName36=Filter.SchDoc\r
  IsEnabled36=1\r
  SelectionScope36=All\r
-Order36=37\r
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  IndexEnabled36=0\r
  IndexStartValue36=1\r
  Suffix36=\r
-UniqueIDPath37=\RXOWUMFV\GXDGLFQC\DWQAQFTU\r
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  DocumentName37=Filter.SchDoc\r
  IsEnabled37=1\r
  SelectionScope37=All\r
-Order37=38\r
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  IndexEnabled37=0\r
  IndexStartValue37=1\r
  Suffix37=\r
-UniqueIDPath38=\RXOWUMFV\GXDGLFQC\SYXKAWTN\r
+UniqueIDPath38=\RXOWUMFV\GXDGLFQC\ACMKAJLX\r
  DocumentName38=Filter.SchDoc\r
  IsEnabled38=1\r
  SelectionScope38=All\r
-Order38=39\r
+Order38=23\r
  IndexEnabled38=0\r
  IndexStartValue38=1\r
  Suffix38=\r
-UniqueIDPath39=\RXOWUMFV\GXDGLFQC\CYJKWHKH\r
+UniqueIDPath39=\RXOWUMFV\GXDGLFQC\WGMKQNUJ\r
  DocumentName39=Filter.SchDoc\r
  IsEnabled39=1\r
  SelectionScope39=All\r
-Order39=40\r
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  IndexEnabled39=0\r
  IndexStartValue39=1\r
  Suffix39=\r
-UniqueIDPath40=\RXOWUMFV\GXDGLFQC\XBDAAQHW\r
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  DocumentName40=Filter.SchDoc\r
  IsEnabled40=1\r
  SelectionScope40=All\r
-Order40=41\r
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  IndexEnabled40=0\r
  IndexStartValue40=1\r
  Suffix40=\r
-UniqueIDPath41=\RXOWUMFV\GXDGLFQC\FRXSFKHH\r
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  DocumentName41=Filter.SchDoc\r
  IsEnabled41=1\r
  SelectionScope41=All\r
-Order41=42\r
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  IndexEnabled41=0\r
  IndexStartValue41=1\r
  Suffix41=\r
-UniqueIDPath42=\RXOWUMFV\GXDGLFQC\BCADURWC\r
+UniqueIDPath42=\RXOWUMFV\GXDGLFQC\VJKFLNCY\r
  DocumentName42=Filter.SchDoc\r
  IsEnabled42=1\r
  SelectionScope42=All\r
-Order42=43\r
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  IndexEnabled42=0\r
  IndexStartValue42=1\r
  Suffix42=\r
-UniqueIDPath43=\RXOWUMFV\GXDGLFQC\YVDFPKTC\r
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  DocumentName43=Filter.SchDoc\r
  IsEnabled43=1\r
  SelectionScope43=All\r
-Order43=44\r
+Order43=28\r
  IndexEnabled43=0\r
  IndexStartValue43=1\r
  Suffix43=\r
-UniqueIDPath44=\RXOWUMFV\GXDGLFQC\CVSOQHBJ\r
+UniqueIDPath44=\RXOWUMFV\GXDGLFQC\CRKGBWXC\r
  DocumentName44=Filter.SchDoc\r
  IsEnabled44=1\r
  SelectionScope44=All\r
-Order44=45\r
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  IndexEnabled44=0\r
  IndexStartValue44=1\r
  Suffix44=\r
-UniqueIDPath45=\RXOWUMFV\GXDGLFQC\GQBKEOCK\r
+UniqueIDPath45=\RXOWUMFV\GXDGLFQC\XJPHOWBY\r
  DocumentName45=Filter.SchDoc\r
  IsEnabled45=1\r
  SelectionScope45=All\r
-Order45=46\r
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  IndexEnabled45=0\r
  IndexStartValue45=1\r
  Suffix45=\r
-UniqueIDPath46=\RXOWUMFV\GXDGLFQC\LYEFPVWR\r
+UniqueIDPath46=\RXOWUMFV\GXDGLFQC\REUQQFKP\r
  DocumentName46=Filter.SchDoc\r
  IsEnabled46=1\r
  SelectionScope46=All\r
-Order46=47\r
+Order46=31\r
  IndexEnabled46=0\r
  IndexStartValue46=1\r
  Suffix46=\r
-UniqueIDPath47=\RXOWUMFV\GXDGLFQC\HSPONIYO\r
+UniqueIDPath47=\RXOWUMFV\GXDGLFQC\HPXCEQEG\r
  DocumentName47=Filter.SchDoc\r
  IsEnabled47=1\r
  SelectionScope47=All\r
-Order47=48\r
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  IndexEnabled47=0\r
  IndexStartValue47=1\r
  Suffix47=\r
-UniqueIDPath48=\RXOWUMFV\GXDGLFQC\r
-DocumentName48=FPGA2.SchDoc\r
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+DocumentName48=Filter.SchDoc\r
  IsEnabled48=1\r
  SelectionScope48=All\r
-Order48=49\r
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  IndexEnabled48=0\r
  IndexStartValue48=1\r
  Suffix48=\r
-UniqueIDPath49=\RXOWUMFV\r
-DocumentName49=FPGA.SchDoc\r
+UniqueIDPath49=\RXOWUMFV\GXDGLFQC\WCRMJAYV\r
+DocumentName49=Filter.SchDoc\r
  IsEnabled49=1\r
  SelectionScope49=All\r
-Order49=50\r
+Order49=34\r
  IndexEnabled49=0\r
  IndexStartValue49=1\r
  Suffix49=\r
-UniqueIDPath50=\RXOWUMFV\BCQJHWMK\r
-DocumentName50=FPGA_Power.SchDoc\r
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+DocumentName50=Filter.SchDoc\r
  IsEnabled50=1\r
  SelectionScope50=All\r
-Order50=52\r
+Order50=35\r
  IndexEnabled50=0\r
  IndexStartValue50=1\r
  Suffix50=\r
-UniqueIDPath51=\RXOWUMFV\DXLQOYHU\r
-DocumentName51=Inputs2.SchDoc\r
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+DocumentName51=Filter.SchDoc\r
  IsEnabled51=1\r
  SelectionScope51=All\r
-Order51=53\r
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  IndexEnabled51=0\r
  IndexStartValue51=1\r
  Suffix51=\r
-UniqueIDPath52=\RXOWUMFV\AIURFWGK\r
-DocumentName52=Inputs.SchDoc\r
+UniqueIDPath52=\RXOWUMFV\GXDGLFQC\QABAFRVT\r
+DocumentName52=Filter.SchDoc\r
  IsEnabled52=1\r
  SelectionScope52=All\r
-Order52=54\r
+Order52=37\r
  IndexEnabled52=0\r
  IndexStartValue52=1\r
  Suffix52=\r
-UniqueIDPath53=\r
-DocumentName53=Main.SchDoc\r
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  IsEnabled53=1\r
  SelectionScope53=All\r
-Order53=55\r
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  IndexEnabled53=0\r
  IndexStartValue53=1\r
  Suffix53=\r
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+Suffix54=\r
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+Suffix59=\r
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+IndexStartValue62=1\r
+Suffix62=\r
+UniqueIDPath63=\RXOWUMFV\GXDGLFQC\HSPONIYO\r
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+IndexEnabled63=0\r
+IndexStartValue63=1\r
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+UniqueIDPath64=\RXOWUMFV\GXDGLFQC\r
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+SelectionScope64=All\r
+Order64=49\r
+IndexEnabled64=0\r
+IndexStartValue64=1\r
+Suffix64=\r
+UniqueIDPath65=\RXOWUMFV\r
+DocumentName65=FPGA.SchDoc\r
+IsEnabled65=1\r
+SelectionScope65=All\r
+Order65=50\r
+IndexEnabled65=0\r
+IndexStartValue65=1\r
+Suffix65=\r
+UniqueIDPath66=\RXOWUMFV\BCQJHWMK\r
+DocumentName66=FPGA_Power.SchDoc\r
+IsEnabled66=1\r
+SelectionScope66=All\r
+Order66=52\r
+IndexEnabled66=0\r
+IndexStartValue66=1\r
+Suffix66=\r
+UniqueIDPath67=\RXOWUMFV\DXLQOYHU\r
+DocumentName67=Inputs2.SchDoc\r
+IsEnabled67=1\r
+SelectionScope67=All\r
+Order67=53\r
+IndexEnabled67=0\r
+IndexStartValue67=1\r
+Suffix67=\r
+UniqueIDPath68=\RXOWUMFV\AIURFWGK\r
+DocumentName68=Inputs.SchDoc\r
+IsEnabled68=1\r
+SelectionScope68=All\r
+Order68=54\r
+IndexEnabled68=0\r
+IndexStartValue68=1\r
+Suffix68=\r
+UniqueIDPath69=\r
+DocumentName69=Main.SchDoc\r
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+SelectionScope69=All\r
+Order69=55\r
+IndexEnabled69=0\r
+IndexStartValue69=1\r
+Suffix69=\r
  \r
  [PrjClassGen]\r
  CompClassManualEnabled=1\r
@@ -1507,7 +1687,7 @@ NetClassManualEnabled=1
  NetClassSeparateForBusSections=0\r
  \r
  [LibraryUpdateOptions]\r
-SelectedOnly=1\r
+SelectedOnly=0\r
  UpdateVariants=1\r
  PartTypes=0\r
  ComponentLibIdentifierKind0=Library Name And Type\r
@@ -1530,14 +1710,14 @@ ComponentUpdate2=1
  ComponentIsDeviceSheet2=0\r
  ComponentLibIdentifierKind3=Library Name And Type\r
  ComponentLibraryIdentifier3=CB2013.SCHLIB\r
-ComponentDesignItemID3=BFP720F\r
-ComponentSymbolReference3=BFP720F\r
+ComponentDesignItemID3=ADS1018IRUGT\r
+ComponentSymbolReference3=ADS1018IRUGT\r
  ComponentUpdate3=1\r
  ComponentIsDeviceSheet3=0\r
  ComponentLibIdentifierKind4=Library Name And Type\r
  ComponentLibraryIdentifier4=CB2013.SCHLIB\r
-ComponentDesignItemID4=BLM15HG102SN1\r
-ComponentSymbolReference4=BLM15HG102SN1\r
+ComponentDesignItemID4=BFP740F\r
+ComponentSymbolReference4=BFP740F\r
  ComponentUpdate4=1\r
  ComponentIsDeviceSheet4=0\r
  ComponentLibIdentifierKind5=Library Name And Type\r
@@ -1578,20 +1758,20 @@ ComponentUpdate10=1
  ComponentIsDeviceSheet10=0\r
  ComponentLibIdentifierKind11=Library Name And Type\r
  ComponentLibraryIdentifier11=CB2013.SCHLIB\r
-ComponentDesignItemID11=C 0402 2u2\r
-ComponentSymbolReference11=C 0402 2u2\r
+ComponentDesignItemID11=C 0402 220n\r
+ComponentSymbolReference11=C 0402 220n\r
  ComponentUpdate11=1\r
  ComponentIsDeviceSheet11=0\r
  ComponentLibIdentifierKind12=Library Name And Type\r
  ComponentLibraryIdentifier12=CB2013.SCHLIB\r
-ComponentDesignItemID12=C 0402 39p\r
-ComponentSymbolReference12=C 0402 39p\r
+ComponentDesignItemID12=C 0402 2u2\r
+ComponentSymbolReference12=C 0402 2u2\r
  ComponentUpdate12=1\r
  ComponentIsDeviceSheet12=0\r
  ComponentLibIdentifierKind13=Library Name And Type\r
  ComponentLibraryIdentifier13=CB2013.SCHLIB\r
-ComponentDesignItemID13=C 0402 4p7\r
-ComponentSymbolReference13=C 0402 4p7\r
+ComponentDesignItemID13=C 0402 39p\r
+ComponentSymbolReference13=C 0402 39p\r
  ComponentUpdate13=1\r
  ComponentIsDeviceSheet13=0\r
  ComponentLibIdentifierKind14=Library Name And Type\r
@@ -1602,20 +1782,20 @@ ComponentUpdate14=1
  ComponentIsDeviceSheet14=0\r
  ComponentLibIdentifierKind15=Library Name And Type\r
  ComponentLibraryIdentifier15=CB2013.SCHLIB\r
-ComponentDesignItemID15=C 0805 22u\r
-ComponentSymbolReference15=C 0805 22u\r
+ComponentDesignItemID15=C 1206 100u\r
+ComponentSymbolReference15=C 1206 100u\r
  ComponentUpdate15=1\r
  ComponentIsDeviceSheet15=0\r
  ComponentLibIdentifierKind16=Library Name And Type\r
  ComponentLibraryIdentifier16=CB2013.SCHLIB\r
-ComponentDesignItemID16=DSC8103\r
-ComponentSymbolReference16=DSC8103\r
+ComponentDesignItemID16=FT234XD-R\r
+ComponentSymbolReference16=FT234XD-R\r
  ComponentUpdate16=1\r
  ComponentIsDeviceSheet16=0\r
  ComponentLibIdentifierKind17=Library Name And Type\r
  ComponentLibraryIdentifier17=CB2013.SCHLIB\r
-ComponentDesignItemID17=FT234XD-R\r
-ComponentSymbolReference17=FT234XD-R\r
+ComponentDesignItemID17=GoetheLogo\r
+ComponentSymbolReference17=GoetheLogo\r
  ComponentUpdate17=1\r
  ComponentIsDeviceSheet17=0\r
  ComponentLibIdentifierKind18=Library Name And Type\r
@@ -1626,118 +1806,178 @@ ComponentUpdate18=1
  ComponentIsDeviceSheet18=0\r
  ComponentLibIdentifierKind19=Library Name And Type\r
  ComponentLibraryIdentifier19=CB2013.SCHLIB\r
-ComponentDesignItemID19=L 0805 100uH\r
-ComponentSymbolReference19=L 0805 100uH\r
+ComponentDesignItemID19=Header 6\r
+ComponentSymbolReference19=Header 6\r
  ComponentUpdate19=1\r
  ComponentIsDeviceSheet19=0\r
  ComponentLibIdentifierKind20=Library Name And Type\r
  ComponentLibraryIdentifier20=CB2013.SCHLIB\r
-ComponentDesignItemID20=LCMXO3LF-1K/2K/4K/7K-BG256\r
-ComponentSymbolReference20=LCMXO3LF-1K/2K/4K/7K-BG256\r
+ComponentDesignItemID20=IKF_HEADER\r
+ComponentSymbolReference20=IKF_HEADER\r
  ComponentUpdate20=1\r
  ComponentIsDeviceSheet20=0\r
  ComponentLibIdentifierKind21=Library Name And Type\r
  ComponentLibraryIdentifier21=CB2013.SCHLIB\r
-ComponentDesignItemID21=MicroUSBFemale\r
-ComponentSymbolReference21=MicroUSBFemale\r
+ComponentDesignItemID21=L 0603 6.8uH\r
+ComponentSymbolReference21=L 0603 6.8uH\r
  ComponentUpdate21=1\r
  ComponentIsDeviceSheet21=0\r
  ComponentLibIdentifierKind22=Library Name And Type\r
  ComponentLibraryIdentifier22=CB2013.SCHLIB\r
-ComponentDesignItemID22=MX-502207-1060\r
-ComponentSymbolReference22=MX-502207-1060\r
+ComponentDesignItemID22=Layermark8\r
+ComponentSymbolReference22=Layermark8\r
  ComponentUpdate22=1\r
  ComponentIsDeviceSheet22=0\r
  ComponentLibIdentifierKind23=Library Name And Type\r
  ComponentLibraryIdentifier23=CB2013.SCHLIB\r
-ComponentDesignItemID23=PIN1\r
-ComponentSymbolReference23=PIN1\r
+ComponentDesignItemID23=LCMXO3LF-1K/2K/4K/7K-BG256\r
+ComponentSymbolReference23=LCMXO3LF-1K/2K/4K/7K-BG256\r
  ComponentUpdate23=1\r
  ComponentIsDeviceSheet23=0\r
  ComponentLibIdentifierKind24=Library Name And Type\r
  ComponentLibraryIdentifier24=CB2013.SCHLIB\r
-ComponentDesignItemID24=Pin2X20\r
-ComponentSymbolReference24=Pin2X20\r
+ComponentDesignItemID24=MicroUSBFemale\r
+ComponentSymbolReference24=MicroUSBFemale\r
  ComponentUpdate24=1\r
  ComponentIsDeviceSheet24=0\r
  ComponentLibIdentifierKind25=Library Name And Type\r
  ComponentLibraryIdentifier25=CB2013.SCHLIB\r
-ComponentDesignItemID25=R 0402 0R solder bridge\r
-ComponentSymbolReference25=R 0402 0R Solder Bridge\r
+ComponentDesignItemID25=MX-502207-1060\r
+ComponentSymbolReference25=MX-502207-1060\r
  ComponentUpdate25=1\r
  ComponentIsDeviceSheet25=0\r
  ComponentLibIdentifierKind26=Library Name And Type\r
  ComponentLibraryIdentifier26=CB2013.SCHLIB\r
-ComponentDesignItemID26=R 0402 100R\r
-ComponentSymbolReference26=R 0402 100R\r
+ComponentDesignItemID26=PIN1\r
+ComponentSymbolReference26=PIN1\r
  ComponentUpdate26=1\r
  ComponentIsDeviceSheet26=0\r
  ComponentLibIdentifierKind27=Library Name And Type\r
  ComponentLibraryIdentifier27=CB2013.SCHLIB\r
-ComponentDesignItemID27=R 0402 10k\r
-ComponentSymbolReference27=R 0402 10k\r
+ComponentDesignItemID27=Pin2X20\r
+ComponentSymbolReference27=Pin2X20\r
  ComponentUpdate27=1\r
  ComponentIsDeviceSheet27=0\r
  ComponentLibIdentifierKind28=Library Name And Type\r
  ComponentLibraryIdentifier28=CB2013.SCHLIB\r
-ComponentDesignItemID28=R 0402 120k\r
-ComponentSymbolReference28=R 0402 120k\r
+ComponentDesignItemID28=R 0402 0R solder bridge\r
+ComponentSymbolReference28=R 0402 0R Solder Bridge\r
  ComponentUpdate28=1\r
  ComponentIsDeviceSheet28=0\r
  ComponentLibIdentifierKind29=Library Name And Type\r
  ComponentLibraryIdentifier29=CB2013.SCHLIB\r
-ComponentDesignItemID29=R 0402 220R\r
-ComponentSymbolReference29=R 0402 220R\r
+ComponentDesignItemID29=R 0402 100k\r
+ComponentSymbolReference29=R 0402 100k\r
  ComponentUpdate29=1\r
  ComponentIsDeviceSheet29=0\r
  ComponentLibIdentifierKind30=Library Name And Type\r
  ComponentLibraryIdentifier30=CB2013.SCHLIB\r
-ComponentDesignItemID30=R 0402 27R\r
-ComponentSymbolReference30=R 0402 27R\r
+ComponentDesignItemID30=R 0402 100R\r
+ComponentSymbolReference30=R 0402 100R\r
  ComponentUpdate30=1\r
  ComponentIsDeviceSheet30=0\r
  ComponentLibIdentifierKind31=Library Name And Type\r
  ComponentLibraryIdentifier31=CB2013.SCHLIB\r
-ComponentDesignItemID31=R 0402 33k\r
-ComponentSymbolReference31=R 0402 33k\r
+ComponentDesignItemID31=R 0402 10k\r
+ComponentSymbolReference31=R 0402 10k\r
  ComponentUpdate31=1\r
  ComponentIsDeviceSheet31=0\r
  ComponentLibIdentifierKind32=Library Name And Type\r
  ComponentLibraryIdentifier32=CB2013.SCHLIB\r
-ComponentDesignItemID32=R 0402 5k6\r
-ComponentSymbolReference32=R 0402 5k6\r
+ComponentDesignItemID32=R 0402 18k\r
+ComponentSymbolReference32=R 0402 18k\r
  ComponentUpdate32=1\r
  ComponentIsDeviceSheet32=0\r
  ComponentLibIdentifierKind33=Library Name And Type\r
  ComponentLibraryIdentifier33=CB2013.SCHLIB\r
-ComponentDesignItemID33=R 0402 6k8\r
-ComponentSymbolReference33=R 0402 6k8\r
+ComponentDesignItemID33=R 0402 1k\r
+ComponentSymbolReference33=R 0402 1k\r
  ComponentUpdate33=1\r
  ComponentIsDeviceSheet33=0\r
  ComponentLibIdentifierKind34=Library Name And Type\r
  ComponentLibraryIdentifier34=CB2013.SCHLIB\r
-ComponentDesignItemID34=R 0402 8k2\r
-ComponentSymbolReference34=R 0402 8k2\r
+ComponentDesignItemID34=R 0402 200R\r
+ComponentSymbolReference34=R 0402 200R\r
  ComponentUpdate34=1\r
  ComponentIsDeviceSheet34=0\r
  ComponentLibIdentifierKind35=Library Name And Type\r
  ComponentLibraryIdentifier35=CB2013.SCHLIB\r
-ComponentDesignItemID35=R 0603 560R HV\r
-ComponentSymbolReference35=R 0603 560R HV\r
+ComponentDesignItemID35=R 0402 220R\r
+ComponentSymbolReference35=R 0402 220R\r
  ComponentUpdate35=1\r
  ComponentIsDeviceSheet35=0\r
  ComponentLibIdentifierKind36=Library Name And Type\r
  ComponentLibraryIdentifier36=CB2013.SCHLIB\r
-ComponentDesignItemID36=WBC1-1L\r
-ComponentSymbolReference36=WBC1-1L\r
+ComponentDesignItemID36=R 0402 27R\r
+ComponentSymbolReference36=R 0402 27R\r
  ComponentUpdate36=1\r
  ComponentIsDeviceSheet36=0\r
  ComponentLibIdentifierKind37=Library Name And Type\r
  ComponentLibraryIdentifier37=CB2013.SCHLIB\r
-ComponentDesignItemID37=ZentrierLarge\r
-ComponentSymbolReference37=ZentrierLarge\r
+ComponentDesignItemID37=R 0402 300R\r
+ComponentSymbolReference37=R 0402 300R\r
  ComponentUpdate37=1\r
  ComponentIsDeviceSheet37=0\r
+ComponentLibIdentifierKind38=Library Name And Type\r
+ComponentLibraryIdentifier38=CB2013.SCHLIB\r
+ComponentDesignItemID38=R 0402 33k\r
+ComponentSymbolReference38=R 0402 33k\r
+ComponentUpdate38=1\r
+ComponentIsDeviceSheet38=0\r
+ComponentLibIdentifierKind39=Library Name And Type\r
+ComponentLibraryIdentifier39=CB2013.SCHLIB\r
+ComponentDesignItemID39=R 0402 51k\r
+ComponentSymbolReference39=R 0402 51k\r
+ComponentUpdate39=1\r
+ComponentIsDeviceSheet39=0\r
+ComponentLibIdentifierKind40=Library Name And Type\r
+ComponentLibraryIdentifier40=CB2013.SCHLIB\r
+ComponentDesignItemID40=R 0402 5k6\r
+ComponentSymbolReference40=R 0402 5k6\r
+ComponentUpdate40=1\r
+ComponentIsDeviceSheet40=0\r
+ComponentLibIdentifierKind41=Library Name And Type\r
+ComponentLibraryIdentifier41=CB2013.SCHLIB\r
+ComponentDesignItemID41=R 0402 75R\r
+ComponentSymbolReference41=R 0402 75R\r
+ComponentUpdate41=1\r
+ComponentIsDeviceSheet41=0\r
+ComponentLibIdentifierKind42=Library Name And Type\r
+ComponentLibraryIdentifier42=CB2013.SCHLIB\r
+ComponentDesignItemID42=R 0402 8k2\r
+ComponentSymbolReference42=R 0402 8k2\r
+ComponentUpdate42=1\r
+ComponentIsDeviceSheet42=0\r
+ComponentLibIdentifierKind43=Library Name And Type\r
+ComponentLibraryIdentifier43=CB2013.SCHLIB\r
+ComponentDesignItemID43=R 0603 560R HV\r
+ComponentSymbolReference43=R 0603 560R HV\r
+ComponentUpdate43=1\r
+ComponentIsDeviceSheet43=0\r
+ComponentLibIdentifierKind44=Library Name And Type\r
+ComponentLibraryIdentifier44=CB2013.SCHLIB\r
+ComponentDesignItemID44=SG3225_125\r
+ComponentSymbolReference44=SG3225_125\r
+ComponentUpdate44=1\r
+ComponentIsDeviceSheet44=0\r
+ComponentLibIdentifierKind45=Library Name And Type\r
+ComponentLibraryIdentifier45=CB2013.SCHLIB\r
+ComponentDesignItemID45=sn74lvc1g125\r
+ComponentSymbolReference45=sn74lvc1g125\r
+ComponentUpdate45=1\r
+ComponentIsDeviceSheet45=0\r
+ComponentLibIdentifierKind46=Library Name And Type\r
+ComponentLibraryIdentifier46=CB2013.SCHLIB\r
+ComponentDesignItemID46=WBC1-1L\r
+ComponentSymbolReference46=WBC1-1L\r
+ComponentUpdate46=1\r
+ComponentIsDeviceSheet46=0\r
+ComponentLibIdentifierKind47=Library Name And Type\r
+ComponentLibraryIdentifier47=CB2013.SCHLIB\r
+ComponentDesignItemID47=ZentrierLarge\r
+ComponentSymbolReference47=ZentrierLarge\r
+ComponentUpdate47=1\r
+ComponentIsDeviceSheet47=0\r
  FullReplace=1\r
  UpdateDesignatorLock=1\r
  UpdatePartIDLock=1\r
@@ -1793,6 +2033,8 @@ ParameterName19=SWAP_INFO
  ParameterUpdate19=1\r
  ParameterName20=Value\r
  ParameterUpdate20=1\r
+ParameterName21=Voltage\r
+ParameterUpdate21=1\r
  ModelTypeGroup0=PCBLIB\r
  ModelTypeUpdate0=1\r
  ModelType0=PCBLIB\r
@@ -1808,10 +2050,10 @@ ModelType3=PCBLIB
  ModelName3=0603C\r
  ModelUpdate3=1\r
  ModelType4=PCBLIB\r
-ModelName4=0805C\r
+ModelName4=0603L\r
  ModelUpdate4=1\r
  ModelType5=PCBLIB\r
-ModelName5=0805L\r
+ModelName5=1206C\r
  ModelUpdate5=1\r
  ModelType6=PCBLIB\r
  ModelName6=37203-1AEO-003-PL\r
@@ -1823,66 +2065,90 @@ ModelType8=PCBLIB
  ModelName8=DFN-12_V\r
  ModelUpdate8=1\r
  ModelType9=PCBLIB\r
-ModelName9=GSIKEL-8930E-040-178MS\r
+ModelName9=Groundpad\r
  ModelUpdate9=1\r
  ModelType10=PCBLIB\r
-ModelName10=HDR1X2H\r
+ModelName10=GSIKEL-8930E-040-178MS\r
  ModelUpdate10=1\r
  ModelType11=PCBLIB\r
-ModelName11=MICRO8EP\r
+ModelName11=HDR1X2H\r
  ModelUpdate11=1\r
  ModelType12=PCBLIB\r
-ModelName12=MX522071060\r
+ModelName12=HDR1X6\r
  ModelUpdate12=1\r
  ModelType13=PCBLIB\r
-ModelName13=OSC3.2x2.5\r
+ModelName13=IKF_LOGO\r
  ModelUpdate13=1\r
  ModelType14=PCBLIB\r
-ModelName14=SOD-882\r
+ModelName14=IKF_LOGO_SMALL\r
  ModelUpdate14=1\r
  ModelType15=PCBLIB\r
-ModelName15=TESTPAD1\r
+ModelName15=LAYERMARK8\r
  ModelUpdate15=1\r
  ModelType16=PCBLIB\r
-ModelName16=TESTPAD2\r
+ModelName16=MICRO8EP\r
  ModelUpdate16=1\r
  ModelType17=PCBLIB\r
-ModelName17=TSFP-4-1\r
+ModelName17=MX522071060\r
  ModelUpdate17=1\r
  ModelType18=PCBLIB\r
-ModelName18=USB/ZX62-B-5PA\r
+ModelName18=SG3225\r
  ModelUpdate18=1\r
  ModelType19=PCBLIB\r
-ModelName19=WBC1\r
+ModelName19=SOD-882\r
  ModelUpdate19=1\r
  ModelType20=PCBLIB\r
-ModelName20=Zentrier1\r
+ModelName20=SOT353\r
  ModelUpdate20=1\r
-ModelTypeGroup1=SI\r
-ModelTypeUpdate1=1\r
-ModelType21=SI\r
-ModelName21=1N4148\r
+ModelType21=PCBLIB\r
+ModelName21=TESTPAD1\r
  ModelUpdate21=1\r
-ModelType22=SI\r
-ModelName22=Cap\r
+ModelType22=PCBLIB\r
+ModelName22=TESTPAD2\r
  ModelUpdate22=1\r
-ModelType23=SI\r
-ModelName23=Connector\r
+ModelType23=PCBLIB\r
+ModelName23=TI-RUG10_V\r
  ModelUpdate23=1\r
-ModelType24=SI\r
-ModelName24=Inductor\r
+ModelType24=PCBLIB\r
+ModelName24=TSFP-4-1\r
  ModelUpdate24=1\r
-ModelType25=SI\r
-ModelName25=Res\r
+ModelType25=PCBLIB\r
+ModelName25=UNI_LOGO_NEU_TOP_OVERLAY\r
  ModelUpdate25=1\r
-ModelTypeGroup2=SIM\r
-ModelTypeUpdate2=1\r
-ModelType26=SIM\r
-ModelName26=1N4148\r
+ModelType26=PCBLIB\r
+ModelName26=USB/ZX62-B-5PA\r
  ModelUpdate26=1\r
-ModelType27=SIM\r
-ModelName27=INDUCTOR\r
+ModelType27=PCBLIB\r
+ModelName27=WBC1\r
  ModelUpdate27=1\r
+ModelType28=PCBLIB\r
+ModelName28=Zentrier1\r
+ModelUpdate28=1\r
+ModelTypeGroup1=SI\r
+ModelTypeUpdate1=1\r
+ModelType29=SI\r
+ModelName29=1N4148\r
+ModelUpdate29=1\r
+ModelType30=SI\r
+ModelName30=Cap\r
+ModelUpdate30=1\r
+ModelType31=SI\r
+ModelName31=Connector\r
+ModelUpdate31=1\r
+ModelType32=SI\r
+ModelName32=Inductor\r
+ModelUpdate32=1\r
+ModelType33=SI\r
+ModelName33=Res\r
+ModelUpdate33=1\r
+ModelTypeGroup2=SIM\r
+ModelTypeUpdate2=1\r
+ModelType34=SIM\r
+ModelName34=1N4148\r
+ModelUpdate34=1\r
+ModelType35=SIM\r
+ModelName35=INDUCTOR\r
+ModelUpdate35=1\r
  \r
  [DatabaseUpdateOptions]\r
  SelectedOnly=0\r
diff --git a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcbStructure b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcbStructure

index 2dd5d62a8f17806a9fdc37827b2ed07334aebb8b..1e07fe8e773b2def2cb8c5a0af32df3d62efc1b6 100755 (executable)
--- a/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcbStructure
+++ b/MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcbStructure
@@ -1,54 +1,70 @@
  Record=TopLevelDocument|FileName=Main.SchDoc\r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FB|SchDesignator=FB|FileName=FPGA2.SchDoc|SymbolType=Normal|RawFileName=FPGA2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FC|SchDesignator=FC|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FD|SchDesignator=FD|FileName=Inputs.SchDoc|SymbolType=Normal|RawFileName=Inputs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FE|SchDesignator=FE|FileName=Inputs2.SchDoc|SymbolType=Normal|RawFileName=Inputs2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter1|SchDesignator=Filter1|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter2|SchDesignator=Filter2|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter3|SchDesignator=Filter3|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter4|SchDesignator=Filter4|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter5|SchDesignator=Filter5|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter6|SchDesignator=Filter6|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter7|SchDesignator=Filter7|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter8|SchDesignator=Filter8|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter9|SchDesignator=Filter9|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter10|SchDesignator=Filter10|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter11|SchDesignator=Filter11|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter12|SchDesignator=Filter12|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter13|SchDesignator=Filter13|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter14|SchDesignator=Filter14|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter15|SchDesignator=Filter15|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter16|SchDesignator=Filter16|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter17|SchDesignator=Filter17|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter18|SchDesignator=Filter18|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter19|SchDesignator=Filter19|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter20|SchDesignator=Filter20|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter21|SchDesignator=Filter21|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter22|SchDesignator=Filter22|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter23|SchDesignator=Filter23|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter24|SchDesignator=Filter24|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter25|SchDesignator=Filter25|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter26|SchDesignator=Filter26|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter27|SchDesignator=Filter27|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter28|SchDesignator=Filter28|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter29|SchDesignator=Filter29|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter30|SchDesignator=Filter30|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter31|SchDesignator=Filter31|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter32|SchDesignator=Filter32|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch1|SchDesignator=Ch1|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch2|SchDesignator=Ch2|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch3|SchDesignator=Ch3|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch4|SchDesignator=Ch4|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch5|SchDesignator=Ch5|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch6|SchDesignator=Ch6|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch7|SchDesignator=Ch7|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch8|SchDesignator=Ch8|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch9|SchDesignator=Ch9|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch10|SchDesignator=Ch10|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch11|SchDesignator=Ch11|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch12|SchDesignator=Ch12|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch13|SchDesignator=Ch13|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch14|SchDesignator=Ch14|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch15|SchDesignator=Ch15|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch16|SchDesignator=Ch16|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FB|SchDesignator=FB|FileName=FPGA2.SchDoc|SymbolType=Normal|RawFileName=FPGA2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FC|SchDesignator=FC|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FD|SchDesignator=FD|FileName=Inputs.SchDoc|SymbolType=Normal|RawFileName=Inputs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FE|SchDesignator=FE|FileName=Inputs2.SchDoc|SymbolType=Normal|RawFileName=Inputs2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter1|SchDesignator=Filter1|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter2|SchDesignator=Filter2|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter3|SchDesignator=Filter3|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter4|SchDesignator=Filter4|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter5|SchDesignator=Filter5|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter6|SchDesignator=Filter6|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter7|SchDesignator=Filter7|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter8|SchDesignator=Filter8|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter9|SchDesignator=Filter9|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter10|SchDesignator=Filter10|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter11|SchDesignator=Filter11|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter12|SchDesignator=Filter12|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter13|SchDesignator=Filter13|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter14|SchDesignator=Filter14|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter15|SchDesignator=Filter15|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter16|SchDesignator=Filter16|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter17|SchDesignator=Filter17|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter18|SchDesignator=Filter18|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter19|SchDesignator=Filter19|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter20|SchDesignator=Filter20|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter21|SchDesignator=Filter21|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter22|SchDesignator=Filter22|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter23|SchDesignator=Filter23|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter24|SchDesignator=Filter24|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter25|SchDesignator=Filter25|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter26|SchDesignator=Filter26|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter27|SchDesignator=Filter27|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter28|SchDesignator=Filter28|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter29|SchDesignator=Filter29|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter30|SchDesignator=Filter30|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter31|SchDesignator=Filter31|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=FPGA2.SchDoc|Designator=Filter32|SchDesignator=Filter32|FileName=Filter.SchDoc|SymbolType=Normal|RawFileName=Filter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch1|SchDesignator=Ch1|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch2|SchDesignator=Ch2|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch3|SchDesignator=Ch3|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch4|SchDesignator=Ch4|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch5|SchDesignator=Ch5|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch6|SchDesignator=Ch6|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch7|SchDesignator=Ch7|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Ch8|SchDesignator=Ch8|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int1|SchDesignator=Int1|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int2|SchDesignator=Int2|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int3|SchDesignator=Int3|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int4|SchDesignator=Int4|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int5|SchDesignator=Int5|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int6|SchDesignator=Int6|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int7|SchDesignator=Int7|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs.SchDoc|Designator=Int8|SchDesignator=Int8|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch9|SchDesignator=Ch9|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch10|SchDesignator=Ch10|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch11|SchDesignator=Ch11|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch12|SchDesignator=Ch12|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch13|SchDesignator=Ch13|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch14|SchDesignator=Ch14|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch15|SchDesignator=Ch15|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Ch16|SchDesignator=Ch16|FileName=Analog.SchDoc|SymbolType=Normal|RawFileName=Analog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int9|SchDesignator=Int9|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int10|SchDesignator=Int10|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int11|SchDesignator=Int11|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int12|SchDesignator=Int12|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int13|SchDesignator=Int13|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int14|SchDesignator=Int14|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int15|SchDesignator=Int15|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Inputs2.SchDoc|Designator=Int16|SchDesignator=Int16|FileName=AnalogIntegrator.SchDoc|SymbolType=Normal|RawFileName=AnalogIntegrator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=DBO|SchDesignator=DBO|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= \r
diff --git a/MdcFeeUtil/MdcAnalogWK/MdcFeeUtil.OutJob b/MdcFeeUtil/MdcAnalogWK/MdcFeeUtil.OutJob

index e398c9adcf0474e1002509976728b32f574c6dba..49efce51f4beccc653c81fb5a5f87119218a466b 100755 (executable)
--- a/MdcFeeUtil/MdcAnalogWK/MdcFeeUtil.OutJob
+++ b/MdcFeeUtil/MdcAnalogWK/MdcFeeUtil.OutJob
@@ -33,6 +33,8 @@ OutputMedium3=Assembly Files
  OutputMedium3_Type=GeneratedFiles\r
  OutputMedium4=Gerber Files\r
  OutputMedium4_Type=GeneratedFiles\r
+OutputMedium5=Test\r
+OutputMedium5_Type=Publish\r
  OutputType1=Schematic Print\r
  OutputName1=Schematic Prints\r
  OutputCategory1=Documentation\r
@@ -43,8 +45,9 @@ OutputEnabled1_OutputMedium1=0
  OutputEnabled1_OutputMedium2=1\r
  OutputEnabled1_OutputMedium3=0\r
  OutputEnabled1_OutputMedium4=0\r
+OutputEnabled1_OutputMedium5=0\r
  OutputDefault1=0\r
-PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=0.73|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration1_Name1=OutputConfigurationParameter1\r
  Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0\r
  OutputType2=PCB Print\r
@@ -57,8 +60,9 @@ OutputEnabled2_OutputMedium1=0
  OutputEnabled2_OutputMedium2=2\r
  OutputEnabled2_OutputMedium3=0\r
  OutputEnabled2_OutputMedium4=0\r
+OutputEnabled2_OutputMedium5=0\r
  OutputDefault2=0\r
-PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=2.29|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.70|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration2_Name1=OutputConfigurationParameter1\r
  Configuration2_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\r
  Configuration2_Name2=OutputConfigurationParameter2\r
@@ -142,6 +146,7 @@ OutputEnabled3_OutputMedium1=0
  OutputEnabled3_OutputMedium2=6\r
  OutputEnabled3_OutputMedium3=1\r
  OutputEnabled3_OutputMedium4=0\r
+OutputEnabled3_OutputMedium5=0\r
  OutputDefault3=0\r
  PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration3_Name1=ColumnNameFormat\r
@@ -166,6 +171,7 @@ OutputEnabled4_OutputMedium1=0
  OutputEnabled4_OutputMedium2=3\r
  OutputEnabled4_OutputMedium3=0\r
  OutputEnabled4_OutputMedium4=0\r
+OutputEnabled4_OutputMedium5=0\r
  OutputDefault4=0\r
  PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=2.56|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration4_Name1=OutputConfigurationParameter1\r
@@ -180,6 +186,7 @@ OutputEnabled5_OutputMedium1=0
  OutputEnabled5_OutputMedium2=4\r
  OutputEnabled5_OutputMedium3=0\r
  OutputEnabled5_OutputMedium4=0\r
+OutputEnabled5_OutputMedium5=0\r
  OutputDefault5=0\r
  PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=2.02|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration5_Name1=OutputConfigurationParameter1\r
@@ -194,6 +201,7 @@ OutputEnabled6_OutputMedium1=0
  OutputEnabled6_OutputMedium2=0\r
  OutputEnabled6_OutputMedium3=2\r
  OutputEnabled6_OutputMedium4=4\r
+OutputEnabled6_OutputMedium5=0\r
  OutputDefault6=0\r
  Configuration6_Name1=OutputConfigurationParameter1\r
  Configuration6_Item1=AssyAdjacencyDistance=250000|AssyGenerateCSVFormat=True|AssyGenerateIPCFormat=False|AssyGenerateSpreadSheetFormat=False|AssyGenerateTextFormat=False|AssyOriginPosition=Relative|AssyOutlineLayer=56|AssyOutputAdjancencies=False|AssyOutputBoardOutline=False|AssyOutputTraces=False|AssyReportBottomLayerTestpoints=True|AssyReportTopLayerTestpoints=True|AssyUnits=Metric|Record=TestPointView\r
@@ -207,8 +215,9 @@ OutputEnabled7_OutputMedium1=0
  OutputEnabled7_OutputMedium2=5\r
  OutputEnabled7_OutputMedium3=0\r
  OutputEnabled7_OutputMedium4=0\r
+OutputEnabled7_OutputMedium5=0\r
  OutputDefault7=0\r
-PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=2.26|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.67|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration7_Name1=OutputConfigurationParameter1\r
  Configuration7_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\r
  Configuration7_Name2=OutputConfigurationParameter2\r
@@ -246,6 +255,7 @@ OutputEnabled8_OutputMedium1=0
  OutputEnabled8_OutputMedium2=0\r
  OutputEnabled8_OutputMedium3=3\r
  OutputEnabled8_OutputMedium4=3\r
+OutputEnabled8_OutputMedium5=0\r
  OutputDefault8=0\r
  Configuration8_Name1=OutputConfigurationParameter1\r
  Configuration8_Item1=Record=PickPlaceView|Units=Metric|GenerateCSVFormat=True|GenerateTextFormat=False\r
@@ -259,6 +269,7 @@ OutputEnabled9_OutputMedium1=0
  OutputEnabled9_OutputMedium2=8\r
  OutputEnabled9_OutputMedium3=0\r
  OutputEnabled9_OutputMedium4=0\r
+OutputEnabled9_OutputMedium5=0\r
  OutputDefault9=0\r
  PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
  Configuration9_Name1=OutputConfigurationParameter1\r
@@ -273,6 +284,7 @@ OutputEnabled10_OutputMedium1=0
  OutputEnabled10_OutputMedium2=0\r
  OutputEnabled10_OutputMedium3=0\r
  OutputEnabled10_OutputMedium4=1\r
+OutputEnabled10_OutputMedium5=0\r
  OutputDefault10=0\r
  Configuration10_Name1=OutputConfigurationParameter1\r
  Configuration10_Item1=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=4|NumberOfUnits=4|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Metric|ZeroesMode=SuppressTrailingZeroes\r
@@ -286,6 +298,7 @@ OutputEnabled11_OutputMedium1=0
  OutputEnabled11_OutputMedium2=0\r
  OutputEnabled11_OutputMedium3=0\r
  OutputEnabled11_OutputMedium4=2\r
+OutputEnabled11_OutputMedium5=0\r
  OutputDefault11=0\r
  Configuration11_Name1=OutputConfigurationParameter1\r
  Configuration11_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set="Electrical Layers"|LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16973835~1,16973833~1,16973831~1,16908289~1,16973837~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False\r
@@ -299,6 +312,7 @@ OutputEnabled12_OutputMedium1=0
  OutputEnabled12_OutputMedium2=0\r
  OutputEnabled12_OutputMedium3=0\r
  OutputEnabled12_OutputMedium4=0\r
+OutputEnabled12_OutputMedium5=0\r
  OutputDefault12=0\r
  Configuration12_Name1=OutputConfigurationParameter1\r
  Configuration12_Item1=Record=ExportSTEPView|ExportComponentOptions=0|ExportModelsOption=2|ExportHolesOption=0|CanSelectPrimitives=False|IncludeMechanicalPadHoles=False|IncludeElectricalPadHoles=False|IncludeFreePadHoles=False|ExportFoldedBoard=True|ExportFoldedBoardRate=0|ComponentSuffixType=0|ComponentSuffix= |ExportCopperOption=0|ExportCopperLayer=1\r
@@ -312,6 +326,7 @@ OutputEnabled13_OutputMedium1=0
  OutputEnabled13_OutputMedium2=7\r
  OutputEnabled13_OutputMedium3=0\r
  OutputEnabled13_OutputMedium4=0\r
+OutputEnabled13_OutputMedium5=0\r
  OutputDefault13=0\r
  PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1\r
  Configuration13_Name1=ColumnNameFormat\r
@@ -328,6 +343,38 @@ Configuration13_Name6=SortOrder
  Configuration13_Item6=LibRef=Up\r
  Configuration13_Name7=VisibleOrder\r
  Configuration13_Item7=LibRef=170|Comment=170|Description=393|Footprint=141|OrderCode=164|GSI=67|Quantity=89\r
+OutputType14=Composite\r
+OutputName14=Composite Drawing\r
+OutputCategory14=Documentation\r
+OutputDocumentPath14=\r
+OutputVariantName14=\r
+OutputEnabled14=0\r
+OutputEnabled14_OutputMedium1=0\r
+OutputEnabled14_OutputMedium2=0\r
+OutputEnabled14_OutputMedium3=0\r
+OutputEnabled14_OutputMedium4=0\r
+OutputEnabled14_OutputMedium5=1\r
+OutputDefault14=0\r
+PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\r
+Configuration14_Name1=OutputConfigurationParameter1\r
+Configuration14_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\r
+Configuration14_Name2=OutputConfigurationParameter2\r
+Configuration14_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Top|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\r
+Configuration14_Name3=OutputConfigurationParameter3\r
+Configuration14_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical20|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\r
+Configuration14_Name4=OutputConfigurationParameter4\r
+Configuration14_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\r
+Configuration14_Name5=OutputConfigurationParameter5\r
+Configuration14_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\r
+Configuration14_Name6=OutputConfigurationParameter6\r
+Configuration14_Item6=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=1|Mirror=False|Name=Bottom|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\r
+Configuration14_Name7=OutputConfigurationParameter7\r
+Configuration14_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical21|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer\r
+Configuration14_Name8=OutputConfigurationParameter8\r
+Configuration14_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer\r
+Configuration14_Name9=OutputConfigurationParameter9\r
+Configuration14_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=200000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer\r
+PcbPrintPreferences14=SubsititueFont_Default=True|SubsititueFont_Serif=True|SubsititueFont_SansSerif=True|PrintKeepOuts=False|NetColorOverride=True|PrintPositivePlaneLayers=False|V7_M0.Name=Mechanical Layer 1|V7_M0.Value=True|V7_M1.Name=Mechanical Layer 2|V7_M1.Value=True|V7_M2.Name=Mechanical Layer 3|V7_M2.Value=True|V7_M3.Name=Mechanical Layer 4|V7_M3.Value=True|V7_M4.Name=Mechanical Layer 5|V7_M4.Value=True|V7_M5.Name=Mechanical Layer 6|V7_M5.Value=True|V7_M6.Name=Mechanical Layer 7|V7_M6.Value=True|V7_M7.Name=Mechanical Layer 8|V7_M7.Value=True|V7_M8.Name=Mechanical Layer 9|V7_M8.Value=True|V7_M9.Name=Mechanical Layer 10|V7_M9.Value=True|V7_M10.Name=Mechanical Layer 11|V7_M10.Value=True|V7_M11.Name=Mechanical Layer 12|V7_M11.Value=True|V7_M12.Name=Mechanical Layer 13|V7_M12.Value=True|V7_M13.Name=Mechanical Layer 14|V7_M13.Value=True|V7_M14.Name=Mechanical Layer 15|V7_M14.Value=True|V7_M15.Name=Mechanical Layer 16|V7_M15.Value=True|V7_G0.Name=Top Layer|V7_G0.Value=30|V7_G1.Name=Mid Layer 1|V7_G1.Value=60|V7_G2.Name=Mid Layer 2|V7_G2.Value=90|V7_G3.Name=Mid Layer 3|V7_G3.Value=120|V7_G4.Name=Mid Layer 4|V7_G4.Value=150|V7_G5.Name=Mid Layer 5|V7_G5.Value=180|V7_G6.Name=Mid Layer 6|V7_G6.Value=210|V7_G7.Name=Mid Layer 7|V7_G7.Value=60|V7_G8.Name=Mid Layer 8|V7_G8.Value=90|V7_G9.Name=Mid Layer 9|V7_G9.Value=120|V7_G10.Name=Mid Layer 10|V7_G10.Value=150|V7_G11.Name=Mid Layer 11|V7_G11.Value=180|V7_G12.Name=Mid Layer 12|V7_G12.Value=210|V7_G13.Name=Mid Layer 13|V7_G13.Value=60|V7_G14.Name=Mid Layer 14|V7_G14.Value=95|V7_G15.Name=Mid Layer 15|V7_G15.Value=60|V7_G16.Name=Mid Layer 16|V7_G16.Value=90|V7_G17.Name=Mid Layer 17|V7_G17.Value=120|V7_G18.Name=Mid Layer 18|V7_G18.Value=150|V7_G19.Name=Mid Layer 19|V7_G19.Value=180|V7_G20.Name=Mid Layer 20|V7_G20.Value=210|V7_G21.Name=Mid Layer 21|V7_G21.Value=60|V7_G22.Name=Mid Layer 22|V7_G22.Value=90|V7_G23.Name=Mid Layer 23|V7_G23.Value=120|V7_G24.Name=Mid Layer 24|V7_G24.Value=150|V7_G25.Name=Mid Layer 25|V7_G25.Value=180|V7_G26.Name=Mid Layer 26|V7_G26.Value=210|V7_G27.Name=Mid Layer 27|V7_G27.Value=60|V7_G28.Name=Mid Layer 28|V7_G28.Value=95|V7_G29.Name=Mid Layer 29|V7_G29.Value=60|V7_G30.Name=Mid Layer 30|V7_G30.Value=95|V7_G31.Name=Bottom Layer|V7_G31.Value=90|V7_G32.Name=Top Overlay|V7_G32.Value=192|V7_G33.Name=Bottom Overlay|V7_G33.Value=140|V7_G34.Name=Top Paste|V7_G34.Value=0|V7_G35.Name=Bottom Paste|V7_G35.Value=0|V7_G36.Name=Top Solder Mask|V7_G36.Value=0|V7_G37.Name=Bottom Solder Mask|V7_G37.Value=0|V7_G38.Name=Drill Guide|V7_G38.Value=0|V7_G39.Name=Keep Out Layer|V7_G39.Value=120|V7_G40.Name=Drill Drawing|V7_G40.Value=0|V7_G41.Name=Multi Layer|V7_G41.Value=0|V7_G42.Name=Connect Layer|V7_G42.Value=0|V7_G43.Name=BackGround|V7_G43.Value=255|V7_G44.Name=DRC Errors|V7_G44.Value=0|V7_G45.Name=Highlight Layer|V7_G45.Value=0|V7_G46.Name=Grid Color 1|V7_G46.Value=0|V7_G47.Name=Grid Color 10|V7_G47.Value=0|V7_G48.Name=Pad Hole Layer|V7_G48.Value=210|V7_G49.Name=Via Hole Layer|V7_G49.Value=210|V7_G50.Name=Mechanical Layers|V7_G50.Value=90|V7_G51.Name=Internal Plane Layers|V7_G51.Value=0|V7_G52.Name=Internal Plane 1|V7_G52.Value=0|V7_G53.Name=Internal Plane 2|V7_G53.Value=0|V7_G54.Name=Internal Plane 3|V7_G54.Value=0|V7_G55.Name=Internal Plane 4|V7_G55.Value=0|V7_G56.Name=Internal Plane 5|V7_G56.Value=0|V7_G57.Name=Internal Plane 6|V7_G57.Value=0|V7_G58.Name=Internal Plane 7|V7_G58.Value=0|V7_G59.Name=Internal Plane 8|V7_G59.Value=0|V7_G60.Name=Internal Plane 9|V7_G60.Value=0|V7_G61.Name=Internal Plane 10|V7_G61.Value=0|V7_G62.Name=Internal Plane 11|V7_G62.Value=0|V7_G63.Name=Internal Plane 12|V7_G63.Value=0|V7_G64.Name=Internal Plane 13|V7_G64.Value=0|V7_G65.Name=Internal Plane 14|V7_G65.Value=0|V7_G66.Name=Internal Plane 15|V7_G66.Value=0|V7_G67.Name=Internal Plane 16|V7_G67.Value=0|V7_G68.Name=Mechanical Layer 1|V7_G68.Value=90|V7_G69.Name=Mechanical Layer 2|V7_G69.Value=90|V7_G70.Name=Mechanical Layer 3|V7_G70.Value=90|V7_G71.Name=Mechanical Layer 4|V7_G71.Value=90|V7_G72.Name=Mechanical Layer 5|V7_G72.Value=90|V7_G73.Name=Mechanical Layer 6|V7_G73.Value=90|V7_G74.Name=Mechanical Layer 7|V7_G74.Value=90|V7_G75.Name=Mechanical Layer 8|V7_G75.Value=90|V7_G76.Name=Mechanical Layer 9|V7_G76.Value=90|V7_G77.Name=Mechanical Layer 10|V7_G77.Value=90|V7_G78.Name=Mechanical Layer 11|V7_G78.Value=90|V7_G79.Name=Mechanical Layer 12|V7_G79.Value=90|V7_G80.Name=Mechanical Layer 13|V7_G80.Value=90|V7_G81.Name=Mechanical Layer 14|V7_G81.Value=90|V7_G82.Name=Mechanical Layer 15|V7_G82.Value=90|V7_G83.Name=Mechanical Layer 16|V7_G83.Value=90|V7_C0.Name=Mid Layer 1|V7_C0.Value=36540|V7_C1.Name=Mid Layer 2|V7_C1.Value=16440176|V7_C2.Name=Mid Layer 3|V7_C2.Value=6736896|V7_C3.Name=Mid Layer 4|V7_C3.Value=16737945|V7_C4.Name=Mid Layer 5|V7_C4.Value=10342018|V7_C5.Name=Mid Layer 6|V7_C5.Value=8388736|V7_C6.Name=Mid Layer 7|V7_C6.Value=16711935|V7_C7.Name=Mid Layer 8|V7_C7.Value=32896|V7_C8.Name=Mid Layer 9|V7_C8.Value=65535|V7_C9.Name=Mid Layer 10|V7_C9.Value=8421504|V7_C10.Name=Mid Layer 11|V7_C10.Value=16777215|V7_C11.Name=Mid Layer 12|V7_C11.Value=8388736|V7_C12.Name=Mid Layer 13|V7_C12.Value=8421376|V7_C13.Name=Mid Layer 14|V7_C13.Value=12632256|V7_C14.Name=Mid Layer 15|V7_C14.Value=128|V7_C15.Name=Mid Layer 16|V7_C15.Value=32768|V7_C16.Name=Mid Layer 17|V7_C16.Value=65280|V7_C17.Name=Mid Layer 18|V7_C17.Value=8388608|V7_C18.Name=Mid Layer 19|V7_C18.Value=16776960|V7_C19.Name=Mid Layer 20|V7_C19.Value=8388736|V7_C20.Name=Mid Layer 21|V7_C20.Value=16711935|V7_C21.Name=Mid Layer 22|V7_C21.Value=32896|V7_C22.Name=Mid Layer 23|V7_C22.Value=65535|V7_C23.Name=Mid Layer 24|V7_C23.Value=8421504|V7_C24.Name=Mid Layer 25|V7_C24.Value=16777215|V7_C25.Name=Mid Layer 26|V7_C25.Value=8388736|V7_C26.Name=Mid Layer 27|V7_C26.Value=8421376|V7_C27.Name=Mid Layer 28|V7_C27.Value=12632256|V7_C28.Name=Mid Layer 29|V7_C28.Value=128|V7_C29.Name=Mid Layer 30|V7_C29.Value=32768|V7_C30.Name=Top Overlay|V7_C30.Value=65535|V7_C31.Name=Bottom Overlay|V7_C31.Value=65535|V7_C32.Name=Top Paste|V7_C32.Value=8421504|V7_C33.Name=Top Solder Mask|V7_C33.Value=8388736|V7_C34.Name=Bottom Solder Mask|V7_C34.Value=16711935|V7_C35.Name=Keep Out Layer|V7_C35.Value=16711935|V7_C36.Name=Mechanical Layer 1|V7_C36.Value=16711935|V7_C37.Name=Mechanical Layer 2|V7_C37.Value=8388736|V7_C38.Name=Mechanical Layer 4|V7_C38.Value=32896|V7_C39.Name=Mechanical Layer 5|V7_C39.Value=16711935|V7_C40.Name=Mechanical Layer 6|V7_C40.Value=8388736|V7_C41.Name=Mechanical Layer 8|V7_C41.Value=32896|V7_C42.Name=Mechanical Layer 9|V7_C42.Value=16711935|V7_C43.Name=Mechanical Layer 10|V7_C43.Value=8388736|V7_C44.Name=Mechanical Layer 12|V7_C44.Value=32896|V7_C45.Name=Mechanical Layer 13|V7_C45.Value=16711935|V7_C46.Name=Mechanical Layer 14|V7_C46.Value=8388736|V7_C47.Name=Drill Drawing|V7_C47.Value=2752767|V7_C48.Name=Multi Layer|V7_C48.Value=12632256|V7_C49.Name=Grid Color 10|V7_C49.Value=8287349|V7_C50.Name=Mechanical Layer 30|V7_C50.Value=8388736|V7_C51.Name=Mechanical Layer 29|V7_C51.Value=16711935|V7_C52.Name=Mechanical Layer 28|V7_C52.Value=32896|V7_C53.Name=Mechanical Layer 26|V7_C53.Value=8388736|V7_C54.Name=Mechanical Layer 25|V7_C54.Value=16711935|V7_C55.Name=Mechanical Layer 24|V7_C55.Value=32896|V7_C56.Name=Mechanical Layer 22|V7_C56.Value=8388736|V7_C57.Name=Mechanical Layer 21|V7_C57.Value=0|V7_C58.Name=Mechanical Layer 18|V7_C58.Value=8388736|V7_C59.Name=Mechanical Layer 17|V7_C59.Value=16711935|Mechanical1=True|Mechanical2=True|Mechanical3=True|Mechanical4=True|Mechanical5=True|Mechanical6=True|Mechanical7=True|Mechanical8=True|Mechanical9=True|Mechanical10=True|Mechanical11=True|Mechanical12=True|Mechanical13=True|Mechanical14=True|Mechanical15=True|Mechanical16=True|Gray Level For TopLayer=30|Gray Level For MidLayer1=60|Gray Level For MidLayer2=90|Gray Level For MidLayer3=120|Gray Level For MidLayer4=150|Gray Level For MidLayer5=180|Gray Level For MidLayer6=210|Gray Level For MidLayer7=60|Gray Level For MidLayer8=90|Gray Level For MidLayer9=120|Gray Level For MidLayer10=150|Gray Level For MidLayer11=180|Gray Level For MidLayer12=210|Gray Level For MidLayer13=60|Gray Level For MidLayer14=95|Gray Level For MidLayer15=60|Gray Level For MidLayer16=90|Gray Level For MidLayer17=120|Gray Level For MidLayer18=150|Gray Level For MidLayer19=180|Gray Level For MidLayer20=210|Gray Level For MidLayer21=60|Gray Level For MidLayer22=90|Gray Level For MidLayer23=120|Gray Level For MidLayer24=150|Gray Level For MidLayer25=180|Gray Level For MidLayer26=210|Gray Level For MidLayer27=60|Gray Level For MidLayer28=95|Gray Level For MidLayer29=60|Gray Level For MidLayer30=95|Gray Level For BottomLayer=90|Gray Level For TopOverlay=192|Gray Level For BottomOverlay=140|Gray Level For TopPaste=0|Gray Level For BottomPaste=0|Gray Level For TopSolder=0|Gray Level For BottomSolder=0|Gray Level For InternalPlane1=0|Gray Level For InternalPlane2=0|Gray Level For InternalPlane3=0|Gray Level For InternalPlane4=0|Gray Level For InternalPlane5=0|Gray Level For InternalPlane6=0|Gray Level For InternalPlane7=0|Gray Level For InternalPlane8=0|Gray Level For InternalPlane9=0|Gray Level For InternalPlane10=0|Gray Level For InternalPlane11=0|Gray Level For InternalPlane12=0|Gray Level For InternalPlane13=0|Gray Level For InternalPlane14=0|Gray Level For InternalPlane15=0|Gray Level For InternalPlane16=0|Gray Level For DrillGuide=0|Gray Level For KeepOutLayer=120|Gray Level For Mechanical1=90|Gray Level For Mechanical2=90|Gray Level For Mechanical3=90|Gray Level For Mechanical4=90|Gray Level For Mechanical5=90|Gray Level For Mechanical6=90|Gray Level For Mechanical7=90|Gray Level For Mechanical8=90|Gray Level For Mechanical9=90|Gray Level For Mechanical10=90|Gray Level For Mechanical11=90|Gray Level For Mechanical12=90|Gray Level For Mechanical13=90|Gray Level For Mechanical14=90|Gray Level For Mechanical15=90|Gray Level For Mechanical16=90|Gray Level For DrillDrawing=0|Gray Level For MultiLayer=0|Gray Level For ConnectLayer=0|Gray Level For BackGroundLayer=255|Gray Level For DRCErrorLayer=0|Gray Level For HighlightLayer=0|Gray Level For GridColor1=0|Gray Level For GridColor10=0|Gray Level For PadHoleLayer=210|Gray Level For ViaHoleLayer=210|Color For TopLayer=255|Color For MidLayer1=36540|Color For MidLayer2=16440176|Color For MidLayer3=6736896|Color For MidLayer4=16737945|Color For MidLayer5=10342018|Color For MidLayer6=8388736|Color For MidLayer7=16711935|Color For MidLayer8=32896|Color For MidLayer9=65535|Color For MidLayer10=8421504|Color For MidLayer11=16777215|Color For MidLayer12=8388736|Color For MidLayer13=8421376|Color For MidLayer14=12632256|Color For MidLayer15=128|Color For MidLayer16=32768|Color For MidLayer17=65280|Color For MidLayer18=8388608|Color For MidLayer19=16776960|Color For MidLayer20=8388736|Color For MidLayer21=16711935|Color For MidLayer22=32896|Color For MidLayer23=65535|Color For MidLayer24=8421504|Color For MidLayer25=16777215|Color For MidLayer26=8388736|Color For MidLayer27=8421376|Color For MidLayer28=12632256|Color For MidLayer29=128|Color For MidLayer30=32768|Color For BottomLayer=16711680|Color For TopOverlay=65535|Color For BottomOverlay=65535|Color For TopPaste=8421504|Color For BottomPaste=128|Color For TopSolder=8388736|Color For BottomSolder=16711935|Color For InternalPlane1=32768|Color For InternalPlane2=128|Color For InternalPlane3=8388736|Color For InternalPlane4=8421376|Color For InternalPlane5=32768|Color For InternalPlane6=128|Color For InternalPlane7=8388736|Color For InternalPlane8=8421376|Color For InternalPlane9=32768|Color For InternalPlane10=128|Color For InternalPlane11=8388736|Color For InternalPlane12=8421376|Color For InternalPlane13=32768|Color For InternalPlane14=128|Color For InternalPlane15=8388736|Color For InternalPlane16=8421376|Color For DrillGuide=128|Color For KeepOutLayer=16711935|Color For Mechanical1=16711935|Color For Mechanical2=8388736|Color For Mechanical3=32768|Color For Mechanical4=32896|Color For Mechanical5=16711935|Color For Mechanical6=8388736|Color For Mechanical7=32768|Color For Mechanical8=32896|Color For Mechanical9=16711935|Color For Mechanical10=8388736|Color For Mechanical11=32768|Color For Mechanical12=32896|Color For Mechanical13=16711935|Color For Mechanical14=8388736|Color For Mechanical15=32768|Color For Mechanical16=0|Color For DrillDrawing=2752767|Color For MultiLayer=12632256|Color For ConnectLayer=8421376|Color For BackGroundLayer=15269887|Color For DRCErrorLayer=65280|Color For HighlightLayer=65535|Color For GridColor1=12632256|Color For GridColor10=8287349|Color For PadHoleLayer=6899487|Color For ViaHoleLayer=9279142\r
  \r
  [PublishSettings]\r
  OutputFilePath2=\\vmware-host\Shared Folders\local\Elektronik\Projekte\MdcFeeUtil\MdcAnalogWK\Project Outputs\MdcAnalogWK.PDF\r
@@ -381,6 +428,30 @@ OutputFileNameMulti4=
  UseOutputNameForMulti4=1\r
  OutputFileNameSpecial4=\r
  OpenOutput4=0\r
+OutputFilePath5=\\vmware-host\Shared Folders\local\Elektronik\Projekte\MdcFeeUtil\MdcAnalogWK\Project Outputs for MdcAnalogWK\MdcFeeUtil.PDF\r
+ReleaseManaged5=1\r
+OutputBasePath5=Project Outputs for MdcAnalogWK\r
+OutputPathMedia5=\r
+OutputPathMediaValue5=\r
+OutputPathOutputer5=[Output Type]\r
+OutputPathOutputerPrefix5=\r
+OutputPathOutputerValue5=\r
+OutputFileName5=MdcFeeUtil.PDF\r
+OutputFileNameMulti5=\r
+UseOutputNameForMulti5=1\r
+OutputFileNameSpecial5=\r
+OpenOutput5=0\r
+PromptOverwrite5=1\r
+PublishMethod5=0\r
+ZoomLevel5=50\r
+FitSCHPrintSizeToDoc5=1\r
+FitPCBPrintSizeToDoc5=1\r
+GenerateNetsInfo5=1\r
+MarkPins5=1\r
+MarkNetLabels5=1\r
+MarkPortsId5=1\r
+ShowComponentParameters5=1\r
+GlobalBookmarks5=0\r
  \r
  [GeneratedFilesSettings]\r
  RelativeOutputPath2=\\vmware-host\Shared Folders\local\Elektronik\Projekte\MdcFeeUtil\MdcAnalogWK\Project Outputs\MdcAnalogWK.PDF\r
@@ -405,4 +476,6 @@ OpenGerberOutput4=0
  OpenNCDrillOutput4=0\r
  OpenIPCOutput4=0\r
  EnableReload4=0\r
+RelativeOutputPath5=\\vmware-host\Shared Folders\local\Elektronik\Projekte\MdcFeeUtil\MdcAnalogWK\Project Outputs for MdcAnalogWK\MdcFeeUtil.PDF\r
+OpenOutputs5=0\r
  \r
diff --git a/MdcFeeUtil/MdcAnalogWK/PCB.PcbDoc b/MdcFeeUtil/MdcAnalogWK/PCB.PcbDoc

index faa1b35cf04247e650540f77f9e1425d8b3e7666..3e7a8a9becaf722418b620524d54c6922effdd10 100755 (executable)

Binary files a/MdcFeeUtil/MdcAnalogWK/PCB.PcbDoc and b/MdcFeeUtil/MdcAnalogWK/PCB.PcbDoc differ
author	Maps <maps@ikf>
	Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)
committer	Maps <maps@ikf>
	Wed, 28 Mar 2018 14:33:11 +0000 (16:33 +0200)
MdcFeeUtil/MdcAnalogWK/Analog.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/FPGA.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/FPGA2.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/FPGA_Power.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/Filter.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/Inputs.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/Inputs2.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/Main.SchDoc		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.Annotation		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcb		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/MdcAnalogWK.PrjPcbStructure		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/MdcFeeUtil.OutJob		patch \| blob \| history
MdcFeeUtil/MdcAnalogWK/PCB.PcbDoc		patch \| blob \| history