*** empty log message ***

diff --git a/testbenches/tb_fifo_18bit.vhd b/testbenches/tb_fifo_18bit.vhd
new file mode 100755 (executable)
index 0000000..d0650a4
--- /dev/null
+++ b/testbenches/tb_fifo_18bit.vhd
@@ -0,0 +1,132 @@
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+       COMPONENT trb_net_fifo_18bit_bram_dualport\r
+       PORT(\r
+               READ_CLOCK_IN : IN std_logic;\r
+               WRITE_CLOCK_IN : IN std_logic;\r
+               READ_ENABLE_IN : IN std_logic;\r
+               WRITE_ENABLE_IN : IN std_logic;\r
+               FIFO_GSR_IN : IN std_logic;\r
+               WRITE_DATA_IN : IN std_logic_vector(17 downto 0);          \r
+               READ_DATA_OUT : OUT std_logic_vector(17 downto 0);\r
+               FULL_OUT : OUT std_logic;\r
+               EMPTY_OUT : OUT std_logic;\r
+               WCNT_OUT : OUT std_logic_vector(9 downto 0);\r
+               RCNT_OUT : OUT std_logic_vector(9 downto 0)\r
+               );\r
+       END COMPONENT;\r
+\r
+       SIGNAL READ_CLOCK_IN :  std_logic;\r
+       SIGNAL WRITE_CLOCK_IN :  std_logic;\r
+       SIGNAL READ_ENABLE_IN :  std_logic;\r
+       SIGNAL WRITE_ENABLE_IN :  std_logic;\r
+       SIGNAL FIFO_GSR_IN :  std_logic;\r
+       SIGNAL WRITE_DATA_IN :  std_logic_vector(17 downto 0);\r
+       SIGNAL READ_DATA_OUT :  std_logic_vector(17 downto 0);\r
+       SIGNAL FULL_OUT :  std_logic;\r
+       SIGNAL EMPTY_OUT :  std_logic;\r
+       SIGNAL WCNT_OUT :  std_logic_vector(9 downto 0);\r
+       SIGNAL RCNT_OUT :  std_logic_vector(9 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+       uut: trb_net_fifo_18bit_bram_dualport PORT MAP(\r
+               READ_CLOCK_IN => READ_CLOCK_IN,\r
+               WRITE_CLOCK_IN => WRITE_CLOCK_IN,\r
+               READ_ENABLE_IN => READ_ENABLE_IN,\r
+               WRITE_ENABLE_IN => WRITE_ENABLE_IN,\r
+               FIFO_GSR_IN => FIFO_GSR_IN,\r
+               WRITE_DATA_IN => WRITE_DATA_IN,\r
+               READ_DATA_OUT => READ_DATA_OUT,\r
+               FULL_OUT => FULL_OUT,\r
+               EMPTY_OUT => EMPTY_OUT,\r
+               WCNT_OUT => WCNT_OUT,\r
+               RCNT_OUT => RCNT_OUT\r
+       );\r
+\r
+-- Write clock (25MHz)\r
+WRITE_CLOCK_GEN: process\r
+begin\r
+       write_clock_in <= '1'; wait for 20.1 ns;\r
+       write_clock_in <= '0'; wait for 20.1 ns;\r
+end process WRITE_CLOCK_GEN;\r
+\r
+-- Read clock (100MHz)\r
+READ_CLOCK_GEN: process\r
+begin\r
+       read_clock_in <= '1'; wait for 4.9 ns;\r
+       read_clock_in <= '0'; wait for 4.9 ns;\r
+end process READ_CLOCK_GEN;\r
+\r
+-- Testbench\r
+THE_TESTBENCH: process\r
+begin\r
+       -- Setup signals\r
+       read_enable_in <= '0';\r
+       write_enable_in <= '0';\r
+       fifo_gsr_in <= '0';\r
+       write_data_in <= (others => '0');\r
+\r
+       wait for 20 ns;\r
+       \r
+       -- Reset the whole stuff\r
+       fifo_gsr_in <= '1'; wait for 33 ns;\r
+       fifo_gsr_in <= '0'; wait for 55 ns;\r
+       \r
+       -- Tests may start now...\r
+       wait until rising_edge(write_clock_in);\r
+       write_enable_in <= '1';\r
+       write_data_in <= b"11_1111_1111_0000_0000";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0001";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0010";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0011";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0100";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0101";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0110";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_0111";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_1000";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"11_1111_1111_0000_1001";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= b"00_0000_0000_0000_0000";\r
+       write_enable_in <= '0';\r
+       \r
+       wait for 333 ns;\r
+       \r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '1';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '0';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '1';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '0';\r
+       wait until rising_edge(read_clock_in);\r
+       \r
+       \r
+       -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+       wait;\r
+       \r
+end process THE_TESTBENCH;\r
+\r
+END;\r

diff --git a/testbenches/tb_fifo_8b16b.vhd b/testbenches/tb_fifo_8b16b.vhd
new file mode 100755 (executable)
index 0000000..8db5e08
--- /dev/null
+++ b/testbenches/tb_fifo_8b16b.vhd
@@ -0,0 +1,138 @@
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+       COMPONENT trb_net_fifo_8bit_16bit_bram_dualport\r
+       PORT(\r
+               READ_CLOCK_IN : IN std_logic;\r
+               WRITE_CLOCK_IN : IN std_logic;\r
+               READ_ENABLE_IN : IN std_logic;\r
+               WRITE_ENABLE_IN : IN std_logic;\r
+               FIFO_GSR_IN : IN std_logic;\r
+               WRITE_DATA_IN : IN std_logic_vector(7 downto 0);          \r
+               READ_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+               FULL_OUT : OUT std_logic;\r
+               EMPTY_OUT : OUT std_logic;\r
+               WCNT_OUT : OUT std_logic_vector(9 downto 0);\r
+               RCNT_OUT : OUT std_logic_vector(8 downto 0)\r
+               );\r
+       END COMPONENT;\r
+\r
+       SIGNAL READ_CLOCK_IN :  std_logic;\r
+       SIGNAL WRITE_CLOCK_IN :  std_logic;\r
+       SIGNAL READ_ENABLE_IN :  std_logic;\r
+       SIGNAL WRITE_ENABLE_IN :  std_logic;\r
+       SIGNAL FIFO_GSR_IN :  std_logic;\r
+       SIGNAL WRITE_DATA_IN :  std_logic_vector(7 downto 0);\r
+       SIGNAL READ_DATA_OUT :  std_logic_vector(15 downto 0);\r
+       SIGNAL FULL_OUT :  std_logic;\r
+       SIGNAL EMPTY_OUT :  std_logic;\r
+       SIGNAL WCNT_OUT :  std_logic_vector(9 downto 0);\r
+       SIGNAL RCNT_OUT :  std_logic_vector(8 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+       uut: trb_net_fifo_8bit_16bit_bram_dualport PORT MAP(\r
+               READ_CLOCK_IN => READ_CLOCK_IN,\r
+               WRITE_CLOCK_IN => WRITE_CLOCK_IN,\r
+               READ_ENABLE_IN => READ_ENABLE_IN,\r
+               WRITE_ENABLE_IN => WRITE_ENABLE_IN,\r
+               FIFO_GSR_IN => FIFO_GSR_IN,\r
+               WRITE_DATA_IN => WRITE_DATA_IN,\r
+               READ_DATA_OUT => READ_DATA_OUT,\r
+               FULL_OUT => FULL_OUT,\r
+               EMPTY_OUT => EMPTY_OUT,\r
+               WCNT_OUT => WCNT_OUT,\r
+               RCNT_OUT => RCNT_OUT\r
+       );\r
+\r
+-- Write clock (25MHz)\r
+WRITE_CLOCK_GEN: process\r
+begin\r
+       write_clock_in <= '1'; wait for 20.1 ns;\r
+       write_clock_in <= '0'; wait for 20.1 ns;\r
+end process WRITE_CLOCK_GEN;\r
+\r
+-- Read clock (100MHz)\r
+READ_CLOCK_GEN: process\r
+begin\r
+       read_clock_in <= '1'; wait for 4.9 ns;\r
+       read_clock_in <= '0'; wait for 4.9 ns;\r
+end process READ_CLOCK_GEN;\r
+\r
+-- Testbench\r
+THE_TESTBENCH: process\r
+begin\r
+       -- Setup signals\r
+       read_enable_in <= '0';\r
+       write_enable_in <= '0';\r
+       fifo_gsr_in <= '0';\r
+       write_data_in <= (others => '0');\r
+\r
+       wait for 20 ns;\r
+       \r
+       -- Reset the whole stuff\r
+       fifo_gsr_in <= '1'; wait for 33 ns;\r
+       fifo_gsr_in <= '0'; wait for 55 ns;\r
+       \r
+       -- Tests may start now...\r
+       wait until rising_edge(write_clock_in);\r
+       write_enable_in <= '1';\r
+       write_data_in <= x"01";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"02";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"03";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"04";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"05";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"06";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"07";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"08";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"09";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"0a";\r
+       wait until rising_edge(write_clock_in);\r
+       write_data_in <= x"0b";\r
+       write_enable_in <= '0';\r
+       \r
+       wait for 333 ns;\r
+       \r
+       -- Reset the whole stuff\r
+       fifo_gsr_in <= '1'; wait for 33 ns;\r
+       fifo_gsr_in <= '0'; wait for 55 ns;\r
+       \r
+       \r
+       \r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '1';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '0';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '1';\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       wait until rising_edge(read_clock_in);\r
+       read_enable_in <= '0';\r
+       wait until rising_edge(read_clock_in);\r
+       \r
+       \r
+       -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+       wait;\r
+       \r
+end process THE_TESTBENCH;\r
+\r
+END;\r