corrected

diff --git a/cts.tex b/cts.tex
index cb7ace71158fa1abfe36102ba8f7a028e54c11a7..b10bcd10703bf58d1783287b72b6722129267bf7 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -12,8 +12,6 @@
 For all registers described in this subsection refer to the Fig.\ref{cts_logic}
 \begin{description}
 
-\item[RW registers] of the trigger logic
-  \begin{description}
   \item [0xA0CC] Individual bits are enabling inputs 
   \item [0xA0D1 - 0xA0D4] Delay input signals, each nibble corresponds to one input e.g. 0xA0D1(3 to 0) corresponds to first input of the start part (Start 0). Delay value = 4 bit value * clock period (5ns)
   \item [0xA0CD - 0xA0CE] Downscale input signals,  each input signal is downscaled - $2^{value}$
@@ -39,12 +37,8 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
   \item [0xA0DC bit 6] Force update Shower pedestals trigger (write ..1..0)
   \item [0xA0DC bit 7] Disable Shower pedestals update (generated once during each spill off)
   \item [0xA0DC 11 down to 8] Select frequency for internally generated trigger - $781.25kHz/(2^value)$
-  \end{description}
-\item[R registers] of the trigger logic
-  \begin{description}
   \item [0xA089] Trigger logic debug out
   \item [0xA09B -0xA0BA] Scalers out 
-  \end{description}
 \end{description}
 
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