change CTS to variable trigger logic output number

diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf
index 3fcc7b1eb0fd3cb984af9a44231a8facd826ec68..fe5ce1ff5d9fb880d2a8c85bcaacc60ed0c57557 100644 (file)
--- a/cts/trb3sc_cts.lpf
+++ b/cts/trb3sc_cts.lpf
@@ -13,6 +13,7 @@ LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE
 BLOCK PATH FROM CELL THE_TDC/calibration_o*;
 BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*;
 BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0];
+BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/edge_rising_100_r[0];
 
 # REGION         "MEDIA_GBE" "R89C2" 25 53;
 REGION         "MEDIA_A" "R75C100D"  45 46;
@@ -117,6 +118,12 @@ MAXDELAY   TO ASIC  gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns
 #MULTICYCLE TO ASIC  gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
 #MAXDELAY   TO ASIC  gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
 
+MULTICYCLE FROM ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+
+
+
 PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; 
 
 # PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_rx_full" ;

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index d03e6e60437e76f5d37eac7cca353d536d7a1a05..257c562dad5f7ab0c67553b4e61bf6752135e730 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -931,19 +931,19 @@ end generate;
 gen_inputs_kel : if USE_BACKPLANE = 0 and USE_RJADAPT = 0 generate        
   cts_addon_triggers_in(1 downto 0)  <= SPARE_IN(1 downto 0);
   cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
-  cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+  cts_addon_triggers_in(34 + TRIG_GEN_OUTPUT_NUM - 1 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
 end generate;
 gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate        
   cts_addon_triggers_in(1 downto 0)  <= SPARE_IN(1 downto 0);
   cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0);
-  cts_addon_triggers_in(23 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+  cts_addon_triggers_in(22 + TRIG_GEN_OUTPUT_NUM - 1 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys);
 end generate;
 gen_inputs_bkpl : if USE_BACKPLANE = 1 generate        
   cts_addon_triggers_in(1 downto 0)  <= SPARE_IN(1 downto 0);
   cts_addon_triggers_in(33 downto 2) <= INP(95 downto 64);
-  cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);  
+  cts_addon_triggers_in(34 + TRIG_GEN_OUTPUT_NUM - 1 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);  
   gen_trg_inputs : for i in 0 to 8 generate
-    cts_addon_triggers_in(i*2+37 downto i*2+36) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+    cts_addon_triggers_in(i*2+34 + TRIG_GEN_OUTPUT_NUM - 1 downto i*2+34+TRIG_GEN_OUTPUT_NUM) <= BACK_TRIG2(i) & BACK_TRIG1(i);
   end generate;   
 
 end generate;