--- /dev/null
+NOTE "CREATOR" "Xilinx iMPACT Software";
+NOTE "DATE" "2012/11/24";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "ALG_VERSION" "1";
+NOTE "DEVICE" "UNSPECIFIED";
+NOTE "CHECKSUM" "UNSPECIFIED";
+NOTE "IDCODE" "UNSPECIFIED";
+NOTE "USERCODE" "UNSPECIFIED";
+NOTE "TARGET" "UNSPECIFIED";
+NOTE "STACK_DEPTH" "4";
+NOTE "MAX_FREQ" "1000000";
+ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC;
+DATA MAINDATA;
+INTEGER I = 0;
+INTEGER D = 0;
+ENDDATA;
+PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA;
+BOOLEAN X = 0;
+IRSTOP IDLE;
+DRSTOP IDLE;
+STATE RESET IDLE;
+' //Operation: Program -p 0 -defaultVersion 0
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Boundary Scan Chain Contents
+' //Position 1: xc4vlx40
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' // Loading device with a `jprogram` instruction.
+IRSCAN 10, $03cb
+ ;
+D = 1;
+WAIT D CYCLES;
+' // Loading device with a `bypass` instruction.
+IRSCAN 10, $03ff
+ ;
+D = 21000;
+WAIT D CYCLES;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+ ;
+D = 100000;
+WAIT D CYCLES;
+' // Check init_complete in ircapture.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0010
+, $0010
+, X;
+IF (!X) THEN GOTO F;
+' STATE RESET;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+, COMPARE $0000
+, $0000
+, X;
+IF (!X) THEN GOTO F;
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@81040002W000G088000010WW00000000880000120W0P0
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@j700m0000GaJ4Dud1040W0000W210000O001080000WH00000208102Y00XG0W880G2
+40e020C0X6ZPmWa6O86W4G0W00Ge48n1300e40000030C0010000030e00ZUm000eyggJuZU
+m000B1vEy30
+ ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 13;
+WAIT D CYCLES;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 13;
+WAIT D CYCLES;
+' //Checking done pin status.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0021
+, $0020
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+IRSCAN 10, $03ff
+ ;
+DRSCAN 1, $00
+ ;
+
+SUCCESS:
+PRINT "Successful File Execution.";
+EXIT 0;
+
+F:
+PRINT "File Execution Failure.";
+EXIT 16;
+
+ENDPROC;
+
+DATA TMPDATA;
+INTEGER TMP_DELAY;
+ENDDATA;
+
+PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D / 100;
+TMP_DELAY = TMP_DELAY * 25;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D * 25;
+TMP_DELAY = TMP_DELAY / 100;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY;
+IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
+IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
+ENDPROC;
+
+CRC B37A;
--- /dev/null
+NOTE "CREATOR" "Xilinx iMPACT Software";
+NOTE "DATE" "2013/01/10";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "ALG_VERSION" "1";
+NOTE "DEVICE" "UNSPECIFIED";
+NOTE "CHECKSUM" "UNSPECIFIED";
+NOTE "IDCODE" "UNSPECIFIED";
+NOTE "USERCODE" "UNSPECIFIED";
+NOTE "TARGET" "UNSPECIFIED";
+NOTE "STACK_DEPTH" "4";
+NOTE "MAX_FREQ" "1000000";
+ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC;
+DATA MAINDATA;
+INTEGER I = 0;
+INTEGER D = 0;
+ENDDATA;
+PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA;
+BOOLEAN X = 0;
+IRSTOP IDLE;
+DRSTOP IDLE;
+STATE RESET IDLE;
+' //Operation: Program -p 0 -defaultVersion 0
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Boundary Scan Chain Contents
+' //Position 1: xc4vlx40
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' // Loading device with a `jprogram` instruction.
+IRSCAN 10, $03cb
+ ;
+D = 1;
+WAIT D CYCLES;
+' // Loading device with a `bypass` instruction.
+IRSCAN 10, $03ff
+ ;
+D = 21000;
+WAIT D CYCLES;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+ ;
+D = 100000;
+WAIT D CYCLES;
+' // Check init_complete in ircapture.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0010
+, $0010
+, X;
+IF (!X) THEN GOTO F;
+' STATE RESET;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+, COMPARE $0000
+, $0000
+, X;
+IF (!X) THEN GOTO F;
+DRSCAN 12259744, @q8s50000000@@l@@lAPggP8000003080010000E20000G000006081020GvtfC0e004GM9Go
+1D00GI00000C0m00400060C0W2040006080WqC82421YW09G05G03m@3W@dV@F@x@yp@pV@F
+__@uV@7Vy@ud@dUz@ql@dU_@qt@7U@@m@_Fym@3VCX88P0000GYa6a3G280G0YbC10081000
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+Gy0m00OdlA0Kp0A0aWgFk700W1K603L0eGZ090001W220e00C0015WH18n3Ws00GG8GmA00C
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Bk@@X@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@Vrn0000mzBqzXm0020G0000WY00000Ca1W10c000004a001H0WG80G440
+8120K0106WGZnCaGI3C43W10W0010WGH060G0020000q47Cm00200000C0G1H0O0000GoNLd
+Wd1040W0000WDtXV0m@@30
+ ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 13;
+WAIT D CYCLES;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 13;
+WAIT D CYCLES;
+' //Checking done pin status.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0021
+, $0020
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+IRSCAN 10, $03ff
+ ;
+DRSCAN 1, $00
+ ;
+
+SUCCESS:
+PRINT "Successful File Execution.";
+EXIT 0;
+
+F:
+PRINT "File Execution Failure.";
+EXIT 16;
+
+ENDPROC;
+
+DATA TMPDATA;
+INTEGER TMP_DELAY;
+ENDDATA;
+
+PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D / 100;
+TMP_DELAY = TMP_DELAY * 25;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D * 25;
+TMP_DELAY = TMP_DELAY / 100;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY;
+IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
+IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
+ENDPROC;
+
+CRC 76DE;
--- /dev/null
+patched with patch of 18.12.2012 for correct remove sensor function
+bn
--- /dev/null
+#!/usr/bin/perl -w
+use strict;
+use warnings;
+use CGI::Carp qw(fatalsToBrowser);
+print "Content-type: text/html\r\n\r\n";
+
+
+my $output = qq$
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/>
+<title>JTAG Monitor</title>
+
+<META HTTP-EQUIV="Refresh" CONTENT="2">
+
+</head>
+
+$;
+
+
+
+ print $output;
+ print '<body>';
+ open FILE, "/local.1/daq/mvdmon/files/jtagmonitor_usechainsini.htt" or die $!;
+ while (<FILE>) { print $_; }
+
+ print "</body></html>";
+
+
--- /dev/null
+package HPlot;
+use POSIX qw/floor ceil strftime/;
+use Data::Dumper;
+use warnings;
+use strict;
+use FileHandle;
+
+my $p;
+
+use constant {TYPE_HISTORY => 1};
+
+use constant {OUT_PNG => 1,
+ OUT_SVG => 2, #n/a
+ OUT_SCREEN => 3}; #n/a
+
+my @color= ('#2222dd','#dd2222','#22dd22','#dd8822','#dd22dd','#22dddd');
+
+sub plot_write {
+ my ($file,$str,$no) = @_;
+ return unless $str;
+ if($no || 0) {
+ print $file $str;
+ }
+ else {
+ print $file $str."\n";
+ }
+ }
+
+
+sub makeTimeString{
+ return strftime("set label 100 \"%H:%M:%S\" at screen 0.02,0.02 left tc rgb \"#000044\" font \"monospace,8\"\n", localtime())
+ }
+
+
+sub PlotInit {
+ my ($c) = @_;
+
+ my $name = $c->{name};
+
+ my $fn = "gnuplot";
+ my $fh = new FileHandle ("|$fn") or die "error: no gnuplot";
+ $fh->autoflush(1);
+
+
+
+ $p->{$name} = $c;
+ $p->{$name}->{fh} = $fh;
+ $p->{$name}->{run} = 0;
+ $p->{$name}->{sizex} = $p->{$name}->{sizex} || 600 ;
+ $p->{$name}->{sizey} = $p->{$name}->{sizey} || 400 ;
+ $p->{$name}->{file} = $p->{$name}->{file} || "dummy" ;
+ $p->{$name}->{curves} = $p->{$name}->{curves} || 1 ;
+ $p->{$name}->{xscale} = $p->{$name}->{xscale} || 1;
+ $p->{$name}->{type} or die "No plot type specified";
+ $p->{$name}->{output} or die "No destination specified";
+
+ @color = @{$p->{$name}->{colors}} if($p->{$name}->{colors});
+
+ foreach my $i (0..($c->{entries}-1)) {
+ for my $j (0..($c->{curves}-1)) {
+ push(@{$p->{$name}->{value}->[$j]},0) ;
+ }
+ }
+
+ if($p->{$name}->{output} == OUT_PNG) {
+ $p->{$name}->{file} or die "No filename specified";
+ plot_write($fh,"set term png size ".$p->{$name}->{sizex}.",".$p->{$name}->{sizey}." font \"monospace,8\"");
+ plot_write($fh,"set out \"".$p->{$name}->{file}.".png\"");
+ }
+ else {
+ die "Output mode not supported yet";
+ }
+
+ if ($p->{$name}->{nokey}) {
+ plot_write($fh,"unset key");
+ }
+
+
+ plot_write($fh,"set xlabel \"".$p->{$name}->{xlabel}."\"") if $p->{$name}->{xlabel};
+ plot_write($fh,"set ylabel \"".$p->{$name}->{ylabel}."\"") if $p->{$name}->{ylabel};
+
+ if(defined $p->{$name}->{ymin} && defined $p->{$name}->{ymax}) {
+ plot_write($fh,"set yrange [".$p->{$name}->{ymin}.":".$p->{$name}->{ymax}."]");
+ }
+ elsif(defined $p->{$name}->{ymax}) {
+ plot_write($fh,"set yrange [:".$p->{$name}->{ymax}."]");
+ }
+ elsif(defined $p->{$name}->{ymin}) {
+ plot_write($fh,"set yrange [".$p->{$name}->{ymin}.":]");
+ }
+
+ if($p->{$name}->{type} == TYPE_HISTORY) {
+ if($p->{$name}->{fill}) {
+ plot_write($fh,"set style fill solid 1.00");
+ }
+ else {
+ plot_write($fh,"set style fill solid 0");
+ }
+ plot_write($fh,"set boxwidth 2 absolute");
+ plot_write($fh,"set autoscale fix");
+ plot_write($fh,"set xtics autofreq"); #$p->{$name}->{entries}
+ plot_write($fh,"set grid");
+# plot_write($fh,"set style fill solid 1.0");
+ plot_write($fh,"plot ",1);
+ for(my $j=0; $j<$p->{$name}->{curves};$j++) {
+ if($p->{$name}->{fill}) {
+ plot_write($fh,"'-' using 1:2 with filledcurves x1 lt rgb \"$color[$j]\" title \"".($p->{$name}->{titles}->[$j] || "$j")."\" ",1);
+ }
+ elsif($p->{$name}->{dots}) {
+ plot_write($fh,"'-' using 1:2 with points pointsize 0.6 pointtype 2 lt rgb \"$color[$j]\" title \"".($p->{$name}->{titles}->[$j] || "$j")."\" ",1);
+ }
+ else {
+ plot_write($fh,"'-' using 1:2 with lines lt rgb \"$color[$j]\" title \"".($p->{$name}->{titles}->[$j] || "$j")."\" ",1);
+ }
+ plot_write($fh,', ',1) unless ($j+1==$p->{$name}->{curves});
+ }
+ plot_write($fh," ");
+ }
+ else {
+ die "Plot type not supported";
+ }
+
+ }
+
+
+sub PlotDraw {
+ my($name) = @_;
+ if($p->{$name}->{run}>=1) {
+ plot_write($p->{$name}->{fh},"set out \"".$p->{$name}->{file}.".png\"");
+ plot_write($p->{$name}->{fh},makeTimeString());
+ plot_write($p->{$name}->{fh},"replot");
+ }
+ for(my $j=0; $j<$p->{$name}->{curves}; $j++) {
+ for(my $i=0; $i< scalar @{$p->{$name}->{value}->[$j]}; $i++) {
+ plot_write($p->{$name}->{fh},(($i-$p->{$name}->{entries})/$p->{$name}->{xscale})." ".$p->{$name}->{value}->[$j]->[$i]) unless $p->{$name}->{countup};
+ plot_write($p->{$name}->{fh},($i/$p->{$name}->{xscale})." ".$p->{$name}->{value}->[$j]->[$i]) if $p->{$name}->{countup};
+# print $j." ".$i." ".$p->{$name}->{entries}." ".$p->{$name}->{xscale}." ".$p->{$name}->{value}->[$j]->[$i]."\n";
+ }
+ plot_write($p->{$name}->{fh},"e");
+ }
+ $p->{$name}->{run}++;
+ }
+
+
+sub PlotAdd {
+ my($name,$value,$curve) = @_;
+ $curve = 0 unless $curve;
+
+ if($p->{$name}->{type} == TYPE_HISTORY) {
+ push(@{$p->{$name}->{value}->[$curve]},$value||0);
+ shift(@{$p->{$name}->{value}->[$curve]});
+ }
+
+ }
+
+
+1;
\ No newline at end of file
--- /dev/null
+package Hmon;
+use POSIX qw/floor ceil strftime/;
+use Data::Dumper;
+use warnings;
+use strict;
+
+use constant HMONDIR => "/local.1/daq/mvdmon/";
+
+our %hublist;
+our $r_hublist = \%hublist;
+
+print STDERR "Script started at ".strftime("%d.%m.%y %H:%M:%S", localtime()).".\n";
+
+###############################################################################
+# Make Title & Footer
+###############################################################################
+sub MakeTitle {
+ my ($width,$height,$title,$time,$error) = @_;
+ my $str;
+ $time = 1 unless defined $time;
+ $str = "<div class=\"width$width height$height\">\n";
+ if ($time) {
+ $str .= "<div class=\"timestamp\">".strftime("%H:%M:%S", localtime())."</div>\n";
+ }
+ if (defined $error && $error ne "") {
+ $str .= "<div class=\"errorstamp\">$error</div>\n";
+ }
+ $str .= "<h3 id='title'>$title</h3>";
+ return $str;
+}
+
+sub MakeFooter {
+ my $str;
+ $str = "</div>\n";
+ return $str;
+}
+
+sub AddStyle {
+ return "";
+}
+
+###############################################################################
+# Local Logfile
+###############################################################################
+sub OpenLogfile {
+ return 0;
+# my $fh;
+# open($fh, ">>",HMONDIR."/files/locallog");
+# $fh->autoflush(1);
+# return $fh;
+}
+
+sub WriteLog {
+ return 0;
+# my ($fh,$title,$format,@vars) = @_;
+# # $format =~ s/\s/\t/g;
+# if ($fh == 0) {
+# $fh = OpenLogfile();
+# }
+# my $tmp = sprintf("%s\t%i\t".$format."\n",$title,time(),@vars);
+# print $fh $tmp;
+}
+
+
+############################################
+# Write to File
+############################################
+sub WriteFile {
+ my ($name,$str) = @_;
+ open FH,"> ".Hmon::HMONDIR."files/$name.htt";
+ print FH $str;
+ close FH;
+}
+
+############################################
+# Nettrace DB
+############################################
+sub TraceDBLoad {
+ open FILE, "</home/hadaq/trbsoft/daq/tools/nettrace.db" or die "Can't open dbfile: $!";
+ local $/;
+ eval <FILE>;
+ close FILE;
+}
+
+sub TraceDBGet {
+ my ($addr, $port) = @_;
+ if (defined $r_hublist->{$addr}->{$port}) {
+ return $r_hublist->{$addr}->{$port};
+ }
+ else {
+ return 0;
+ }
+}
+
+
+###############################################################################
+# Voice Synthesis
+###############################################################################
+my $speaklog;
+sub Speak {
+ my ($id,$str) = @_;
+# print "$id $str $speaklog->{$id}\n";
+ if (!defined $speaklog->{$id} || $speaklog->{$id} < time()-120) {
+# my $cmd = "ssh hades30 'espeak -ven-male2 -s 120 -g 1 \"$str\" ' 2>/dev/null";
+ my $fh;
+ open($fh, ">>",Hmon::HMONDIR."/files/speaklog");
+ $fh->autoflush(1);
+ print $fh $str."\n";
+ $speaklog->{$id} = time();
+ close($fh);
+ }
+ }
+
+###############################################################################
+# Calculate Colors
+###############################################################################
+sub findcolor {
+ my ($v,$min,$max,$lg) = @_;
+ my ($r,$g,$b);
+ $v = 0 unless defined $v;
+ $v = log($v) if $v && $lg;
+ $min = log($min) if $min && $lg;
+ $max = log($max) if $max && $lg;
+ $max = 1 unless $max;
+
+ my $step = (($max-$min)/655);
+
+
+ if ($v == 0) {
+ $r = 220;
+ $g = 220;
+ $b = 220;
+ } else {
+ $v -= $min;
+ $v = $v/$step if $step;
+ if ($v<156) {
+ $r = 0;
+ $g = $v+100;
+ $b = 0;
+ } elsif ($v<412) {
+ $v -= 156;
+ $r = $v;
+ $g = 255;
+ $b = 0;
+ } else {
+ $v -= 412;
+ $r = 255;
+ $g = 255-$v;
+ $b = 0;
+ }
+ }
+
+ my $ret = sprintf("#%02x%02x%02x",$r%256,$g%256,$b%256);
+
+ return $ret;
+}
+
+###############################################################################
+# Make a nice colored drawing of MDC
+###############################################################################
+sub DrawMDC {
+ my ($plane,$sector,$color,$val) = @_;
+ my $str;
+ $str .= "<table class=\"mdc sector$sector\">\n";
+ if ($plane == 0) {
+ $str .= "<tr><td><td><td $color->{12} title=\"$val->{12}\">C<td><td $color->{13} title=\"$val->{13}\">D<td><td>\n";
+ $str .= "<tr><td><td><td $color->{10} title=\"$val->{10}\">A<td><td $color->{11} title=\"$val->{11}\">B<td><td>\n";
+ $str .= "<tr><td><td $color->{2} title=\"$val->{2}\">2<td colspan=3 rowspan=2 class=\"ctr\">$sector<td $color->{7} title=\"$val->{7}\">7<td>\n";
+ $str .= "<tr><td $color->{4} title=\"$val->{4}\">4<td $color->{1} title=\"$val->{1}\">1<td $color->{6} title=\"$val->{6}\">6<td $color->{9} title=\"$val->{9}\">9\n";
+ $str .= "<tr><td $color->{3} title=\"$val->{3}\">3<td $color->{0} title=\"$val->{0}\">0<td><td><td><td $color->{5} title=\"$val->{5}\">5<td $color->{8} title=\"$val->{8}\">8<tr>\n";
+ } elsif ($plane == 1) {
+ $str .= "<tr><td><td><td $color->{14} title=\"$val->{14}\">E<td><td $color->{15} title=\"$val->{15}\">F<td><td>\n";
+ $str .= "<tr><td><td><td $color->{12} title=\"$val->{12}\">C<td><td $color->{13} title=\"$val->{13}\">D<td><td>\n";
+ $str .= "<tr><td><td $color->{5} title=\"$val->{5}\">5<td colspan=3 rowspan=2 class=\"ctr\">$sector<td $color->{11} title=\"$val->{11}\">B<td>\n";
+ $str .= "<tr><td><td $color->{4} title=\"$val->{4}\">4<td $color->{10} title=\"$val->{10}\">A<td>\n";
+ $str .= "<tr><td><td $color->{3} title=\"$val->{3}\">3<td $color->{1} title=\"$val->{1}\">1<td><td $color->{7} title=\"$val->{7}\">7<td $color->{9} title=\"$val->{9}\">9<td>\n";
+ $str .= "<tr><td><td $color->{2} title=\"$val->{2}\">2<td $color->{0} title=\"$val->{0}\">0<td><td $color->{6} title=\"$val->{6}\">6<td $color->{8} title=\"$val->{8}\">8<td>\n";
+ # $str .= "<tr><td><td><td $color->{1} title=\"$val->{1}\">1<td><td $color->{7} title=\"$val->{7}\">7<td><td>\n";
+ # $str .= "<tr><td><td><td $color->{0} title=\"$val->{0}\">0<td><td $color->{6} title=\"$val->{6}\">6<td><td>\n";
+ } else {
+ $str .= "<tr><td><td $color->{12} title=\"$val->{12}\">C<td $color->{13} title=\"$val->{13}\">D<td><td $color->{14} title=\"$val->{14}\">E<td $color->{15} title=\"$val->{15}\">F<td>\n";
+ $str .= "<tr><td $color->{5} title=\"$val->{5}\">5<td><td><td><td><td><td $color->{11} title=\"$val->{11}\">B\n";
+ $str .= "<tr><td $color->{4} title=\"$val->{4}\">4<td><td colspan=3 rowspan=2 class=\"ctr\">$sector<td><td $color->{10} title=\"$val->{10}\">A\n";
+ $str .= "<tr><td><td $color->{3} title=\"$val->{3}\">3<td $color->{9} title=\"$val->{9}\">9<td>\n";
+ $str .= "<tr><td><td $color->{2} title=\"$val->{2}\">2<td><td><td><td $color->{8} title=\"$val->{8}\">8<td>\n";
+ $str .= "<tr><td><td><td $color->{1} title=\"$val->{1}\">1<td><td $color->{7} title=\"$val->{7}\">7<td><td>\n";
+ $str .= "<tr><td><td><td $color->{0} title=\"$val->{0}\">0<td><td $color->{6} title=\"$val->{6}\">6<td><td>\n";
+ }
+ $str .= "</table>\n";
+ return $str;
+}
+
+###############################################################################
+# Draw Scale
+###############################################################################
+sub DrawScale {
+ my ($min,$max,$steps) = @_;
+ my $str;
+ # print "$min $max $steps\n";
+ return "" if $max == $min;
+ $str .= "<table class=\"scale\"><tr>";
+ $str .= sprintf("<td style=\"background-color:%4s;\">",Hmon::findcolor(0,0,$steps,0));
+ return $str.="</table>" if $max == $min;
+ $str .= sprintf("<td class=\"label\">%#2.3G",$min);
+ for (my $i = 1;$i<$steps;$i++) {
+ # my $j = ($max-$min)/$steps*$i;
+ $str .= sprintf("<td style=\"background-color:%4s;\">",Hmon::findcolor($i,0,$steps,0));
+ }
+ $str .= sprintf("<td class=\"label\">%#2.3G",$max);
+ $str .= "</table>\n";
+ # $str .= "<table class=\"scalelabels\"><tr>";
+ # $str .= sprintf("<td>%2.1G<td>%2.1G<td>%2.1G\n",$min+($max-$min)/4,$min+($max-$min)*2/4,$min+($max-$min)*3/4);
+ # $str .= "</table>\n";
+
+ return $str;
+}
+
+###############################################################################
+# Makes Diffs to last stored value.
+# Loops over last plane/sector/board
+###############################################################################
+sub MakeDifferences {
+ my ($store, $laststore, $limit) = @_;
+ my $values = {};
+ for (my $l = 0; $l < 4;$l++) {
+ for (my $s = 0; $s < 6;$s++) {
+ for (my $b = 0; $b < 16; $b++) {
+ $values->{$l}->{$s}->{$b} = 0;
+ if (exists $store->{$l}->{$s}->{$b} && exists $laststore->{$l}->{$s}->{$b}) {
+ # if ($store->{$l}->{$s}->{$b} < $laststore->{$l}->{$s}->{$b}) {
+ # $values->{$l}->{$s}->{$b} = ($store->{$l}->{$s}->{$b} - $laststore->{$l}->{$s}->{$b}) & 0xFFFFFFFF ;
+ # }
+ # else {
+ $values->{$l}->{$s}->{$b} = ($store->{$l}->{$s}->{$b} - $laststore->{$l}->{$s}->{$b}) ; # & 0xFFFFFFFF
+ while ($values->{$l}->{$s}->{$b} < 0) {
+ $values->{$l}->{$s}->{$b} = ($values->{$l}->{$s}->{$b} + $limit);
+ } # & 0xFFFFFFFF
+ # }
+ }
+ }
+ }
+ }
+ return $values;
+}
+
+###############################################################################
+# Find min/max
+###############################################################################
+sub MakeMinMax3 {
+ my ($values,$d1,$d2,$d3,$ignore) = @_;
+ $ignore = 1 unless defined $ignore;
+ my $max = 0;
+ my $min = 2**32;
+ my $avg = 0;
+ my $num = 0;
+ for (my $l = 0; $l < $d1;$l++) {
+ for (my $s = 0; $s < $d2;$s++) {
+ for (my $b=0;$b<$d3;$b++) {
+ if (! exists $values->{$l}->{$s}->{$b}) {
+ $values->{$l}->{$s}->{$b} = 0;
+ } else {
+ $num++;
+ $avg += $values->{$l}->{$s}->{$b};
+ }
+ if ($max < $values->{$l}->{$s}->{$b}) {
+ $max = $values->{$l}->{$s}->{$b};
+ }
+ if ($min > $values->{$l}->{$s}->{$b} && ($values->{$l}->{$s}->{$b} != 0 || !$ignore)) {
+ $min = $values->{$l}->{$s}->{$b};
+ }
+ }
+ }
+ }
+ $avg /= ($num || 1);
+ return ($min,$max,$avg);
+}
+
+sub MakeMinMax2 {
+ my ($values, $d1, $d2, $ignore) = @_;
+ $ignore = 1 unless defined $ignore;
+ my $max = 0;
+ my $min = 2**32;
+ my $avg = 0;
+ my $num = 0;
+ # print Dumper $values;
+ for (my $l = 0; $l < $d1;$l++) {
+ for (my $s = 0; $s < $d2;$s++) {
+ if (! exists $values->{$l}->{$s}) {
+ $values->{$l}->{$s} = 0;
+ } else {
+ $num++;
+ $avg += $values->{$l}->{$s};
+ }
+ if ($max < $values->{$l}->{$s}) {
+ $max = $values->{$l}->{$s};
+ }
+ if ($min > $values->{$l}->{$s} && ($values->{$l}->{$s} != 0 || !$ignore)) {
+ $min = $values->{$l}->{$s};
+ }
+ }
+ }
+ $avg /= $num;
+ return ($min,$max,$avg);
+}
+
+sub MakeMinMax1 {
+ my ($values,$d1,$ignore) = @_;
+ $ignore = 1 unless defined $ignore;
+ my $max = 0;
+ my $min = 2**32;
+ for (my $l = 0; $l < $d1;$l++) {
+ if (! exists $values->{$l}) {
+ $values->{$l} = 0;
+ }
+ if ($max < $values->{$l}) {
+ $max = $values->{$l};
+ }
+ if ($min > $values->{$l} && ($values->{$l} != 0 || !$ignore)) {
+ $min = $values->{$l};
+ }
+ }
+ return ($min,$max);
+}
+
+sub qxtimeout {
+ my ($cmd, $time) = @_;
+ my @out;
+ $SIG{ALRM} = sub { $out[0] = "qxtimeout"; die };
+ $SIG{CHLD} = "IGNORE";
+ eval {
+ alarm($time);
+ @out = qx($cmd);
+ alarm(0);
+ };
+ return @out;
+}
+
+
+###############################################################################
+# MVD Make vertical list (HTML Table)
+###############################################################################
+sub MakeVerticalList {
+ my @list = @_;
+
+ if (scalar(@list) < 2){
+ print "ERROR list args < 2";
+ return "ERROR list args < 2";
+ }
+ else{
+ my $str = "\n";
+ my $i = 0;
+
+ $str .= qq$<table border="0">\n$;
+ my $style = "";
+ my $width = 0;
+ foreach (@list){
+ if ($i == 0) {
+ $i++;
+ $width = $_;
+ }
+ elsif ($i == 1) {
+ $i++;
+ $style = $_;
+ }
+ else{
+ if ($style=~/BOLD/){
+ if ($_) {$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4><b>$.$_.qq$</b></td></tr>\n$;}
+ else{$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4> </td></tr>\n$;}
+ }
+ elsif ($style=~/NOT_ZERO_ERROR/){
+ if ($_) {
+ if ($_ > 0) {$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=RED FACE="Geneva, Arial" SIZE=4><b>$.$_.qq$</b></td></tr>\n$;}
+ else{$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$_.qq$</td></tr>\n$;}
+ }
+ else{$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4> </td></tr>\n$;}
+ }
+ else{
+ if ($_) {$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$_.qq$</td></tr>\n$;}
+ else{$str .= qq$<tr><td width="$.$width.qq$"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4> </td></tr>\n$;}
+ }
+ }
+ }
+
+ $str .= qq$</table>\n$;
+
+ return $str;
+ }
+}
+
+###############################################################################
+# MVD Merge 2 vertical lists into 1 table
+###############################################################################
+sub Merge2Lists{
+ my ($width1,$width2,$str1,$str2) = @_;
+ my $str = "\n";
+ $str .= qq$<table border="0" style="border-collapse:collapse;table-layout: fixed; border-width: 1px; border-color:#000000; border-style: solid;" >\n$;
+ $str .= qq$<colgroup><col width="$.$width1.qq$"><col width="$.$width2.qq$"></colgroup>$;
+ $str .= qq$<tr><td>$.$str1.qq$</td><td>$.$str2.qq$</td></tr>\n$;
+ $str .= qq$</table>\n$;
+ return $str;
+
+}
+
+
+###############################################################################
+# MVD Add Date
+###############################################################################
+sub MakeDate {
+
+ my @months = qw(Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec);
+ my @weekDays = qw(Sun Mon Tue Wed Thu Fri Sat Sun);
+ my ($second, $minute, $hour, $dayOfMonth, $month, $yearOffset, $dayOfWeek) = localtime();
+ my $year = 1900 + $yearOffset;
+ my $theTime = "$hour:$minute:$second, $weekDays[$dayOfWeek] $months[$month] $dayOfMonth, $year";
+
+ my ($width,$height,$text) = @_;
+ my $str;
+ $str = "<div class=\"width$width height$height\">\n";
+ $str .= "<div class=\"timestamp\">".$theTime."</div>\n";
+ $str .= "".$text."</div>";
+
+ return $str;
+
+}
+
+
+
+###############################################################################
+# MVD Make a table (3x subs: Start, Insert and End)
+###############################################################################
+sub StartBlock {
+ my $str = "\n";
+ my ($title, $width) = @_;
+ $str .= qq$<table width="$.$width.qq$" border="1" style="text-align:center;border-collapse:collapse;table-layout: fixed; border-width: 3px; border-color:#007FFF; border-style: solid;" >\n$;
+# $str .= "<tr><td>".$title."</td></tr>\n";
+# $str .= qq$<tr><td><FONT COLOR=GREY FACE="Geneva, Arial" SIZE=4><b>$.$title.qq$</b></tr></td>\n$;
+ $str .= "<tr><td>\n";
+ #$str .= qq$<table border="1" width="$.$width.qq$">\n$;
+ $str .= qq$<table border="0">\n$;
+ $str .= qq$<tr><td><FONT COLOR=GREY FACE="Geneva, Arial" SIZE=4><b>$.$title.qq$</b></td></tr>\n$;
+ return $str;
+}
+
+sub InsertMatrix {
+ my $str = "\n";
+ my ($id, $good, $bad, $a, $b, $c, $d, $ref) = @_;
+ my $text;
+ $text = "$id ($good/$bad) : $a / $b / $c / $d";
+ $str .= qq$<table width="450" border="1" style="text-align:center;border-collapse:collapse;table-layout: fixed; border-width: 3px; border-color:#007FFF; border-style: solid;" >$;
+# $str .= "<tr><td>".$title."</td></tr>\n";
+# $str .= qq$<tr><td><FONT COLOR=GREY FACE="Geneva, Arial" SIZE=4><b>$.$title.qq$</b></tr></td>\n$;
+# $str .= "<tr><td>\n";
+ #$str .= qq$<table border="1" width="$.$width.qq$">\n$;
+# $str .= qq$<table border="0">\n$;
+ $str .= qq$<tr><td>$;
+ $str .= qq$<img src="../matrix_$.$id.qq$.png" height="315" width="420" alt="matrix">$;
+ $str .= qq$</tr></td>$;
+ $str .= qq$<tr><td><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=3><b>$.$text.qq$</b></td></tr>$;
+ $str .= qq$</table>$;
+ return $str;
+}
+
+sub InsertValue {
+
+ my $i;
+ my $str = "";
+ my $type;
+ my $value;
+ my @params = @_;
+ #style="text-align:center;"
+ $str .= qq$<tr>\n$;
+ for ($i=0;$i<(scalar(@params)/2);$i++){
+ $type = $params[2*$i];
+ $value = $params[2*$i+1];
+ if ($type =~ /TEXT/){
+ $str .= qq$<td width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+ elsif ($type =~ /WTEXT/){
+ $str .= qq$<td width="120"><FONT COLOR=WHITE FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+ elsif ($type =~ /VALUE/){
+ $str .= qq$<td width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /WVALUE/){
+ $str .= qq$<td width="120"><FONT COLOR=WHITE FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /RED/){
+ $str .= qq$<td width="120"><FONT COLOR=RED FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /DARKRED/){
+ $str .= qq$<td width="120"><FONT COLOR=DARKRED FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /GREEN/){
+ $str .= qq$<td width="120"><FONT COLOR=DARKGREEN FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /LEFT/){
+ $str .= qq$<td align="left" width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+
+ }
+ $str .= qq$</tr>\n$;
+
+
+
+
+ return $str;
+}
+
+sub InsertValueBG {
+
+ my $i;
+ my $str = "";
+ my $type;
+ my $value;
+ my @params = @_;
+ #style="text-align:center;"
+ my $col= pop(@params);
+ if ($col == 0) {
+ $str .= qq$<tr>\n$;
+ }
+ elsif ($col == 1){
+ $str .= qq$<tr style="background-color:#A3E7FF;">\n$;
+ }
+ elsif ($col == 2){
+ $str .= qq$<tr style="background-color:#DDFFCC;">\n$;
+ }
+ elsif ($col == 2){
+ $str .= qq$<tr style="background-color:#EEFFFF;">\n$;
+ }
+ elsif ($col == 3){
+ $str .= qq$<tr style="background-color:#FF2222;">\n$;
+ }
+ elsif ($col == 4){
+ $str .= qq$<tr style="background-color:#008888;">\n$;
+ }
+
+ for ($i=0;$i<((scalar(@params)-1)/2);$i++){
+ $type = $params[2*$i];
+ $value = $params[2*$i+1];
+
+ if ($type =~ /BGRED/){
+ if ($value == 0){
+ $str .= qq$<td width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>No Error</td>\n$;
+ }
+ else{
+ $str .= qq$<td width="120"><FONT COLOR=WHITE style="background-color:#FF0000;" FACE="Geneva, Arial" SIZE=4> Error </td>\n$;
+ }
+ }
+ elsif ($type =~ /TEXT/){
+ $str .= qq$<td width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+ elsif ($type =~ /WTEXT/){
+ $str .= qq$<td width="120"><FONT COLOR=WHITE FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+ elsif ($type =~ /VALUE/){
+ $str .= qq$<td width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /WVALUE/){
+ $str .= qq$<td width="120"><FONT COLOR=WHITE FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /RED/){
+ $str .= qq$<td width="120"><FONT COLOR=RED FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /DARKRED/){
+ $str .= qq$<td width="120"><FONT COLOR=DARKRED FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /GREEN/){
+ $str .= qq$<td width="120"><FONT COLOR=DARKGREEN FACE="Geneva, Arial" SIZE=4><b>$.$value.qq$</b></td>\n$;
+ }
+ elsif ($type =~ /LEFT/){
+ $str .= qq$<td align="left" width="120"><FONT COLOR=BLACK FACE="Geneva, Arial" SIZE=4>$.$value.qq$</td>\n$;
+ }
+
+ }
+ $str .= qq$</tr>\n$;
+
+
+
+
+ return $str;
+}
+
+
+
+sub EndBlock {
+ my $str = "";
+ $str .= qq$</table></td></tr>\n$;
+ $str .= qq$</table>\n$;
+
+ return $str;
+}
+
+
+1;
+__END__
--- /dev/null
+package QA;
+
+use Hmon;
+###############################################################################
+# Screen Configuration
+###############################################################################
+# List of categories & names
+our $cats = {'main'=>"Main",
+ 'daq'=>"DAQ",
+ 'trg'=>"Trig",
+ 'server'=>"Srv",
+ 'eb'=>"EB",
+ 'mdc'=>"MDC",
+ 'endp'=>"Endp",
+ 'feeerr'=>"Fee",
+ 'other'=>"Other"};
+
+# Order of categories
+our $entries->{'cats'} = ["main",
+ "daq",
+ "trg",
+ "server",
+ "eb",
+ "mdc",
+ "endp",
+ "feeerr",
+ "other"];
+
+# Order of entries in each cat
+$entries->{'main'} = ['time', 'rate','onlineqa'];
+$entries->{'daq'} = ['trbnet', 'timeouts', 'busy','readout'];
+$entries->{'trg'} = ['spill', 'source', 'accepted', 'ptrate', 'start'];
+$entries->{'server'} = ['fill', 'cpu', 'icinga', 'etrax', 'pwrsup'];
+$entries->{'eb'} = ['run', 'rate','bytes', 'lostevt', 'errbits'];
+$entries->{'mdc'} = ['token', 'blocked', 'temp', 'linkqual', 'voltage'];
+$entries->{'endp'} = ['mdc', 'rich', 'tof', 'rpc', 'other'];
+$entries->{'feeerr'} = ['rich', 'trb', 'feeerr','trginp','trgqual'];
+$entries->{'other'} = ['magnet','speech','shower','rich','mdcinvalid'];
+
+
+our $QAServer = "hades33";
+
+###############################################################################
+# Thresholds
+###############################################################################
+# #MDC Temperatures
+# use constant {MdcTempOk => 78, MdcTempWarn => 85, MdcTempErr => 90};
+#
+# #MDC locked OEP
+# use constant {MdcLockOk => 0, MdcLockWarn => 3, MdcLockErr => 5};
+#
+# #MDC OEP Numbers
+# use constant {MdcOepOk => 326};
+# use constant {MdcOepWarn => MdcOepOk-2};
+# use constant {MdcOepErr => MdcOepOk-4};
+#
+# #Frontend errors
+# use constant { FeeErrOk => 0, FeeErrWarn => 2, FeeErrErr => 5};
+
+our @FeeErrLimits = (0, 5, 10);
+our @MdcOepLimits = (372, 372-1, 372-3);
+our @MdcVoltageLimits = (50, 60, 100);
+our @MdcLockLimits = (0, 3, 5);
+our @MdcTempLimits = (78, 85, 90);
+our @TrgErrLimits = (100, 1000, 10000);
+our @CPULimits = (95, 100, 100);
+our @TimeoutLimits = (0, 0, 1);
+our @LinkErrLimits = (50, 500, 1000);
+our @MdcEndpMissingLimits = (0, 0, 1);
+our @RichEndpMissingLimits = (0, 0, 0);
+our @TofEndpMissingLimits = (0, 0, 0);
+our @RpcEndpMissingLimits = (0, 0, 0);
+our @OtherEndpMissingLimits = (0, 0, 0);
+our @EBDeltaRateLimits = (10, 15, 25);
+our $TrgCheckPolarity = 1;
+our @Eventsbroken = (.5,5,10);
+our @MdcTokenMissLimits = (10,50,100);
+
+
+our @LimitTriggerPerSpill = (1000, 0, 0);
+our $AcceleratorCycle = 12;
+use constant {CTSAddress => 0x0003};
+
+###############################################################################
+# Missing Boards
+###############################################################################
+
+our @mdc_boards_removed =(0x223b);
+our @mdc_chambers_removed =();
+our @rich_boards_removed =();
+our @tof_boards_removed =();
+our @rpc_boards_removed =();
+our @other_boards_removed =();
+
+
+###############################################################################
+# Error Levels
+###############################################################################
+use constant {
+ SCRIPTERROR => -1,
+ NA => 0,
+ OK => 10,
+ NOTE => 20,
+ NOTE_2 => 22,
+ WARN => 40,
+ WARN_2 => 42,
+ ERROR => 70,
+ ERROR_2 => 72,
+ LETHAL => 100,
+ FATAL => 100
+};
+
+###############################################################################
+# Functions
+###############################################################################
+
+
+############################################
+# Opens QA Logfile and gives back a filehandle
+sub OpenQAFile {
+ my $fh;
+ open($fh, ">>",Hmon::HMONDIR."/files/qalog");
+ $fh->autoflush(1);
+ return $fh;
+}
+
+
+
+############################################
+# Writes an entry to the QA file. Arguments:
+# $fh file handle of logfile
+# $cat category of entry
+# $entry name of entry
+# $ttl time the entry is valid (in seconds)
+# $status Status, one of the constants defined above
+# $title First line of monitor entry
+# $value Second line of monitor entry
+# $longtext Long description text (PopUp)
+sub WriteQALog {
+ my ($fh, $category, $entry, $ttl, $status, $title, $value, $longtext) = @_;
+ my $close = 0;
+ my $tmp = time()."\t$category\t$entry\t$ttl\t$status\t$title\t$value\t$longtext\n";
+
+ if ($fh eq "remote") {
+ system("ssh $QAServer \"echo '$tmp' >> /home/hadaq/trbsoft/daq/tools/hmon/files/qalog\"");
+ return;
+ }
+
+ # $format =~ s/\s/\t/g;
+ if ($fh == 0) {
+ $fh = OpenQAfile();
+ $close = 1;
+ }
+
+ print $fh $tmp;
+ close $fh if($close);
+}
+
+############################################
+# Returns the appropriate status flag (simplified). Arguments:
+# $mode how to determine status, supported: "below","above"
+# $val the value
+# @limits Array with limits
+sub GetQAState {
+ my ($mode, $val, @limits) = @_;
+ my ($ok, $warn, $err) = @limits;
+ if (!defined($val)) {
+ return NA;
+ }
+ if ($val eq "err") {
+ return SCRIPTERROR;
+ }
+ if ($_[0] eq 'below') {
+ if ($val <= $ok) {
+ return OK;
+ }
+ if ($val <= $warn) {
+ return WARN;
+ }
+ if ($val <= $err) {
+ return ERROR;
+ }
+ if ($val > $err) {
+ return FATAL;
+ }
+ } elsif ($_[0] eq 'above') {
+ if ($val >= $ok) {
+ return OK;
+ }
+ if ($val >= $warn) {
+ return WARN;
+ }
+ if ($val >= $err) {
+ return ERROR;
+ }
+ if ($val < $err) {
+ return FATAL;
+ }
+ } elsif ($_[0] eq 'inside') {
+ if (abs($val) <= $ok) {
+ return OK;
+ }
+ if (abs($val) <= $warn) {
+ return WARN;
+ }
+ if (abs($val) <= $err) {
+ return ERROR;
+ }
+ return FATAL;
+ }
+ return SCRIPTERROR;
+}
+
+############################################
+#Returns a string matching the given severity level
+sub LevelName {
+ my ($level) = @_;
+ if ($level == SCRIPTERROR) {
+ return "Script Error";
+ }
+ if ($level == NA) {
+ return "Not available";
+ }
+ if ($level < NOTE ) {
+ return "OK";
+ }
+ if ($level < WARN ) {
+ return "Note";
+ }
+ if ($level < ERROR ) {
+ return "Warning";
+ }
+ if ($level < FATAL ) {
+ return "Error";
+ }
+ return "Severe Error";
+ }
+
+############################################
+# Tries to nicely format an integer
+sub SciNotation {
+ my $v = shift;
+ return "undef" if (!defined $v);
+ return "0" if $v == 0;
+# print $v."\n";
+ if(abs($v) >= 1) {
+ return sprintf("%i", $v) if (abs($v) < 1000) ;
+ return sprintf("%.1fk", $v / 1000.) if (abs($v) < 20000) ;
+ return sprintf("%ik", $v / 1000.) if (abs($v) < 1E6) ;
+ return sprintf("%.1fM", $v / 1000000.) if (abs($v) < 20E6) ;
+ return sprintf("%iM", $v / 1000000.) if (abs($v) < 1E9) ;
+ return sprintf("%i",$v);
+ }
+ else {
+ return sprintf("%in", $v*1E9) if (abs($v) < 1E-6) ;
+ return sprintf("%iu", $v*1E6) if (abs($v) < 1E-3) ;
+ return sprintf("%.1fm", $v*1E3);
+ }
+}
+
+1;
+__END__
--- /dev/null
+[board01]
+chainsini=chains.ini
+FPGAboard_hostname=trb1577
+FPGAboard_staplfilename=jcb_trb_009.stapl
+FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
+FPGAboard_addonortrb=trb
+FPGAtrbnetAddr=0xf013
+CONFperiod_trbnetAddr=0xc001
+CONFoffspillcounter_trbnetAddr=0xc002
+CONFwaitstart_trbnetAddr=0xc007
+CONFtriginitseq_trbnetAddr=0xc003
+CONFtrigmapsstart_trbnetAddr=0xc00b
+CONFtrigmapsreset_trbnetAddr=0xc00a
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+;gui_defaults is a comma-separated list of the following strings representing buttons in the gui:
+;'h_prog_fpga','h_start_trbnetd','h_period_0_15s','h_period_1s','h_period_10s', 'h_no_period'
+;be aware that h_prog_fpga doesn't wait until the optical link is up on the Trb
+gui_defaults=h_period_0_15s
+guiBM_NP_defaults=h_waitbeforestart_6us
+
--- /dev/null
+;WARNING this file is generated automatically. don't edit manually.
+
+[chain1]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xb000
+CMDreg_trbnetAddr=0xb120
+RAMbase_trbnetAddr=0xb121
+DATAreg_trbnetAddr=0xb122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163
+STATUS2RAM3BtrbnetAddr=0xb170
+CONFsignals_trbnetAddr=0xc006
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=0
+DEBUGram1baddr=0xb147
+DEBUGram1bdata=0xb148
+DEBUGram1caddr=0xb149
+DEBUGram1cdata=0xb14a
+DEBUGram1crun=0xb14b
+;CONFperiod_trbnetAddr=0xc001
+;CONFoffspillcounter_trbnetAddr=0xc002
+;CONFwaitstart_trbnetAddr=0xc007
+FPGAboard_hostname=trb126
+;FPGAboard_staplfilename=jcb_trb_007.stapl
+FPGAboard_staplfilename=jcb_trb_009.stapl
+FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
+FPGAboard_addonortrb=trb
+; gui_defaults1/gui_defaults2 is a comma separated list of the following strings representing buttons in the gui:
+;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz',
+;'h_start', 'h_stop', 'h_set_inout', 'h_maps_reset_on', 'h_maps_reset_off', 'h_maps_start_on', 'h_maps_start_off',
+;'h_maps_clk_on', 'h_maps_clk_off'
+; gui_defaults1: executed in this order, before board defaults
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain1
+JNR0_sensor4=sensor4.ini
+JNR1_sensor3=sensor3.ini
+JNR2_sensor2=sensor2.ini
+JNR3_sensor1=sensor1.ini
+;END GENERATE_CHAINORDER chain1
+
+[chain2]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xd000
+CMDreg_trbnetAddr=0xd120
+RAMbase_trbnetAddr=0xd121
+DATAreg_trbnetAddr=0xd122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xd163
+STATUS2RAM3BtrbnetAddr=0xd170
+CONFsignals_trbnetAddr=0xc008
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=1
+DEBUGram1baddr=0xd147
+DEBUGram1bdata=0xd148
+DEBUGram1caddr=0xd149
+DEBUGram1cdata=0xd14a
+DEBUGram1crun=0xd14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain2
+JNR0_sensor8=sensor8.ini
+JNR1_sensor7=sensor7.ini
+JNR2_sensor6=sensor6.ini
+JNR3_sensor5=sensor5.ini
+;END GENERATE_CHAINORDER chain2
+
+[chain3]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xe000
+CMDreg_trbnetAddr=0xe120
+RAMbase_trbnetAddr=0xe121
+DATAreg_trbnetAddr=0xe122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xe163
+STATUS2RAM3BtrbnetAddr=0xe170
+CONFsignals_trbnetAddr=0xc009
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=2
+DEBUGram1baddr=0xe147
+DEBUGram1bdata=0xe148
+DEBUGram1caddr=0xe149
+DEBUGram1cdata=0xe14a
+DEBUGram1crun=0xe14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain3
+JNR0_sensor12=sensor12.ini
+JNR1_sensor10=sensor10.ini
+JNR2_sensor9=sensor9.ini
+;END GENERATE_CHAINORDER chain3
--- /dev/null
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xb000
+CMDreg_trbnetAddr=0xb120
+RAMbase_trbnetAddr=0xb121
+DATAreg_trbnetAddr=0xb122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163
+STATUS2RAM3BtrbnetAddr=0xb170
+CONFsignals_trbnetAddr=0xc006
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=0
+DEBUGram1baddr=0xb147
+DEBUGram1bdata=0xb148
+DEBUGram1caddr=0xb149
+DEBUGram1cdata=0xb14a
+DEBUGram1crun=0xb14b
+;CONFperiod_trbnetAddr=0xc001
+;CONFoffspillcounter_trbnetAddr=0xc002
+;CONFwaitstart_trbnetAddr=0xc007
+FPGAboard_hostname=trb126
+;FPGAboard_staplfilename=jcb_trb_007.stapl
+FPGAboard_staplfilename=jcb_trb_009.stapl
+FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
+FPGAboard_addonortrb=trb
+; gui_defaults1/gui_defaults2 is a comma separated list of the following strings representing buttons in the gui:
+;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz',
+;'h_start', 'h_stop', 'h_set_inout', 'h_maps_reset_on', 'h_maps_reset_off', 'h_maps_start_on', 'h_maps_start_off',
+;'h_maps_clk_on', 'h_maps_clk_off'
+; gui_defaults1: executed in this order, before board defaults
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
--- /dev/null
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xd000
+CMDreg_trbnetAddr=0xd120
+RAMbase_trbnetAddr=0xd121
+DATAreg_trbnetAddr=0xd122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xd163
+STATUS2RAM3BtrbnetAddr=0xd170
+CONFsignals_trbnetAddr=0xc008
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=1
+DEBUGram1baddr=0xd147
+DEBUGram1bdata=0xd148
+DEBUGram1caddr=0xd149
+DEBUGram1cdata=0xd14a
+DEBUGram1crun=0xd14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
--- /dev/null
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xe000
+CMDreg_trbnetAddr=0xe120
+RAMbase_trbnetAddr=0xe121
+DATAreg_trbnetAddr=0xe122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xe163
+STATUS2RAM3BtrbnetAddr=0xe170
+CONFsignals_trbnetAddr=0xc009
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=2
+DEBUGram1baddr=0xe147
+DEBUGram1bdata=0xe148
+DEBUGram1caddr=0xe149
+DEBUGram1cdata=0xe14a
+DEBUGram1crun=0xe14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
--- /dev/null
+#!/usr/bin/perl -w
+
+#use warnings;
+#use strict;
+use Time::HiRes qw( gettimeofday usleep time );
+use FileHandle;
+use Data::Dumper;
+use POSIX qw/floor ceil strftime/;
+use Config::Abstract::Ini;
+use Sys::Syslog;
+my %laststore;
+my $totalsum = 0;
+use HADES::TrbNet;
+use lib qw(/daq/toolbox);
+use Hmon;
+use QA;
+use HPlot;
+use Getopt::Long;
+
+my $opt_help;
+my $opt_chain;
+
+GetOptions ('h|help' => \$opt_help,
+ 'c|chain=s' => \$opt_chain
+ );
+if($opt_help) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ print "Usage: copy_on_datachanged.pl [-c <chain name> ]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+"
+}
+
+$ENV{DAQOPSERVER}='trb124';
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+
+trb_init_ports() or die trb_strerror();
+my $chainsfile= './chains.ini';
+
+
+my $fqa = QA::OpenQAFile();
+openlog("atomic,copy_on_datachanged.pl", "perror", "local1");
+
+my %run_counter_last;
+while (1){
+ # read last error counters from disk
+ my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+ my %allchains = $chainsSettings->get_all_settings;
+ sleep(1);
+ foreach my $chain (keys %allchains) {
+ if(defined($opt_chain) and not ($opt_chain eq $chain)) { next; }
+ my %settings=%{$allchains{$chain}};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $debug_ram1c_run = $settings{'DEBUGram1crun'};
+ # trigger on data changed
+ #syslog("debug", "setting trigger on data changed chain $chain.");
+ my $date = strftime "%Y%m%d%H%M%S", localtime;
+ print "$date: setting trigger on data changed chain $chain.\n";
+ system("trbcmd w $fpga_addr $cmd_reg_addr 0x0000006c"); # command: M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED
+ }
+ if(-e "/tmp/jtag_ipc_datachanged_copyram") {
+ foreach my $chain (keys %allchains) {
+ if(defined($opt_chain) and not ($opt_chain eq $chain)) { next; }
+ my %settings=%{$allchains{$chain}};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $debug_ram1c_run = $settings{'DEBUGram1crun'};
+
+ my $ram1c_run = trb_register_read(hex($fpga_addr), hex($debug_ram1c_run));
+ my ($k, $v) = each %$ram1c_run;
+ my $run_counter = $v;
+ if(defined($run_counter_last{$chain}) and !($run_counter eq $run_counter_last{$chain})) {
+ syslog("INFO", "copy of RAM for $chain triggered in run: $run_counter.");
+ system("perl debug_read_ram1c.pl -c $chain");
+ }
+ $run_counter_last{$chain} = $run_counter;
+ }
+ system("rm /tmp/jtag_ipc_datachanged_copyram");
+ }
+ sleep(1);
+}
+
+
--- /dev/null
+#!/bin/bash
+echo "Run Counter before Triggers:"
+trbcmd r 0xf013 0xb14b
+
+trbcmd w 0xf013 0xb122 0x00000007 # ADDR_DEBUG_RAM1BADDR
+trbcmd w 0xf013 0xb120 0x00000064 # ADDR_DEBUG_RAM1BADDR
+echo "Run Counter after Triggers:"
+trbcmd r 0xf013 0xb14b
--- /dev/null
+#!/usr/bin/perl
+
+
+# Use the TRUE and FALSE constants exported by the Glib module.
+#use Glib qw/TRUE FALSE/;
+#use Gtk2 '-init';
+use FileHandle;
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX;
+use Sys::Syslog;
+openlog("atomic,debug_read_ram1c.pl", "perror", "local1");
+use Getopt::Long;
+
+my $opt_help;
+my $opt_chain;
+
+GetOptions ('h|help' => \$opt_help,
+ 'c|chain=s' => \$opt_chain
+ );
+if($opt_help) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ print "Usage: debug_read_ram1c.pl [-c <chain name> ]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+"
+}
+
+
+# Get last programmed values
+
+open LPPH, "<", "/tmp/jtag_initmem/lastprog.txt";
+my $lastprogfilenameprefix = <LPPH>;
+
+my $chainsfile= 'chains.ini';
+my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+my %allchains = $chainsSettings->get_all_settings;
+
+
+# my helper function
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+
+
+my $date = strftime "%Y%m%d%H%M%S", localtime;
+my $comparemem_folder = "comparemem/$date";
+syslog("INFO", "Saving RAM1C from FPGA to folder $comparemem_folder.");
+if(-e $comparemem_folder) {
+ die("Error: Folder with the same date already exists!");
+}
+mkdir $comparemem_folder,0755;
+
+
+my $result = "";
+my $hexaddr;
+my $lines;
+foreach my $chain (keys %allchains) {
+ if(defined($opt_chain) and not ($opt_chain eq $chain)) { next; }
+ my %settings=%{$allchains{$chain}};
+ my $k = 0; # sensor number in chain
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram1c_addr = $settings{'DEBUGram1caddr'};
+ my $ram1c_data = $settings{'DEBUGram1cdata'};
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ my $comparemem_filehandle = FileHandle->new("$comparemem_folder/$chain.$setting_name.txt", "w");
+ # create a new window
+
+ my $lastprogfilename = $lastprogfilenameprefix . '/' . $chain.".".$setting_name.".txt";
+ print "lastprogfilename: $lastprogfilename.\n";
+ my $handle_lastprog = FileHandle->new($lastprogfilename, 'r');
+ for(my $i=0;$i<256;$i++) {
+ $hexaddr = int_to_32bit_hex($i+256*$k);
+ $result = `trbcmd w $fpga_addr $ram1c_addr 0x$hexaddr`; # ADDR_DEBUG_RAM1BADDR
+ print "trbcmd w $fpga_addr $ram1c_addr 0x$hexaddr\n"; # ADDR_DEBUG_RAM1BADDR
+ print "trbcmd r $fpga_addr $ram1c_data\n";
+ $result = `trbcmd r $fpga_addr $ram1c_data`;
+ print $result;
+ $result = substr($result,8,10);
+ #$result="0x11111111";
+ my $compare = $handle_lastprog->getline();
+ #$lines .= "123456789" . trim($compare) . $result ."\n";
+ #$textbuffer->set_text($lines);
+ my $line;
+ if(defined($compare)) {
+ $line = $result ."\t(programmed:". trim($compare).")\n";
+ }
+ else {
+ $line = $result ."\t(nothing programmed)\n";
+ }
+ print $comparemem_filehandle $line;
+ }
+
+ $k++;
+ }
+
+ }
+}
+
--- /dev/null
+#!/usr/bin/perl
+
+
+# Use the TRUE and FALSE constants exported by the Glib module.
+use Glib qw/TRUE FALSE/;
+use Gtk2 '-init';
+use FileHandle;
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX;
+
+# Get last programmed values
+
+open LPPH, "<", "/tmp/jtag_initmem/lastprog.txt";
+my $lastprogfilenameprefix = <LPPH>;
+
+my $chainsfile= 'chains.ini';
+my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+my %allchains = $chainsSettings->get_all_settings;
+
+
+# my helper function
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+
+# This is a callback function. We simply say hello to the world, and destroy
+# the window object in order to close the program.
+sub hello
+{
+ my ($widget, $window) = @_;
+ print "Hello, World\n";
+
+ $window->destroy;
+}
+
+sub delete_event
+{
+ # If you return FALSE in the "delete_event" signal handler,
+ # GTK will emit the "destroy" signal. Returning TRUE means
+ # you don't want the window to be destroyed.
+ # This is useful for popping up 'are you sure you want to quit?'
+ # type dialogs.
+ print "delete event occurred\n";
+
+ # Change TRUE to FALSE and the main window will be destroyed with
+ # a "delete_event".
+ return FALSE;
+}
+
+my $date = strftime "%Y%m%d%H%M%S", localtime;
+my $comparemem_folder = "comparemem/$date";
+if(-e $comparemem_folder) {
+ die("Error: Folder with the same date already exists!");
+}
+mkdir $comparemem_folder,0755;
+
+
+my $result = "";
+my $hexaddr;
+my $lines;
+foreach my $chain (keys %allchains) {
+ my %settings=%{$allchains{$chain}};
+ my $k = 0; # sensor number in chain
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram1c_addr = $settings{'DEBUGram1caddr'};
+ my $ram1c_data = $settings{'DEBUGram1cdata'};
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ my $comparemem_filehandle = FileHandle->new("$comparemem_folder/$chain.$setting_name.txt", "w");
+ # create a new window
+ my $window = Gtk2::Window->new('toplevel');
+
+ # When the window is given the "delete_event" signal (this is given
+ # by the window manager, usually by the "close" option, or on the
+ # titlebar), we ask it to call the delete_event () functio
+ # as defined above. No data is passed to the callback function.
+ $window->signal_connect(delete_event => \&delete_event);
+
+ # Here we connect the "destroy" event to a signal handler.
+ # This event occurs when we call Gtk2::Widget::destroy on the window,
+ # or if we return FALSE in the "delete_event" callback. Perl supports
+ # anonymous subs, so we can use one of them for one line callbacks.
+ $window->signal_connect(destroy => sub { Gtk2->main_quit; });
+
+ # Sets the border width of the window.
+ $window->set_border_width(10);
+
+ # Creates a new button with a label "Hello World".
+ my $button = Gtk2::Button->new("Hello World");
+
+ # Create a GtkTextView
+ my $textview = Gtk2::TextView->new();
+ my $textbuffer = $textview->get_buffer();
+
+ # When the button receives the "clicked" signal, it will call the function
+ # hello() with the window reference passed to it.The hello() function is
+ # defined above.
+ $button->signal_connect(clicked => \&hello, $window);
+ my $tag = $textbuffer->create_tag("redbg", "background", "#FF0000");
+ my $tagok = $textbuffer->create_tag("greenbg", "background", "#00FF00");
+
+ my $lastprogfilename = $lastprogfilenameprefix . '/' . $chain.".".$setting_name.".txt";
+ print "lastprogfilename: $lastprogfilename.\n";
+ my $handle_lastprog = FileHandle->new($lastprogfilename, 'r');
+ for(my $i=0;$i<256;$i++) {
+ $hexaddr = int_to_32bit_hex($i+256*$k);
+ $result = `trbcmd w $fpga_addr $ram1c_addr 0x$hexaddr`; # ADDR_DEBUG_RAM1BADDR
+ print "trbcmd w $fpga_addr $ram1c_addr 0x$hexaddr\n"; # ADDR_DEBUG_RAM1BADDR
+ print "trbcmd r $fpga_addr $ram1c_data\n";
+ $result = `trbcmd r $fpga_addr $ram1c_data`;
+ print $result;
+ $result = substr($result,8,10);
+ #$result="0x11111111";
+ my $compare = $handle_lastprog->getline();
+ #$lines .= "123456789" . trim($compare) . $result ."\n";
+ #$textbuffer->set_text($lines);
+ my $line;
+ if(defined($compare)) {
+ $line = $result ."\t(programmed:". trim($compare).")\n";
+ if((lc substr($compare,0,10)) ne (lc substr($result,0,10))) {
+ $textbuffer->insert_at_cursor($line);
+ my $iter1 = $textbuffer->get_iter_at_line_offset($i,2);
+ my $iter2 = $textbuffer->get_iter_at_line_offset($i,10);
+ $textbuffer->apply_tag($tag,$iter1,$iter2);
+ }
+ else {
+ $textbuffer->insert_at_cursor($line);
+ my $iter1 = $textbuffer->get_iter_at_line_offset($i,2);
+ my $iter2 = $textbuffer->get_iter_at_line_offset($i,10);
+ $textbuffer->apply_tag($tagok,$iter1,$iter2);
+ }
+ }
+ else {
+ $line = $result ."\t(nothing programmed)\n";
+ $textbuffer->insert_at_cursor($line);
+ }
+ print $comparemem_filehandle $line;
+ }
+ # This packs the vbox into the window (a gtk container).
+ my $vbox = Gtk2::VBox->new(FALSE, 6);
+ # pack with reference to start of box after any other packed with reference to start
+ # want a scrolled textview
+ my $scroll = Gtk2::ScrolledWindow->new;
+ $scroll->add($textview);
+ $vbox->pack_start($scroll, TRUE, TRUE, 0);
+ $vbox->pack_start($button, FALSE, FALSE, 0);
+ $window->add($vbox);
+ # The final step is to display this newly created widget.
+ #$button->show;
+
+ $window->set_title($chain.".".$setting_name );
+ # and the window
+ $window->show_all;
+
+ $k++;
+ }
+
+ }
+}
+
+# All GTK applications must have a call to the main() method. Control ends here
+# and waits for an event to occur (like a key press or a mouse event).
+Gtk2->main;
+0;
--- /dev/null
+#!/bin/bash
+
+export DAQOPSERVER=trb124
+export PATH=$PATH:/home/hadaq/bin
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+
+my %chains = ();
+my $namecol = 0; # column of chain name, column counting from zero
+my $chaincol = 1; # column of chain name, column counting from zero
+my $jnrcol = 2; # column of JNR for sorting, column counting from zero
+my $minnumcols = 4;
+
+open(PROTOTYPEDBFILE,"/daq/toolbox/prototype_setup.db") || die("Cannot open file chains.ini!");
+my @lines_db = <PROTOTYPEDBFILE>;
+close(PROTOTYPEDBFILE);
+my $keydesc = 0;
+foreach my $line (@lines_db) {
+ # skip commented out lines
+ if(substr($line, 0, 1) eq "#") {
+ next;
+ }
+ if($keydesc == 1 and substr($line, 0, 4) eq "====") { last; }
+ # if new section begins stop interpreting lines
+ if(substr($line, 0, 3) eq "key") {
+ $keydesc = 0;
+ }
+ if($keydesc == 1) {
+ my @entries = split(/\s+/, $line);
+ if((scalar @entries) < $minnumcols) {
+ if(!($line eq "\n")) {print "Warning: row with too little entries. skipping."};
+ next;
+ }
+ my $sensorname = $entries[$namecol];
+ my $chainname = $entries[$chaincol];
+ my $jnr = $entries[$jnrcol];
+ if(! defined ($chains{$chainname})) {
+ my %sensors = ();
+ $chains{$chainname} = \%sensors;
+ }
+ my %sensors = %{$chains{$chainname}};
+ # only add sensor to chain if JNR matches following regexp
+ if ($jnr =~ /[0-9]+/) {
+ my $jnrname;
+ $jnrname= "JNR".$jnr."_".$sensorname;
+ $sensors{$jnrname} = $sensorname . ".ini";
+ }
+ $chains{$chainname} = \%sensors;
+ }
+ # if desc section begins, start interpreting next line
+ if(substr($line, 0, 8) eq "key jtag") {
+ $keydesc = 1;
+ }
+}
+
+# for each of the possible three chains generate a section with name and sensor-file references in the correct order
+my @chain_names = sort keys (%chains);
+open(CHAINSFILE,">", "./chains.ini") || die("Cannot open file chains.ini!");
+print CHAINSFILE ";WARNING this file is generated automatically. don't edit manually.\n";
+
+for (my $i=0;$i<3;$i++) {
+ my $chainname = $chain_names[$i];
+ my %sensors = %{$chains{$chainname}};
+ print CHAINSFILE "\n[$chainname]\n";
+
+ open(CHAINSFILE_CHAINI,"./chains.ini.chain$i") || die("Cannot open file chains.ini.chain$i!");
+ my @lines_chaini = <CHAINSFILE_CHAINI>;
+ close(CHAINSFILE_CHAINI);
+ foreach (@lines_chaini){
+ print CHAINSFILE $_;
+ }
+ print CHAINSFILE "\n;BEGIN GENERATE_CHAINORDER $chainname\n";
+ foreach (sort keys %sensors){
+ print CHAINSFILE $_."=".$sensors{$_}."\n";
+ }
+ print CHAINSFILE ";END GENERATE_CHAINORDER $chainname\n";
+}
+close(CHAINSFILE);
--- /dev/null
+10
+
+dir
+156
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj/trb_maps_jtag3/ui/gui
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--- /dev/null
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+18958
+\f
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<interface>
+ <requires lib="gtk+" version="2.24"/>
+ <!-- interface-naming-policy project-wide -->
+ <object class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <object class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <object class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ </object>
+ </child>
+ </object>
+</interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">13</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">no period</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_no_period" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">trigger initialization sequence</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trigger_init_sequence" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">TCK 100 kHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_100khz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings (don't START)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Waitbeforestart</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">6 us</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_waitbeforestart_6us" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">1 ms</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="yalign">0.50999999046325684</property>
+ <signal name="clicked" handler="h_waitbeforestart_1ms" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">1 s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_waitbeforestart_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">trigger initialization sequence</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trigger_init_sequence" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">MAPS_RESET all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">RUN_JTAG all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_run_jtag" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">MAPS_START all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="btn_set_standard_settings">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">TCK 100 kHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_100khz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">MAPS_CLK</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset before</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset after 1st WR</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_after_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_after_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">trig. init. seq.</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trig_init_seq" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">MAPS_RESET</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">RUN_JTAG</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_run_jtag" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">MAPS_START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">13</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">prog FPGA (TDOdelay=1)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_sensorname">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">sensor #</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">insert (virt.)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_insert_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">remove (virt.)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_remove_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_sensorname">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">sensor #</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">insert</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_insert_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">remove</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_remove_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<interface>
+ <requires lib="gtk+" version="2.24"/>
+ <!-- interface-naming-policy project-wide -->
+ <object class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <object class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </object>
+ </child>
+ <child type="label">
+ <object class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </object>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </object>
+ </child>
+ </object>
+</interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload boards.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_boardsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload boards.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_boardsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow3">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_err">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Errors:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<interface>
+ <requires lib="gtk+" version="2.24"/>
+ <!-- interface-naming-policy project-wide -->
+ <object class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <object class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <object class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ </object>
+ </child>
+ </object>
+</interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<interface>
+ <requires lib="gtk+" version="2.24"/>
+ <!-- interface-naming-policy project-wide -->
+ <object class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkButton" id="button1">
+ <property name="label" translatable="yes">button</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <placeholder/>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <placeholder/>
+ </child>
+ <child>
+ <placeholder/>
+ </child>
+ </object>
+ </child>
+ </object>
+</interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">13</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">no period</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_no_period" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">trigger initialization sequence</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trigger_init_sequence" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">TCK 100 kHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_100khz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">set standard settings (don't START)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">TCK 100 kHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_100khz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">MAPS_CLK</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset before</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset after 1st WR</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_after_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reset_after_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">trig. init. seq.</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trig_init_seq" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">MAPS_RESET</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">RUN_JTAG</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_run_jtag" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">MAPS_START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">13</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_buttons">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Waitbeforestart</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">6 us</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_waitbeforestart_6us" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">1 ms</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="yalign">0.50999999046325684</property>
+ <signal name="clicked" handler="h_waitbeforestart_1ms" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">1 s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_waitbeforestart_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">trigger initialization sequence</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trigger_init_sequence" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">MAPS_RESET all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">RUN_JTAG all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_run_jtag" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">MAPS_START all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">WRITE_ONCE_JTAG all chains</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_write_once" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="btn_set_standard_settings">
+ <property name="label" translatable="yes">set standard settings</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_standard" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Board Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_chains">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame3</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Chain Commands</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">delay 0</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay0" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button20">
+ <property name="label" translatable="yes">1</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button21">
+ <property name="label" translatable="yes">2</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay2" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button22">
+ <property name="label" translatable="yes">3</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_delay3" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">TCK 100 kHz</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_100khz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">MAPS_CLK</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset before</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_before_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">reset after 1st WR</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_after_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">off</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_after_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">trig. init. seq.</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_trig_init_seq" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">MAPS_RESET</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">RUN_JTAG</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_run_jtag" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">MAPS_START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">13</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">WRITE_ONCE_JTAG</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_write_once" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">14</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_chainnr">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">chain nr.</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button17">
+ <property name="label" translatable="yes">prog FPGA</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button19">
+ <property name="label" translatable="yes">prog FPGA (TDOdelay=1)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_fpga_delay1" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button18">
+ <property name="label" translatable="yes">start trbnetd</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start_trbnetd" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">prog RAM</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_prog_ram" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">TCK 10 MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_10mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button3">
+ <property name="label" translatable="yes">TCK 1MHz timing</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_timing_1mhz" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button4">
+ <property name="label" translatable="yes">START</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_start" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button5">
+ <property name="label" translatable="yes">STOP</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_stop" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">5</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">6</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button16">
+ <property name="label" translatable="yes">set IN/OUT pol.;start,clk on</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_set_inout" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">7</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button6">
+ <property name="label" translatable="yes">reg. MAPS_reset ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button7">
+ <property name="label" translatable="yes">reg. MAPS_reset OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_reset_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">8</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="homogeneous">True</property>
+ <child>
+ <widget class="GtkButton" id="button11">
+ <property name="label" translatable="yes">MAPS_start ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <property name="xalign">0.44999998807907104</property>
+ <signal name="clicked" handler="h_maps_start_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button12">
+ <property name="label" translatable="yes">MAPS_start OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_start_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">9</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button9">
+ <property name="label" translatable="yes">MAPS_CLK ON</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_on" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button10">
+ <property name="label" translatable="yes">MAPS_CLK OFF</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_maps_clk_off" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">10</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkButton" id="button13">
+ <property name="label" translatable="yes">period 0.15s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_0_15s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button14">
+ <property name="label" translatable="yes">period 1s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_1s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button15">
+ <property name="label" translatable="yes">period 10s</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_period_10s" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">11</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button8">
+ <property name="label" translatable="yes">man. MAPS_reset</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_man_maps_reset" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">12</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_sensorname">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">sensor #</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">insert (virt.)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_insert_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">remove (virt.)</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_remove_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox_top">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label_sensorname">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">sensor #</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button1">
+ <property name="label" translatable="yes">insert</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_insert_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button2">
+ <property name="label" translatable="yes">remove</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_remove_sensor" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<interface>
+ <requires lib="gtk+" version="2.24"/>
+ <!-- interface-naming-policy project-wide -->
+ <object class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <object class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="use_action_appearance">False</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <object class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </object>
+ </child>
+ <child type="label">
+ <object class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </object>
+ </child>
+ </object>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <object class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </object>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </object>
+ </child>
+ </object>
+</interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload boards.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_boardsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload boards.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_boardsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkNotebook" id="notebook1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label6">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHBox" id="hbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkFrame" id="frame_messages">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow1">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msg">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow3">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_err">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label5">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Errors:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Control</property>
+ </widget>
+ <packing>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment3">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <widget class="GtkScrolledWindow" id="scrolledwindow2">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="hscrollbar_policy">automatic</property>
+ <property name="vscrollbar_policy">automatic</property>
+ <child>
+ <widget class="GtkTextView" id="textview_msgdetailed">
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label7">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>Detailed Messages:</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label4">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Log</property>
+ </widget>
+ <packing>
+ <property name="position">1</property>
+ <property name="tab_fill">False</property>
+ <property name="type">tab</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<glade-interface>
+ <!-- interface-requires gtk+ 2.24 -->
+ <!-- interface-naming-policy project-wide -->
+ <widget class="GtkWindow" id="window1">
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkVBox" id="vbox1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkHBox" id="hbox2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <child>
+ <widget class="GtkLabel" id="label">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">Load configuration:</property>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkButton" id="button">
+ <property name="label" translatable="yes">reload chains.ini</property>
+ <property name="visible">True</property>
+ <property name="can_focus">True</property>
+ <property name="receives_default">True</property>
+ <signal name="clicked" handler="h_reload_chainsini" swapped="no"/>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">0</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">1</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkFrame" id="frame_subst">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label_xalign">0</property>
+ <property name="shadow_type">none</property>
+ <child>
+ <widget class="GtkAlignment" id="alignment1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="left_padding">12</property>
+ <child>
+ <placeholder/>
+ </child>
+ </widget>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label1">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes"><b>frame1</b></property>
+ <property name="use_markup">True</property>
+ </widget>
+ <packing>
+ <property name="type">label_item</property>
+ </packing>
+ </child>
+ </widget>
+ <packing>
+ <property name="expand">True</property>
+ <property name="fill">True</property>
+ <property name="position">2</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkHSeparator" id="hseparator2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">3</property>
+ </packing>
+ </child>
+ <child>
+ <widget class="GtkLabel" id="label2">
+ <property name="visible">True</property>
+ <property name="can_focus">False</property>
+ <property name="label" translatable="yes">2012 Goethe-Universität, Frankfurt am Main.</property>
+ </widget>
+ <packing>
+ <property name="expand">False</property>
+ <property name="fill">True</property>
+ <property name="position">4</property>
+ </packing>
+ </child>
+ </widget>
+ </child>
+ </widget>
+</glade-interface>
--- /dev/null
+[chain1]
+JNR3_sensor1_rerrors=
+JNR3_sensor1_werrors=
+JNR3_sensor1_run=
+JNR3_sensor1_datach=
+JNR2_sensor2_rerrors=
+JNR2_sensor2_werrors=
+JNR2_sensor2_run=
+JNR2_sensor2_datach=
+JNR1_sensor3_rerrors=
+JNR1_sensor3_werrors=
+JNR1_sensor3_run=
+JNR1_sensor3_datach=
+JNR0_sensor4_rerrors=
+JNR0_sensor4_werrors=
+JNR0_sensor4_run=
+JNR0_sensor4_datach=
+[chain2]
+JNR3_sensor5_rerrors=
+JNR3_sensor5_werrors=
+JNR3_sensor5_run=
+JNR3_sensor5_datach=
+JNR2_sensor6_rerrors=
+JNR2_sensor6_werrors=
+JNR2_sensor6_run=
+JNR2_sensor6_datach=
+JNR1_sensor7_rerrors=
+JNR1_sensor7_werrors=
+JNR1_sensor7_run=
+JNR1_sensor7_datach=
+JNR0_sensor8_rerrors=
+JNR0_sensor8_werrors=
+JNR0_sensor8_run=
+JNR0_sensor8_datach=
+[chain3]
--- /dev/null
+#!/usr/bin/perl -w
+
+#use warnings;
+#use strict;
+use Time::HiRes qw( gettimeofday usleep time );
+use FileHandle;
+use Data::Dumper;
+use POSIX qw/floor ceil/;
+use Config::Abstract::Ini;
+use Sys::Syslog;
+my %laststore;
+my $totalsum = 0;
+use HADES::TrbNet;
+use lib qw(/daq/toolbox);
+use Hmon;
+use QA;
+use HPlot;
+openlog("atomic,jtagmonitor_usechainsini4.pl", "perror", "local1");
+syslog("INFO", "starting monitor");
+$ENV{DAQOPSERVER}='trb124';
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub colored_table {
+ my @rows = @{$_[0]};
+ my $string;
+ $string .= "<table>";
+ foreach my $row (@rows) {
+ $string .= "<tr>";
+ foreach my $cell (@{$row}) {
+ my %cellhash = %{$cell};
+ $string .= "<td style=\"background-color:$cellhash{'bgcolor'};\">$cellhash{'text'}</td>";
+ }
+ $string .= "</tr>";
+ }
+ $string .= "</table>";
+
+}
+
+$ENV{DAQOPSERVER}='trb124';
+
+trb_init_ports() or die trb_strerror();
+my $chainsfile= './chains.ini';
+my $lastcountersfile= 'jtagmonitor_lastcounters.ini';
+
+
+my $fqa = QA::OpenQAFile();
+
+while (1){
+ # read last error counters from disk
+ my $chainsLastCounters = new Config::Abstract::Ini($lastcountersfile);
+ my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+ my %allchains = $chainsSettings->get_all_settings;
+ my %chainsLastCountersHash = $chainsLastCounters->get_all_settings;
+
+ sleep(1);
+ foreach my $chain (keys %allchains) {
+ my %settings=%{$allchains{$chain}};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $status2_ram3b_baseaddr_reg_addr = $settings{'STATUS2RAM3BBASEADDRREGtrbnetAddr'};
+ my $status2_ram3b_addr = $settings{'STATUS2RAM3BtrbnetAddr'};
+ system("trbcmd w $fpga_addr $cmd_reg_addr 0x00000063"); # command: M26C_CMD_COPY_TO_STATUS2
+ }
+ sleep(1);
+# my $str = Hmon::MakeDate(0,0,"");
+ my $str = Hmon::MakeTitle(8,5,"JTAG Monitor",1);
+ my $status_str = Hmon::MakeTitle(8,5,"JTAG Monitor",1);
+ my $vert_list_counter = 0;
+ # file to write counter values to
+ open(my $lastcounters_fh, ">", $lastcountersfile);
+ my $run_counter_changed = 0;
+ foreach my $chain (sort(keys %allchains)) {
+ my %settings=%{$allchains{$chain}};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $status2_ram3b_baseaddr_reg_addr = $settings{'STATUS2RAM3BBASEADDRREGtrbnetAddr'};
+ my $status2_ram3b_addr = $settings{'STATUS2RAM3BtrbnetAddr'};
+ my @sensors;
+ my @vert_list1;
+ my @vert_list2;
+ my %last_counters = %{$chainsLastCountersHash{$chain}};
+ my @status_table_row1;
+ my @status_table_row2;
+ print $lastcounters_fh "[$chain]\n";
+ my $deviderrors = 0;
+ my $wrregerrors = 0;
+ my $botherrors = 0;
+ my $minlastruncounter = 0;
+ my $maxruncounter = 0;
+ foreach my $setting_name (reverse sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ push(@sensors, $setting_name);
+ my $i = (scalar @sensors)-1;
+ my $rambasepointer=int_to_32bit_hex(($i)*4);
+ print "trbcmd w $fpga_addr $status2_ram3b_baseaddr_reg_addr 0x$rambasepointer\n"; # ADDR_STATUS2_RAM3B_BASEADDR // FIRST COL
+ system("trbcmd w $fpga_addr $status2_ram3b_baseaddr_reg_addr 0x$rambasepointer"); # ADDR_STATUS2_RAM3B_BASEADDR // FIRST COL
+
+ print "reading $fpga_addr $status2_ram3b_addr.\n";
+ my $rerrors1 = trb_register_read(hex($fpga_addr), hex($status2_ram3b_addr));
+ print "reading $fpga_addr " .(hex($status2_ram3b_addr)+2) ."\n";
+ my $werrors1 = trb_register_read(hex($fpga_addr), hex($status2_ram3b_addr)+2);
+
+ $rambasepointer=int_to_32bit_hex(($i)*4+2);
+ print "trbcmd w $fpga_addr $status2_ram3b_baseaddr_reg_addr 0x$rambasepointer\n"; # ADDR_STATUS2_RAM3B_BASEADDR // FIRST COL
+ system("trbcmd w $fpga_addr $status2_ram3b_baseaddr_reg_addr 0x$rambasepointer"); # ADDR_STATUS2_RAM3B_BASEADDR // SECOND COL
+ my $run = trb_register_read(hex($fpga_addr), hex($status2_ram3b_addr));
+ my $dat = trb_register_read(hex($fpga_addr), hex($status2_ram3b_addr)+2);
+
+
+ my $k=0, $v=0;
+
+ ($k, $v) = each %$rerrors1;
+# $hexkey = sprintf("%x", $k);
+# $hexval = sprintf("%x", $v);
+ my $read_errors1 = $v;
+ print "read_errors1: $read_errors1\n";
+ ($k, $v) = each %$werrors1;
+# $hexkey = sprintf("%x", $k);
+# $hexval = sprintf("%x", $v);
+ my $write_errors1 = $v;
+ print "write_errors1: $write_errors1\n";
+
+ ($k, $v) = each %$run;
+# $hexkey = sprintf("%x", $k);
+# $hexval = sprintf("%x", $v);
+ my $run_counter = $v;
+ print "run_counter: $run_counter\n";
+
+ ($k, $v) = each %$dat;
+# $hexkey = sprintf("%x", $k);
+# $hexval = sprintf("%x", $v);
+ my $data_changed = $v;
+
+ print $lastcounters_fh "$setting_name"."_rerrors=".$read_errors1."\n";
+ print $lastcounters_fh "$setting_name"."_werrors=".$write_errors1."\n";
+ print $lastcounters_fh "$setting_name"."_run=".$run_counter."\n";
+ print $lastcounters_fh "$setting_name"."_datach=".$data_changed."\n";
+
+ # get last values
+ my $last_read_errors1 = $last_counters{$setting_name."_rerrors"};
+ my $last_write_errors1 = $last_counters{$setting_name."_werrors"};
+ my $last_run_counter = $last_counters{$setting_name."_run"};
+ my $last_data_changed = $last_counters{$setting_name."_datach"};
+ my $bgcolor = "#FFFFFF";
+ if($last_run_counter == $run_counter) {
+ $bgcolor = "#AAAAFF"; # blue: not included in last run/not running at all
+ }
+ elsif($last_run_counter < $run_counter) {
+ if (($last_read_errors1 == $read_errors1) and ($last_write_errors1 == $write_errors1)) {
+ $bgcolor = "#99FF99"; # green: no read or write errors
+ }
+ elsif ((!($last_read_errors1 == $read_errors1)) and ($last_write_errors1 == $write_errors1)) {
+ $bgcolor = "#FF9999"; # red: read id errors
+ $deviderrors = 1;
+
+ }
+ elsif ((($last_read_errors1 == $read_errors1)) and (!($last_write_errors1 == $write_errors1))) {
+ $bgcolor = "#FFCC99"; # orange: write errors
+ $wrregerrors = 1;
+ }
+ else {
+ $botherrors = 1;
+ $bgcolor = "#FF0000"; # pure red: write and read id errors
+ }
+ # for triggering copyram
+ if ((!($last_data_changed == $data_changed)) and (($last_write_errors1 == $write_errors1))) {
+ #$bgcolor = "#FFCC99"; # orange: write errors
+ syslog("WARNING", "Data Changed Occured in $setting_name, $chain between runs $last_run_counter and $run_counter.");
+ system("touch /tmp/jtag_ipc_datachanged_copyram");
+ }
+ }
+ if(!($last_run_counter == $run_counter)) {
+ $run_counter_changed = 1;
+ }
+ if(($minlastruncounter == 0) or ($last_run_counter < $minlastruncounter)) { $minlastruncounter = $last_run_counter; }
+ if($run_counter > $maxruncounter) { $maxruncounter = $run_counter; }
+ my %head_cell = ("bgcolor"=>"#FFFFFF", "text" => $setting_name);
+ my %color_cell =("bgcolor"=>$bgcolor, "text" => "");
+ push(@status_table_row1, \%head_cell);
+ push(@status_table_row2, \%color_cell);
+ push(@vert_list1, "");
+ push(@vert_list1, "Run Counter $i");
+ push(@vert_list1, "Read Errors $i");
+ push(@vert_list1, "Write Errors $i");
+ push(@vert_list1, "Data Changed $i");
+ push(@vert_list2, "");
+ push(@vert_list2, $run_counter);
+ push(@vert_list2, $read_errors1);
+ push(@vert_list2, $write_errors1);
+ push(@vert_list2, $data_changed);
+ }
+ }
+ if($deviderrors == 1) {
+ syslog("ERR", "MIMOSA26 Dev ID $chain wrong/missing between runs $minlastruncounter and $maxruncounter (READ_ERROR). Check bypass switches?");
+ }
+ elsif($wrregerrors == 1) {
+ syslog("ERR", "MIMOSA26 Registers $chain not returned correct between runs $minlastruncounter and $maxruncounter(WRITE_ERROR). Check bypass switches and TDI/TDO connection?");
+ }
+ elsif($botherrors == 1) {
+ syslog("WARNING", "Only WRITE_ERROR and READ_ERROR $chain between runs $minlastruncounter and $maxruncounter. Power off?");
+ }
+ $status_str .= Hmon::MakeTitle(8,5,$chain,1);
+ my @table = [\@status_table_row1,\@status_table_row2];
+ $status_str .= colored_table(@table) . "<br><!-- end status //-->";
+ #print $status_str;
+ $str .= Hmon::MakeTitle(8,5,$chain,1);
+ my $str1 = Hmon::MakeVerticalList(200,"",@vert_list1);
+ my $str2 = Hmon::MakeVerticalList(100,"NOT_ZERO_ERROR",@vert_list2);
+ $str .= Hmon::Merge2Lists(200,100,$str1,$str2);
+ $vert_list_counter+=1000;
+ }
+ $str .= Hmon::MakeFooter();
+ my @legend_table = [[{"bgcolor"=>"#FFFFFF", "text" => "not programmed"},{"bgcolor"=>"#FFFFFF", "text" => "read ID errors only"},
+ { "bgcolor"=>"#FFFFFF", "text" => "write errors only"}, {"bgcolor"=>"#FFFFFF", "text" => "write + read ID errors"}, {"bgcolor"=>"#FFFFFF", "text" => "no errors"}],
+ [{"bgcolor"=>"#AAAAFF", "text" => ""},{"bgcolor"=>"#FF9999", "text" => ""},
+ {"bgcolor"=>"#FFCC99", "text" => ""}, {"bgcolor"=>"#FF0000", "text" => ""}, {"bgcolor"=>"#99FF99", "text" => ""}]];
+ $status_str .= "<h4>Legend</h4>".colored_table(@legend_table) . "<br><!-- end status //-->";
+ $str = $status_str . $str;
+ if(!($run_counter_changed == 0)) {
+ Hmon::WriteFile("jtagmonitor_usechainsini",$str);
+ }
+
+
+
+}
+
+
--- /dev/null
+10
+
+dir
+135
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj/trb_maps_jtag3/ui/libs
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj
+
+
+
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+b00609d0-aec6-11df-b1c7-bba583a822eb
+\f
+Config
+dir
+\f
--- /dev/null
+#/usr/bin/perl -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/lib
+#
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+use BN::CRC32;
+
+print "PERL:" . crc32("A string.");
--- /dev/null
+/*
+ * This file was generated automatically by ExtUtils::ParseXS version 3.16 from the
+ * contents of CRC32.xs. Do not edit this file, edit CRC32.xs instead.
+ *
+ * ANY CHANGES MADE HERE WILL BE LOST!
+ *
+ */
+
+#line 1 "CRC32.xs"
+/*
+ Perl Extension for 32bit CRC computations
+ by Soenke J. Peters
+*/
+
+#include "EXTERN.h"
+#include "perl.h"
+#include "XSUB.h"
+
+/*
+ Based on CRC-32 version 1.04 by Craig Bruce, 05-Dec-1994
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef GENTABLE
+U32
+crcTable[256];
+
+void
+crcgen( void )
+{
+ U32 crc, poly;
+ int i, j;
+
+ poly = 0xEDB88320L;
+ //poly = 0x04C11DB7L;
+ for (i=0; i<256; i++) {
+ //crc = i<<24;
+ crc = i;
+ for (j=8; j>0; j--) {
+ if (crc&1) {
+ crc = (crc >> 1) ^ poly;
+ //if (crc&0x80000000) {
+ // crc = (crc << 1) ^ poly;
+ } else {
+ crc >>= 1;
+ // crc <<= 1;
+ }
+ }
+ crcTable[i] = crc;
+ }
+ printf("crcTable[15]=%x\n", crcTable[15]);
+}
+#else /* GENTABLE */
+U32
+crcTable[256] = {
+0x0, 0x77073096, 0xee0e612c, 0x990951ba, 0x76dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+0xedb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x9b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+0x76dc4190, 0x1db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x6b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+0x7807c9a2, 0xf00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x86d3d2d, 0x91646c97, 0xe6635c01,
+0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+0xedb88320, 0x9abfb3b6, 0x3b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x4db2615, 0x73dc1683,
+0xe3630b12, 0x94643b84, 0xd6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0xa00ae27, 0x7d079eb1,
+0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x26d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x5005713,
+0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0xcb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0xbdbdf21,
+0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+#endif /* GENTABLE */
+
+U32
+getcrc(char *c, int len, U32 crcinit)
+{
+ register U32 crc;
+ char *e = c + len;
+
+ crc = crcinit^0xFFFFFFFF;
+ //crc = crcinit;
+ while (c < e) {
+ //printf("CALCULATING CRC OF: %X;\n", (crc^ *c) & 0xFF);
+ crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[ (crc^ *c) & 0xFF ];
+ //crc = ((crc << 8) & 0xFFFFFF00) ^ crcTable[ (crc^ *c) & 0xFF ];
+ ++c;
+ }
+ return( crc^0xFFFFFFFF );
+ //return( crc );
+}
+
+#define BUFSIZE 32768
+
+U32
+getcrc_fp( PerlIO *fp, U32 crcinit )
+{
+ register U32 crc;
+ register U16 len;
+ unsigned char buf[BUFSIZE];
+
+ crc = crcinit^0xFFFFFFFF;
+ while((len = PerlIO_read(fp, buf, BUFSIZE)) > 0 ) {
+ unsigned char * p = buf;
+ do {
+ crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[(unsigned char)( (crc & 0xff) ^ *(p++) )];
+ } while (--len);
+ }
+ return( crc^0xFFFFFFFF );
+}
+
+svtype
+getsvtype(SV *sv)
+{
+ if (sv == NULL )
+ return SVt_NULL;
+ if (SvROK(sv))
+ return SvTYPE(SvRV(sv));
+ else
+ return SvTYPE(sv);
+}
+
+#line 143 "CRC32.c"
+#ifndef PERL_UNUSED_VAR
+# define PERL_UNUSED_VAR(var) if (0) var = var
+#endif
+
+#ifndef dVAR
+# define dVAR dNOOP
+#endif
+
+
+/* This stuff is not part of the API! You have been warned. */
+#ifndef PERL_VERSION_DECIMAL
+# define PERL_VERSION_DECIMAL(r,v,s) (r*1000000 + v*1000 + s)
+#endif
+#ifndef PERL_DECIMAL_VERSION
+# define PERL_DECIMAL_VERSION \
+ PERL_VERSION_DECIMAL(PERL_REVISION,PERL_VERSION,PERL_SUBVERSION)
+#endif
+#ifndef PERL_VERSION_GE
+# define PERL_VERSION_GE(r,v,s) \
+ (PERL_DECIMAL_VERSION >= PERL_VERSION_DECIMAL(r,v,s))
+#endif
+#ifndef PERL_VERSION_LE
+# define PERL_VERSION_LE(r,v,s) \
+ (PERL_DECIMAL_VERSION <= PERL_VERSION_DECIMAL(r,v,s))
+#endif
+
+/* XS_INTERNAL is the explicit static-linkage variant of the default
+ * XS macro.
+ *
+ * XS_EXTERNAL is the same as XS_INTERNAL except it does not include
+ * "STATIC", ie. it exports XSUB symbols. You probably don't want that
+ * for anything but the BOOT XSUB.
+ *
+ * See XSUB.h in core!
+ */
+
+
+/* TODO: This might be compatible further back than 5.10.0. */
+#if PERL_VERSION_GE(5, 10, 0) && PERL_VERSION_LE(5, 15, 1)
+# undef XS_EXTERNAL
+# undef XS_INTERNAL
+# if defined(__CYGWIN__) && defined(USE_DYNAMIC_LOADING)
+# define XS_EXTERNAL(name) __declspec(dllexport) XSPROTO(name)
+# define XS_INTERNAL(name) STATIC XSPROTO(name)
+# endif
+# if defined(__SYMBIAN32__)
+# define XS_EXTERNAL(name) EXPORT_C XSPROTO(name)
+# define XS_INTERNAL(name) EXPORT_C STATIC XSPROTO(name)
+# endif
+# ifndef XS_EXTERNAL
+# if defined(HASATTRIBUTE_UNUSED) && !defined(__cplusplus)
+# define XS_EXTERNAL(name) void name(pTHX_ CV* cv __attribute__unused__)
+# define XS_INTERNAL(name) STATIC void name(pTHX_ CV* cv __attribute__unused__)
+# else
+# ifdef __cplusplus
+# define XS_EXTERNAL(name) extern "C" XSPROTO(name)
+# define XS_INTERNAL(name) static XSPROTO(name)
+# else
+# define XS_EXTERNAL(name) XSPROTO(name)
+# define XS_INTERNAL(name) STATIC XSPROTO(name)
+# endif
+# endif
+# endif
+#endif
+
+/* perl >= 5.10.0 && perl <= 5.15.1 */
+
+
+/* The XS_EXTERNAL macro is used for functions that must not be static
+ * like the boot XSUB of a module. If perl didn't have an XS_EXTERNAL
+ * macro defined, the best we can do is assume XS is the same.
+ * Dito for XS_INTERNAL.
+ */
+#ifndef XS_EXTERNAL
+# define XS_EXTERNAL(name) XS(name)
+#endif
+#ifndef XS_INTERNAL
+# define XS_INTERNAL(name) XS(name)
+#endif
+
+/* Now, finally, after all this mess, we want an ExtUtils::ParseXS
+ * internal macro that we're free to redefine for varying linkage due
+ * to the EXPORT_XSUB_SYMBOLS XS keyword. This is internal, use
+ * XS_EXTERNAL(name) or XS_INTERNAL(name) in your code if you need to!
+ */
+
+#undef XS_EUPXS
+#if defined(PERL_EUPXS_ALWAYS_EXPORT)
+# define XS_EUPXS(name) XS_EXTERNAL(name)
+#else
+ /* default to internal */
+# define XS_EUPXS(name) XS_INTERNAL(name)
+#endif
+
+#ifndef PERL_ARGS_ASSERT_CROAK_XS_USAGE
+#define PERL_ARGS_ASSERT_CROAK_XS_USAGE assert(cv); assert(params)
+
+/* prototype to pass -Wmissing-prototypes */
+STATIC void
+S_croak_xs_usage(pTHX_ const CV *const cv, const char *const params);
+
+STATIC void
+S_croak_xs_usage(pTHX_ const CV *const cv, const char *const params)
+{
+ const GV *const gv = CvGV(cv);
+
+ PERL_ARGS_ASSERT_CROAK_XS_USAGE;
+
+ if (gv) {
+ const char *const gvname = GvNAME(gv);
+ const HV *const stash = GvSTASH(gv);
+ const char *const hvname = stash ? HvNAME(stash) : NULL;
+
+ if (hvname)
+ Perl_croak(aTHX_ "Usage: %s::%s(%s)", hvname, gvname, params);
+ else
+ Perl_croak(aTHX_ "Usage: %s(%s)", gvname, params);
+ } else {
+ /* Pants. I don't think that it should be possible to get here. */
+ Perl_croak(aTHX_ "Usage: CODE(0x%"UVxf")(%s)", PTR2UV(cv), params);
+ }
+}
+#undef PERL_ARGS_ASSERT_CROAK_XS_USAGE
+
+#ifdef PERL_IMPLICIT_CONTEXT
+#define croak_xs_usage(a,b) S_croak_xs_usage(aTHX_ a,b)
+#else
+#define croak_xs_usage S_croak_xs_usage
+#endif
+
+#endif
+
+/* NOTE: the prototype of newXSproto() is different in versions of perls,
+ * so we define a portable version of newXSproto()
+ */
+#ifdef newXS_flags
+#define newXSproto_portable(name, c_impl, file, proto) newXS_flags(name, c_impl, file, proto, 0)
+#else
+#define newXSproto_portable(name, c_impl, file, proto) (PL_Sv=(SV*)newXS(name, c_impl, file), sv_setpv(PL_Sv, proto), (CV*)PL_Sv)
+#endif /* !defined(newXS_flags) */
+
+#line 285 "CRC32.c"
+
+XS_EUPXS(XS_BN__CRC32_crc32); /* prototype to pass -Wmissing-prototypes */
+XS_EUPXS(XS_BN__CRC32_crc32)
+{
+ dVAR; dXSARGS;
+ if (items < 1)
+ croak_xs_usage(cv, "data, ...");
+ PERL_UNUSED_VAR(ax); /* -Wall */
+ SP -= items;
+ {
+ char * data;
+#line 142 "CRC32.xs"
+ U32 crcinit = 0xFFFFFFFF;
+ STRLEN data_len;
+#line 300 "CRC32.c"
+ U32 RETVAL;
+ dXSTARG;
+#line 145 "CRC32.xs"
+ int sv_type;
+ IO *io;
+ SV *sv;
+ U32 rv = 0;
+ {
+#ifdef GENTABLE
+ crcgen();
+#endif /* GENTABLE */
+ /* Horst Fickenscher <horst_fickenscher@sepp.de> mailed me that it
+ could be useful to supply an initial value other than 0, e.g.
+ to calculate checksums of big files without the need of keeping
+ them comletely in memory */
+ if ( items > 1 )
+ crcinit = (U32) SvNV(ST(items - 1));
+ //printf("crcinit: %x.\n", crcinit);
+
+ sv_type = getsvtype(ST(0));
+
+ if (sv_type == SVt_PVGV)
+ {
+ io = sv_2io(ST(0));
+ rv = getcrc_fp(IoIFP(io), crcinit);
+ }
+ else
+ {
+ data = (char *)SvPV(ST(0),data_len);
+ //printf("C: data: ");
+ int l; char c_high, c_low;
+ for(l=0;l<data_len;l++){
+ //printf("%02x ", (unsigned char*)data[l]);
+ char c;
+ switch( (data[l]>>4)&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_high = c;
+ switch( (data[l])&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_low = c;
+ //printf("%c%c ", c_high, c_low);
+ }
+ //printf(";\n");
+ rv = getcrc(data, data_len, crcinit);
+ }
+ EXTEND(sp, 1);
+ sv = newSV(0);
+ sv_setuv(sv, (UV)rv);
+ PUSHs(sv_2mortal(sv));
+ }
+#line 383 "CRC32.c"
+ PUTBACK;
+ return;
+ }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+XS_EXTERNAL(boot_BN__CRC32); /* prototype to pass -Wmissing-prototypes */
+XS_EXTERNAL(boot_BN__CRC32)
+{
+ dVAR; dXSARGS;
+#if (PERL_REVISION == 5 && PERL_VERSION < 9)
+ char* file = __FILE__;
+#else
+ const char* file = __FILE__;
+#endif
+
+ PERL_UNUSED_VAR(cv); /* -W */
+ PERL_UNUSED_VAR(items); /* -W */
+#ifdef XS_APIVERSION_BOOTCHECK
+ XS_APIVERSION_BOOTCHECK;
+#endif
+ newXS("BN::CRC32::crc32", XS_BN__CRC32_crc32, file);
+#if (PERL_REVISION == 5 && PERL_VERSION >= 9)
+ if (PL_unitcheckav)
+ call_list(PL_scopestack_ix, PL_unitcheckav);
+#endif
+ XSRETURN_YES;
+}
+
--- /dev/null
+
+package BN::CRC32;
+
+require Exporter;
+require DynaLoader;
+
+@ISA = qw(Exporter DynaLoader);
+
+$VERSION = 1.4;
+
+# Items to export into callers namespace by default
+@EXPORT = qw(crc32);
+
+# Other items we are prepared to export if requested
+@EXPORT_OK = qw();
+
+bootstrap BN::CRC32;
+
+1;
--- /dev/null
+=head1 NAME
+
+String::CRC32 - Perl interface for cyclic redundency check generation
+
+=head1 SYNOPSIS
+
+ use String::CRC32;
+
+ $crc = crc32("some string");
+ $crc = crc32("some string", initvalue);
+
+ $somestring = "some string";
+ $crc = crc32($somestring);
+
+ open(SOMEFILE, "location/of/some.file");
+ $crc = crc32(*SOMEFILE);
+ close(SOMEFILE);
+
+=head1 DESCRIPTION
+
+The B<CRC32> module calculates CRC sums of 32 bit lenghts.
+It generates the same CRC values as ZMODEM, PKZIP, PICCHECK and
+many others.
+
+Despite its name, this module is able to compute
+the checksum of files as well as strings.
+
+=head1 EXAMPLES
+
+ $crc = crc32("some string");
+
+ results in the same as
+
+ $crc = crc32(" string", crc32("some"));
+
+This is useful for subsequent CRC checking of substrings.
+
+You may even check files:
+
+ open(SOMEFILE, "location/of/some.file");
+ $crc = crc32(*SOMEFILE);
+ close(SOMEFILE);
+
+A init value may also been supplied in the above example.
+
+=head1 AUTHOR
+
+Soenke J. Peters <peters__perl@opcenter.de>
+
+Please be so kind as to report any bugs/suggestions to the above address.
+
+=head1 COPYRIGHT
+
+CRC algorithm code taken from CRC-32 by Craig Bruce.
+The module stuff is inspired by a similar perl module called
+String::CRC by David Sharnoff & Matthew Dillon.
+Horst Fickenscher told me that it could be useful to supply an init
+value to the crc checking function and so I included this possibility.
+
+The author of this package disclaims all copyrights and
+releases it into the public domain.
--- /dev/null
+/*
+ Perl Extension for 32bit CRC computations
+ by Soenke J. Peters
+*/
+
+#include "EXTERN.h"
+#include "perl.h"
+#include "XSUB.h"
+
+/*
+ Based on CRC-32 version 1.04 by Craig Bruce, 05-Dec-1994
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef GENTABLE
+U32
+crcTable[256];
+
+void
+crcgen( void )
+{
+ U32 crc, poly;
+ int i, j;
+
+ poly = 0xEDB88320L;
+ //poly = 0x04C11DB7L;
+ for (i=0; i<256; i++) {
+ //crc = i<<24;
+ crc = i;
+ for (j=8; j>0; j--) {
+ if (crc&1) {
+ crc = (crc >> 1) ^ poly;
+ //if (crc&0x80000000) {
+ // crc = (crc << 1) ^ poly;
+ } else {
+ crc >>= 1;
+ // crc <<= 1;
+ }
+ }
+ crcTable[i] = crc;
+ }
+ printf("crcTable[15]=%x\n", crcTable[15]);
+}
+#else /* GENTABLE */
+U32
+crcTable[256] = {
+0x0, 0x77073096, 0xee0e612c, 0x990951ba, 0x76dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+0xedb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x9b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+0x76dc4190, 0x1db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x6b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+0x7807c9a2, 0xf00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x86d3d2d, 0x91646c97, 0xe6635c01,
+0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+0xedb88320, 0x9abfb3b6, 0x3b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x4db2615, 0x73dc1683,
+0xe3630b12, 0x94643b84, 0xd6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0xa00ae27, 0x7d079eb1,
+0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x26d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x5005713,
+0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0xcb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0xbdbdf21,
+0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+#endif /* GENTABLE */
+
+U32
+getcrc(char *c, int len, U32 crcinit)
+{
+ register U32 crc;
+ char *e = c + len;
+
+ crc = crcinit^0xFFFFFFFF;
+ //crc = crcinit;
+ while (c < e) {
+ printf("CALCULATING CRC OF: %X;\n", (crc^ *c) & 0xFF);
+ crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[ (crc^ *c) & 0xFF ];
+ //crc = ((crc << 8) & 0xFFFFFF00) ^ crcTable[ (crc^ *c) & 0xFF ];
+ ++c;
+ }
+ return( crc^0xFFFFFFFF );
+ //return( crc );
+}
+
+#define BUFSIZE 32768
+
+U32
+getcrc_fp( PerlIO *fp, U32 crcinit )
+{
+ register U32 crc;
+ register U16 len;
+ unsigned char buf[BUFSIZE];
+
+ crc = crcinit^0xFFFFFFFF;
+ while((len = PerlIO_read(fp, buf, BUFSIZE)) > 0 ) {
+ unsigned char * p = buf;
+ do {
+ crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[(unsigned char)( (crc & 0xff) ^ *(p++) )];
+ } while (--len);
+ }
+ return( crc^0xFFFFFFFF );
+}
+
+svtype
+getsvtype(SV *sv)
+{
+ if (sv == NULL )
+ return SVt_NULL;
+ if (SvROK(sv))
+ return SvTYPE(SvRV(sv));
+ else
+ return SvTYPE(sv);
+}
+
+MODULE = BN::CRC32 PACKAGE = BN::CRC32
+
+VERSIONCHECK: DISABLE
+PROTOTYPES: DISABLE
+
+U32
+crc32(data, ...)
+ char *data = NO_INIT
+ PREINIT:
+ U32 crcinit = 0xFFFFFFFF;
+ STRLEN data_len;
+ PPCODE:
+ int sv_type;
+ IO *io;
+ SV *sv;
+ U32 rv = 0;
+ {
+#ifdef GENTABLE
+ crcgen();
+#endif /* GENTABLE */
+ /* Horst Fickenscher <horst_fickenscher@sepp.de> mailed me that it
+ could be useful to supply an initial value other than 0, e.g.
+ to calculate checksums of big files without the need of keeping
+ them comletely in memory */
+ if ( items > 1 )
+ crcinit = (U32) SvNV(ST(items - 1));
+ printf("crcinit: %x.\n", crcinit);
+
+ sv_type = getsvtype(ST(0));
+
+ if (sv_type == SVt_PVGV)
+ {
+ io = sv_2io(ST(0));
+ rv = getcrc_fp(IoIFP(io), crcinit);
+ }
+ else
+ {
+ data = (char *)SvPV(ST(0),data_len);
+ printf("C: data: ");
+ int l; char c_high, c_low;
+ for(l=0;l<data_len;l++){
+ //printf("%02x ", (unsigned char*)data[l]);
+ char c;
+ switch( (data[l]>>4)&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_high = c;
+ switch( (data[l])&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_low = c;
+ printf("%c%c ", c_high, c_low);
+ }
+ printf(";\n");
+ rv = getcrc(data, data_len, crcinit);
+ }
+ EXTEND(sp, 1);
+ sv = newSV(0);
+ sv_setuv(sv, (UV)rv);
+ PUSHs(sv_2mortal(sv));
+ }
--- /dev/null
+/*
+ Perl Extension for 32bit CRC computations
+ by Soenke J. Peters
+*/
+
+#include "EXTERN.h"
+#include "perl.h"
+#include "XSUB.h"
+
+/*
+ Based on CRC-32 version 1.04 by Craig Bruce, 05-Dec-1994
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef GENTABLE
+U32
+crcTable[256];
+
+void
+crcgen( void )
+{
+ U32 crc, poly;
+ int i, j;
+
+ //poly = 0xEDB88320L;
+ poly = 0x04C11DB7L;
+ for (i=0; i<256; i++) {
+ crc = i<<24;
+ for (j=8; j>0; j--) {
+ //if (crc&1) {
+ // crc = (crc >> 1) ^ poly;
+ if (crc&0x80000000) {
+ crc = (crc << 1) ^ poly;
+ } else {
+ // crc >>= 1;
+ crc <<= 1;
+ }
+ }
+ crcTable[i] = crc;
+ }
+ printf("crcTable[15]=%x\n", crcTable[15]);
+}
+#else /* GENTABLE */
+U32
+crcTable[256] = {
+0x0, 0x77073096, 0xee0e612c, 0x990951ba, 0x76dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+0xedb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x9b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+0x76dc4190, 0x1db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x6b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+0x7807c9a2, 0xf00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x86d3d2d, 0x91646c97, 0xe6635c01,
+0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+0xedb88320, 0x9abfb3b6, 0x3b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x4db2615, 0x73dc1683,
+0xe3630b12, 0x94643b84, 0xd6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0xa00ae27, 0x7d079eb1,
+0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x26d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x5005713,
+0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0xcb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0xbdbdf21,
+0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+#endif /* GENTABLE */
+
+U32
+getcrc(char *c, int len, U32 crcinit)
+{
+ register U32 crc;
+ char *e = c + len;
+
+ crc = crcinit^0xFFFFFFFF;
+ while (c < e) {
+ printf("CALCULATING CRC OF: %X;\n", (crc^ *c) & 0xFF);
+ //crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[ (crc^ *c) & 0xFF ];
+ crc = ((crc << 8) & 0xFFFFFF00) ^ crcTable[ (crc^ *c) & 0xFF ];
+ ++c;
+ }
+ return( crc^0xFFFFFFFF );
+}
+
+#define BUFSIZE 32768
+
+U32
+getcrc_fp( PerlIO *fp, U32 crcinit )
+{
+ register U32 crc;
+ register U16 len;
+ unsigned char buf[BUFSIZE];
+
+ crc = crcinit^0xFFFFFFFF;
+ while((len = PerlIO_read(fp, buf, BUFSIZE)) > 0 ) {
+ unsigned char * p = buf;
+ do {
+ crc = ((crc >> 8) & 0x00FFFFFF) ^ crcTable[(unsigned char)( (crc & 0xff) ^ *(p++) )];
+ } while (--len);
+ }
+ return( crc^0xFFFFFFFF );
+}
+
+svtype
+getsvtype(SV *sv)
+{
+ if (sv == NULL )
+ return SVt_NULL;
+ if (SvROK(sv))
+ return SvTYPE(SvRV(sv));
+ else
+ return SvTYPE(sv);
+}
+
+MODULE = BN::CRC32 PACKAGE = BN::CRC32
+
+VERSIONCHECK: DISABLE
+PROTOTYPES: DISABLE
+
+U32
+crc32(data, ...)
+ char *data = NO_INIT
+ PREINIT:
+ U32 crcinit = 0xFFFFFFFF;
+ STRLEN data_len;
+ PPCODE:
+ int sv_type;
+ IO *io;
+ SV *sv;
+ U32 rv = 0;
+ {
+#ifdef GENTABLE
+ crcgen();
+#endif /* GENTABLE */
+ /* Horst Fickenscher <horst_fickenscher@sepp.de> mailed me that it
+ could be useful to supply an initial value other than 0, e.g.
+ to calculate checksums of big files without the need of keeping
+ them comletely in memory */
+ if ( items > 1 )
+ crcinit = (U32) SvNV(ST(items - 1));
+ printf("crcinit: %x.\n", crcinit);
+
+ sv_type = getsvtype(ST(0));
+
+ if (sv_type == SVt_PVGV)
+ {
+ io = sv_2io(ST(0));
+ rv = getcrc_fp(IoIFP(io), crcinit);
+ }
+ else
+ {
+ data = (char *)SvPV(ST(0),data_len);
+ printf("C: data: ");
+ int l; char c_high, c_low;
+ for(l=0;l<data_len;l++){
+ //printf("%02x ", (unsigned char*)data[l]);
+ char c;
+ switch( (data[l]>>4)&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_high = c;
+ switch( (data[l])&0x0F) {
+ case 0x00: c = '0'; break;
+ case 0x01: c = '1'; break;
+ case 0x02: c = '2'; break;
+ case 0x03: c = '3'; break;
+ case 0x04: c = '4'; break;
+ case 0x05: c = '5'; break;
+ case 0x06: c = '6'; break;
+ case 0x07: c = '7'; break;
+ case 0x08: c = '8'; break;
+ case 0x09: c = '9'; break;
+ case 0x0a: c = 'a'; break;
+ case 0x0b: c = 'b'; break;
+ case 0x0c: c = 'c'; break;
+ case 0x0d: c = 'd'; break;
+ case 0x0e: c = 'e'; break;
+ case 0x0f: c = 'f'; break;
+ }
+ c_low = c;
+ printf("%c%c ", c_high, c_low);
+ }
+ printf(";\n");
+ rv = getcrc(data, data_len, crcinit);
+ }
+ EXTEND(sp, 1);
+ sv = newSV(0);
+ sv_setuv(sv, (UV)rv);
+ PUSHs(sv_2mortal(sv));
+ }
--- /dev/null
+#/usr/bin/perl -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/lib
+#
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+use BN::CRC32;
+
+print "PERL:" . crc32("A string.");
--- /dev/null
+10
+
+dir
+135
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj/trb_maps_jtag3/ui/libs/Config
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj
+
+
+
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+b00609d0-aec6-11df-b1c7-bba583a822eb
+\f
+Abstract
+dir
+\f
+Abstract.pm
+file
+
+
+
+
+2011-11-23T15:34:42.000000Z
+f5d25acfa44435494d72210c975f97c2
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+11703
+\f
--- /dev/null
+package Config::Abstract;
+
+use 5.006;
+use strict;
+use warnings;
+
+use Data::Dumper;
+
+require Exporter;
+#use AutoLoader qw(AUTOLOAD);
+
+use overload qw{""} => \&_to_string;
+
+our @ISA = qw(Exporter);
+our %EXPORT_TAGS = ( 'all' => [ qw( ) ] );
+our @EXPORT_OK = ( @{ $EXPORT_TAGS{'all'} } );
+our @EXPORT = qw( );
+
+our $VERSION = '0.16';
+
+#
+# ------------------------------------------------------------------------------------------------------- structural methods -----
+#
+
+sub new {
+ my($class,$initialiser) = @_;
+ my $self = {
+ _settings => undef,
+ _settingsfile => undef
+ };
+ bless $self,ref $class || $class;
+ $self->init($initialiser);
+ return $self;
+}
+
+sub init {
+ my($self,$settingsfile) = @_;
+ return unless(defined($settingsfile));
+ return if($settingsfile eq '');
+ $self->{_settings} = $self->_read_settings($settingsfile);
+ $self->{_settingsfile} = $settingsfile;
+}
+
+
+#
+# --------------------------------------------------------------------------------------------------------- accessor methods -----
+#
+
+sub get_all_settings {
+ my($self) = @_;
+ # Make sure we don't crash and burn trying to return a hash from an undef reference
+ return undef unless(defined($self->{_settings}));
+ # Return the settings as a hash in array contect and a hash reference in scalar context
+ if(wantarray){
+ return %{$self->{_settings}};
+ }else{
+ return $self->{_settings};
+ }
+}
+
+sub get_entry {
+ my($self,$entryname) = @_;
+ my $val;
+ if($entryname =~ m|//|){
+ # Getting an entry by path
+ my $unpathed = $self->_unpath($entryname);
+ eval("\$val = \"\${ \$self->{_settings} }$unpathed\";");
+# print("\$val = '\${ \$self->{_settings} }$unpathed ';\n");#DEBUG!!!
+# print("\$val: $val\n");#DEBUG!!!
+ }else{
+ $val = ${$self->{_settings}}{$entryname};
+ }
+ if(defined($val)){
+ if(wantarray && ref($val) eq 'HASH'){
+# print STDERR ("Returning HASH in $self" . "->get_entry($entryname)\n");#DEBUG!!!
+ return(%{$val});
+ }else{
+# print STDERR ("Returning ref in $self" . "->get_entry($entryname)\n");#DEBUG!!!
+ return($val);
+ }
+ }else{
+ return (wantarray ? () : undef);
+ }
+}
+
+sub get_entry_setting {
+ my($self,$entryname,$settingname,$default) = @_;
+ # Return undef if the requested entry doesn't exist
+ my %entry = ();
+ return(undef) unless(%entry = $self->get_entry($entryname));
+ if(defined($entry{$settingname})){
+ return $entry{$settingname};
+ }else{
+ return $default;
+ }
+}
+
+sub get {
+ my($self,$section,$key,$default) = @_;
+ # If everything up to the key is given, get a specific key
+ return $self->get_entry_setting($section,$key,$default) if(defined($key));
+ # If section is given, but not key, get a specific section
+ return $self->get_entry($section) if(defined($section));
+ # If no parameter is given, return the entire hash
+ return $self->get_all_settings();
+}
+
+#
+# ---------------------------------------------------------------------------------------------------------- mutator methods -----
+#
+
+sub set_all_settings {
+ my($self,%allsettings) = @_;
+ return %{$self->{_settings}} = %allsettings;
+}
+
+sub set_entry {
+ my($self,$entryname,$entry) = @_;
+ my $unpathed = $self->_unpath($entryname);
+ my $val;
+ eval('${$self->{_settings}}' . $unpathed . ' = $entry;');
+ return $self->get_entry($entryname) ;
+}
+
+sub set_entry_setting {
+ my($self,$entryname,$settingname,$setting) = @_;
+ return (${${$self->{_settings}}{$entryname}}{$settingname} = $setting);
+}
+
+sub set {
+ my($self,$section,$key,$value) = @_;
+ # If everything up to the key is given, set a specific key
+ return $self->set_entry_setting($section,$key,$value) if(defined($value));
+ # If section is given, but not key, set a specific section
+ return $self->set_entry($section,$key) if(defined($key));
+ # If no parameter is given, return the entire hash
+ return $self->set_all_settings(%{$section});
+}
+
+sub exists {
+ my($self,$section,$key) = @_;
+ return defined($self->{$section}) unless (defined($key));
+ return defined($self->{$section}{$key});
+}
+
+sub get_entry_names {
+ my($self) = @_;
+ return sort(keys(%{$self->{_settings}}));
+}
+
+#
+# ------------------------------------------------------------------------------------------------------- arithmetic methods -----
+#
+
+##################################################
+#%name: diff
+#%syntax: diff($other_config_object)
+#%summary: Generates an object with overrides for entries that can be used to patch $self into $other_config_object
+#%returns: a Config::Abstract object
+#%NB: This method is nowhere near working atm /EWT
+sub diff {
+ my($self,$diff) = @_;
+ my %self_pathed = $self->_pathalise_object( '',$self->{_settings} );
+ my %diff_pathed = $self->_pathalise_object( '',$diff->{_settings} );
+ my $result = $self->new();
+ while( my($k,$v) = each(%diff_pathed) ) {
+ next if( defined($self_pathed{$k}) && $self_pathed{$k} eq $v);
+ $result->set($k,$v);
+ }
+ return $result;
+}
+
+
+##################################################
+#%name: patch
+#%syntax: patch($patch_from_other_config_object)
+#%summary: Overrides all settings that are found in the $patch object with the $patch values
+#%returns: Nothing
+sub patch {
+ my($self,$patch) = @_;
+ my %patch_pathed = $self->_pathalise_object( '',$patch->{_settings} );
+ while( my($k,$v) = each(%patch_pathed) ) {
+ $self->set($k,$v);
+ }
+}
+
+
+
+sub _unpath {
+ my($self,$path) = @_;
+ $path =~ s|^/+|{'|;
+ $path =~ s|/+|'}{'|g;
+ $path .= '\'}';
+ return $path;
+}
+##################################################
+#%name: _pathalise_object
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Recursively generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _pathalise_object{
+ my($self,$name,$obj,@parents) = @_;
+ my @result = ();
+ if(ref($obj) eq 'HASH'){
+ unless($name eq '' ){
+ push(@parents,$name);
+ }
+ while(my($key,$val) = each(%{$obj})){
+ push(@result,$self->_pathalise_object($key,$val,@parents));
+ }
+ }elsif(ref($obj) eq 'SCALAR'){
+ push(@result,'//' . join('//',@parents) . "//$name",${$obj});
+ }elsif(ref($obj) eq 'ARRAY'){
+ push(@parents,$name);
+ for(my $i = 0;scalar(@{$obj});$i++){
+ push(@result,$self->_pathalise_object($i,${$obj}[$i],@parents));
+ }
+ }else{
+ push(@result,'//' . join('//',@parents) . "//$name",$obj);
+ }
+ return @result;
+}
+#
+# ------------------------------------------------------------------------------------------------ (de)serialisation methods -----
+#
+
+##################################################
+#%name: _to_string
+#%syntax: _to_string
+#%summary: Recursively generates a string representation of the settings hash
+#%returns: a string in perl source format
+
+sub _to_string{
+ my($self) = @_;
+ return $self->_dumpobject();
+}
+
+##################################################
+#%name: _dumpobject
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _dumpobject{
+ my($self) = @_;
+ my $dumper = Data::Dumper->new([$self->{_settings}],[qw(settings)]);
+ $dumper->Purity(1);
+ return($dumper->Dump());
+}
+
+##################################################
+#%name: _read_settings
+#%syntax: _read_settings(<$settingsfilename>)
+#%summary: Reads the key-values to keep track of
+#%returns: a reference to a hash of $key:$value
+
+sub _read_settings{
+ my ($self,$settingdata) = @_;
+ my @conflines;
+ if(ref($settingdata) eq 'ARRAY'){
+ @conflines = @{$settingdata};
+ }else{
+ my $settingsfile = $settingdata;
+ # Read in the ini file we want to use
+ # Probably not a good idea to die on error at this
+ # point, but that's what we've got for the moment
+ open(SETTINGS,$settingsfile) || die("Failed to open ini file ($settingsfile) for reading\n");
+ @conflines = <SETTINGS>;
+ close(SETTINGS);
+ }
+ my $settings = $self->_parse_settings_file(@conflines);
+ return($settings);
+}
+
+##################################################
+#%name: _parse_settings_file
+#%syntax: _parse_settings_file(<@settings>)
+#%summary: Reads the key-values into a hash
+#%returns: a reference to a hash of $key:$value
+
+sub _parse_settings_file{
+ my $settings = {};
+ eval(join('',@_));
+ return($settings);
+}
+
+#
+# ---------------------------------------------------------------------------------------------------------- utility methods -----
+#
+
+
+sub expand_tilde {
+ defined($ENV{'HOME'}) && do {
+ $_[0] =~ s/^~/$ENV{'HOME'}/;
+ };
+ return $_[0];
+}
+
+
+# We provide a DESTROY method so that the autoloader
+# doesn't bother trying to find it.
+sub DESTROY {
+ print STDERR ("Destroying Config::Abstract\n"); #DEBUG!!!
+}
+
+1;
+__END__
+=head1 NAME
+
+Config::Abstract - Perl extension for abstracting configuration files
+
+=head1 SYNOPSIS
+
+ use Config::Abstract;
+ my $ini = new Config::Abstract('testdata.pl');
+
+=head1 DESCRIPTION
+
+ Config::Abstract is the base class for a number of other classes
+ created to facilitate use and handling of a variety of different
+ configuration file formats. It uses the Data::Dumper file format to
+ serialise it self and can be initialise from a file of that format
+
+=head1 EXAMPLES
+
+ We assume the content of the file 'testdata.pl' to be:
+
+ $settings = {
+ 'book' => {
+ 'chapter1' => {
+ 'title' => 'The First Chapter, ever',
+ 'file' => 'book/chapter1.txt'
+ },
+ 'title' => 'A book of chapters',
+ 'chapter2' => {
+ 'title' => 'The Next Chapter, after the First Chapter, ever',
+ 'file' => 'book/chapter2.txt'
+ },
+ 'author' => 'Me, Myself and Irene'
+ }
+ };
+
+ use Config::Abstract;
+ my $settingsfile = 'testdata.pl';
+ my $abstract = new Config::Abstract($settingsfile);
+
+ my %book = $abstract->get_entry('book');
+ my %chap1 = $abstract->get_entry_setting('book','chapter1');
+ my $chap1title = $chapter1{'title'};
+
+ # Want to see the file?
+ # If you can live without comments and blank lines ;),
+ # try this:
+ print("My abstract file looks like this:\n$abstract\nCool, huh?\n");
+
+ # We can also create an ini file from it
+ # A bit crude, but it does the job
+ bless($abstract,'Config::Abstract::Ini');
+ print($abstract);
+
+=head1 METHODS
+
+=item get_all_settings
+
+Returns a hash of all settings found in the processed file
+
+=item get ENTRYPATH
+
+Returns the setting at the given 'path' where the path divider is '//'.
+
+=item get_entry ENTRYNAME
+
+Returns a hash of the settings within the entry ENTRYNAME. OBSOLETE, use get instead
+
+=item get_entry_setting ENTRYNAME,SETTINGNAME [,DEFAULTVALUE]
+
+Returns the value corresponding to ENTRYNAME,SETTINGSNAME. If the value isn't set it returns undef or, optionally, the DEFAULTVALUE. OBSOLETE, use get instead
+
+=item set_all_settings SETTINGSHASH
+
+Fill settings with data from SETTINGSHASH
+
+=item set ENTRYPATH VALUE
+
+Setting the entry at the given 'path', where the path divider is '//', to VALUE.
+
+=item set_entry ENTRYNAME,ENTRYHASH
+
+Fill the entry ENTRYNAME with data from ENTRYHASH
+
+=item set_entry_setting ENTRYNAME,SETTINGNAME,VALUE
+
+Set the setting ENTRYNAME,SETTINGSNAME to VALUE
+
+=item diff OBJECT
+
+Returns an object of type Config::Abstract that is a representation of the values in this object that needs altering to make it identical to OBJECT
+
+=item patch OBJECT
+
+Sets the entries in this object to whatever they are in OBJECT, creating entries as necessary. $obj_a->patch( $obj_a->diff( $obj_b ) ); should make $obj_a identical to $obj_b except for entries in obj_a that don't exist in $obj_b.
+
+=head1 COPYRIGHT
+
+Copyright (c) 2003 Eddie Olsson. All rights reserved.
+
+ This library is free software; you can redistribute it
+ and/or modify it under the same terms as Perl itself.
+
+
+=head1 AUTHOR
+
+Eddie Olsson <ewt@avajadi.org>
+
+=head1 SEE ALSO
+
+L<perl>.
+
+=cut
--- /dev/null
+package Config::Abstract;
+
+use 5.006;
+use strict;
+use warnings;
+
+use Data::Dumper;
+
+require Exporter;
+#use AutoLoader qw(AUTOLOAD);
+
+use overload qw{""} => \&_to_string;
+
+our @ISA = qw(Exporter);
+our %EXPORT_TAGS = ( 'all' => [ qw( ) ] );
+our @EXPORT_OK = ( @{ $EXPORT_TAGS{'all'} } );
+our @EXPORT = qw( );
+
+our $VERSION = '0.16';
+
+#
+# ------------------------------------------------------------------------------------------------------- structural methods -----
+#
+
+sub new {
+ my($class,$initialiser) = @_;
+ my $self = {
+ _settings => undef,
+ _settingsfile => undef
+ };
+ bless $self,ref $class || $class;
+ $self->init($initialiser);
+ return $self;
+}
+
+sub init {
+ my($self,$settingsfile) = @_;
+ return unless(defined($settingsfile));
+ return if($settingsfile eq '');
+ $self->{_settings} = $self->_read_settings($settingsfile);
+ $self->{_settingsfile} = $settingsfile;
+}
+
+
+#
+# --------------------------------------------------------------------------------------------------------- accessor methods -----
+#
+
+sub get_all_settings {
+ my($self) = @_;
+ # Make sure we don't crash and burn trying to return a hash from an undef reference
+ return undef unless(defined($self->{_settings}));
+ # Return the settings as a hash in array contect and a hash reference in scalar context
+ if(wantarray){
+ return %{$self->{_settings}};
+ }else{
+ return $self->{_settings};
+ }
+}
+
+sub get_entry {
+ my($self,$entryname) = @_;
+ my $val;
+ if($entryname =~ m|//|){
+ # Getting an entry by path
+ my $unpathed = $self->_unpath($entryname);
+ eval("\$val = \"\${ \$self->{_settings} }$unpathed\";");
+# print("\$val = '\${ \$self->{_settings} }$unpathed ';\n");#DEBUG!!!
+# print("\$val: $val\n");#DEBUG!!!
+ }else{
+ $val = ${$self->{_settings}}{$entryname};
+ }
+ if(defined($val)){
+ if(wantarray && ref($val) eq 'HASH'){
+# print STDERR ("Returning HASH in $self" . "->get_entry($entryname)\n");#DEBUG!!!
+ return(%{$val});
+ }else{
+# print STDERR ("Returning ref in $self" . "->get_entry($entryname)\n");#DEBUG!!!
+ return($val);
+ }
+ }else{
+ return (wantarray ? () : undef);
+ }
+}
+
+sub get_entry_setting {
+ my($self,$entryname,$settingname,$default) = @_;
+ # Return undef if the requested entry doesn't exist
+ my %entry = ();
+ return(undef) unless(%entry = $self->get_entry($entryname));
+ if(defined($entry{$settingname})){
+ return $entry{$settingname};
+ }else{
+ return $default;
+ }
+}
+
+sub get {
+ my($self,$section,$key,$default) = @_;
+ # If everything up to the key is given, get a specific key
+ return $self->get_entry_setting($section,$key,$default) if(defined($key));
+ # If section is given, but not key, get a specific section
+ return $self->get_entry($section) if(defined($section));
+ # If no parameter is given, return the entire hash
+ return $self->get_all_settings();
+}
+
+#
+# ---------------------------------------------------------------------------------------------------------- mutator methods -----
+#
+
+sub set_all_settings {
+ my($self,%allsettings) = @_;
+ return %{$self->{_settings}} = %allsettings;
+}
+
+sub set_entry {
+ my($self,$entryname,$entry) = @_;
+ my $unpathed = $self->_unpath($entryname);
+ my $val;
+ eval('${$self->{_settings}}' . $unpathed . ' = $entry;');
+ return $self->get_entry($entryname) ;
+}
+
+sub set_entry_setting {
+ my($self,$entryname,$settingname,$setting) = @_;
+ return (${${$self->{_settings}}{$entryname}}{$settingname} = $setting);
+}
+
+sub set {
+ my($self,$section,$key,$value) = @_;
+ # If everything up to the key is given, set a specific key
+ return $self->set_entry_setting($section,$key,$value) if(defined($value));
+ # If section is given, but not key, set a specific section
+ return $self->set_entry($section,$key) if(defined($key));
+ # If no parameter is given, return the entire hash
+ return $self->set_all_settings(%{$section});
+}
+
+sub exists {
+ my($self,$section,$key) = @_;
+ return defined($self->{$section}) unless (defined($key));
+ return defined($self->{$section}{$key});
+}
+
+sub get_entry_names {
+ my($self) = @_;
+ return sort(keys(%{$self->{_settings}}));
+}
+
+#
+# ------------------------------------------------------------------------------------------------------- arithmetic methods -----
+#
+
+##################################################
+#%name: diff
+#%syntax: diff($other_config_object)
+#%summary: Generates an object with overrides for entries that can be used to patch $self into $other_config_object
+#%returns: a Config::Abstract object
+#%NB: This method is nowhere near working atm /EWT
+sub diff {
+ my($self,$diff) = @_;
+ my %self_pathed = $self->_pathalise_object( '',$self->{_settings} );
+ my %diff_pathed = $self->_pathalise_object( '',$diff->{_settings} );
+ my $result = $self->new();
+ while( my($k,$v) = each(%diff_pathed) ) {
+ next if( defined($self_pathed{$k}) && $self_pathed{$k} eq $v);
+ $result->set($k,$v);
+ }
+ return $result;
+}
+
+
+##################################################
+#%name: patch
+#%syntax: patch($patch_from_other_config_object)
+#%summary: Overrides all settings that are found in the $patch object with the $patch values
+#%returns: Nothing
+sub patch {
+ my($self,$patch) = @_;
+ my %patch_pathed = $self->_pathalise_object( '',$patch->{_settings} );
+ while( my($k,$v) = each(%patch_pathed) ) {
+ $self->set($k,$v);
+ }
+}
+
+
+
+sub _unpath {
+ my($self,$path) = @_;
+ $path =~ s|^/+|{'|;
+ $path =~ s|/+|'}{'|g;
+ $path .= '\'}';
+ return $path;
+}
+##################################################
+#%name: _pathalise_object
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Recursively generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _pathalise_object{
+ my($self,$name,$obj,@parents) = @_;
+ my @result = ();
+ if(ref($obj) eq 'HASH'){
+ unless($name eq '' ){
+ push(@parents,$name);
+ }
+ while(my($key,$val) = each(%{$obj})){
+ push(@result,$self->_pathalise_object($key,$val,@parents));
+ }
+ }elsif(ref($obj) eq 'SCALAR'){
+ push(@result,'//' . join('//',@parents) . "//$name",${$obj});
+ }elsif(ref($obj) eq 'ARRAY'){
+ push(@parents,$name);
+ for(my $i = 0;scalar(@{$obj});$i++){
+ push(@result,$self->_pathalise_object($i,${$obj}[$i],@parents));
+ }
+ }else{
+ push(@result,'//' . join('//',@parents) . "//$name",$obj);
+ }
+ return @result;
+}
+#
+# ------------------------------------------------------------------------------------------------ (de)serialisation methods -----
+#
+
+##################################################
+#%name: _to_string
+#%syntax: _to_string
+#%summary: Recursively generates a string representation of the settings hash
+#%returns: a string in perl source format
+
+sub _to_string{
+ my($self) = @_;
+ return $self->_dumpobject();
+}
+
+##################################################
+#%name: _dumpobject
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _dumpobject{
+ my($self) = @_;
+ my $dumper = Data::Dumper->new([$self->{_settings}],[qw(settings)]);
+ $dumper->Purity(1);
+ return($dumper->Dump());
+}
+
+##################################################
+#%name: _read_settings
+#%syntax: _read_settings(<$settingsfilename>)
+#%summary: Reads the key-values to keep track of
+#%returns: a reference to a hash of $key:$value
+
+sub _read_settings{
+ my ($self,$settingdata) = @_;
+ my @conflines;
+ if(ref($settingdata) eq 'ARRAY'){
+ @conflines = @{$settingdata};
+ }else{
+ my $settingsfile = $settingdata;
+ # Read in the ini file we want to use
+ # Probably not a good idea to die on error at this
+ # point, but that's what we've got for the moment
+ open(SETTINGS,$settingsfile) || die("Failed to open ini file ($settingsfile) for reading\n");
+ @conflines = <SETTINGS>;
+ close(SETTINGS);
+ }
+ my $settings = $self->_parse_settings_file(@conflines);
+ return($settings);
+}
+
+##################################################
+#%name: _parse_settings_file
+#%syntax: _parse_settings_file(<@settings>)
+#%summary: Reads the key-values into a hash
+#%returns: a reference to a hash of $key:$value
+
+sub _parse_settings_file{
+ my $settings = {};
+ eval(join('',@_));
+ return($settings);
+}
+
+#
+# ---------------------------------------------------------------------------------------------------------- utility methods -----
+#
+
+
+sub expand_tilde {
+ defined($ENV{'HOME'}) && do {
+ $_[0] =~ s/^~/$ENV{'HOME'}/;
+ };
+ return $_[0];
+}
+
+
+# We provide a DESTROY method so that the autoloader
+# doesn't bother trying to find it.
+sub DESTROY {
+ print STDERR ("Destroying Config::Abstract\n"); #DEBUG!!!
+}
+
+1;
+__END__
+=head1 NAME
+
+Config::Abstract - Perl extension for abstracting configuration files
+
+=head1 SYNOPSIS
+
+ use Config::Abstract;
+ my $ini = new Config::Abstract('testdata.pl');
+
+=head1 DESCRIPTION
+
+ Config::Abstract is the base class for a number of other classes
+ created to facilitate use and handling of a variety of different
+ configuration file formats. It uses the Data::Dumper file format to
+ serialise it self and can be initialise from a file of that format
+
+=head1 EXAMPLES
+
+ We assume the content of the file 'testdata.pl' to be:
+
+ $settings = {
+ 'book' => {
+ 'chapter1' => {
+ 'title' => 'The First Chapter, ever',
+ 'file' => 'book/chapter1.txt'
+ },
+ 'title' => 'A book of chapters',
+ 'chapter2' => {
+ 'title' => 'The Next Chapter, after the First Chapter, ever',
+ 'file' => 'book/chapter2.txt'
+ },
+ 'author' => 'Me, Myself and Irene'
+ }
+ };
+
+ use Config::Abstract;
+ my $settingsfile = 'testdata.pl';
+ my $abstract = new Config::Abstract($settingsfile);
+
+ my %book = $abstract->get_entry('book');
+ my %chap1 = $abstract->get_entry_setting('book','chapter1');
+ my $chap1title = $chapter1{'title'};
+
+ # Want to see the file?
+ # If you can live without comments and blank lines ;),
+ # try this:
+ print("My abstract file looks like this:\n$abstract\nCool, huh?\n");
+
+ # We can also create an ini file from it
+ # A bit crude, but it does the job
+ bless($abstract,'Config::Abstract::Ini');
+ print($abstract);
+
+=head1 METHODS
+
+=item get_all_settings
+
+Returns a hash of all settings found in the processed file
+
+=item get ENTRYPATH
+
+Returns the setting at the given 'path' where the path divider is '//'.
+
+=item get_entry ENTRYNAME
+
+Returns a hash of the settings within the entry ENTRYNAME. OBSOLETE, use get instead
+
+=item get_entry_setting ENTRYNAME,SETTINGNAME [,DEFAULTVALUE]
+
+Returns the value corresponding to ENTRYNAME,SETTINGSNAME. If the value isn't set it returns undef or, optionally, the DEFAULTVALUE. OBSOLETE, use get instead
+
+=item set_all_settings SETTINGSHASH
+
+Fill settings with data from SETTINGSHASH
+
+=item set ENTRYPATH VALUE
+
+Setting the entry at the given 'path', where the path divider is '//', to VALUE.
+
+=item set_entry ENTRYNAME,ENTRYHASH
+
+Fill the entry ENTRYNAME with data from ENTRYHASH
+
+=item set_entry_setting ENTRYNAME,SETTINGNAME,VALUE
+
+Set the setting ENTRYNAME,SETTINGSNAME to VALUE
+
+=item diff OBJECT
+
+Returns an object of type Config::Abstract that is a representation of the values in this object that needs altering to make it identical to OBJECT
+
+=item patch OBJECT
+
+Sets the entries in this object to whatever they are in OBJECT, creating entries as necessary. $obj_a->patch( $obj_a->diff( $obj_b ) ); should make $obj_a identical to $obj_b except for entries in obj_a that don't exist in $obj_b.
+
+=head1 COPYRIGHT
+
+Copyright (c) 2003 Eddie Olsson. All rights reserved.
+
+ This library is free software; you can redistribute it
+ and/or modify it under the same terms as Perl itself.
+
+
+=head1 AUTHOR
+
+Eddie Olsson <ewt@avajadi.org>
+
+=head1 SEE ALSO
+
+L<perl>.
+
+=cut
--- /dev/null
+10
+
+dir
+135
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj/trb_maps_jtag3/ui/libs/Config/Abstract
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj
+
+
+
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+b00609d0-aec6-11df-b1c7-bba583a822eb
+\f
+Ini.pm
+file
+
+
+
+
+2011-11-23T15:34:43.000000Z
+d01b31af88c63accbc49dc8b5e1e4882
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+7188
+\f
--- /dev/null
+package Config::Abstract::Ini;
+
+use 5.006;
+use strict;
+use warnings;
+
+require Exporter;
+use Config::Abstract;
+
+use overload qw{""} => \&_to_string;
+
+our @ISA = qw(Config::Abstract Exporter);
+our %EXPORT_TAGS = ( 'all' => [ qw( ) ] );
+our @EXPORT_OK = ( @{ $EXPORT_TAGS{'all'} } );
+our @EXPORT = qw( );
+
+our $VERSION = '0.16';
+
+#
+# ------------------------------------------------------------------------------------------------------- structural methods -----
+#
+
+# All inherited from Config::Abstract
+
+#
+# --------------------------------------------------------------------------------------------------------- accessor methods -----
+#
+
+# All inherited from Config::Abstract
+
+#
+# ------------------------------------------------------------------------------------------------ (un)serialisation methods -----
+#
+
+##################################################
+#%name: _to_string
+#%syntax: _to_string
+#%summary: Recursively generates a string representation of the settings hash
+#%returns: a string in .ini format
+
+sub _to_string{
+ my($self) = @_;
+ return $self->_dumpobject('',$self->{_settings});
+}
+
+##################################################
+#%name: _dumpobject
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Recursively generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _dumpobject{
+ my($self,$name,$obj,@parents) = @_;
+ my @result = ();
+ if(ref($obj) eq 'HASH'){
+ unless($name eq ''){
+ push(@parents,"$name");
+ push(@result,'[' . join('::',@parents) . ']');
+ }
+ while(my($key,$val) = each(%{$obj})){
+ push(@result,$self->_dumpobject($key,$val,@parents));
+ }
+ }elsif(ref($obj) eq 'SCALAR'){
+ push(@result,"$name = ${$obj}");
+ }elsif(ref($obj) eq 'ARRAY'){
+ push(@parents,"$name");
+ push(@result,'[' . join('::',@parents) . ']');
+ for(my $i = 0;scalar(@{$obj});$i++){
+ push(@result,$self->_dumpobject($i,${$obj}[$i],@parents));
+ }
+ }else{
+# print("Why are we here? name: " . ( defined($name) ? $name : 'empty' ) . " obj:" . ( defined($obj) ? $obj : 'empty' ) . "\n");#DEBUG!!!
+ push(@result,"$name = " . (defined($obj) ? $obj : '') ) unless(!defined($name));
+ }
+ return(join("\n",@result));
+}
+
+
+##################################################
+#%name: _parse_settings_file
+#%syntax: _parse_settings_file(<@settings>)
+#%summary: Reads the projects to keep track of
+#%returns: a hash of $projectkey:$projectlabel
+
+sub _parse_settings_file{
+ my %result = ();
+ my ($entry,$subentry) = ('',undef);
+ chomp(@_);
+ foreach(@_){
+ # Get rid of starting/ending whitespace
+ s/^\s*(.*?)\s*$/$1/;
+
+ #Delete comments
+ ($_) = split(/[;#]/,$_);
+ #Skip if there's no data
+ next if((! defined($_)) || $_ eq '');
+ /^\s*(.*?)\s*=\s*(['"]|)(.*)\2\s*/ && do {
+ my($key,$val) = ($1,$3);
+ next if($key eq '' || $val eq '');
+ if(! defined($subentry) || $subentry =~ /^\s*$/){
+ ${$result{$entry}}{$key} = $val;
+ }else{
+ ${$result{$entry}}{$subentry}{$key} = $val;
+ }
+ next;
+ };
+ # Select a new entry if this is such a line
+ /\[(.*?)\]/ && do{
+
+ $_ = $1;
+ ($entry,$subentry) = split('::');
+ if(! defined($subentry) || $subentry =~ /^\s*$/){
+ $result{$entry} = {};
+ }elsif($result{$entry}){
+ $result{$entry}{$subentry} = {};
+ }
+ next;
+ };
+ }
+ return(\%result);
+}
+
+# We provide a DESTROY method so that the autoloader
+# doesn't bother trying to find it.
+sub DESTROY { }
+
+# Autoload methods go after =cut, and are processed by the autosplit program.
+
+1;
+__END__
+=head1 NAME
+
+Config::Abstract::Ini - Perl extension for handling ini style files
+
+=head1 SYNOPSIS
+
+ use Config::Abstract::Ini;
+ my $ini = new Config::Abstract::Ini('testdata.ini');
+
+=head1 DESCRIPTION
+
+ Have you ever wanted an easy to use interface to your own
+ config files, but ended up doing 'require mysettings.pl'
+ because you couldn't be bothered? Config::Abstract::Ini solves
+ that for you, giving you an object in exchange for the
+ name of your settings file.
+
+ For compatibility with other config file formats, Ini can
+ understand hierarchical ini files using double colons as
+ delimiters. Just make sure you don't create name clashes
+ by assigning both a value and a subentry to the same name
+ in the file. This is currently supported for one sublevel
+ only, which will have to be improved in future releases.
+
+=head1 EXAMPLES
+
+ We assume the content of the file 'testdata.ini' to be:
+ [myentry]
+ ;comment
+ thisssetting = that
+ thatsetting=this
+ ;end of ini
+
+
+ use Config::Abstract::Ini;
+ my $settingsfile = 'testdata.ini';
+ my $settings = new Config::Abstract::Ini($Settingsfile);
+
+ # Get all settings
+ my %allsettings = $settings->get_all_settings;
+
+ # Get a subsection (called an entry here, but it's
+ # whatever's beneath a [section] header)
+ my %entry = $settings->get_entry('myentry');
+
+ # Get a specific setting from an entry
+ my $value = $settings->get_entry_setting('myentry',
+ 'thissetting');
+
+ # Get a specific setting from an entry, giving a default
+ # to fall back on
+ my value = $settings->get_entry_setting('myentry',
+ 'missingsetting',
+ 'defaultvalue');
+ We can also make use of subentries, with a ini file like
+ this:
+
+ [book]
+ title=A book of chapters
+ author=Me, Myself and Irene
+
+ [book::chapter1]
+ title=The First Chapter, ever
+ file=book/chapter1.txt
+
+ [book::chapter2]
+ title=The Next Chapter, after the First Chapter, ever
+ file=book/chapter2.txt
+ # btw, you can use unix style comments, too...
+ ;end of ini
+
+ use Config::Abstract::Ini;
+ my $settingsfile = 'test2.ini';
+ my $ini = new Config::Abstract::Ini($Settingsfile);
+
+ my %book = $ini->get_entry('book');
+ my %chap1 = $ini->get_entry_setting('book','chapter1');
+ my $chap1title = $chapter1{'title'};
+
+ # Want to see the inifile?
+ # If you can live without comments and blank lines ;),
+ # try this:
+ print("My inifile looks like this:\n$ini\nCool, huh?\n");
+
+=head1 METHODS
+
+=item get_all_settings
+
+Returns a hash of all settings found in the processed file
+
+=item get_entry ENTRYNAME
+
+Returns a hash of the settings within the entry ENTRYNAME
+
+=item get_entry_setting ENTRYNAME,SETTINGNAME [,DEFAULTVALUE]
+
+Returns the value corresponding to ENTRYNAME,SETTINGSNAME. If the value isn't set it returns undef or, optionally, the DEFAULTVALUE
+
+=item set_all_settings SETTINGSHASH
+
+Fill settings with data from SETTINGSHASH
+
+=item set_entry ENTRYNAME,ENTRYHASH
+
+Fill the entry ENTRYNAME with data from ENTRYHASH
+
+=item set_entry_setting ENTRYNAME,SETTINGNAME,VALUE
+
+Set the setting ENTRYNAME,SETTINGSNAME to VALUE
+
+=head1 BUGS
+
+* Comments have to be on their own lines, end of line comments won't work properly
+* Serialisation does not take original line ordering into consideration, so comments may end up far from what they're supposed to document
+
+=head1 COPYRIGHT
+
+Copyright (c) 2003 Eddie Olsson. All rights reserved.
+
+ This library is free software; you can redistribute it
+ and/or modify it under the same terms as Perl itself.
+
+
+=head1 AUTHOR
+
+Eddie Olsson <ewt@avajadi.org>
+
+=head1 SEE ALSO
+
+L<perl>.
+
+=cut
--- /dev/null
+package Config::Abstract::Ini;
+
+use 5.006;
+use strict;
+use warnings;
+
+require Exporter;
+use Config::Abstract;
+
+use overload qw{""} => \&_to_string;
+
+our @ISA = qw(Config::Abstract Exporter);
+our %EXPORT_TAGS = ( 'all' => [ qw( ) ] );
+our @EXPORT_OK = ( @{ $EXPORT_TAGS{'all'} } );
+our @EXPORT = qw( );
+
+our $VERSION = '0.16';
+
+#
+# ------------------------------------------------------------------------------------------------------- structural methods -----
+#
+
+# All inherited from Config::Abstract
+
+#
+# --------------------------------------------------------------------------------------------------------- accessor methods -----
+#
+
+# All inherited from Config::Abstract
+
+#
+# ------------------------------------------------------------------------------------------------ (un)serialisation methods -----
+#
+
+##################################################
+#%name: _to_string
+#%syntax: _to_string
+#%summary: Recursively generates a string representation of the settings hash
+#%returns: a string in .ini format
+
+sub _to_string{
+ my($self) = @_;
+ return $self->_dumpobject('',$self->{_settings});
+}
+
+##################################################
+#%name: _dumpobject
+#%syntax: _dumpobject(<$objectcaption>,<$objectref>,[<@parentobjectcaptions>])
+#%summary: Recursively generates a string representation of the object referenced
+# by $objectref
+#%returns: a string representation of the object
+
+sub _dumpobject{
+ my($self,$name,$obj,@parents) = @_;
+ my @result = ();
+ if(ref($obj) eq 'HASH'){
+ unless($name eq ''){
+ push(@parents,"$name");
+ push(@result,'[' . join('::',@parents) . ']');
+ }
+ while(my($key,$val) = each(%{$obj})){
+ push(@result,$self->_dumpobject($key,$val,@parents));
+ }
+ }elsif(ref($obj) eq 'SCALAR'){
+ push(@result,"$name = ${$obj}");
+ }elsif(ref($obj) eq 'ARRAY'){
+ push(@parents,"$name");
+ push(@result,'[' . join('::',@parents) . ']');
+ for(my $i = 0;scalar(@{$obj});$i++){
+ push(@result,$self->_dumpobject($i,${$obj}[$i],@parents));
+ }
+ }else{
+# print("Why are we here? name: " . ( defined($name) ? $name : 'empty' ) . " obj:" . ( defined($obj) ? $obj : 'empty' ) . "\n");#DEBUG!!!
+ push(@result,"$name = " . (defined($obj) ? $obj : '') ) unless(!defined($name));
+ }
+ return(join("\n",@result));
+}
+
+
+##################################################
+#%name: _parse_settings_file
+#%syntax: _parse_settings_file(<@settings>)
+#%summary: Reads the projects to keep track of
+#%returns: a hash of $projectkey:$projectlabel
+
+sub _parse_settings_file{
+ my %result = ();
+ my ($entry,$subentry) = ('',undef);
+ chomp(@_);
+ foreach(@_){
+ # Get rid of starting/ending whitespace
+ s/^\s*(.*?)\s*$/$1/;
+
+ #Delete comments
+ ($_) = split(/[;#]/,$_);
+ #Skip if there's no data
+ next if((! defined($_)) || $_ eq '');
+ /^\s*(.*?)\s*=\s*(['"]|)(.*)\2\s*/ && do {
+ my($key,$val) = ($1,$3);
+ next if($key eq '' || $val eq '');
+ if(! defined($subentry) || $subentry =~ /^\s*$/){
+ ${$result{$entry}}{$key} = $val;
+ }else{
+ ${$result{$entry}}{$subentry}{$key} = $val;
+ }
+ next;
+ };
+ # Select a new entry if this is such a line
+ /\[(.*?)\]/ && do{
+
+ $_ = $1;
+ ($entry,$subentry) = split('::');
+ if(! defined($subentry) || $subentry =~ /^\s*$/){
+ $result{$entry} = {};
+ }elsif($result{$entry}){
+ $result{$entry}{$subentry} = {};
+ }
+ next;
+ };
+ }
+ return(\%result);
+}
+
+# We provide a DESTROY method so that the autoloader
+# doesn't bother trying to find it.
+sub DESTROY { }
+
+# Autoload methods go after =cut, and are processed by the autosplit program.
+
+1;
+__END__
+=head1 NAME
+
+Config::Abstract::Ini - Perl extension for handling ini style files
+
+=head1 SYNOPSIS
+
+ use Config::Abstract::Ini;
+ my $ini = new Config::Abstract::Ini('testdata.ini');
+
+=head1 DESCRIPTION
+
+ Have you ever wanted an easy to use interface to your own
+ config files, but ended up doing 'require mysettings.pl'
+ because you couldn't be bothered? Config::Abstract::Ini solves
+ that for you, giving you an object in exchange for the
+ name of your settings file.
+
+ For compatibility with other config file formats, Ini can
+ understand hierarchical ini files using double colons as
+ delimiters. Just make sure you don't create name clashes
+ by assigning both a value and a subentry to the same name
+ in the file. This is currently supported for one sublevel
+ only, which will have to be improved in future releases.
+
+=head1 EXAMPLES
+
+ We assume the content of the file 'testdata.ini' to be:
+ [myentry]
+ ;comment
+ thisssetting = that
+ thatsetting=this
+ ;end of ini
+
+
+ use Config::Abstract::Ini;
+ my $settingsfile = 'testdata.ini';
+ my $settings = new Config::Abstract::Ini($Settingsfile);
+
+ # Get all settings
+ my %allsettings = $settings->get_all_settings;
+
+ # Get a subsection (called an entry here, but it's
+ # whatever's beneath a [section] header)
+ my %entry = $settings->get_entry('myentry');
+
+ # Get a specific setting from an entry
+ my $value = $settings->get_entry_setting('myentry',
+ 'thissetting');
+
+ # Get a specific setting from an entry, giving a default
+ # to fall back on
+ my value = $settings->get_entry_setting('myentry',
+ 'missingsetting',
+ 'defaultvalue');
+ We can also make use of subentries, with a ini file like
+ this:
+
+ [book]
+ title=A book of chapters
+ author=Me, Myself and Irene
+
+ [book::chapter1]
+ title=The First Chapter, ever
+ file=book/chapter1.txt
+
+ [book::chapter2]
+ title=The Next Chapter, after the First Chapter, ever
+ file=book/chapter2.txt
+ # btw, you can use unix style comments, too...
+ ;end of ini
+
+ use Config::Abstract::Ini;
+ my $settingsfile = 'test2.ini';
+ my $ini = new Config::Abstract::Ini($Settingsfile);
+
+ my %book = $ini->get_entry('book');
+ my %chap1 = $ini->get_entry_setting('book','chapter1');
+ my $chap1title = $chapter1{'title'};
+
+ # Want to see the inifile?
+ # If you can live without comments and blank lines ;),
+ # try this:
+ print("My inifile looks like this:\n$ini\nCool, huh?\n");
+
+=head1 METHODS
+
+=item get_all_settings
+
+Returns a hash of all settings found in the processed file
+
+=item get_entry ENTRYNAME
+
+Returns a hash of the settings within the entry ENTRYNAME
+
+=item get_entry_setting ENTRYNAME,SETTINGNAME [,DEFAULTVALUE]
+
+Returns the value corresponding to ENTRYNAME,SETTINGSNAME. If the value isn't set it returns undef or, optionally, the DEFAULTVALUE
+
+=item set_all_settings SETTINGSHASH
+
+Fill settings with data from SETTINGSHASH
+
+=item set_entry ENTRYNAME,ENTRYHASH
+
+Fill the entry ENTRYNAME with data from ENTRYHASH
+
+=item set_entry_setting ENTRYNAME,SETTINGNAME,VALUE
+
+Set the setting ENTRYNAME,SETTINGSNAME to VALUE
+
+=head1 BUGS
+
+* Comments have to be on their own lines, end of line comments won't work properly
+* Serialisation does not take original line ordering into consideration, so comments may end up far from what they're supposed to document
+
+=head1 COPYRIGHT
+
+Copyright (c) 2003 Eddie Olsson. All rights reserved.
+
+ This library is free software; you can redistribute it
+ and/or modify it under the same terms as Perl itself.
+
+
+=head1 AUTHOR
+
+Eddie Olsson <ewt@avajadi.org>
+
+=head1 SEE ALSO
+
+L<perl>.
+
+=cut
--- /dev/null
+README
+Makefile.PL
+t/crc.t # some tests
+t/testfile # a file to check during tests
+CRC32.xs # the heart of the module
+CRC32.pm
+CRC32.pod # documentation
+MANIFEST
+crcgen.c # use this to rebuild your crc table
+typemap # my typemap for a correct mapping from C types to perl
--- /dev/null
+{
+ "abstract" : "unknown",
+ "author" : [
+ "unknown"
+ ],
+ "dynamic_config" : 0,
+ "generated_by" : "ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120630",
+ "license" : [
+ "unknown"
+ ],
+ "meta-spec" : {
+ "url" : "http://search.cpan.org/perldoc?CPAN::Meta::Spec",
+ "version" : "2"
+ },
+ "name" : "BN-CRC32",
+ "no_index" : {
+ "directory" : [
+ "t",
+ "inc"
+ ]
+ },
+ "prereqs" : {
+ "build" : {
+ "requires" : {
+ "ExtUtils::MakeMaker" : "0"
+ }
+ },
+ "configure" : {
+ "requires" : {
+ "ExtUtils::MakeMaker" : "0"
+ }
+ },
+ "runtime" : {
+ "requires" : {}
+ }
+ },
+ "release_status" : "stable",
+ "version" : "1.4"
+}
--- /dev/null
+---
+abstract: unknown
+author:
+ - unknown
+build_requires:
+ ExtUtils::MakeMaker: 0
+configure_requires:
+ ExtUtils::MakeMaker: 0
+dynamic_config: 0
+generated_by: 'ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120630'
+license: unknown
+meta-spec:
+ url: http://module-build.sourceforge.net/META-spec-v1.4.html
+ version: 1.4
+name: BN-CRC32
+no_index:
+ directory:
+ - t
+ - inc
+requires: {}
+version: 1.4
--- /dev/null
+# This Makefile is for the BN::CRC32 extension to perl.
+#
+# It was generated automatically by MakeMaker version
+# 6.6302 (Revision: 66302) from the contents of
+# Makefile.PL. Don't edit this file, edit Makefile.PL instead.
+#
+# ANY CHANGES MADE HERE WILL BE LOST!
+#
+# MakeMaker ARGV: ()
+#
+
+# MakeMaker Parameters:
+
+# BUILD_REQUIRES => { }
+# CONFIGURE_REQUIRES => { }
+# DISTNAME => q[BN-CRC32]
+# NAME => q[BN::CRC32]
+# OBJECT => q[CRC32.o]
+# PREREQ_PM => { }
+# VERSION => q[1.4]
+# dist => { COMPRESS=>q[gzip], SUFFIX=>q[gz] }
+
+# --- MakeMaker post_initialize section:
+
+
+# --- MakeMaker const_config section:
+
+# These definitions are from config.sh (via /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/Config.pm).
+# They may have been overridden via Makefile.PL or on the command line.
+AR = ar
+CC = cc
+CCCDLFLAGS = -fPIC
+CCDLFLAGS = -Wl,-E -Wl,-rpath,/usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/CORE
+DLEXT = so
+DLSRC = dl_dlopen.xs
+EXE_EXT =
+FULL_AR = /usr/bin/ar
+LD = cc
+LDDLFLAGS = -shared -L/usr/local/lib64 -fstack-protector
+LDFLAGS = -L/usr/local/lib64 -fstack-protector
+LIBC = /lib64/libc-2.15.so
+LIB_EXT = .a
+OBJ_EXT = .o
+OSNAME = linux
+OSVERS = 3.1.10-1.9-default
+RANLIB = :
+SITELIBEXP = /usr/lib/perl5/site_perl/5.16.0
+SITEARCHEXP = /usr/lib/perl5/site_perl/5.16.0/x86_64-linux-thread-multi
+SO = so
+VENDORARCHEXP = /usr/lib/perl5/vendor_perl/5.16.0/x86_64-linux-thread-multi
+VENDORLIBEXP = /usr/lib/perl5/vendor_perl/5.16.0
+
+
+# --- MakeMaker constants section:
+AR_STATIC_ARGS = cr
+DIRFILESEP = /
+DFSEP = $(DIRFILESEP)
+NAME = BN::CRC32
+NAME_SYM = BN_CRC32
+VERSION = 1.4
+VERSION_MACRO = VERSION
+VERSION_SYM = 1_4
+DEFINE_VERSION = -D$(VERSION_MACRO)=\"$(VERSION)\"
+XS_VERSION = 1.4
+XS_VERSION_MACRO = XS_VERSION
+XS_DEFINE_VERSION = -D$(XS_VERSION_MACRO)=\"$(XS_VERSION)\"
+INST_ARCHLIB = blib/arch
+INST_SCRIPT = blib/script
+INST_BIN = blib/bin
+INST_LIB = blib/lib
+INST_MAN1DIR = blib/man1
+INST_MAN3DIR = blib/man3
+MAN1EXT = 1
+MAN3EXT = 3pm
+INSTALLDIRS = site
+DESTDIR =
+PREFIX = $(SITEPREFIX)
+PERLPREFIX = /usr
+SITEPREFIX = /usr
+VENDORPREFIX = /usr
+INSTALLPRIVLIB = /usr/lib/perl5/5.16.0
+DESTINSTALLPRIVLIB = $(DESTDIR)$(INSTALLPRIVLIB)
+INSTALLSITELIB = /usr/lib/perl5/site_perl/5.16.0
+DESTINSTALLSITELIB = $(DESTDIR)$(INSTALLSITELIB)
+INSTALLVENDORLIB = /usr/lib/perl5/vendor_perl/5.16.0
+DESTINSTALLVENDORLIB = $(DESTDIR)$(INSTALLVENDORLIB)
+INSTALLARCHLIB = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLARCHLIB = $(DESTDIR)$(INSTALLARCHLIB)
+INSTALLSITEARCH = /usr/lib/perl5/site_perl/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLSITEARCH = $(DESTDIR)$(INSTALLSITEARCH)
+INSTALLVENDORARCH = /usr/lib/perl5/vendor_perl/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLVENDORARCH = $(DESTDIR)$(INSTALLVENDORARCH)
+INSTALLBIN = /usr/bin
+DESTINSTALLBIN = $(DESTDIR)$(INSTALLBIN)
+INSTALLSITEBIN = /usr/bin
+DESTINSTALLSITEBIN = $(DESTDIR)$(INSTALLSITEBIN)
+INSTALLVENDORBIN = /usr/bin
+DESTINSTALLVENDORBIN = $(DESTDIR)$(INSTALLVENDORBIN)
+INSTALLSCRIPT = /usr/bin
+DESTINSTALLSCRIPT = $(DESTDIR)$(INSTALLSCRIPT)
+INSTALLSITESCRIPT = /usr/bin
+DESTINSTALLSITESCRIPT = $(DESTDIR)$(INSTALLSITESCRIPT)
+INSTALLVENDORSCRIPT = /usr/bin
+DESTINSTALLVENDORSCRIPT = $(DESTDIR)$(INSTALLVENDORSCRIPT)
+INSTALLMAN1DIR = /usr/share/man/man1
+DESTINSTALLMAN1DIR = $(DESTDIR)$(INSTALLMAN1DIR)
+INSTALLSITEMAN1DIR = /usr/share/man/man1
+DESTINSTALLSITEMAN1DIR = $(DESTDIR)$(INSTALLSITEMAN1DIR)
+INSTALLVENDORMAN1DIR = /usr/share/man/man1
+DESTINSTALLVENDORMAN1DIR = $(DESTDIR)$(INSTALLVENDORMAN1DIR)
+INSTALLMAN3DIR = /usr/share/man/man3
+DESTINSTALLMAN3DIR = $(DESTDIR)$(INSTALLMAN3DIR)
+INSTALLSITEMAN3DIR = /usr/share/man/man3
+DESTINSTALLSITEMAN3DIR = $(DESTDIR)$(INSTALLSITEMAN3DIR)
+INSTALLVENDORMAN3DIR = /usr/share/man/man3
+DESTINSTALLVENDORMAN3DIR = $(DESTDIR)$(INSTALLVENDORMAN3DIR)
+PERL_LIB = /usr/lib/perl5/5.16.0
+PERL_ARCHLIB = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi
+LIBPERL_A = libperl.a
+FIRST_MAKEFILE = Makefile
+MAKEFILE_OLD = Makefile.old
+MAKE_APERL_FILE = Makefile.aperl
+PERLMAINCC = $(CC)
+PERL_INC = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/CORE
+PERL = /usr/bin/perl
+FULLPERL = /usr/bin/perl
+ABSPERL = $(PERL)
+PERLRUN = $(PERL)
+FULLPERLRUN = $(FULLPERL)
+ABSPERLRUN = $(ABSPERL)
+PERLRUNINST = $(PERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+FULLPERLRUNINST = $(FULLPERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+ABSPERLRUNINST = $(ABSPERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+PERL_CORE = 0
+PERM_DIR = 755
+PERM_RW = 644
+PERM_RWX = 755
+
+MAKEMAKER = /usr/lib/perl5/5.16.0/ExtUtils/MakeMaker.pm
+MM_VERSION = 6.6302
+MM_REVISION = 66302
+
+# FULLEXT = Pathname for extension directory (eg Foo/Bar/Oracle).
+# BASEEXT = Basename part of FULLEXT. May be just equal FULLEXT. (eg Oracle)
+# PARENT_NAME = NAME without BASEEXT and no trailing :: (eg Foo::Bar)
+# DLBASE = Basename part of dynamic library. May be just equal BASEEXT.
+MAKE = make
+FULLEXT = BN/CRC32
+BASEEXT = CRC32
+PARENT_NAME = BN
+DLBASE = $(BASEEXT)
+VERSION_FROM =
+OBJECT = CRC32$(OBJ_EXT)
+LDFROM = $(OBJECT)
+LINKTYPE = dynamic
+BOOTDEP =
+
+# Handy lists of source code files:
+XS_FILES = CRC32.xs \
+ CRC32_mod.xs
+C_FILES = CRC32.c \
+ CRC32_mod.c \
+ crcgen.c
+O_FILES = CRC32.o \
+ CRC32_mod.o \
+ crcgen.o
+H_FILES =
+MAN1PODS =
+MAN3PODS = CRC32.pod
+
+# Where is the Config information that we are using/depend on
+CONFIGDEP = $(PERL_ARCHLIB)$(DFSEP)Config.pm $(PERL_INC)$(DFSEP)config.h
+
+# Where to build things
+INST_LIBDIR = $(INST_LIB)/BN
+INST_ARCHLIBDIR = $(INST_ARCHLIB)/BN
+
+INST_AUTODIR = $(INST_LIB)/auto/$(FULLEXT)
+INST_ARCHAUTODIR = $(INST_ARCHLIB)/auto/$(FULLEXT)
+
+INST_STATIC = $(INST_ARCHAUTODIR)/$(BASEEXT)$(LIB_EXT)
+INST_DYNAMIC = $(INST_ARCHAUTODIR)/$(DLBASE).$(DLEXT)
+INST_BOOT = $(INST_ARCHAUTODIR)/$(BASEEXT).bs
+
+# Extra linker info
+EXPORT_LIST =
+PERL_ARCHIVE =
+PERL_ARCHIVE_AFTER =
+
+
+TO_INST_PM = CRC32.pm \
+ CRC32.pod \
+ CRC32_test.pm
+
+PM_TO_BLIB = CRC32.pod \
+ $(INST_LIB)/BN/CRC32.pod \
+ CRC32_test.pm \
+ $(INST_LIB)/BN/CRC32_test.pm \
+ CRC32.pm \
+ $(INST_LIB)/BN/CRC32.pm
+
+
+# --- MakeMaker platform_constants section:
+MM_Unix_VERSION = 6.6302
+PERL_MALLOC_DEF = -DPERL_EXTMALLOC_DEF -Dmalloc=Perl_malloc -Dfree=Perl_mfree -Drealloc=Perl_realloc -Dcalloc=Perl_calloc
+
+
+# --- MakeMaker tool_autosplit section:
+# Usage: $(AUTOSPLITFILE) FileToSplit AutoDirToSplitInto
+AUTOSPLITFILE = $(ABSPERLRUN) -e 'use AutoSplit; autosplit($$$$ARGV[0], $$$$ARGV[1], 0, 1, 1)' --
+
+
+
+# --- MakeMaker tool_xsubpp section:
+
+XSUBPPDIR = /usr/lib/perl5/5.16.0/ExtUtils
+XSUBPP = $(XSUBPPDIR)$(DFSEP)xsubpp
+XSUBPPRUN = $(PERLRUN) $(XSUBPP)
+XSPROTOARG =
+XSUBPPDEPS = /usr/lib/perl5/5.16.0/ExtUtils/typemap typemap $(XSUBPP)
+XSUBPPARGS = -typemap /usr/lib/perl5/5.16.0/ExtUtils/typemap -typemap typemap
+XSUBPP_EXTRA_ARGS =
+
+
+# --- MakeMaker tools_other section:
+SHELL = /bin/sh
+CHMOD = chmod
+CP = cp
+MV = mv
+NOOP = $(TRUE)
+NOECHO = @
+RM_F = rm -f
+RM_RF = rm -rf
+TEST_F = test -f
+TOUCH = touch
+UMASK_NULL = umask 0
+DEV_NULL = > /dev/null 2>&1
+MKPATH = $(ABSPERLRUN) -MExtUtils::Command -e 'mkpath' --
+EQUALIZE_TIMESTAMP = $(ABSPERLRUN) -MExtUtils::Command -e 'eqtime' --
+FALSE = false
+TRUE = true
+ECHO = echo
+ECHO_N = echo -n
+UNINST = 0
+VERBINST = 0
+MOD_INSTALL = $(ABSPERLRUN) -MExtUtils::Install -e 'install([ from_to => {@ARGV}, verbose => '\''$(VERBINST)'\'', uninstall_shadows => '\''$(UNINST)'\'', dir_mode => '\''$(PERM_DIR)'\'' ]);' --
+DOC_INSTALL = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'perllocal_install' --
+UNINSTALL = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'uninstall' --
+WARN_IF_OLD_PACKLIST = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'warn_if_old_packlist' --
+MACROSTART =
+MACROEND =
+USEMAKEFILE = -f
+FIXIN = $(ABSPERLRUN) -MExtUtils::MY -e 'MY->fixin(shift)' --
+
+
+# --- MakeMaker makemakerdflt section:
+makemakerdflt : all
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dist section:
+TAR = tar
+TARFLAGS = cvf
+ZIP = zip
+ZIPFLAGS = -r
+COMPRESS = gzip
+SUFFIX = gz
+SHAR = shar
+PREOP = $(NOECHO) $(NOOP)
+POSTOP = $(NOECHO) $(NOOP)
+TO_UNIX = $(NOECHO) $(NOOP)
+CI = ci -u
+RCS_LABEL = rcs -Nv$(VERSION_SYM): -q
+DIST_CP = best
+DIST_DEFAULT = tardist
+DISTNAME = BN-CRC32
+DISTVNAME = BN-CRC32-1.4
+
+
+# --- MakeMaker macro section:
+
+
+# --- MakeMaker depend section:
+
+
+# --- MakeMaker cflags section:
+
+CCFLAGS = -D_REENTRANT -D_GNU_SOURCE -DPERL_USE_SAFE_PUTENV -fno-strict-aliasing -pipe -fstack-protector -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64
+OPTIMIZE = -fmessage-length=0 -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables -g -Wall -pipe
+PERLTYPE =
+MPOLLUTE =
+
+
+# --- MakeMaker const_loadlibs section:
+
+# BN::CRC32 might depend on some other libraries:
+# See ExtUtils::Liblist for details
+#
+
+
+# --- MakeMaker const_cccmd section:
+CCCMD = $(CC) -c $(PASTHRU_INC) $(INC) \
+ $(CCFLAGS) $(OPTIMIZE) \
+ $(PERLTYPE) $(MPOLLUTE) $(DEFINE_VERSION) \
+ $(XS_DEFINE_VERSION)
+
+# --- MakeMaker post_constants section:
+
+
+# --- MakeMaker pasthru section:
+
+PASTHRU = LIBPERL_A="$(LIBPERL_A)"\
+ LINKTYPE="$(LINKTYPE)"\
+ OPTIMIZE="$(OPTIMIZE)"\
+ PREFIX="$(PREFIX)"
+
+
+# --- MakeMaker special_targets section:
+.SUFFIXES : .xs .c .C .cpp .i .s .cxx .cc $(OBJ_EXT)
+
+.PHONY: all config static dynamic test linkext manifest blibdirs clean realclean disttest distdir
+
+
+
+# --- MakeMaker c_o section:
+
+.c.i:
+ cc -E -c $(PASTHRU_INC) $(INC) \
+ $(CCFLAGS) $(OPTIMIZE) \
+ $(PERLTYPE) $(MPOLLUTE) $(DEFINE_VERSION) \
+ $(XS_DEFINE_VERSION) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c > $*.i
+
+.c.s:
+ $(CCCMD) -S $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+.c$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+.cpp$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cpp
+
+.cxx$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cxx
+
+.cc$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cc
+
+.C$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.C
+
+
+# --- MakeMaker xs_c section:
+
+.xs.c:
+ $(XSUBPPRUN) $(XSPROTOARG) $(XSUBPPARGS) $(XSUBPP_EXTRA_ARGS) $*.xs > $*.xsc && $(MV) $*.xsc $*.c
+
+
+# --- MakeMaker xs_o section:
+
+.xs$(OBJ_EXT):
+ $(XSUBPPRUN) $(XSPROTOARG) $(XSUBPPARGS) $*.xs > $*.xsc && $(MV) $*.xsc $*.c
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+
+# --- MakeMaker top_targets section:
+all :: pure_all manifypods
+ $(NOECHO) $(NOOP)
+
+
+pure_all :: config pm_to_blib subdirs linkext
+ $(NOECHO) $(NOOP)
+
+subdirs :: $(MYEXTLIB)
+ $(NOECHO) $(NOOP)
+
+config :: $(FIRST_MAKEFILE) blibdirs
+ $(NOECHO) $(NOOP)
+
+help :
+ perldoc ExtUtils::MakeMaker
+
+
+# --- MakeMaker blibdirs section:
+blibdirs : $(INST_LIBDIR)$(DFSEP).exists $(INST_ARCHLIB)$(DFSEP).exists $(INST_AUTODIR)$(DFSEP).exists $(INST_ARCHAUTODIR)$(DFSEP).exists $(INST_BIN)$(DFSEP).exists $(INST_SCRIPT)$(DFSEP).exists $(INST_MAN1DIR)$(DFSEP).exists $(INST_MAN3DIR)$(DFSEP).exists
+ $(NOECHO) $(NOOP)
+
+# Backwards compat with 6.18 through 6.25
+blibdirs.ts : blibdirs
+ $(NOECHO) $(NOOP)
+
+$(INST_LIBDIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_LIBDIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_LIBDIR)
+ $(NOECHO) $(TOUCH) $(INST_LIBDIR)$(DFSEP).exists
+
+$(INST_ARCHLIB)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_ARCHLIB)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_ARCHLIB)
+ $(NOECHO) $(TOUCH) $(INST_ARCHLIB)$(DFSEP).exists
+
+$(INST_AUTODIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_AUTODIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_AUTODIR)
+ $(NOECHO) $(TOUCH) $(INST_AUTODIR)$(DFSEP).exists
+
+$(INST_ARCHAUTODIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_ARCHAUTODIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_ARCHAUTODIR)
+ $(NOECHO) $(TOUCH) $(INST_ARCHAUTODIR)$(DFSEP).exists
+
+$(INST_BIN)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_BIN)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_BIN)
+ $(NOECHO) $(TOUCH) $(INST_BIN)$(DFSEP).exists
+
+$(INST_SCRIPT)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_SCRIPT)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_SCRIPT)
+ $(NOECHO) $(TOUCH) $(INST_SCRIPT)$(DFSEP).exists
+
+$(INST_MAN1DIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_MAN1DIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_MAN1DIR)
+ $(NOECHO) $(TOUCH) $(INST_MAN1DIR)$(DFSEP).exists
+
+$(INST_MAN3DIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_MAN3DIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_MAN3DIR)
+ $(NOECHO) $(TOUCH) $(INST_MAN3DIR)$(DFSEP).exists
+
+
+
+# --- MakeMaker linkext section:
+
+linkext :: $(LINKTYPE)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dlsyms section:
+
+
+# --- MakeMaker dynamic section:
+
+dynamic :: $(FIRST_MAKEFILE) $(INST_DYNAMIC) $(INST_BOOT)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dynamic_bs section:
+BOOTSTRAP = $(BASEEXT).bs
+
+# As Mkbootstrap might not write a file (if none is required)
+# we use touch to prevent make continually trying to remake it.
+# The DynaLoader only reads a non-empty file.
+$(BOOTSTRAP) : $(FIRST_MAKEFILE) $(BOOTDEP) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(NOECHO) $(ECHO) "Running Mkbootstrap for $(NAME) ($(BSLOADLIBS))"
+ $(NOECHO) $(PERLRUN) \
+ "-MExtUtils::Mkbootstrap" \
+ -e "Mkbootstrap('$(BASEEXT)','$(BSLOADLIBS)');"
+ $(NOECHO) $(TOUCH) $@
+ $(CHMOD) $(PERM_RW) $@
+
+$(INST_BOOT) : $(BOOTSTRAP) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(NOECHO) $(RM_RF) $@
+ - $(CP) $(BOOTSTRAP) $@
+ $(CHMOD) $(PERM_RW) $@
+
+
+# --- MakeMaker dynamic_lib section:
+
+# This section creates the dynamically loadable $(INST_DYNAMIC)
+# from $(OBJECT) and possibly $(MYEXTLIB).
+ARMAYBE = :
+OTHERLDFLAGS =
+INST_DYNAMIC_DEP =
+INST_DYNAMIC_FIX =
+
+$(INST_DYNAMIC): $(OBJECT) $(MYEXTLIB) $(BOOTSTRAP) $(INST_ARCHAUTODIR)$(DFSEP).exists $(EXPORT_LIST) $(PERL_ARCHIVE) $(PERL_ARCHIVE_AFTER) $(INST_DYNAMIC_DEP)
+ $(RM_F) $@
+ $(LD) $(LDDLFLAGS) $(LDFROM) $(OTHERLDFLAGS) -o $@ $(MYEXTLIB) \
+ $(PERL_ARCHIVE) $(LDLOADLIBS) $(PERL_ARCHIVE_AFTER) $(EXPORT_LIST) \
+ $(INST_DYNAMIC_FIX)
+ $(CHMOD) $(PERM_RWX) $@
+
+
+# --- MakeMaker static section:
+
+## $(INST_PM) has been moved to the all: target.
+## It remains here for awhile to allow for old usage: "make static"
+static :: $(FIRST_MAKEFILE) $(INST_STATIC)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker static_lib section:
+
+$(INST_STATIC) : $(OBJECT) $(MYEXTLIB) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(RM_RF) $@
+ $(FULL_AR) $(AR_STATIC_ARGS) $@ $(OBJECT) && $(RANLIB) $@
+ $(CHMOD) $(PERM_RWX) $@
+ $(NOECHO) $(ECHO) "$(EXTRALIBS)" > $(INST_ARCHAUTODIR)/extralibs.ld
+
+
+# --- MakeMaker manifypods section:
+
+POD2MAN_EXE = $(PERLRUN) "-MExtUtils::Command::MM" -e pod2man "--"
+POD2MAN = $(POD2MAN_EXE)
+
+
+manifypods : pure_all \
+ CRC32.pod
+ $(NOECHO) $(POD2MAN) --section=3 --perm_rw=$(PERM_RW) \
+ CRC32.pod $(INST_MAN3DIR)/BN::CRC32.$(MAN3EXT)
+
+
+
+
+# --- MakeMaker processPL section:
+
+
+# --- MakeMaker installbin section:
+
+
+# --- MakeMaker subdirs section:
+
+# none
+
+# --- MakeMaker clean_subdirs section:
+clean_subdirs :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker clean section:
+
+# Delete temporary files but do not touch installed files. We don't delete
+# the Makefile here so a later make realclean still has a makefile to use.
+
+clean :: clean_subdirs
+ - $(RM_F) \
+ core.[0-9] $(BASEEXT).bso \
+ pm_to_blib.ts core.[0-9][0-9][0-9][0-9] \
+ MYMETA.yml perl$(EXE_EXT) \
+ tmon.out *$(OBJ_EXT) \
+ pm_to_blib blibdirs.ts \
+ *perl.core core.*perl.*.? \
+ $(BASEEXT).def core.[0-9][0-9][0-9] \
+ mon.out lib$(BASEEXT).def \
+ perlmain.c perl.exe \
+ so_locations $(BASEEXT).exp \
+ CRC32.c CRC32_mod.c \
+ *$(LIB_EXT) core \
+ $(INST_ARCHAUTODIR)/extralibs.all core.[0-9][0-9] \
+ MYMETA.json $(BOOTSTRAP) \
+ $(BASEEXT).x $(INST_ARCHAUTODIR)/extralibs.ld \
+ core.[0-9][0-9][0-9][0-9][0-9] $(MAKE_APERL_FILE) \
+ perl
+ - $(RM_RF) \
+ blib
+ - $(MV) $(FIRST_MAKEFILE) $(MAKEFILE_OLD) $(DEV_NULL)
+
+
+# --- MakeMaker realclean_subdirs section:
+realclean_subdirs :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker realclean section:
+# Delete temporary files (via clean) and also delete dist files
+realclean purge :: clean realclean_subdirs
+ - $(RM_F) \
+ $(OBJECT) $(MAKEFILE_OLD) \
+ $(FIRST_MAKEFILE)
+ - $(RM_RF) \
+ $(DISTVNAME)
+
+
+# --- MakeMaker metafile section:
+metafile : create_distdir
+ $(NOECHO) $(ECHO) Generating META.yml
+ $(NOECHO) $(ECHO) '---' > META_new.yml
+ $(NOECHO) $(ECHO) 'abstract: unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'author:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'build_requires:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' ExtUtils::MakeMaker: 0' >> META_new.yml
+ $(NOECHO) $(ECHO) 'configure_requires:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' ExtUtils::MakeMaker: 0' >> META_new.yml
+ $(NOECHO) $(ECHO) 'dynamic_config: 1' >> META_new.yml
+ $(NOECHO) $(ECHO) 'generated_by: '\''ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120630'\''' >> META_new.yml
+ $(NOECHO) $(ECHO) 'license: unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'meta-spec:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' url: http://module-build.sourceforge.net/META-spec-v1.4.html' >> META_new.yml
+ $(NOECHO) $(ECHO) ' version: 1.4' >> META_new.yml
+ $(NOECHO) $(ECHO) 'name: BN-CRC32' >> META_new.yml
+ $(NOECHO) $(ECHO) 'no_index:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' directory:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - t' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - inc' >> META_new.yml
+ $(NOECHO) $(ECHO) 'requires: {}' >> META_new.yml
+ $(NOECHO) $(ECHO) 'version: 1.4' >> META_new.yml
+ -$(NOECHO) $(MV) META_new.yml $(DISTVNAME)/META.yml
+ $(NOECHO) $(ECHO) Generating META.json
+ $(NOECHO) $(ECHO) '{' > META_new.json
+ $(NOECHO) $(ECHO) ' "abstract" : "unknown",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "author" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "unknown"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ],' >> META_new.json
+ $(NOECHO) $(ECHO) ' "dynamic_config" : 1,' >> META_new.json
+ $(NOECHO) $(ECHO) ' "generated_by" : "ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120630",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "license" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "unknown"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ],' >> META_new.json
+ $(NOECHO) $(ECHO) ' "meta-spec" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "url" : "http://search.cpan.org/perldoc?CPAN::Meta::Spec",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "version" : "2"' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "name" : "BN-CRC32",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "no_index" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "directory" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "t",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "inc"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ]' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "prereqs" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "build" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "ExtUtils::MakeMaker" : "0"' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "configure" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "ExtUtils::MakeMaker" : "0"' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "runtime" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {}' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "release_status" : "stable",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "version" : "1.4"' >> META_new.json
+ $(NOECHO) $(ECHO) '}' >> META_new.json
+ -$(NOECHO) $(MV) META_new.json $(DISTVNAME)/META.json
+
+
+# --- MakeMaker signature section:
+signature :
+ cpansign -s
+
+
+# --- MakeMaker dist_basics section:
+distclean :: realclean distcheck
+ $(NOECHO) $(NOOP)
+
+distcheck :
+ $(PERLRUN) "-MExtUtils::Manifest=fullcheck" -e fullcheck
+
+skipcheck :
+ $(PERLRUN) "-MExtUtils::Manifest=skipcheck" -e skipcheck
+
+manifest :
+ $(PERLRUN) "-MExtUtils::Manifest=mkmanifest" -e mkmanifest
+
+veryclean : realclean
+ $(RM_F) *~ */*~ *.orig */*.orig *.bak */*.bak *.old */*.old
+
+
+
+# --- MakeMaker dist_core section:
+
+dist : $(DIST_DEFAULT) $(FIRST_MAKEFILE)
+ $(NOECHO) $(ABSPERLRUN) -l -e 'print '\''Warning: Makefile possibly out of date with $(VERSION_FROM)'\''' \
+ -e ' if -e '\''$(VERSION_FROM)'\'' and -M '\''$(VERSION_FROM)'\'' < -M '\''$(FIRST_MAKEFILE)'\'';' --
+
+tardist : $(DISTVNAME).tar$(SUFFIX)
+ $(NOECHO) $(NOOP)
+
+uutardist : $(DISTVNAME).tar$(SUFFIX)
+ uuencode $(DISTVNAME).tar$(SUFFIX) $(DISTVNAME).tar$(SUFFIX) > $(DISTVNAME).tar$(SUFFIX)_uu
+
+$(DISTVNAME).tar$(SUFFIX) : distdir
+ $(PREOP)
+ $(TO_UNIX)
+ $(TAR) $(TARFLAGS) $(DISTVNAME).tar $(DISTVNAME)
+ $(RM_RF) $(DISTVNAME)
+ $(COMPRESS) $(DISTVNAME).tar
+ $(POSTOP)
+
+zipdist : $(DISTVNAME).zip
+ $(NOECHO) $(NOOP)
+
+$(DISTVNAME).zip : distdir
+ $(PREOP)
+ $(ZIP) $(ZIPFLAGS) $(DISTVNAME).zip $(DISTVNAME)
+ $(RM_RF) $(DISTVNAME)
+ $(POSTOP)
+
+shdist : distdir
+ $(PREOP)
+ $(SHAR) $(DISTVNAME) > $(DISTVNAME).shar
+ $(RM_RF) $(DISTVNAME)
+ $(POSTOP)
+
+
+# --- MakeMaker distdir section:
+create_distdir :
+ $(RM_RF) $(DISTVNAME)
+ $(PERLRUN) "-MExtUtils::Manifest=manicopy,maniread" \
+ -e "manicopy(maniread(),'$(DISTVNAME)', '$(DIST_CP)');"
+
+distdir : create_distdir distmeta
+ $(NOECHO) $(NOOP)
+
+
+
+# --- MakeMaker dist_test section:
+disttest : distdir
+ cd $(DISTVNAME) && $(ABSPERLRUN) Makefile.PL
+ cd $(DISTVNAME) && $(MAKE) $(PASTHRU)
+ cd $(DISTVNAME) && $(MAKE) test $(PASTHRU)
+
+
+
+# --- MakeMaker dist_ci section:
+
+ci :
+ $(PERLRUN) "-MExtUtils::Manifest=maniread" \
+ -e "@all = keys %{ maniread() };" \
+ -e "print(qq{Executing $(CI) @all\n}); system(qq{$(CI) @all});" \
+ -e "print(qq{Executing $(RCS_LABEL) ...\n}); system(qq{$(RCS_LABEL) @all});"
+
+
+# --- MakeMaker distmeta section:
+distmeta : create_distdir metafile
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'exit unless -e q{META.yml};' \
+ -e 'eval { maniadd({q{META.yml} => q{Module YAML meta-data (added by MakeMaker)}}) }' \
+ -e ' or print "Could not add META.yml to MANIFEST: $$$${'\''@'\''}\n"' --
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'exit unless -f q{META.json};' \
+ -e 'eval { maniadd({q{META.json} => q{Module JSON meta-data (added by MakeMaker)}}) }' \
+ -e ' or print "Could not add META.json to MANIFEST: $$$${'\''@'\''}\n"' --
+
+
+
+# --- MakeMaker distsignature section:
+distsignature : create_distdir
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'eval { maniadd({q{SIGNATURE} => q{Public-key signature (added by MakeMaker)}}) } ' \
+ -e ' or print "Could not add SIGNATURE to MANIFEST: $$$${'\''@'\''}\n"' --
+ $(NOECHO) cd $(DISTVNAME) && $(TOUCH) SIGNATURE
+ cd $(DISTVNAME) && cpansign -s
+
+
+
+# --- MakeMaker install section:
+
+install :: pure_install doc_install
+ $(NOECHO) $(NOOP)
+
+install_perl :: pure_perl_install doc_perl_install
+ $(NOECHO) $(NOOP)
+
+install_site :: pure_site_install doc_site_install
+ $(NOECHO) $(NOOP)
+
+install_vendor :: pure_vendor_install doc_vendor_install
+ $(NOECHO) $(NOOP)
+
+pure_install :: pure_$(INSTALLDIRS)_install
+ $(NOECHO) $(NOOP)
+
+doc_install :: doc_$(INSTALLDIRS)_install
+ $(NOECHO) $(NOOP)
+
+pure__install : pure_site_install
+ $(NOECHO) $(ECHO) INSTALLDIRS not defined, defaulting to INSTALLDIRS=site
+
+doc__install : doc_site_install
+ $(NOECHO) $(ECHO) INSTALLDIRS not defined, defaulting to INSTALLDIRS=site
+
+pure_perl_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(PERL_ARCHLIB)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLARCHLIB)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLPRIVLIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLARCHLIB) \
+ $(INST_BIN) $(DESTINSTALLBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLSCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLMAN3DIR)
+ $(NOECHO) $(WARN_IF_OLD_PACKLIST) \
+ $(SITEARCHEXP)/auto/$(FULLEXT)
+
+
+pure_site_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(SITEARCHEXP)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLSITEARCH)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLSITELIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLSITEARCH) \
+ $(INST_BIN) $(DESTINSTALLSITEBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLSITESCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLSITEMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLSITEMAN3DIR)
+ $(NOECHO) $(WARN_IF_OLD_PACKLIST) \
+ $(PERL_ARCHLIB)/auto/$(FULLEXT)
+
+pure_vendor_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(VENDORARCHEXP)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLVENDORARCH)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLVENDORLIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLVENDORARCH) \
+ $(INST_BIN) $(DESTINSTALLVENDORBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLVENDORSCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLVENDORMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLVENDORMAN3DIR)
+
+doc_perl_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLPRIVLIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+doc_site_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLSITELIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+doc_vendor_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLVENDORLIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+
+uninstall :: uninstall_from_$(INSTALLDIRS)dirs
+ $(NOECHO) $(NOOP)
+
+uninstall_from_perldirs ::
+ $(NOECHO) $(UNINSTALL) $(PERL_ARCHLIB)/auto/$(FULLEXT)/.packlist
+
+uninstall_from_sitedirs ::
+ $(NOECHO) $(UNINSTALL) $(SITEARCHEXP)/auto/$(FULLEXT)/.packlist
+
+uninstall_from_vendordirs ::
+ $(NOECHO) $(UNINSTALL) $(VENDORARCHEXP)/auto/$(FULLEXT)/.packlist
+
+
+# --- MakeMaker force section:
+# Phony target to force checking subdirectories.
+FORCE :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker perldepend section:
+
+PERL_HDRS = \
+ $(PERL_INC)/EXTERN.h \
+ $(PERL_INC)/INTERN.h \
+ $(PERL_INC)/XSUB.h \
+ $(PERL_INC)/av.h \
+ $(PERL_INC)/config.h \
+ $(PERL_INC)/cop.h \
+ $(PERL_INC)/cv.h \
+ $(PERL_INC)/dosish.h \
+ $(PERL_INC)/embed.h \
+ $(PERL_INC)/embedvar.h \
+ $(PERL_INC)/fakethr.h \
+ $(PERL_INC)/form.h \
+ $(PERL_INC)/gv.h \
+ $(PERL_INC)/handy.h \
+ $(PERL_INC)/hv.h \
+ $(PERL_INC)/intrpvar.h \
+ $(PERL_INC)/iperlsys.h \
+ $(PERL_INC)/keywords.h \
+ $(PERL_INC)/mg.h \
+ $(PERL_INC)/nostdio.h \
+ $(PERL_INC)/op.h \
+ $(PERL_INC)/opcode.h \
+ $(PERL_INC)/patchlevel.h \
+ $(PERL_INC)/perl.h \
+ $(PERL_INC)/perlio.h \
+ $(PERL_INC)/perlsdio.h \
+ $(PERL_INC)/perlsfio.h \
+ $(PERL_INC)/perlvars.h \
+ $(PERL_INC)/perly.h \
+ $(PERL_INC)/pp.h \
+ $(PERL_INC)/pp_proto.h \
+ $(PERL_INC)/proto.h \
+ $(PERL_INC)/regcomp.h \
+ $(PERL_INC)/regexp.h \
+ $(PERL_INC)/regnodes.h \
+ $(PERL_INC)/scope.h \
+ $(PERL_INC)/sv.h \
+ $(PERL_INC)/thread.h \
+ $(PERL_INC)/unixish.h \
+ $(PERL_INC)/util.h
+
+$(OBJECT) : $(PERL_HDRS)
+
+CRC32.c CRC32_mod.c : $(XSUBPPDEPS)
+
+
+# --- MakeMaker makefile section:
+
+$(OBJECT) : $(FIRST_MAKEFILE)
+
+# We take a very conservative approach here, but it's worth it.
+# We move Makefile to Makefile.old here to avoid gnu make looping.
+$(FIRST_MAKEFILE) : Makefile.PL $(CONFIGDEP)
+ $(NOECHO) $(ECHO) "Makefile out-of-date with respect to $?"
+ $(NOECHO) $(ECHO) "Cleaning current config before rebuilding Makefile..."
+ -$(NOECHO) $(RM_F) $(MAKEFILE_OLD)
+ -$(NOECHO) $(MV) $(FIRST_MAKEFILE) $(MAKEFILE_OLD)
+ - $(MAKE) $(USEMAKEFILE) $(MAKEFILE_OLD) clean $(DEV_NULL)
+ $(PERLRUN) Makefile.PL
+ $(NOECHO) $(ECHO) "==> Your Makefile has been rebuilt. <=="
+ $(NOECHO) $(ECHO) "==> Please rerun the $(MAKE) command. <=="
+ $(FALSE)
+
+
+
+# --- MakeMaker staticmake section:
+
+# --- MakeMaker makeaperl section ---
+MAP_TARGET = perl
+FULLPERL = /usr/bin/perl
+
+$(MAP_TARGET) :: static $(MAKE_APERL_FILE)
+ $(MAKE) $(USEMAKEFILE) $(MAKE_APERL_FILE) $@
+
+$(MAKE_APERL_FILE) : $(FIRST_MAKEFILE) pm_to_blib
+ $(NOECHO) $(ECHO) Writing \"$(MAKE_APERL_FILE)\" for this $(MAP_TARGET)
+ $(NOECHO) $(PERLRUNINST) \
+ Makefile.PL DIR= \
+ MAKEFILE=$(MAKE_APERL_FILE) LINKTYPE=static \
+ MAKEAPERL=1 NORECURS=1 CCCDLFLAGS=
+
+
+# --- MakeMaker test section:
+
+TEST_VERBOSE=0
+TEST_TYPE=test_$(LINKTYPE)
+TEST_FILE = test.pl
+TEST_FILES = t/*.t
+TESTDB_SW = -d
+
+testdb :: testdb_$(LINKTYPE)
+
+test :: $(TEST_TYPE) subdirs-test
+
+subdirs-test ::
+ $(NOECHO) $(NOOP)
+
+
+test_dynamic :: pure_all
+ PERL_DL_NONLAZY=1 $(FULLPERLRUN) "-MExtUtils::Command::MM" "-e" "test_harness($(TEST_VERBOSE), '$(INST_LIB)', '$(INST_ARCHLIB)')" $(TEST_FILES)
+
+testdb_dynamic :: pure_all
+ PERL_DL_NONLAZY=1 $(FULLPERLRUN) $(TESTDB_SW) "-I$(INST_LIB)" "-I$(INST_ARCHLIB)" $(TEST_FILE)
+
+test_ : test_dynamic
+
+test_static :: pure_all $(MAP_TARGET)
+ PERL_DL_NONLAZY=1 ./$(MAP_TARGET) "-MExtUtils::Command::MM" "-e" "test_harness($(TEST_VERBOSE), '$(INST_LIB)', '$(INST_ARCHLIB)')" $(TEST_FILES)
+
+testdb_static :: pure_all $(MAP_TARGET)
+ PERL_DL_NONLAZY=1 ./$(MAP_TARGET) $(TESTDB_SW) "-I$(INST_LIB)" "-I$(INST_ARCHLIB)" $(TEST_FILE)
+
+
+
+# --- MakeMaker ppd section:
+# Creates a PPD (Perl Package Description) for a binary distribution.
+ppd :
+ $(NOECHO) $(ECHO) '<SOFTPKG NAME="$(DISTNAME)" VERSION="$(VERSION)">' > $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <ABSTRACT></ABSTRACT>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <AUTHOR></AUTHOR>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <IMPLEMENTATION>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <ARCHITECTURE NAME="x86_64-linux-thread-multi-5.16" />' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <CODEBASE HREF="" />' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' </IMPLEMENTATION>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) '</SOFTPKG>' >> $(DISTNAME).ppd
+
+
+# --- MakeMaker pm_to_blib section:
+
+pm_to_blib : $(FIRST_MAKEFILE) $(TO_INST_PM)
+ $(NOECHO) $(ABSPERLRUN) -MExtUtils::Install -e 'pm_to_blib({@ARGV}, '\''$(INST_LIB)/auto'\'', q[$(PM_FILTER)], '\''$(PERM_DIR)'\'')' -- \
+ CRC32.pod $(INST_LIB)/BN/CRC32.pod \
+ CRC32_test.pm $(INST_LIB)/BN/CRC32_test.pm \
+ CRC32.pm $(INST_LIB)/BN/CRC32.pm
+ $(NOECHO) $(TOUCH) pm_to_blib
+
+
+# --- MakeMaker selfdocument section:
+
+
+# --- MakeMaker postamble section:
+
+
+# End.
--- /dev/null
+#! /usr/local/bin/perl
+
+use ExtUtils::MakeMaker;
+# See lib/ExtUtils/MakeMaker.pm for details of how to influence
+# the contents of the Makefile being created.
+WriteMakefile(
+ 'NAME' => 'BN::CRC32',
+ 'DISTNAME' => 'BN-CRC32',
+ 'VERSION' => '1.4',
+ 'OBJECT' => 'CRC32.o',
+ 'dist' => {COMPRESS=>'gzip', SUFFIX=>'gz'}
+);
--- /dev/null
+# This Makefile is for the BN::CRC32 extension to perl.
+#
+# It was generated automatically by MakeMaker version
+# 6.6302 (Revision: 66302) from the contents of
+# Makefile.PL. Don't edit this file, edit Makefile.PL instead.
+#
+# ANY CHANGES MADE HERE WILL BE LOST!
+#
+# MakeMaker ARGV: ()
+#
+
+# MakeMaker Parameters:
+
+# BUILD_REQUIRES => { }
+# CONFIGURE_REQUIRES => { }
+# DISTNAME => q[BN-CRC32]
+# NAME => q[BN::CRC32]
+# OBJECT => q[CRC32.o]
+# PREREQ_PM => { }
+# VERSION => q[1.4]
+# dist => { COMPRESS=>q[gzip], SUFFIX=>q[gz] }
+
+# --- MakeMaker post_initialize section:
+
+
+# --- MakeMaker const_config section:
+
+# These definitions are from config.sh (via /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/Config.pm).
+# They may have been overridden via Makefile.PL or on the command line.
+AR = ar
+CC = cc
+CCCDLFLAGS = -fPIC
+CCDLFLAGS = -Wl,-E -Wl,-rpath,/usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/CORE
+DLEXT = so
+DLSRC = dl_dlopen.xs
+EXE_EXT =
+FULL_AR = /usr/bin/ar
+LD = cc
+LDDLFLAGS = -shared -L/usr/local/lib64 -fstack-protector
+LDFLAGS = -L/usr/local/lib64 -fstack-protector
+LIBC = /lib64/libc-2.15.so
+LIB_EXT = .a
+OBJ_EXT = .o
+OSNAME = linux
+OSVERS = 3.1.10-1.9-default
+RANLIB = :
+SITELIBEXP = /usr/lib/perl5/site_perl/5.16.0
+SITEARCHEXP = /usr/lib/perl5/site_perl/5.16.0/x86_64-linux-thread-multi
+SO = so
+VENDORARCHEXP = /usr/lib/perl5/vendor_perl/5.16.0/x86_64-linux-thread-multi
+VENDORLIBEXP = /usr/lib/perl5/vendor_perl/5.16.0
+
+
+# --- MakeMaker constants section:
+AR_STATIC_ARGS = cr
+DIRFILESEP = /
+DFSEP = $(DIRFILESEP)
+NAME = BN::CRC32
+NAME_SYM = BN_CRC32
+VERSION = 1.4
+VERSION_MACRO = VERSION
+VERSION_SYM = 1_4
+DEFINE_VERSION = -D$(VERSION_MACRO)=\"$(VERSION)\"
+XS_VERSION = 1.4
+XS_VERSION_MACRO = XS_VERSION
+XS_DEFINE_VERSION = -D$(XS_VERSION_MACRO)=\"$(XS_VERSION)\"
+INST_ARCHLIB = blib/arch
+INST_SCRIPT = blib/script
+INST_BIN = blib/bin
+INST_LIB = blib/lib
+INST_MAN1DIR = blib/man1
+INST_MAN3DIR = blib/man3
+MAN1EXT = 1
+MAN3EXT = 3pm
+INSTALLDIRS = site
+DESTDIR =
+PREFIX = $(SITEPREFIX)
+PERLPREFIX = /usr
+SITEPREFIX = /usr
+VENDORPREFIX = /usr
+INSTALLPRIVLIB = /usr/lib/perl5/5.16.0
+DESTINSTALLPRIVLIB = $(DESTDIR)$(INSTALLPRIVLIB)
+INSTALLSITELIB = /usr/lib/perl5/site_perl/5.16.0
+DESTINSTALLSITELIB = $(DESTDIR)$(INSTALLSITELIB)
+INSTALLVENDORLIB = /usr/lib/perl5/vendor_perl/5.16.0
+DESTINSTALLVENDORLIB = $(DESTDIR)$(INSTALLVENDORLIB)
+INSTALLARCHLIB = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLARCHLIB = $(DESTDIR)$(INSTALLARCHLIB)
+INSTALLSITEARCH = /usr/lib/perl5/site_perl/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLSITEARCH = $(DESTDIR)$(INSTALLSITEARCH)
+INSTALLVENDORARCH = /usr/lib/perl5/vendor_perl/5.16.0/x86_64-linux-thread-multi
+DESTINSTALLVENDORARCH = $(DESTDIR)$(INSTALLVENDORARCH)
+INSTALLBIN = /usr/bin
+DESTINSTALLBIN = $(DESTDIR)$(INSTALLBIN)
+INSTALLSITEBIN = /usr/bin
+DESTINSTALLSITEBIN = $(DESTDIR)$(INSTALLSITEBIN)
+INSTALLVENDORBIN = /usr/bin
+DESTINSTALLVENDORBIN = $(DESTDIR)$(INSTALLVENDORBIN)
+INSTALLSCRIPT = /usr/bin
+DESTINSTALLSCRIPT = $(DESTDIR)$(INSTALLSCRIPT)
+INSTALLSITESCRIPT = /usr/bin
+DESTINSTALLSITESCRIPT = $(DESTDIR)$(INSTALLSITESCRIPT)
+INSTALLVENDORSCRIPT = /usr/bin
+DESTINSTALLVENDORSCRIPT = $(DESTDIR)$(INSTALLVENDORSCRIPT)
+INSTALLMAN1DIR = /usr/share/man/man1
+DESTINSTALLMAN1DIR = $(DESTDIR)$(INSTALLMAN1DIR)
+INSTALLSITEMAN1DIR = /usr/share/man/man1
+DESTINSTALLSITEMAN1DIR = $(DESTDIR)$(INSTALLSITEMAN1DIR)
+INSTALLVENDORMAN1DIR = /usr/share/man/man1
+DESTINSTALLVENDORMAN1DIR = $(DESTDIR)$(INSTALLVENDORMAN1DIR)
+INSTALLMAN3DIR = /usr/share/man/man3
+DESTINSTALLMAN3DIR = $(DESTDIR)$(INSTALLMAN3DIR)
+INSTALLSITEMAN3DIR = /usr/share/man/man3
+DESTINSTALLSITEMAN3DIR = $(DESTDIR)$(INSTALLSITEMAN3DIR)
+INSTALLVENDORMAN3DIR = /usr/share/man/man3
+DESTINSTALLVENDORMAN3DIR = $(DESTDIR)$(INSTALLVENDORMAN3DIR)
+PERL_LIB = /usr/lib/perl5/5.16.0
+PERL_ARCHLIB = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi
+LIBPERL_A = libperl.a
+FIRST_MAKEFILE = Makefile
+MAKEFILE_OLD = Makefile.old
+MAKE_APERL_FILE = Makefile.aperl
+PERLMAINCC = $(CC)
+PERL_INC = /usr/lib/perl5/5.16.0/x86_64-linux-thread-multi/CORE
+PERL = /usr/bin/perl
+FULLPERL = /usr/bin/perl
+ABSPERL = $(PERL)
+PERLRUN = $(PERL)
+FULLPERLRUN = $(FULLPERL)
+ABSPERLRUN = $(ABSPERL)
+PERLRUNINST = $(PERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+FULLPERLRUNINST = $(FULLPERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+ABSPERLRUNINST = $(ABSPERLRUN) "-I$(INST_ARCHLIB)" "-I$(INST_LIB)"
+PERL_CORE = 0
+PERM_DIR = 755
+PERM_RW = 644
+PERM_RWX = 755
+
+MAKEMAKER = /usr/lib/perl5/5.16.0/ExtUtils/MakeMaker.pm
+MM_VERSION = 6.6302
+MM_REVISION = 66302
+
+# FULLEXT = Pathname for extension directory (eg Foo/Bar/Oracle).
+# BASEEXT = Basename part of FULLEXT. May be just equal FULLEXT. (eg Oracle)
+# PARENT_NAME = NAME without BASEEXT and no trailing :: (eg Foo::Bar)
+# DLBASE = Basename part of dynamic library. May be just equal BASEEXT.
+MAKE = make
+FULLEXT = BN/CRC32
+BASEEXT = CRC32
+PARENT_NAME = BN
+DLBASE = $(BASEEXT)
+VERSION_FROM =
+OBJECT = CRC32$(OBJ_EXT)
+LDFROM = $(OBJECT)
+LINKTYPE = dynamic
+BOOTDEP =
+
+# Handy lists of source code files:
+XS_FILES = CRC32.xs \
+ CRC32_mod.xs
+C_FILES = CRC32.c \
+ CRC32_mod.c \
+ crcgen.c
+O_FILES = CRC32.o \
+ CRC32_mod.o \
+ crcgen.o
+H_FILES =
+MAN1PODS =
+MAN3PODS = CRC32.pod
+
+# Where is the Config information that we are using/depend on
+CONFIGDEP = $(PERL_ARCHLIB)$(DFSEP)Config.pm $(PERL_INC)$(DFSEP)config.h
+
+# Where to build things
+INST_LIBDIR = $(INST_LIB)/BN
+INST_ARCHLIBDIR = $(INST_ARCHLIB)/BN
+
+INST_AUTODIR = $(INST_LIB)/auto/$(FULLEXT)
+INST_ARCHAUTODIR = $(INST_ARCHLIB)/auto/$(FULLEXT)
+
+INST_STATIC = $(INST_ARCHAUTODIR)/$(BASEEXT)$(LIB_EXT)
+INST_DYNAMIC = $(INST_ARCHAUTODIR)/$(DLBASE).$(DLEXT)
+INST_BOOT = $(INST_ARCHAUTODIR)/$(BASEEXT).bs
+
+# Extra linker info
+EXPORT_LIST =
+PERL_ARCHIVE =
+PERL_ARCHIVE_AFTER =
+
+
+TO_INST_PM = CRC32.pm \
+ CRC32.pod \
+ CRC32_test.pm
+
+PM_TO_BLIB = CRC32.pod \
+ $(INST_LIB)/BN/CRC32.pod \
+ CRC32_test.pm \
+ $(INST_LIB)/BN/CRC32_test.pm \
+ CRC32.pm \
+ $(INST_LIB)/BN/CRC32.pm
+
+
+# --- MakeMaker platform_constants section:
+MM_Unix_VERSION = 6.6302
+PERL_MALLOC_DEF = -DPERL_EXTMALLOC_DEF -Dmalloc=Perl_malloc -Dfree=Perl_mfree -Drealloc=Perl_realloc -Dcalloc=Perl_calloc
+
+
+# --- MakeMaker tool_autosplit section:
+# Usage: $(AUTOSPLITFILE) FileToSplit AutoDirToSplitInto
+AUTOSPLITFILE = $(ABSPERLRUN) -e 'use AutoSplit; autosplit($$$$ARGV[0], $$$$ARGV[1], 0, 1, 1)' --
+
+
+
+# --- MakeMaker tool_xsubpp section:
+
+XSUBPPDIR = /usr/lib/perl5/5.16.0/ExtUtils
+XSUBPP = $(XSUBPPDIR)$(DFSEP)xsubpp
+XSUBPPRUN = $(PERLRUN) $(XSUBPP)
+XSPROTOARG =
+XSUBPPDEPS = /usr/lib/perl5/5.16.0/ExtUtils/typemap typemap $(XSUBPP)
+XSUBPPARGS = -typemap /usr/lib/perl5/5.16.0/ExtUtils/typemap -typemap typemap
+XSUBPP_EXTRA_ARGS =
+
+
+# --- MakeMaker tools_other section:
+SHELL = /bin/sh
+CHMOD = chmod
+CP = cp
+MV = mv
+NOOP = $(TRUE)
+NOECHO = @
+RM_F = rm -f
+RM_RF = rm -rf
+TEST_F = test -f
+TOUCH = touch
+UMASK_NULL = umask 0
+DEV_NULL = > /dev/null 2>&1
+MKPATH = $(ABSPERLRUN) -MExtUtils::Command -e 'mkpath' --
+EQUALIZE_TIMESTAMP = $(ABSPERLRUN) -MExtUtils::Command -e 'eqtime' --
+FALSE = false
+TRUE = true
+ECHO = echo
+ECHO_N = echo -n
+UNINST = 0
+VERBINST = 0
+MOD_INSTALL = $(ABSPERLRUN) -MExtUtils::Install -e 'install([ from_to => {@ARGV}, verbose => '\''$(VERBINST)'\'', uninstall_shadows => '\''$(UNINST)'\'', dir_mode => '\''$(PERM_DIR)'\'' ]);' --
+DOC_INSTALL = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'perllocal_install' --
+UNINSTALL = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'uninstall' --
+WARN_IF_OLD_PACKLIST = $(ABSPERLRUN) -MExtUtils::Command::MM -e 'warn_if_old_packlist' --
+MACROSTART =
+MACROEND =
+USEMAKEFILE = -f
+FIXIN = $(ABSPERLRUN) -MExtUtils::MY -e 'MY->fixin(shift)' --
+
+
+# --- MakeMaker makemakerdflt section:
+makemakerdflt : all
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dist section:
+TAR = tar
+TARFLAGS = cvf
+ZIP = zip
+ZIPFLAGS = -r
+COMPRESS = gzip
+SUFFIX = gz
+SHAR = shar
+PREOP = $(NOECHO) $(NOOP)
+POSTOP = $(NOECHO) $(NOOP)
+TO_UNIX = $(NOECHO) $(NOOP)
+CI = ci -u
+RCS_LABEL = rcs -Nv$(VERSION_SYM): -q
+DIST_CP = best
+DIST_DEFAULT = tardist
+DISTNAME = BN-CRC32
+DISTVNAME = BN-CRC32-1.4
+
+
+# --- MakeMaker macro section:
+
+
+# --- MakeMaker depend section:
+
+
+# --- MakeMaker cflags section:
+
+CCFLAGS = -D_REENTRANT -D_GNU_SOURCE -DPERL_USE_SAFE_PUTENV -fno-strict-aliasing -pipe -fstack-protector -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64
+OPTIMIZE = -fmessage-length=0 -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables -g -Wall -pipe
+PERLTYPE =
+MPOLLUTE =
+
+
+# --- MakeMaker const_loadlibs section:
+
+# BN::CRC32 might depend on some other libraries:
+# See ExtUtils::Liblist for details
+#
+
+
+# --- MakeMaker const_cccmd section:
+CCCMD = $(CC) -c $(PASTHRU_INC) $(INC) \
+ $(CCFLAGS) $(OPTIMIZE) \
+ $(PERLTYPE) $(MPOLLUTE) $(DEFINE_VERSION) \
+ $(XS_DEFINE_VERSION)
+
+# --- MakeMaker post_constants section:
+
+
+# --- MakeMaker pasthru section:
+
+PASTHRU = LIBPERL_A="$(LIBPERL_A)"\
+ LINKTYPE="$(LINKTYPE)"\
+ OPTIMIZE="$(OPTIMIZE)"\
+ PREFIX="$(PREFIX)"
+
+
+# --- MakeMaker special_targets section:
+.SUFFIXES : .xs .c .C .cpp .i .s .cxx .cc $(OBJ_EXT)
+
+.PHONY: all config static dynamic test linkext manifest blibdirs clean realclean disttest distdir
+
+
+
+# --- MakeMaker c_o section:
+
+.c.i:
+ cc -E -c $(PASTHRU_INC) $(INC) \
+ $(CCFLAGS) $(OPTIMIZE) \
+ $(PERLTYPE) $(MPOLLUTE) $(DEFINE_VERSION) \
+ $(XS_DEFINE_VERSION) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c > $*.i
+
+.c.s:
+ $(CCCMD) -S $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+.c$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+.cpp$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cpp
+
+.cxx$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cxx
+
+.cc$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.cc
+
+.C$(OBJ_EXT):
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.C
+
+
+# --- MakeMaker xs_c section:
+
+.xs.c:
+ $(XSUBPPRUN) $(XSPROTOARG) $(XSUBPPARGS) $(XSUBPP_EXTRA_ARGS) $*.xs > $*.xsc && $(MV) $*.xsc $*.c
+
+
+# --- MakeMaker xs_o section:
+
+.xs$(OBJ_EXT):
+ $(XSUBPPRUN) $(XSPROTOARG) $(XSUBPPARGS) $*.xs > $*.xsc && $(MV) $*.xsc $*.c
+ $(CCCMD) $(CCCDLFLAGS) "-I$(PERL_INC)" $(PASTHRU_DEFINE) $(DEFINE) $*.c
+
+
+# --- MakeMaker top_targets section:
+all :: pure_all manifypods
+ $(NOECHO) $(NOOP)
+
+
+pure_all :: config pm_to_blib subdirs linkext
+ $(NOECHO) $(NOOP)
+
+subdirs :: $(MYEXTLIB)
+ $(NOECHO) $(NOOP)
+
+config :: $(FIRST_MAKEFILE) blibdirs
+ $(NOECHO) $(NOOP)
+
+help :
+ perldoc ExtUtils::MakeMaker
+
+
+# --- MakeMaker blibdirs section:
+blibdirs : $(INST_LIBDIR)$(DFSEP).exists $(INST_ARCHLIB)$(DFSEP).exists $(INST_AUTODIR)$(DFSEP).exists $(INST_ARCHAUTODIR)$(DFSEP).exists $(INST_BIN)$(DFSEP).exists $(INST_SCRIPT)$(DFSEP).exists $(INST_MAN1DIR)$(DFSEP).exists $(INST_MAN3DIR)$(DFSEP).exists
+ $(NOECHO) $(NOOP)
+
+# Backwards compat with 6.18 through 6.25
+blibdirs.ts : blibdirs
+ $(NOECHO) $(NOOP)
+
+$(INST_LIBDIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_LIBDIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_LIBDIR)
+ $(NOECHO) $(TOUCH) $(INST_LIBDIR)$(DFSEP).exists
+
+$(INST_ARCHLIB)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_ARCHLIB)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_ARCHLIB)
+ $(NOECHO) $(TOUCH) $(INST_ARCHLIB)$(DFSEP).exists
+
+$(INST_AUTODIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_AUTODIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_AUTODIR)
+ $(NOECHO) $(TOUCH) $(INST_AUTODIR)$(DFSEP).exists
+
+$(INST_ARCHAUTODIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_ARCHAUTODIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_ARCHAUTODIR)
+ $(NOECHO) $(TOUCH) $(INST_ARCHAUTODIR)$(DFSEP).exists
+
+$(INST_BIN)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_BIN)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_BIN)
+ $(NOECHO) $(TOUCH) $(INST_BIN)$(DFSEP).exists
+
+$(INST_SCRIPT)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_SCRIPT)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_SCRIPT)
+ $(NOECHO) $(TOUCH) $(INST_SCRIPT)$(DFSEP).exists
+
+$(INST_MAN1DIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_MAN1DIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_MAN1DIR)
+ $(NOECHO) $(TOUCH) $(INST_MAN1DIR)$(DFSEP).exists
+
+$(INST_MAN3DIR)$(DFSEP).exists :: Makefile.PL
+ $(NOECHO) $(MKPATH) $(INST_MAN3DIR)
+ $(NOECHO) $(CHMOD) $(PERM_DIR) $(INST_MAN3DIR)
+ $(NOECHO) $(TOUCH) $(INST_MAN3DIR)$(DFSEP).exists
+
+
+
+# --- MakeMaker linkext section:
+
+linkext :: $(LINKTYPE)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dlsyms section:
+
+
+# --- MakeMaker dynamic section:
+
+dynamic :: $(FIRST_MAKEFILE) $(INST_DYNAMIC) $(INST_BOOT)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker dynamic_bs section:
+BOOTSTRAP = $(BASEEXT).bs
+
+# As Mkbootstrap might not write a file (if none is required)
+# we use touch to prevent make continually trying to remake it.
+# The DynaLoader only reads a non-empty file.
+$(BOOTSTRAP) : $(FIRST_MAKEFILE) $(BOOTDEP) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(NOECHO) $(ECHO) "Running Mkbootstrap for $(NAME) ($(BSLOADLIBS))"
+ $(NOECHO) $(PERLRUN) \
+ "-MExtUtils::Mkbootstrap" \
+ -e "Mkbootstrap('$(BASEEXT)','$(BSLOADLIBS)');"
+ $(NOECHO) $(TOUCH) $@
+ $(CHMOD) $(PERM_RW) $@
+
+$(INST_BOOT) : $(BOOTSTRAP) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(NOECHO) $(RM_RF) $@
+ - $(CP) $(BOOTSTRAP) $@
+ $(CHMOD) $(PERM_RW) $@
+
+
+# --- MakeMaker dynamic_lib section:
+
+# This section creates the dynamically loadable $(INST_DYNAMIC)
+# from $(OBJECT) and possibly $(MYEXTLIB).
+ARMAYBE = :
+OTHERLDFLAGS =
+INST_DYNAMIC_DEP =
+INST_DYNAMIC_FIX =
+
+$(INST_DYNAMIC): $(OBJECT) $(MYEXTLIB) $(BOOTSTRAP) $(INST_ARCHAUTODIR)$(DFSEP).exists $(EXPORT_LIST) $(PERL_ARCHIVE) $(PERL_ARCHIVE_AFTER) $(INST_DYNAMIC_DEP)
+ $(RM_F) $@
+ $(LD) $(LDDLFLAGS) $(LDFROM) $(OTHERLDFLAGS) -o $@ $(MYEXTLIB) \
+ $(PERL_ARCHIVE) $(LDLOADLIBS) $(PERL_ARCHIVE_AFTER) $(EXPORT_LIST) \
+ $(INST_DYNAMIC_FIX)
+ $(CHMOD) $(PERM_RWX) $@
+
+
+# --- MakeMaker static section:
+
+## $(INST_PM) has been moved to the all: target.
+## It remains here for awhile to allow for old usage: "make static"
+static :: $(FIRST_MAKEFILE) $(INST_STATIC)
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker static_lib section:
+
+$(INST_STATIC) : $(OBJECT) $(MYEXTLIB) $(INST_ARCHAUTODIR)$(DFSEP).exists
+ $(RM_RF) $@
+ $(FULL_AR) $(AR_STATIC_ARGS) $@ $(OBJECT) && $(RANLIB) $@
+ $(CHMOD) $(PERM_RWX) $@
+ $(NOECHO) $(ECHO) "$(EXTRALIBS)" > $(INST_ARCHAUTODIR)/extralibs.ld
+
+
+# --- MakeMaker manifypods section:
+
+POD2MAN_EXE = $(PERLRUN) "-MExtUtils::Command::MM" -e pod2man "--"
+POD2MAN = $(POD2MAN_EXE)
+
+
+manifypods : pure_all \
+ CRC32.pod
+ $(NOECHO) $(POD2MAN) --section=3 --perm_rw=$(PERM_RW) \
+ CRC32.pod $(INST_MAN3DIR)/BN::CRC32.$(MAN3EXT)
+
+
+
+
+# --- MakeMaker processPL section:
+
+
+# --- MakeMaker installbin section:
+
+
+# --- MakeMaker subdirs section:
+
+# none
+
+# --- MakeMaker clean_subdirs section:
+clean_subdirs :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker clean section:
+
+# Delete temporary files but do not touch installed files. We don't delete
+# the Makefile here so a later make realclean still has a makefile to use.
+
+clean :: clean_subdirs
+ - $(RM_F) \
+ core.[0-9] $(BASEEXT).bso \
+ pm_to_blib.ts core.[0-9][0-9][0-9][0-9] \
+ MYMETA.yml perl$(EXE_EXT) \
+ tmon.out *$(OBJ_EXT) \
+ pm_to_blib blibdirs.ts \
+ *perl.core core.*perl.*.? \
+ $(BASEEXT).def core.[0-9][0-9][0-9] \
+ mon.out lib$(BASEEXT).def \
+ perlmain.c perl.exe \
+ so_locations $(BASEEXT).exp \
+ CRC32.c CRC32_mod.c \
+ *$(LIB_EXT) core \
+ $(INST_ARCHAUTODIR)/extralibs.all core.[0-9][0-9] \
+ MYMETA.json $(BOOTSTRAP) \
+ $(BASEEXT).x $(INST_ARCHAUTODIR)/extralibs.ld \
+ core.[0-9][0-9][0-9][0-9][0-9] $(MAKE_APERL_FILE) \
+ perl
+ - $(RM_RF) \
+ blib
+ - $(MV) $(FIRST_MAKEFILE) $(MAKEFILE_OLD) $(DEV_NULL)
+
+
+# --- MakeMaker realclean_subdirs section:
+realclean_subdirs :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker realclean section:
+# Delete temporary files (via clean) and also delete dist files
+realclean purge :: clean realclean_subdirs
+ - $(RM_F) \
+ $(OBJECT) $(MAKEFILE_OLD) \
+ $(FIRST_MAKEFILE)
+ - $(RM_RF) \
+ $(DISTVNAME)
+
+
+# --- MakeMaker metafile section:
+metafile : create_distdir
+ $(NOECHO) $(ECHO) Generating META.yml
+ $(NOECHO) $(ECHO) '---' > META_new.yml
+ $(NOECHO) $(ECHO) 'abstract: unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'author:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'build_requires:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' ExtUtils::MakeMaker: 0' >> META_new.yml
+ $(NOECHO) $(ECHO) 'configure_requires:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' ExtUtils::MakeMaker: 0' >> META_new.yml
+ $(NOECHO) $(ECHO) 'dynamic_config: 1' >> META_new.yml
+ $(NOECHO) $(ECHO) 'generated_by: '\''ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120921'\''' >> META_new.yml
+ $(NOECHO) $(ECHO) 'license: unknown' >> META_new.yml
+ $(NOECHO) $(ECHO) 'meta-spec:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' url: http://module-build.sourceforge.net/META-spec-v1.4.html' >> META_new.yml
+ $(NOECHO) $(ECHO) ' version: 1.4' >> META_new.yml
+ $(NOECHO) $(ECHO) 'name: BN-CRC32' >> META_new.yml
+ $(NOECHO) $(ECHO) 'no_index:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' directory:' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - t' >> META_new.yml
+ $(NOECHO) $(ECHO) ' - inc' >> META_new.yml
+ $(NOECHO) $(ECHO) 'requires: {}' >> META_new.yml
+ $(NOECHO) $(ECHO) 'version: 1.4' >> META_new.yml
+ -$(NOECHO) $(MV) META_new.yml $(DISTVNAME)/META.yml
+ $(NOECHO) $(ECHO) Generating META.json
+ $(NOECHO) $(ECHO) '{' > META_new.json
+ $(NOECHO) $(ECHO) ' "abstract" : "unknown",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "author" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "unknown"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ],' >> META_new.json
+ $(NOECHO) $(ECHO) ' "dynamic_config" : 1,' >> META_new.json
+ $(NOECHO) $(ECHO) ' "generated_by" : "ExtUtils::MakeMaker version 6.6302, CPAN::Meta::Converter version 2.120921",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "license" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "unknown"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ],' >> META_new.json
+ $(NOECHO) $(ECHO) ' "meta-spec" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "url" : "http://search.cpan.org/perldoc?CPAN::Meta::Spec",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "version" : "2"' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "name" : "BN-CRC32",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "no_index" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "directory" : [' >> META_new.json
+ $(NOECHO) $(ECHO) ' "t",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "inc"' >> META_new.json
+ $(NOECHO) $(ECHO) ' ]' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "prereqs" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "build" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "ExtUtils::MakeMaker" : "0"' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "configure" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "ExtUtils::MakeMaker" : "0"' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "runtime" : {' >> META_new.json
+ $(NOECHO) $(ECHO) ' "requires" : {}' >> META_new.json
+ $(NOECHO) $(ECHO) ' }' >> META_new.json
+ $(NOECHO) $(ECHO) ' },' >> META_new.json
+ $(NOECHO) $(ECHO) ' "release_status" : "stable",' >> META_new.json
+ $(NOECHO) $(ECHO) ' "version" : "1.4"' >> META_new.json
+ $(NOECHO) $(ECHO) '}' >> META_new.json
+ -$(NOECHO) $(MV) META_new.json $(DISTVNAME)/META.json
+
+
+# --- MakeMaker signature section:
+signature :
+ cpansign -s
+
+
+# --- MakeMaker dist_basics section:
+distclean :: realclean distcheck
+ $(NOECHO) $(NOOP)
+
+distcheck :
+ $(PERLRUN) "-MExtUtils::Manifest=fullcheck" -e fullcheck
+
+skipcheck :
+ $(PERLRUN) "-MExtUtils::Manifest=skipcheck" -e skipcheck
+
+manifest :
+ $(PERLRUN) "-MExtUtils::Manifest=mkmanifest" -e mkmanifest
+
+veryclean : realclean
+ $(RM_F) *~ */*~ *.orig */*.orig *.bak */*.bak *.old */*.old
+
+
+
+# --- MakeMaker dist_core section:
+
+dist : $(DIST_DEFAULT) $(FIRST_MAKEFILE)
+ $(NOECHO) $(ABSPERLRUN) -l -e 'print '\''Warning: Makefile possibly out of date with $(VERSION_FROM)'\''' \
+ -e ' if -e '\''$(VERSION_FROM)'\'' and -M '\''$(VERSION_FROM)'\'' < -M '\''$(FIRST_MAKEFILE)'\'';' --
+
+tardist : $(DISTVNAME).tar$(SUFFIX)
+ $(NOECHO) $(NOOP)
+
+uutardist : $(DISTVNAME).tar$(SUFFIX)
+ uuencode $(DISTVNAME).tar$(SUFFIX) $(DISTVNAME).tar$(SUFFIX) > $(DISTVNAME).tar$(SUFFIX)_uu
+
+$(DISTVNAME).tar$(SUFFIX) : distdir
+ $(PREOP)
+ $(TO_UNIX)
+ $(TAR) $(TARFLAGS) $(DISTVNAME).tar $(DISTVNAME)
+ $(RM_RF) $(DISTVNAME)
+ $(COMPRESS) $(DISTVNAME).tar
+ $(POSTOP)
+
+zipdist : $(DISTVNAME).zip
+ $(NOECHO) $(NOOP)
+
+$(DISTVNAME).zip : distdir
+ $(PREOP)
+ $(ZIP) $(ZIPFLAGS) $(DISTVNAME).zip $(DISTVNAME)
+ $(RM_RF) $(DISTVNAME)
+ $(POSTOP)
+
+shdist : distdir
+ $(PREOP)
+ $(SHAR) $(DISTVNAME) > $(DISTVNAME).shar
+ $(RM_RF) $(DISTVNAME)
+ $(POSTOP)
+
+
+# --- MakeMaker distdir section:
+create_distdir :
+ $(RM_RF) $(DISTVNAME)
+ $(PERLRUN) "-MExtUtils::Manifest=manicopy,maniread" \
+ -e "manicopy(maniread(),'$(DISTVNAME)', '$(DIST_CP)');"
+
+distdir : create_distdir distmeta
+ $(NOECHO) $(NOOP)
+
+
+
+# --- MakeMaker dist_test section:
+disttest : distdir
+ cd $(DISTVNAME) && $(ABSPERLRUN) Makefile.PL
+ cd $(DISTVNAME) && $(MAKE) $(PASTHRU)
+ cd $(DISTVNAME) && $(MAKE) test $(PASTHRU)
+
+
+
+# --- MakeMaker dist_ci section:
+
+ci :
+ $(PERLRUN) "-MExtUtils::Manifest=maniread" \
+ -e "@all = keys %{ maniread() };" \
+ -e "print(qq{Executing $(CI) @all\n}); system(qq{$(CI) @all});" \
+ -e "print(qq{Executing $(RCS_LABEL) ...\n}); system(qq{$(RCS_LABEL) @all});"
+
+
+# --- MakeMaker distmeta section:
+distmeta : create_distdir metafile
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'exit unless -e q{META.yml};' \
+ -e 'eval { maniadd({q{META.yml} => q{Module YAML meta-data (added by MakeMaker)}}) }' \
+ -e ' or print "Could not add META.yml to MANIFEST: $$$${'\''@'\''}\n"' --
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'exit unless -f q{META.json};' \
+ -e 'eval { maniadd({q{META.json} => q{Module JSON meta-data (added by MakeMaker)}}) }' \
+ -e ' or print "Could not add META.json to MANIFEST: $$$${'\''@'\''}\n"' --
+
+
+
+# --- MakeMaker distsignature section:
+distsignature : create_distdir
+ $(NOECHO) cd $(DISTVNAME) && $(ABSPERLRUN) -MExtUtils::Manifest=maniadd -e 'eval { maniadd({q{SIGNATURE} => q{Public-key signature (added by MakeMaker)}}) } ' \
+ -e ' or print "Could not add SIGNATURE to MANIFEST: $$$${'\''@'\''}\n"' --
+ $(NOECHO) cd $(DISTVNAME) && $(TOUCH) SIGNATURE
+ cd $(DISTVNAME) && cpansign -s
+
+
+
+# --- MakeMaker install section:
+
+install :: pure_install doc_install
+ $(NOECHO) $(NOOP)
+
+install_perl :: pure_perl_install doc_perl_install
+ $(NOECHO) $(NOOP)
+
+install_site :: pure_site_install doc_site_install
+ $(NOECHO) $(NOOP)
+
+install_vendor :: pure_vendor_install doc_vendor_install
+ $(NOECHO) $(NOOP)
+
+pure_install :: pure_$(INSTALLDIRS)_install
+ $(NOECHO) $(NOOP)
+
+doc_install :: doc_$(INSTALLDIRS)_install
+ $(NOECHO) $(NOOP)
+
+pure__install : pure_site_install
+ $(NOECHO) $(ECHO) INSTALLDIRS not defined, defaulting to INSTALLDIRS=site
+
+doc__install : doc_site_install
+ $(NOECHO) $(ECHO) INSTALLDIRS not defined, defaulting to INSTALLDIRS=site
+
+pure_perl_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(PERL_ARCHLIB)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLARCHLIB)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLPRIVLIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLARCHLIB) \
+ $(INST_BIN) $(DESTINSTALLBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLSCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLMAN3DIR)
+ $(NOECHO) $(WARN_IF_OLD_PACKLIST) \
+ $(SITEARCHEXP)/auto/$(FULLEXT)
+
+
+pure_site_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(SITEARCHEXP)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLSITEARCH)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLSITELIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLSITEARCH) \
+ $(INST_BIN) $(DESTINSTALLSITEBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLSITESCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLSITEMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLSITEMAN3DIR)
+ $(NOECHO) $(WARN_IF_OLD_PACKLIST) \
+ $(PERL_ARCHLIB)/auto/$(FULLEXT)
+
+pure_vendor_install :: all
+ $(NOECHO) $(MOD_INSTALL) \
+ read $(VENDORARCHEXP)/auto/$(FULLEXT)/.packlist \
+ write $(DESTINSTALLVENDORARCH)/auto/$(FULLEXT)/.packlist \
+ $(INST_LIB) $(DESTINSTALLVENDORLIB) \
+ $(INST_ARCHLIB) $(DESTINSTALLVENDORARCH) \
+ $(INST_BIN) $(DESTINSTALLVENDORBIN) \
+ $(INST_SCRIPT) $(DESTINSTALLVENDORSCRIPT) \
+ $(INST_MAN1DIR) $(DESTINSTALLVENDORMAN1DIR) \
+ $(INST_MAN3DIR) $(DESTINSTALLVENDORMAN3DIR)
+
+doc_perl_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLPRIVLIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+doc_site_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLSITELIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+doc_vendor_install :: all
+ $(NOECHO) $(ECHO) Appending installation info to $(DESTINSTALLARCHLIB)/perllocal.pod
+ -$(NOECHO) $(MKPATH) $(DESTINSTALLARCHLIB)
+ -$(NOECHO) $(DOC_INSTALL) \
+ "Module" "$(NAME)" \
+ "installed into" "$(INSTALLVENDORLIB)" \
+ LINKTYPE "$(LINKTYPE)" \
+ VERSION "$(VERSION)" \
+ EXE_FILES "$(EXE_FILES)" \
+ >> $(DESTINSTALLARCHLIB)/perllocal.pod
+
+
+uninstall :: uninstall_from_$(INSTALLDIRS)dirs
+ $(NOECHO) $(NOOP)
+
+uninstall_from_perldirs ::
+ $(NOECHO) $(UNINSTALL) $(PERL_ARCHLIB)/auto/$(FULLEXT)/.packlist
+
+uninstall_from_sitedirs ::
+ $(NOECHO) $(UNINSTALL) $(SITEARCHEXP)/auto/$(FULLEXT)/.packlist
+
+uninstall_from_vendordirs ::
+ $(NOECHO) $(UNINSTALL) $(VENDORARCHEXP)/auto/$(FULLEXT)/.packlist
+
+
+# --- MakeMaker force section:
+# Phony target to force checking subdirectories.
+FORCE :
+ $(NOECHO) $(NOOP)
+
+
+# --- MakeMaker perldepend section:
+
+PERL_HDRS = \
+ $(PERL_INC)/EXTERN.h \
+ $(PERL_INC)/INTERN.h \
+ $(PERL_INC)/XSUB.h \
+ $(PERL_INC)/av.h \
+ $(PERL_INC)/config.h \
+ $(PERL_INC)/cop.h \
+ $(PERL_INC)/cv.h \
+ $(PERL_INC)/dosish.h \
+ $(PERL_INC)/embed.h \
+ $(PERL_INC)/embedvar.h \
+ $(PERL_INC)/fakethr.h \
+ $(PERL_INC)/form.h \
+ $(PERL_INC)/gv.h \
+ $(PERL_INC)/handy.h \
+ $(PERL_INC)/hv.h \
+ $(PERL_INC)/intrpvar.h \
+ $(PERL_INC)/iperlsys.h \
+ $(PERL_INC)/keywords.h \
+ $(PERL_INC)/mg.h \
+ $(PERL_INC)/nostdio.h \
+ $(PERL_INC)/op.h \
+ $(PERL_INC)/opcode.h \
+ $(PERL_INC)/patchlevel.h \
+ $(PERL_INC)/perl.h \
+ $(PERL_INC)/perlio.h \
+ $(PERL_INC)/perlsdio.h \
+ $(PERL_INC)/perlsfio.h \
+ $(PERL_INC)/perlvars.h \
+ $(PERL_INC)/perly.h \
+ $(PERL_INC)/pp.h \
+ $(PERL_INC)/pp_proto.h \
+ $(PERL_INC)/proto.h \
+ $(PERL_INC)/regcomp.h \
+ $(PERL_INC)/regexp.h \
+ $(PERL_INC)/regnodes.h \
+ $(PERL_INC)/scope.h \
+ $(PERL_INC)/sv.h \
+ $(PERL_INC)/thread.h \
+ $(PERL_INC)/unixish.h \
+ $(PERL_INC)/util.h
+
+$(OBJECT) : $(PERL_HDRS)
+
+CRC32.c CRC32_mod.c : $(XSUBPPDEPS)
+
+
+# --- MakeMaker makefile section:
+
+$(OBJECT) : $(FIRST_MAKEFILE)
+
+# We take a very conservative approach here, but it's worth it.
+# We move Makefile to Makefile.old here to avoid gnu make looping.
+$(FIRST_MAKEFILE) : Makefile.PL $(CONFIGDEP)
+ $(NOECHO) $(ECHO) "Makefile out-of-date with respect to $?"
+ $(NOECHO) $(ECHO) "Cleaning current config before rebuilding Makefile..."
+ -$(NOECHO) $(RM_F) $(MAKEFILE_OLD)
+ -$(NOECHO) $(MV) $(FIRST_MAKEFILE) $(MAKEFILE_OLD)
+ - $(MAKE) $(USEMAKEFILE) $(MAKEFILE_OLD) clean $(DEV_NULL)
+ $(PERLRUN) Makefile.PL
+ $(NOECHO) $(ECHO) "==> Your Makefile has been rebuilt. <=="
+ $(NOECHO) $(ECHO) "==> Please rerun the $(MAKE) command. <=="
+ $(FALSE)
+
+
+
+# --- MakeMaker staticmake section:
+
+# --- MakeMaker makeaperl section ---
+MAP_TARGET = perl
+FULLPERL = /usr/bin/perl
+
+$(MAP_TARGET) :: static $(MAKE_APERL_FILE)
+ $(MAKE) $(USEMAKEFILE) $(MAKE_APERL_FILE) $@
+
+$(MAKE_APERL_FILE) : $(FIRST_MAKEFILE) pm_to_blib
+ $(NOECHO) $(ECHO) Writing \"$(MAKE_APERL_FILE)\" for this $(MAP_TARGET)
+ $(NOECHO) $(PERLRUNINST) \
+ Makefile.PL DIR= \
+ MAKEFILE=$(MAKE_APERL_FILE) LINKTYPE=static \
+ MAKEAPERL=1 NORECURS=1 CCCDLFLAGS=
+
+
+# --- MakeMaker test section:
+
+TEST_VERBOSE=0
+TEST_TYPE=test_$(LINKTYPE)
+TEST_FILE = test.pl
+TEST_FILES = t/*.t
+TESTDB_SW = -d
+
+testdb :: testdb_$(LINKTYPE)
+
+test :: $(TEST_TYPE) subdirs-test
+
+subdirs-test ::
+ $(NOECHO) $(NOOP)
+
+
+test_dynamic :: pure_all
+ PERL_DL_NONLAZY=1 $(FULLPERLRUN) "-MExtUtils::Command::MM" "-e" "test_harness($(TEST_VERBOSE), '$(INST_LIB)', '$(INST_ARCHLIB)')" $(TEST_FILES)
+
+testdb_dynamic :: pure_all
+ PERL_DL_NONLAZY=1 $(FULLPERLRUN) $(TESTDB_SW) "-I$(INST_LIB)" "-I$(INST_ARCHLIB)" $(TEST_FILE)
+
+test_ : test_dynamic
+
+test_static :: pure_all $(MAP_TARGET)
+ PERL_DL_NONLAZY=1 ./$(MAP_TARGET) "-MExtUtils::Command::MM" "-e" "test_harness($(TEST_VERBOSE), '$(INST_LIB)', '$(INST_ARCHLIB)')" $(TEST_FILES)
+
+testdb_static :: pure_all $(MAP_TARGET)
+ PERL_DL_NONLAZY=1 ./$(MAP_TARGET) $(TESTDB_SW) "-I$(INST_LIB)" "-I$(INST_ARCHLIB)" $(TEST_FILE)
+
+
+
+# --- MakeMaker ppd section:
+# Creates a PPD (Perl Package Description) for a binary distribution.
+ppd :
+ $(NOECHO) $(ECHO) '<SOFTPKG NAME="$(DISTNAME)" VERSION="$(VERSION)">' > $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <ABSTRACT></ABSTRACT>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <AUTHOR></AUTHOR>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <IMPLEMENTATION>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <ARCHITECTURE NAME="x86_64-linux-thread-multi-5.16" />' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' <CODEBASE HREF="" />' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) ' </IMPLEMENTATION>' >> $(DISTNAME).ppd
+ $(NOECHO) $(ECHO) '</SOFTPKG>' >> $(DISTNAME).ppd
+
+
+# --- MakeMaker pm_to_blib section:
+
+pm_to_blib : $(FIRST_MAKEFILE) $(TO_INST_PM)
+ $(NOECHO) $(ABSPERLRUN) -MExtUtils::Install -e 'pm_to_blib({@ARGV}, '\''$(INST_LIB)/auto'\'', q[$(PM_FILTER)], '\''$(PERM_DIR)'\'')' -- \
+ CRC32.pod $(INST_LIB)/BN/CRC32.pod \
+ CRC32_test.pm $(INST_LIB)/BN/CRC32_test.pm \
+ CRC32.pm $(INST_LIB)/BN/CRC32.pm
+ $(NOECHO) $(TOUCH) pm_to_blib
+
+
+# --- MakeMaker selfdocument section:
+
+
+# --- MakeMaker postamble section:
+
+
+# End.
--- /dev/null
+
+Perl Module String::CRC32
+
+This packages provides a perl module to generate checksums from strings
+and from files.
+
+Written 19990310 by Soenke J. Peters <peters__perl@opcenter.de>.
+
+The checksums are the same as those calculated by ZMODEM, PKZIP,
+PICCHECK and many others.
+There's another perl module called String::CRC which allows to calculate
+not only 32 bit CRC numbers, but the generated sums differ from those of
+the programs mentioned above.
+
+Installation:
+ "perl Makefile.PL"
+ "make"
+ "make test"
+ "make install"
+
+If you find any bugs, please send me a good description (or a patch ;-) ).
+Thanks to s0lar(at)gmx.li who sent me a patch to replace PerlIO_getc with
+PerlIO_read to improve performance.
+
+Have fun,
+ Soenke J. Peters
+ Rostock, Germany
+
+
--- /dev/null
+
+package BN::CRC32;
+
+require Exporter;
+require DynaLoader;
+
+@ISA = qw(Exporter DynaLoader);
+
+$VERSION = 1.4;
+
+# Items to export into callers namespace by default
+@EXPORT = qw(crc32);
+
+# Other items we are prepared to export if requested
+@EXPORT_OK = qw();
+
+bootstrap BN::CRC32;
+
+1;
--- /dev/null
+=head1 NAME
+
+String::CRC32 - Perl interface for cyclic redundency check generation
+
+=head1 SYNOPSIS
+
+ use String::CRC32;
+
+ $crc = crc32("some string");
+ $crc = crc32("some string", initvalue);
+
+ $somestring = "some string";
+ $crc = crc32($somestring);
+
+ open(SOMEFILE, "location/of/some.file");
+ $crc = crc32(*SOMEFILE);
+ close(SOMEFILE);
+
+=head1 DESCRIPTION
+
+The B<CRC32> module calculates CRC sums of 32 bit lenghts.
+It generates the same CRC values as ZMODEM, PKZIP, PICCHECK and
+many others.
+
+Despite its name, this module is able to compute
+the checksum of files as well as strings.
+
+=head1 EXAMPLES
+
+ $crc = crc32("some string");
+
+ results in the same as
+
+ $crc = crc32(" string", crc32("some"));
+
+This is useful for subsequent CRC checking of substrings.
+
+You may even check files:
+
+ open(SOMEFILE, "location/of/some.file");
+ $crc = crc32(*SOMEFILE);
+ close(SOMEFILE);
+
+A init value may also been supplied in the above example.
+
+=head1 AUTHOR
+
+Soenke J. Peters <peters__perl@opcenter.de>
+
+Please be so kind as to report any bugs/suggestions to the above address.
+
+=head1 COPYRIGHT
+
+CRC algorithm code taken from CRC-32 by Craig Bruce.
+The module stuff is inspired by a similar perl module called
+String::CRC by David Sharnoff & Matthew Dillon.
+Horst Fickenscher told me that it could be useful to supply an init
+value to the crc checking function and so I included this possibility.
+
+The author of this package disclaims all copyrights and
+releases it into the public domain.
--- /dev/null
+#/usr/bin/perl -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch -I/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/lib
+#
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+use BN::CRC32;
+
+print "PERL:" . crc32("A string.");
--- /dev/null
+.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.20)
+.\"
+.\" Standard preamble:
+.\" ========================================================================
+.de Sp \" Vertical space (when we can't use .PP)
+.if t .sp .5v
+.if n .sp
+..
+.de Vb \" Begin verbatim text
+.ft CW
+.nf
+.ne \\$1
+..
+.de Ve \" End verbatim text
+.ft R
+.fi
+..
+.\" Set up some character translations and predefined strings. \*(-- will
+.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
+.\" double quote, and \*(R" will give a right double quote. \*(C+ will
+.\" give a nicer C++. Capital omega is used to do unbreakable dashes and
+.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff,
+.\" nothing in troff, for use with C<>.
+.tr \(*W-
+.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
+.ie n \{\
+. ds -- \(*W-
+. ds PI pi
+. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
+. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
+. ds L" ""
+. ds R" ""
+. ds C` ""
+. ds C' ""
+'br\}
+.el\{\
+. ds -- \|\(em\|
+. ds PI \(*p
+. ds L" ``
+. ds R" ''
+'br\}
+.\"
+.\" Escape single quotes in literal strings from groff's Unicode transform.
+.ie \n(.g .ds Aq \(aq
+.el .ds Aq '
+.\"
+.\" If the F register is turned on, we'll generate index entries on stderr for
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
+.\" entries marked with X<> in POD. Of course, you'll have to process the
+.\" output yourself in some meaningful fashion.
+.ie \nF \{\
+. de IX
+. tm Index:\\$1\t\\n%\t"\\$2"
+..
+. nr % 0
+. rr F
+.\}
+.el \{\
+. de IX
+..
+.\}
+.\"
+.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
+.\" Fear. Run. Save yourself. No user-serviceable parts.
+. \" fudge factors for nroff and troff
+.if n \{\
+. ds #H 0
+. ds #V .8m
+. ds #F .3m
+. ds #[ \f1
+. ds #] \fP
+.\}
+.if t \{\
+. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
+. ds #V .6m
+. ds #F 0
+. ds #[ \&
+. ds #] \&
+.\}
+. \" simple accents for nroff and troff
+.if n \{\
+. ds ' \&
+. ds ` \&
+. ds ^ \&
+. ds , \&
+. ds ~ ~
+. ds /
+.\}
+.if t \{\
+. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
+. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
+. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
+. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
+. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
+. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
+.\}
+. \" troff and (daisy-wheel) nroff accents
+.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
+.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
+.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
+.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
+.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
+.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
+.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
+.ds ae a\h'-(\w'a'u*4/10)'e
+.ds Ae A\h'-(\w'A'u*4/10)'E
+. \" corrections for vroff
+.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
+.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
+. \" for low resolution devices (crt and lpr)
+.if \n(.H>23 .if \n(.V>19 \
+\{\
+. ds : e
+. ds 8 ss
+. ds o a
+. ds d- d\h'-1'\(ga
+. ds D- D\h'-1'\(hy
+. ds th \o'bp'
+. ds Th \o'LP'
+. ds ae ae
+. ds Ae AE
+.\}
+.rm #[ #] #H #V #F C
+.\" ========================================================================
+.\"
+.IX Title "CRC32 3"
+.TH CRC32 3 "2012-07-16" "perl v5.16.0" "User Contributed Perl Documentation"
+.\" For nroff, turn off justification. Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.if n .ad l
+.nh
+.SH "NAME"
+String::CRC32 \- Perl interface for cyclic redundency check generation
+.SH "SYNOPSIS"
+.IX Header "SYNOPSIS"
+.Vb 1
+\& use String::CRC32;
+\&
+\& $crc = crc32("some string");
+\& $crc = crc32("some string", initvalue);
+\&
+\& $somestring = "some string";
+\& $crc = crc32($somestring);
+\&
+\& open(SOMEFILE, "location/of/some.file");
+\& $crc = crc32(*SOMEFILE);
+\& close(SOMEFILE);
+.Ve
+.SH "DESCRIPTION"
+.IX Header "DESCRIPTION"
+The \fB\s-1CRC32\s0\fR module calculates \s-1CRC\s0 sums of 32 bit lenghts.
+It generates the same \s-1CRC\s0 values as \s-1ZMODEM\s0, \s-1PKZIP\s0, \s-1PICCHECK\s0 and
+many others.
+.PP
+Despite its name, this module is able to compute
+the checksum of files as well as strings.
+.SH "EXAMPLES"
+.IX Header "EXAMPLES"
+.Vb 1
+\& $crc = crc32("some string");
+\&
+\& results in the same as
+\&
+\& $crc = crc32(" string", crc32("some"));
+.Ve
+.PP
+This is useful for subsequent \s-1CRC\s0 checking of substrings.
+.PP
+You may even check files:
+.PP
+.Vb 3
+\& open(SOMEFILE, "location/of/some.file");
+\& $crc = crc32(*SOMEFILE);
+\& close(SOMEFILE);
+.Ve
+.PP
+A init value may also been supplied in the above example.
+.SH "AUTHOR"
+.IX Header "AUTHOR"
+Soenke J. Peters <peters_\|_perl@opcenter.de>
+.PP
+Please be so kind as to report any bugs/suggestions to the above address.
+.SH "COPYRIGHT"
+.IX Header "COPYRIGHT"
+\&\s-1CRC\s0 algorithm code taken from \s-1CRC\-32\s0 by Craig Bruce.
+The module stuff is inspired by a similar perl module called
+String::CRC by David Sharnoff & Matthew Dillon.
+Horst Fickenscher told me that it could be useful to supply an init
+value to the crc checking function and so I included this possibility.
+.PP
+The author of this package disclaims all copyrights and
+releases it into the public domain.
--- /dev/null
+/*
+ Generation of CRC lookup table
+ as used in Perl module "String::CRC32"
+
+ 1999 by Soenke J. Peters <peters__perl@opcenter.de>
+*/
+
+#include <stdio.h>
+
+int
+main ( void )
+{
+ unsigned long crc, poly;
+ int i, j;
+
+ poly = 0xEDB88320L;
+
+ printf("unigned long\ncrcTable[256] = {\n");
+ for (i=0; i<256; i++) {
+ crc = i;
+ for (j=8; j>0; j--) {
+ if (crc&1) {
+ crc = (crc >> 1) ^ poly;
+ } else {
+ crc >>= 1;
+ }
+ }
+ printf( "0x%lx,", crc);
+ if( (i&7) == 7 )
+ printf("\n" );
+ else
+ printf(" ");
+ }
+ printf("};\n");
+ return 0;
+}
--- /dev/null
+10
+
+dir
+135
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj/trb_maps_jtag3/ui/BN/t
+svn+ssh://svnuser@salt.x-matter.uni-frankfurt.de/jtag_proj
+
+
+
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+b00609d0-aec6-11df-b1c7-bba583a822eb
+\f
+testfile
+file
+
+
+
+
+2011-11-23T15:31:54.000000Z
+71028f53a3da56cde4154db3cddf8fcb
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+73
+\f
+crc.t
+file
+
+
+
+
+2011-11-23T15:31:54.000000Z
+4f253d4d9b1bb65c9fb32b015721f898
+2011-11-28T16:19:53.211492Z
+134
+bneumann
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1027
+\f
--- /dev/null
+#!/usr/local/bin/perl -I./blib/arch -I./blib/lib
+
+require BN::CRC32;
+
+$string1 = "This is the test string";
+
+$l1 = length($string1);
+
+print "1..", $l1+4, "\n";
+
+print "\n1) Test the CRC of a string variable\n";
+$v1 = BN::CRC32::crc32($string1);
+print ($v1 == 1835534707 ? "ok 1\n" : "not ok 1\n");
+
+print "\n2) Test the CRC of a string\n";
+$v1 = BN::CRC32::crc32("This is another test string");
+print ($v1 == 2154698217 ? "ok 2\n" : "not ok 2\n");
+
+$i = 2;
+
+$l=$l1+3;
+print "\n3..$l) Test the CRC of various substrings (using crcinit)\n";
+for ($j = 0; $j <= $l1; $j++) {
+ $v1 = BN::CRC32::crc32(substr($string1, 0, $j));
+ $v1 = BN::CRC32::crc32(substr($string1, $j), $v1);
+ $i++;
+ print ($v1 == 1835534707 ? "ok $i\n" : "not ok $i\n");
+}
+
+$l=$l1+4;
+print "\n$l) Test the CRC of a file\n";
+$i++;
+open(TESTFILE,"testfile") ||
+ open(TESTFILE,"t/testfile") ||
+ open(TESTFILE," ../testfile") || die "No such file!\n";
+$v1 = BN::CRC32::crc32(*TESTFILE);
+close TESTFILE;
+print ($v1 == 1925609391 ? "ok $i\n" : "not ok $i\n");
--- /dev/null
+Do not alter this file!
+Changing this file will result in a failing test!
\ No newline at end of file
--- /dev/null
+#!/usr/local/bin/perl -I./blib/arch -I./blib/lib
+
+require BN::CRC32;
+
+$string1 = "This is the test string";
+
+$l1 = length($string1);
+
+print "1..", $l1+4, "\n";
+
+print "\n1) Test the CRC of a string variable\n";
+$v1 = BN::CRC32::crc32($string1);
+print ($v1 == 1835534707 ? "ok 1\n" : "not ok 1\n");
+
+print "\n2) Test the CRC of a string\n";
+$v1 = BN::CRC32::crc32("This is another test string");
+print ($v1 == 2154698217 ? "ok 2\n" : "not ok 2\n");
+
+$i = 2;
+
+$l=$l1+3;
+print "\n3..$l) Test the CRC of various substrings (using crcinit)\n";
+for ($j = 0; $j <= $l1; $j++) {
+ $v1 = BN::CRC32::crc32(substr($string1, 0, $j));
+ $v1 = BN::CRC32::crc32(substr($string1, $j), $v1);
+ $i++;
+ print ($v1 == 1835534707 ? "ok $i\n" : "not ok $i\n");
+}
+
+$l=$l1+4;
+print "\n$l) Test the CRC of a file\n";
+$i++;
+open(TESTFILE,"testfile") ||
+ open(TESTFILE,"t/testfile") ||
+ open(TESTFILE," ../testfile") || die "No such file!\n";
+$v1 = BN::CRC32::crc32(*TESTFILE);
+close TESTFILE;
+print ($v1 == 1925609391 ? "ok $i\n" : "not ok $i\n");
--- /dev/null
+Do not alter this file!
+Changing this file will result in a failing test!
\ No newline at end of file
--- /dev/null
+# $Header$
+# basic C types
+int T_IV
+unsigned T_UV
+unsigned int T_UV
+long T_IV
+unsigned long T_UV
+short T_IV
+unsigned short T_UV
+char T_CHAR
+unsigned char T_U_CHAR
+char * T_PV
+unsigned char * T_PV
+caddr_t T_PV
+wchar_t * T_PV
+wchar_t T_IV
+bool_t T_IV
+size_t T_IV
+ssize_t T_IV
+time_t T_NV
+unsigned long * T_OPAQUEPTR
+char ** T_PACKED
+void * T_PTR
+Time_t * T_PV
+SV * T_SV
+SVREF T_SVREF
+AV * T_AVREF
+HV * T_HVREF
+CV * T_CVREF
+
+IV T_IV
+I32 T_IV
+I16 T_IV
+I8 T_IV
+U32 T_U_LONG
+U16 T_U_SHORT
+U8 T_UV
+Result T_U_CHAR
+Boolean T_IV
+double T_DOUBLE
+SysRet T_SYSRET
+SysRetLong T_SYSRET
+FILE * T_IN
+FileHandle T_PTROBJ
+InputStream T_IN
+InOutStream T_INOUT
+OutputStream T_OUT
+bool T_BOOL
+
+#############################################################################
+INPUT
+T_SV
+ $var = $arg
+T_SVREF
+ if (sv_isa($arg, \"${ntype}\"))
+ $var = (SV*)SvRV($arg);
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_AVREF
+ if (sv_isa($arg, \"${ntype}\"))
+ $var = (AV*)SvRV($arg);
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_HVREF
+ if (sv_isa($arg, \"${ntype}\"))
+ $var = (HV*)SvRV($arg);
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_CVREF
+ if (sv_isa($arg, \"${ntype}\"))
+ $var = (CV*)SvRV($arg);
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_SYSRET
+ $var NOT IMPLEMENTED
+T_UV
+ $var = ($type)SvUV($arg)
+T_IV
+ $var = ($type)SvIV($arg)
+T_INT
+ $var = (int)SvIV($arg)
+T_ENUM
+ $var = ($type)SvIV($arg)
+T_BOOL
+ $var = (int)SvIV($arg)
+T_U_INT
+ $var = (unsigned int)SvUV($arg)
+T_SHORT
+ $var = (short)SvIV($arg)
+T_U_SHORT
+ $var = (unsigned short)SvUV($arg)
+T_LONG
+ $var = (long)SvIV($arg)
+T_U_LONG
+ $var = (unsigned long)SvUV($arg)
+T_CHAR
+ $var = (char)*SvPV($arg,PL_na)
+T_U_CHAR
+ $var = (unsigned char)SvUV($arg)
+T_FLOAT
+ $var = (float)SvNV($arg)
+T_NV
+ $var = ($type)SvNV($arg)
+T_DOUBLE
+ $var = (double)SvNV($arg)
+T_PV
+ $var = ($type)SvPV($arg,PL_na)
+T_PTR
+ $var = ($type)SvIV($arg)
+T_PTRREF
+ if (SvROK($arg)) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = ($type) tmp;
+ }
+ else
+ croak(\"$var is not a reference\")
+T_REF_IV_REF
+ if (sv_isa($arg, \"${type}\")) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = *($type *) tmp;
+ }
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_REF_IV_PTR
+ if (sv_isa($arg, \"${type}\")) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = ($type) tmp;
+ }
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_PTROBJ
+ if (sv_derived_from($arg, \"${ntype}\")) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = ($type) tmp;
+ }
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_PTRDESC
+ if (sv_isa($arg, \"${ntype}\")) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ ${type}_desc = (\U${type}_DESC\E*) tmp;
+ $var = ${type}_desc->ptr;
+ }
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_REFREF
+ if (SvROK($arg)) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = *($type) tmp;
+ }
+ else
+ croak(\"$var is not a reference\")
+T_REFOBJ
+ if (sv_isa($arg, \"${ntype}\")) {
+ IV tmp = SvIV((SV*)SvRV($arg));
+ $var = *($type) tmp;
+ }
+ else
+ croak(\"$var is not of type ${ntype}\")
+T_OPAQUE
+ $var NOT IMPLEMENTED
+T_OPAQUEPTR
+ $var = ($type)SvPV($arg,PL_na)
+T_PACKED
+ $var = XS_unpack_$ntype($arg)
+T_PACKEDARRAY
+ $var = XS_unpack_$ntype($arg)
+T_CALLBACK
+ $var = make_perl_cb_$type($arg)
+T_ARRAY
+ $var = $ntype(items -= $argoff);
+ U32 ix_$var = $argoff;
+ while (items--) {
+ DO_ARRAY_ELEM;
+ }
+T_IN
+ $var = IoIFP(sv_2io($arg))
+T_INOUT
+ $var = IoIFP(sv_2io($arg))
+T_OUT
+ $var = IoOFP(sv_2io($arg))
+#############################################################################
+OUTPUT
+T_SV
+ $arg = $var;
+T_SVREF
+ $arg = newRV((SV*)$var);
+T_AVREF
+ $arg = newRV((SV*)$var);
+T_HVREF
+ $arg = newRV((SV*)$var);
+T_CVREF
+ $arg = newRV((SV*)$var);
+T_IV
+ sv_setiv($arg, (IV)$var);
+T_UV
+ sv_setuv($arg, (UV)$var);
+T_INT
+ sv_setiv($arg, (IV)$var);
+T_SYSRET
+ if ($var != -1) {
+ if ($var == 0)
+ sv_setpvn($arg, "0 but true", 10);
+ else
+ sv_setiv($arg, (IV)$var);
+ }
+T_ENUM
+ sv_setiv($arg, (IV)$var);
+T_BOOL
+ $arg = boolSV($var);
+T_U_INT
+ sv_setuv($arg, (UV)$var);
+T_SHORT
+ sv_setiv($arg, (IV)$var);
+T_U_SHORT
+ sv_setuv($arg, (UV)$var);
+T_LONG
+ sv_setiv($arg, (IV)$var);
+T_U_LONG
+ sv_setuv($arg, (UV)$var);
+T_CHAR
+ sv_setpvn($arg, (char *)&$var, 1);
+T_U_CHAR
+ sv_setuv($arg, (UV)$var);
+T_FLOAT
+ sv_setnv($arg, (double)$var);
+T_NV
+ sv_setnv($arg, (double)$var);
+T_DOUBLE
+ sv_setnv($arg, (double)$var);
+T_PV
+ sv_setpv((SV*)$arg, $var);
+T_PTR
+ sv_setiv($arg, (IV)$var);
+T_PTRREF
+ sv_setref_pv($arg, Nullch, (void*)$var);
+T_REF_IV_REF
+ sv_setref_pv($arg, \"${ntype}\", (void*)new $ntype($var));
+T_REF_IV_PTR
+ sv_setref_pv($arg, \"${ntype}\", (void*)$var);
+T_PTROBJ
+ sv_setref_pv($arg, \"${ntype}\", (void*)$var);
+T_PTRDESC
+ sv_setref_pv($arg, \"${ntype}\", (void*)new\U${type}_DESC\E($var));
+T_REFREF
+ sv_setrefref($arg, \"${ntype}\", XS_service_$ntype,
+ ($var ? (void*)new $ntype($var) : 0));
+T_REFOBJ
+ NOT IMPLEMENTED
+T_OPAQUE
+ sv_setpvn($arg, (char *)&$var, sizeof($var));
+T_OPAQUEPTR
+ sv_setpvn($arg, (char *)$var, sizeof(*$var)), XFree((char *)$var);
+T_PACKED
+ XS_pack_$ntype($arg, $var);
+T_PACKEDARRAY
+ XS_pack_$ntype($arg, $var, count_$ntype);
+T_DATAUNIT
+ sv_setpvn($arg, $var.chp(), $var.size());
+T_CALLBACK
+ sv_setpvn($arg, $var.context.value().chp(),
+ $var.context.value().size());
+T_ARRAY
+ ST_EXTEND($var.size);
+ for (U32 ix_$var = 0; ix_$var < $var.size; ix_$var++) {
+ ST(ix_$var) = sv_newmortal();
+ DO_ARRAY_ELEM
+ }
+ SP += $var.size - 1;
+T_IN
+ {
+ GV *gv = newGVgen("$Package");
+ if ( do_open(gv, "<&", 2, FALSE, 0, 0, $var) )
+ sv_setsv($arg, sv_bless(newRV((SV*)gv), gv_stashpv("$Package",1)));
+ else
+ $arg = &PL_sv_undef;
+ }
+T_INOUT
+ {
+ GV *gv = newGVgen("$Package");
+ if ( do_open(gv, "+<&", 3, FALSE, 0, 0, $var) )
+ sv_setsv($arg, sv_bless(newRV((SV*)gv), gv_stashpv("$Package",1)));
+ else
+ $arg = &PL_sv_undef;
+ }
+T_OUT
+ {
+ GV *gv = newGVgen("$Package");
+ if ( do_open(gv, "+>&", 3, FALSE, 0, 0, $var) )
+ sv_setsv($arg, sv_bless(newRV((SV*)gv), gv_stashpv("$Package",1)));
+ else
+ $arg = &PL_sv_undef;
+ }
+
+# SJP
+
+TYPEMAP
+pdl* T_PDL
+pdl * T_PDL
+Logical T_IV
+float T_NV
+
+INPUT
+
+T_PDL
+ $var = PDL->SvPDLV($arg)
+
+
+OUTPUT
+
+T_PDL
+ PDL->SetSV_PDL($arg,$var);
--- /dev/null
+./start.pl
+
+trbcmd w 0xc001 0xc0 0xaaa1aaa0
+trbcmd w 0xc001 0xc1 0xaaa3aaa2
+trbcmd w 0xc002 0xc0 0xaaa5aaa4
+trbcmd w 0xc002 0xc1 0xaaa7aaa6
+trbcmd w 0xfee1 0xc0 0xaaa9aaa8
+trbcmd w 0xfee1 0xc1 0xaaaaaaab
+trbcmd w 0xf013 0xc0 0x1
+
--- /dev/null
+[board01]
+chainsini=chains.ini
+FPGAboard_hostname=trb1577
+FPGAboard_staplfilename=jcb_trb_009.stapl
+FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
+FPGAboard_addonortrb=trb
+FPGAtrbnetAddr=0xf013
+CONFperiod_trbnetAddr=0xc001
+CONFoffspillcounter_trbnetAddr=0xc002
+CONFwaitstart_trbnetAddr=0xc007
+CONFtriginitseq_trbnetAddr=0xc003
+CONFtrigmapsstart_trbnetAddr=0xc00b
+CONFtrigmapsreset_trbnetAddr=0xc00a
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+;gui_defaults is a comma-separated list of the following strings representing buttons in the gui:
+;'h_prog_fpga','h_start_trbnetd','h_period_0_15s','h_period_1s','h_period_10s', 'h_no_period'
+;be aware that h_prog_fpga doesn't wait until the optical link is up on the Trb
+gui_defaults=h_period_0_15s
+guiBM_NP_defaults=h_waitbeforestart_6us
+
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+;WARNING this file is generated automatically. don't edit manually.
+
+[chain1]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xb000
+CMDreg_trbnetAddr=0xb120
+RAMbase_trbnetAddr=0xb121
+DATAreg_trbnetAddr=0xb122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163
+STATUS2RAM3BtrbnetAddr=0xb170
+CONFsignals_trbnetAddr=0xc006
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=0
+DEBUGram1baddr=0xb147
+DEBUGram1bdata=0xb148
+DEBUGram1caddr=0xb149
+DEBUGram1cdata=0xb14a
+DEBUGram1crun=0xb14b
+;CONFperiod_trbnetAddr=0xc001
+;CONFoffspillcounter_trbnetAddr=0xc002
+;CONFwaitstart_trbnetAddr=0xc007
+FPGAboard_hostname=trb126
+;FPGAboard_staplfilename=jcb_trb_007.stapl
+FPGAboard_staplfilename=jcb_trb_009.stapl
+FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
+FPGAboard_addonortrb=trb
+; gui_defaults1/gui_defaults2 is a comma separated list of the following strings representing buttons in the gui:
+;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz',
+;'h_start', 'h_stop', 'h_set_inout', 'h_maps_reset_on', 'h_maps_reset_off', 'h_maps_start_on', 'h_maps_start_off',
+;'h_maps_clk_on', 'h_maps_clk_off'
+; gui_defaults1: executed in this order, before board defaults
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain1
+JNR0_sensor4=sensor4.ini
+JNR1_sensor3=sensor3.ini
+JNR2_sensor2=sensor2.ini
+JNR3_sensor1=sensor1.ini
+;END GENERATE_CHAINORDER chain1
+
+[chain2]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xd000
+CMDreg_trbnetAddr=0xd120
+RAMbase_trbnetAddr=0xd121
+DATAreg_trbnetAddr=0xd122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xd163
+STATUS2RAM3BtrbnetAddr=0xd170
+CONFsignals_trbnetAddr=0xc008
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=1
+DEBUGram1baddr=0xd147
+DEBUGram1bdata=0xd148
+DEBUGram1caddr=0xd149
+DEBUGram1cdata=0xd14a
+DEBUGram1crun=0xd14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain2
+JNR0_sensor8=sensor8.ini
+JNR1_sensor7=sensor7.ini
+JNR2_sensor6=sensor6.ini
+JNR3_sensor5=sensor5.ini
+;END GENERATE_CHAINORDER chain2
+
+[chain3]
+FPGAtrbnetAddr=0xf013
+RAMtrbnetAddr=0xe000
+CMDreg_trbnetAddr=0xe120
+RAMbase_trbnetAddr=0xe121
+DATAreg_trbnetAddr=0xe122
+STATUS2RAM3BBASEADDRREGtrbnetAddr=0xe163
+STATUS2RAM3BtrbnetAddr=0xe170
+CONFsignals_trbnetAddr=0xc009
+CONFresetafterfirstwrite_trbnetAddr=0xc011
+CONFresetbeforeinit_trbnetAddr=0xc010
+CONFtrigmapsstart_trbnetAddr=0xc00e
+CONFtrigmapsreset_trbnetAddr=0xc00d
+CONFtrigrunjtag_trbnetAddr=0xc00f
+CONFtrigwriteonce_trbnetAddr=0xc014
+CONFtriginitseq_trbnetAddr=0xc00c
+chainnr=2
+DEBUGram1baddr=0xe147
+DEBUGram1bdata=0xe148
+DEBUGram1caddr=0xe149
+DEBUGram1cdata=0xe14a
+DEBUGram1crun=0xe14b
+;CONFperiod_trbnetAddr=0xc001
+gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on
+; gui_defaults2: executed in this order, after board defaults
+gui_defaults2=h_start
+guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on
+guiBM_NP_defaults2=""
+
+
+;BEGIN GENERATE_CHAINORDER chain3
+JNR0_sensor12=sensor12.ini
+JNR1_sensor10=sensor10.ini
+JNR2_sensor9=sensor9.ini
+;END GENERATE_CHAINORDER chain3
--- /dev/null
+/tmp/jtag_initmem/20121123184503
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064C1CB8BAB32648020280A0A0A0A64
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064C8CCB9D632648020280A0A0A0A64
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064AE82BCF732648020280A0A0A0A64
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=1F,1,00000000
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+use Getopt::Long;
+use Sys::Syslog;
+
+$ENV{DAQOPSERVER}='trb124';
+
+my $opt_help;
+my $opt_chain;
+my $opt_board;
+my $opt_operation;
+my $opt_addr;
+my $opt_quiet;
+my %chain_defaults = (); #('h_stop', 'h_delay0', 'h_prog_ram', 'h_set_timing_10mhz',,'h_set_inout');
+my %board_defaults = (); #('h_period_0_15s');
+my %chain_defaults2 = (); #('h_start');
+openlog("atomic,ui.pl", "perror", "local1");
+
+GetOptions ('h|help' => \$opt_help,
+ 'b|board=s' => \$opt_board,
+ 'c|chain=s' => \$opt_chain,
+ 'o|operation=s' => \$opt_operation,
+ 'a|addr=s' => \$opt_addr,
+ 'q|quiet' => \$opt_quiet
+ );
+if($opt_help or not defined $opt_board) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ syslog("debug", "showing usage information.");
+ print "Usage: ui.pl [-c <chain name> ] [-o <Operation>] [-a <address>]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+ [-b|--board <JTAG board name>] : Select the JTAG/MAIN board for setting signals. (use board01)
+ [-o|--operation <handle name from gui.pl without h_>] : Select operation (on the selected JTAG chain).
+ [-a|--addr <address for operation>] : read_ram1b_word needs address
+ [-q|--quiet ] : suppress informative output
+
+board operations (no chain parameter given):
+ prog_fpga : program FPGA on trb
+ start_trbnetd: start trbnet daemon on trb
+ waitbeforestart_6us: set wait before start time to 6 us
+ waitbeforestart_1ms: set wait before start time to 1 ms
+ waitbeforestart_1s: set wait before start time to 1 s
+ trigger_init_sequence: trigger initialization sequence for all chains,
+ 3xWRITE+1xREAD DEV ID, reset as configured
+ maps_reset: generate RESET pulse, all chains
+ run_jtag: Run 3xWRITE Registers+ 1xRead DEV ID, no reset, all chains
+ write_once: Once write all registers all chains
+ maps_start: generate START pulse, all chains
+
+chain operations (with -c parameter)
+ man_maps_reset: software generated reset pulse
+ delay0: set delay 0 JTAG Clock cycles
+ delay1: set delay 1 JTAG Clock cycles
+ delay2: set delay 2 JTAG Clock cycles
+ delay3: set delay 3 JTAG Clock cycles
+ prog_ram: Write from sensor*.ini to RAM with JTAG registers on FPGA
+ set_timing_10mhz: Set 10 MHz TCK
+ set_timing_1mhz: Set 1 MHz TCK
+ set_timing_100khz: Set 100 kHz TCK
+ set_inout: Initialize I/O pin settings (signals_invert)
+ maps_reset_before_on: set reset before first WRITE on trig_init_seq/trigger_init_sequence
+ maps_reset_before_off: set reset before ... off
+ maps_reset_after_on: set reset after ... on
+ maps_reset_after_off: set reset after ... off
+ maps_clk_on: activate MAPS CLK (80MHz) immediately
+ maps_clk_off: deactivate MAPS CLK (80MHz) immediately
+ trig_init_seq: trigger initialization sequence
+ maps_reset: generate RESET pulse
+ run_jtag: run JTAG (see board operation) this chain
+ write_once: write once all registers
+ maps_start: generate START pulse
+ read_ram1b_word: read 32 bit word at address given with -a option from ram1b CONNECTION REMOVED
+ read_ram1c_word: read 32 bit word at address given with -a option from ram1c
+ copy_ram1b1c: trigger copy of ram1b to ram1c
+
+
+";
+
+
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub report {
+ if(defined($opt_quiet)){
+ if($_[0] eq 'data') { print $_[1]; }
+ }
+ else {
+ print $_[1];
+ }
+}
+sub reportd {
+ if(!defined($opt_quiet)){
+ print "debug:" . $_[0];
+ }
+}
+sub init_msg {
+ if(!defined($opt_quiet)){
+ print $_[0];
+ }
+}
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ if(not open ( SHELL , "$command 2>&1 |" )) {
+ report( 'report_general' , "failed to execute command.");
+ syslog("ERR", "command failed.");
+ }
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ syslog("ERR", "unexpected output: $output.");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {
+ report('report_general', "command failed. output: $result");
+ syslog('ERR', "command failed. output: $result.");
+ }
+ return $result;
+}
+
+
+sub generate_h_read_ram1b_word {
+ my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1baddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1bdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+sub generate_h_read_ram1c_word {
+ my ($chain, $fpga_addr, $debug_ram1caddr, $debug_ram1cdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1caddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1cdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+
+
+sub generate_h_copy_ram1b1c {
+ my ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x00000008", ""); # unconditional trigger
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000064", ""); # M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER
+ }
+}
+
+
+sub generate_h_man_maps_reset {
+ my ($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "manual reset chain " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $resetnormal = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal));
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ }
+}
+
+sub generate_h_maps_start_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "generate MAPS start $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<9)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<9)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_maps_reset_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("MAPS reset signal $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<11)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<11)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ }
+}
+sub generate_h_maps_clk_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("generate MAPS clk $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<13)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<13)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_prog_ram {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_;
+ my @memfilenames = @{$memfilenames_ref};
+ return sub {
+ init_msg("program RAM $chain.");
+ my $numchips_hex = int_to_32bit_hex($numsensors);
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", ""); # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ reportd "set RAM base pointer: \n";
+ execute_shell_command("trbcmd w $fpga_addr $ram_base_addr 0x$ihex", "");
+ # write to configuration RAM
+ reportd "write max. 256 32-bit-words: \n";
+ execute_shell_command("trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]", "");
+ }
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000009", ""); # CMD_START
+ }
+}
+
+sub generate_h_set_timing_10mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 10 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ #reportd $cmdline;
+ #system($cmdline);
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_1mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 1 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_100khz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 100 kHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+
+
+sub generate_h_delay {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
+ return sub {
+ init_msg("Delay $delay $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_waitbeforestart_6us {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 6us.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+sub generate_h_waitbeforestart_1ms {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1ms.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_waitbeforestart_1s {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1s.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_maps_reset {
+ my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
+ return sub {
+ init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ }
+}
+
+
+sub generate_h_trig {
+ my ($board, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr " . $board);
+ # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ }
+}
+sub generate_h_chain_trig {
+ my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
+ # set bit in trigger register correspondig to chain-# $chainnr
+ my $newval;
+ $newval = int_to_32bit_hex(((1<<$chainnr)));
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ }
+}
+
+
+
+sub generate_h_trigger_init_sequence {
+ my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_;
+ return sub {
+ init_msg("Send Trigger $board.");
+ if(!defined($conf_fet_trigger_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # generate trigger
+ execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet
+ }
+}
+
+
+sub generate_h_set_inout {
+ my($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("Set IN/OUT $chain.");
+ if(!defined($conf_signals_addr)){
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ }
+}
+
+sub generate_h_prog_fpga {
+ my($board, $trbhostname, $addonortrb, $staplfilename) = @_;
+ return sub {
+ init_msg("Prog FPGA $board.");
+ if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){
+ report('report_general', "Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"",
+ "------------- Connection accepted -------------
+> return value of command: 0
+> stdout:
+Successful File Execution.
+------------- END OF OUTPUT ------------
+");
+ }
+}
+sub generate_h_prog_ram_external {
+ my ($chain) = @_;
+ return sub {
+ my $output = execute_shell_command_return("./ui_writeram.pl -c $chain");
+ #reportd $output;
+ }
+}
+
+
+sub generate_h_start_trbnetd {
+ my($board, $trbhostname) = @_;
+ return sub {
+ init_msg("Start trbnetd $board.");
+ if(!defined($trbhostname)){
+ report('report_general',"Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted -------------
+> return value of command: 0
+------------- END OF OUTPUT ------------
+");
+ }
+}
+
+# sub generate_h_set_standard {
+# my %boards_handlers = %{$_[0]};
+# my %chains_handlers = %{$_[1]};
+# return sub {
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# foreach my $board (reverse sort keys %boards_handlers) {
+# my %board_handlers = %{$boards_handlers{$board}};
+# foreach my $handler_name (@{$board_defaults{$board}}) {
+# &{$board_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# }
+# }
+
+my $boardsfile= 'boards.ini';
+my $boardsSettings = new Config::Abstract::Ini($boardsfile);
+my %allboards = $boardsSettings->get_all_settings;
+foreach my $board (keys %allboards) {
+ my %settings=%{$allboards{$board}};
+ my $chainsini = $settings{'chainsini'};
+ my $trbhostname = $settings{'FPGAboard_hostname'};
+ my $addonortrb = $settings{'FPGAboard_addonortrb'};
+ my $staplfilename = $settings{'FPGAboard_staplfilename'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $conf_period_addr = $settings{'CONFperiod_trbnetAddr'};
+ my $conf_offspillcounter_addr = $settings{'CONFoffspillcounter_trbnetAddr'};
+ my $conf_waitstart_addr = $settings{'CONFwaitstart_trbnetAddr'};
+ my $conf_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+
+ if(defined($opt_board) and not defined($opt_chain)) {
+ # assume board command
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_prog_fpga') {
+ $subr = generate_h_prog_fpga($board, $trbhostname, $addonortrb, $staplfilename)
+ }
+ elsif(("h_".$opt_operation) eq 'h_start_trbnetd'){
+ $subr = generate_h_start_trbnetd($board, $trbhostname);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_6us' ) {
+ $subr = generate_h_waitbeforestart_6us($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1ms' ) {
+ $subr = generate_h_waitbeforestart_1ms($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1s' ) {
+ $subr = generate_h_waitbeforestart_1s($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trigger_init_sequence' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsstart_addr);
+ }
+ if(!defined($opt_quiet)){ print "Starting Board Operation.\n"; }
+ &{$subr}();
+ exit(0);
+ }
+
+
+ my $chainsSettings = new Config::Abstract::Ini($chainsini);
+ my %allchains = $chainsSettings->get_all_settings;
+ if(!defined($allchains{$opt_chain})) { die ("Chain $opt_chain not found.");}
+# foreach my $chain (reverse sort keys %allchains) {
+ my $chain = $opt_chain;
+ my %chain_settings=%{$allchains{$chain}};
+ my $chain_fpga_addr = $chain_settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $chain_settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $chain_settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $chain_settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $chain_settings{'DATAreg_trbnetAddr'};
+ my $conf_signals_addr = $chain_settings{'CONFsignals_trbnetAddr'};
+ my $conf_resetafterfirstwrite_addr = $chain_settings{'CONFresetafterfirstwrite_trbnetAddr'};
+ my $conf_resetbeforeinit_addr = $chain_settings{'CONFresetbeforeinit_trbnetAddr'};
+ my $conf_chain_triginitseq_addr = $chain_settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_chain_trigmapsreset_addr = $chain_settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_chain_trigrunjtag_addr = $chain_settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_chain_trigwriteonce_addr = $chain_settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_chain_trigmapsstart_addr = $chain_settings{'CONFtrigmapsstart_trbnetAddr'};
+ my $debug_chain_ram1baddr_addr = $chain_settings{'DEBUGram1baddr'};
+ my $debug_chain_ram1bdata_addr = $chain_settings{'DEBUGram1bdata'};
+ my $debug_chain_ram1caddr_addr = $chain_settings{'DEBUGram1caddr'};
+ my $debug_chain_ram1cdata_addr = $chain_settings{'DEBUGram1cdata'};
+ my $chainnr = $chain_settings{'chainnr'};
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_man_maps_reset') {
+ $subr = generate_h_man_maps_reset($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay0' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 0);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay1' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 1);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay2' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 2);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay3' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 3);
+ }
+ elsif(("h_".$opt_operation) eq 'h_prog_ram' ) {
+ $subr = generate_h_prog_ram_external($chain);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_10mhz' ) {
+ $subr = generate_h_set_timing_10mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_1mhz' ) {
+ $subr = generate_h_set_timing_1mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_100khz' ) {
+ $subr = generate_h_set_timing_100khz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_inout' ) {
+ $subr = generate_h_set_inout($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_on' ) {
+ $subr = generate_h_maps_clk_signal(1,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_off' ) {
+ $subr = generate_h_maps_clk_signal(0,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trig_init_seq' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1b_word' ) {
+ $subr = generate_h_read_ram1b_word($chain, $chain_fpga_addr, $debug_chain_ram1baddr_addr, $debug_chain_ram1bdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1c_word' ) {
+ $subr = generate_h_read_ram1c_word($chain, $chain_fpga_addr, $debug_chain_ram1caddr_addr, $debug_chain_ram1cdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_copy_ram1b1c' ) {
+ $subr = generate_h_copy_ram1b1c($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr);
+ }
+
+ if(!defined($opt_quiet)){ print "Starting Chain Operation.\n"; }
+ &{$subr}();
+
+}
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+use Getopt::Long;
+
+my $opt_help;
+my $opt_chain;
+my $opt_board;
+my $opt_operation;
+my $opt_addr;
+my $opt_quiet;
+GetOptions ('h|help' => \$opt_help,
+ 'b|board=s' => \$opt_board,
+ 'c|chain=s' => \$opt_chain,
+ 'o|operation=s' => \$opt_operation,
+ 'a|addr=s' => \$opt_addr,
+ 'q|quiet' => \$opt_quiet
+ );
+if($opt_help) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ print "Usage: ui.pl [-c <chain name> ] [-o <Operation>] [-a <address>]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+ [-b|--board <JTAG board name>] : Select the JTAG/MAIN board for setting signals.
+ [-o|--operation <handle name from gui.pl without h_>] : Select operation (on the selected JTAG chain).
+ [-a|--addr <address for operation>] : read_ram1b_word needs address
+ [-q|--quiet ] : suppress informative output
+
+"
+}
+
+#print "operation:".$opt_operation."\n";
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub report {
+ if(defined($opt_quiet)){
+ if($_[0] eq 'data') { print $_[1]; }
+ }
+ else {
+ print $_[1];
+ }
+}
+sub reportd {
+ if(!defined($opt_quiet)){
+ print "debug:" . $_[0];
+ }
+}
+sub init_msg {
+ if(!defined($opt_quiet)){
+ print $_[0];
+ }
+}
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ open ( SHELL , "$command 2>&1 |" ) || report( 'report_general' , "failed to execute command.");
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {report('report_general', "command failed. output: $result");}
+ return $result;
+}
+
+
+sub generate_h_read_ram1b_word {
+ my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1baddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1bdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+sub generate_h_read_ram1c_word {
+ my ($chain, $fpga_addr, $debug_ram1caddr, $debug_ram1cdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1caddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1cdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+
+
+sub generate_h_copy_ram1b1c {
+ my ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x00000008", ""); # unconditional trigger
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000064", ""); # M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER
+ }
+}
+
+
+sub generate_h_man_maps_reset {
+ my ($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "manual reset chain " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $resetnormal = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal));
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ }
+}
+
+sub generate_h_maps_start_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "generate MAPS start $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<9)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<9)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_maps_reset_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("MAPS reset signal $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<11)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<11)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ }
+}
+sub generate_h_maps_clk_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("generate MAPS clk $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<13)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<13)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_prog_ram {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_;
+ my @memfilenames = @{$memfilenames_ref};
+ return sub {
+ init_msg("program RAM $chain.");
+ my $numchips_hex = int_to_32bit_hex($numsensors);
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", ""); # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ reportd "set RAM base pointer: \n";
+ execute_shell_command("trbcmd w $fpga_addr $ram_base_addr 0x$ihex", "");
+ # write to configuration RAM
+ reportd "write max. 256 32-bit-words: \n";
+ execute_shell_command("trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]", "");
+ }
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000009", ""); # CMD_START
+ }
+}
+
+sub generate_h_set_timing_10mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 10 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ #reportd $cmdline;
+ #system($cmdline);
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_1mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 1 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_100khz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 100 kHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+
+
+sub generate_h_delay {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
+ return sub {
+ init_msg("Delay $delay $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_waitbeforestart_6us {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 6us.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+sub generate_h_waitbeforestart_1ms {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1ms.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_waitbeforestart_1s {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1s.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_maps_reset {
+ my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
+ return sub {
+ init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ }
+}
+
+
+sub generate_h_trig {
+ my ($board, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr " . $board);
+ # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ }
+}
+sub generate_h_chain_trig {
+ my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
+ # set bit in trigger register correspondig to chain-# $chainnr
+ my $newval;
+ $newval = int_to_32bit_hex(((1<<$chainnr)));
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ }
+}
+
+
+
+sub generate_h_trigger_init_sequence {
+ my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_;
+ return sub {
+ init_msg("Send Trigger $board.");
+ if(!defined($conf_fet_trigger_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # generate trigger
+ execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet
+ }
+}
+
+
+sub generate_h_set_inout {
+ my($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("Set IN/OUT $chain.");
+ if(!defined($conf_signals_addr)){
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ }
+}
+
+sub generate_h_prog_fpga {
+ my($board, $trbhostname, $addonortrb, $staplfilename) = @_;
+ return sub {
+ init_msg("Prog FPGA $board.");
+ if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){
+ report('report_general', "Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"",
+ "------------- Connection accepted -------------
+> return value of command: 0
+> stdout:
+Successful File Execution.
+------------- END OF OUTPUT ------------
+");
+ }
+}
+sub generate_h_prog_ram_external {
+ my ($chain) = @_;
+ return sub {
+ my $output = execute_shell_command_return("./ui_writeram.pl -c $chain");
+ reportd $output;
+ }
+}
+
+
+sub generate_h_start_trbnetd {
+ my($board, $trbhostname) = @_;
+ return sub {
+ init_msg("Start trbnetd $board.");
+ if(!defined($trbhostname)){
+ report('report_general',"Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted -------------
+> return value of command: 0
+------------- END OF OUTPUT ------------
+");
+ }
+}
+
+# sub generate_h_set_standard {
+# my %boards_handlers = %{$_[0]};
+# my %chains_handlers = %{$_[1]};
+# return sub {
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# foreach my $board (reverse sort keys %boards_handlers) {
+# my %board_handlers = %{$boards_handlers{$board}};
+# foreach my $handler_name (@{$board_defaults{$board}}) {
+# &{$board_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# }
+# }
+
+my $boardsfile= 'boards.ini';
+my $boardsSettings = new Config::Abstract::Ini($boardsfile);
+my %allboards = $boardsSettings->get_all_settings;
+foreach my $board (keys %allboards) {
+ my %settings=%{$allboards{$board}};
+ my $chainsini = $settings{'chainsini'};
+ my $trbhostname = $settings{'FPGAboard_hostname'};
+ my $addonortrb = $settings{'FPGAboard_addonortrb'};
+ my $staplfilename = $settings{'FPGAboard_staplfilename'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $conf_period_addr = $settings{'CONFperiod_trbnetAddr'};
+ my $conf_offspillcounter_addr = $settings{'CONFoffspillcounter_trbnetAddr'};
+ my $conf_waitstart_addr = $settings{'CONFwaitstart_trbnetAddr'};
+ my $conf_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+ if(defined($opt_board) and not defined($opt_chain)) {
+ # assume board command
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_prog_fpga') {
+ $subr = generate_h_prog_fpga($board, $trbhostname, $addonortrb, $staplfilename)
+ }
+ elsif(("h_".$opt_operation) eq 'h_start_trbnetd'){
+ $subr = generate_h_start_trbnetd($board, $trbhostname);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_6us' ) {
+ $subr = generate_h_waitbeforestart_6us($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1ms' ) {
+ $subr = generate_h_waitbeforestart_1ms($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1s' ) {
+ $subr = generate_h_waitbeforestart_1s($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trigger_init_sequence' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsstart_addr);
+ }
+ if(!defined($opt_quiet)){ print "Starting Board Operation.\n"; }
+ &{$subr}();
+ exit(0);
+ }
+
+
+ my $chainsSettings = new Config::Abstract::Ini($chainsini);
+ my %allchains = $chainsSettings->get_all_settings;
+ if(!defined($allchains{$opt_chain})) { die ("Chain $opt_chain not found.");}
+# foreach my $chain (reverse sort keys %allchains) {
+ my $chain = $opt_chain;
+ my %chain_settings=%{$allchains{$chain}};
+ my $chain_fpga_addr = $chain_settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $chain_settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $chain_settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $chain_settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $chain_settings{'DATAreg_trbnetAddr'};
+ my $conf_signals_addr = $chain_settings{'CONFsignals_trbnetAddr'};
+ my $conf_resetafterfirstwrite_addr = $chain_settings{'CONFresetafterfirstwrite_trbnetAddr'};
+ my $conf_resetbeforeinit_addr = $chain_settings{'CONFresetbeforeinit_trbnetAddr'};
+ my $conf_chain_triginitseq_addr = $chain_settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_chain_trigmapsreset_addr = $chain_settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_chain_trigrunjtag_addr = $chain_settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_chain_trigwriteonce_addr = $chain_settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_chain_trigmapsstart_addr = $chain_settings{'CONFtrigmapsstart_trbnetAddr'};
+ my $debug_chain_ram1baddr_addr = $chain_settings{'DEBUGram1baddr'};
+ my $debug_chain_ram1bdata_addr = $chain_settings{'DEBUGram1bdata'};
+ my $debug_chain_ram1caddr_addr = $chain_settings{'DEBUGram1caddr'};
+ my $debug_chain_ram1cdata_addr = $chain_settings{'DEBUGram1cdata'};
+ my $chainnr = $chain_settings{'chainnr'};
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_man_maps_reset') {
+ $subr = generate_h_man_maps_reset($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay0' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 0);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay1' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 1);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay2' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 2);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay3' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 3);
+ }
+ elsif(("h_".$opt_operation) eq 'h_prog_ram' ) {
+ $subr = generate_h_prog_ram_external($chain);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_10mhz' ) {
+ $subr = generate_h_set_timing_10mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_1mhz' ) {
+ $subr = generate_h_set_timing_1mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_100khz' ) {
+ $subr = generate_h_set_timing_100khz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_inout' ) {
+ $subr = generate_h_set_inout($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_on' ) {
+ $subr = generate_h_maps_clk_signal(1,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_off' ) {
+ $subr = generate_h_maps_clk_signal(0,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trig_init_seq' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1b_word' ) {
+ $subr = generate_h_read_ram1b_word($chain, $chain_fpga_addr, $debug_chain_ram1baddr_addr, $debug_chain_ram1bdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1c_word' ) {
+ $subr = generate_h_read_ram1c_word($chain, $chain_fpga_addr, $debug_chain_ram1caddr_addr, $debug_chain_ram1cdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_copy_ram1b1c' ) {
+ $subr = generate_h_copy_ram1b1c($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr);
+ }
+
+ if(!defined($opt_quiet)){ print "Starting Chain Operation.\n"; }
+ &{$subr}();
+
+}
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+use Getopt::Long;
+
+
+#push(@INC, "./BN");
+#use lib "$ENV{PWD}/BN";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+
+use lib "BN/blib/arch";
+use BN::CRC32;
+#use String::CRC32;
+
+#use feature "state";
+use POSIX;
+
+# whitespace trimming from http://www.somacon.com/p114.php
+# Declare the subroutines
+sub trim($);
+sub ltrim($);
+sub rtrim($);
+
+# Create a test string
+my $string = " \t Hello world! ";
+
+# Here is how to output the trimmed text "Hello world!"
+#print trim($string)."\n";
+#print ltrim($string)."\n";
+#print rtrim($string)."\n";
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+# Left trim function to remove leading whitespace
+sub ltrim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ return $string;
+}
+# Right trim function to remove trailing whitespace
+sub rtrim($)
+{
+ my $string = shift;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+sub reverse32bit($) {
+ my ($in) = @_;
+ my $result = unpack("L", pack("B*", scalar reverse unpack("B*", pack("L",$in))));
+ return $result;
+ #return 1;
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+my $num_words = 0;
+
+# this subroutine
+# changes parameter 0, which holds the file handle
+sub memfile_writeline($$$$) {
+ my($memfile, $memfilenames, $memfiles_prefix, $line_string)=@_;
+ my $filenum = floor($num_words/256);
+ my $last_filenum = floor(($num_words-1)/256);
+ my $filenum_str = sprintf "%0.2d", $filenum;
+ my $memfilename = $memfiles_prefix.'.'.$filenum_str.".txt";
+
+ if((!defined $_[0])) {
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ elsif($filenum!=$last_filenum) {
+ $memfile->close();
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ my $fh = $_[0];
+ print $fh $line_string;
+ $num_words++;
+}
+
+my $opt_help;
+my $opt_chain;
+GetOptions ('h|help' => \$opt_help,
+ 'c|chain=s' => \$opt_chain
+ );
+if($opt_help) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ print "Usage: ui_writeram.pl [-c <chain name> ]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+"
+}
+
+system("mkdir /tmp/jtag_initmem");
+
+
+my $chainsfile= 'chains.ini';
+my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+my %allchains = $chainsSettings->get_all_settings;
+
+my $date = strftime "%Y%m%d%H%M%S", localtime;
+#my $initmem_folder = "/tmp/jtag_initmem/$date";
+my $initmem_folder = "/tmp/jtag_initmem/jtag_atomic";
+
+if(-e $initmem_folder) {
+# die("Error: Folder with the same date already exists!");
+}
+else {
+ mkdir $initmem_folder,0755;
+}
+
+# File with prefix names files for last programmed values
+my $lastprogfilename = "/tmp/jtag_initmem/lastprog.txt";
+my $handle_lastprog = FileHandle->new($lastprogfilename, 'w');
+
+# loop through chains
+foreach my $chain (keys %allchains) {
+ if(defined($opt_chain) && not ($chain eq $opt_chain)) {
+ next;
+ }
+ print $chain, ": ";
+ #print join ' ', %{$allchains{$chain}}, "\n";
+ my %settings=%{$allchains{$chain}};
+ my @sensors;
+ my @drs;
+ my @drs_length;
+ my @old_drs;
+ my @old_drs_length;
+ my @irs;
+ my $irlen;
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $memfiles_prefix; # the same prefix is used for the files for one chain
+ # need one file per chip with at maximum 256 32 bit words
+ # that are written at once.
+ # then the RAM base pointer has to be changed for the next chip
+ my @memfilenames=();
+
+ $memfiles_prefix="$initmem_folder/$chain";
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ push(@sensors, $setting_name);
+ @old_drs = @drs;
+ @old_drs_length = @drs_length;
+ @irs = ();
+ @drs = ();
+ @drs_length = ();
+ my $sensorfile = $settings{$setting_name};
+ print "loading sensor file: $sensorfile\n";
+ my $sensorSettingsO = new Config::Abstract::Ini($sensorfile);
+ my %sensorSettings = $sensorSettingsO->get_all_settings;
+ my $this_irlen = $sensorSettingsO->get_entry_setting('General', 'IRLEN', '5');
+ my $bypassreg = $sensorSettingsO->get_entry_setting('General', 'BYPASSREG', '1F');
+ if (!defined $irlen ){
+ $irlen = $this_irlen;
+ }
+ elsif($this_irlen != $irlen) {
+ print "this_irlen=$this_irlen in $sensorfile differs from previously set irlen=$irlen.\nThis should be supported by this version (trb_maps_jtag3) of the JTAG controller.\n But is it really intended?\n";
+ }
+ #print "irlen: ", $this_irlen, "\n";
+ # loop through data registers
+ my %sensorData = $sensorSettingsO->get_entry('Data');
+ foreach my $data_register_ir (sort keys %sensorData) {
+ my $value = $sensorData{$data_register_ir};
+ my ($ir,$drlength,$dr)= split(/,/, $value); # dr is stored MSN first as hexadecimal string
+ $dr = uc(trim($dr));
+ if(length($dr)%8 != 0) {
+ die("Error: DR string is not multiple of 32 bit (4bytes = 8 nibbles)\n");
+ }
+ if($dr =~ /[^0-9A-F]+/) {
+ die("Error: Invalid hexadecimal string for DR given: \$dr=\"$dr\"\n");
+ }
+ #print "drlength: $drlength\n";
+ push(@drs_length, $drlength);
+ push(@drs, $dr);
+ push(@irs, $ir);
+ # only warning
+ if((defined $old_drs_length[@drs-1]) && ($drlength != $old_drs_length[@drs-1])) {
+ print ("Warning: Length of the same DR of two sensors differs.");
+ }
+ }
+ my $memfilename = $memfiles_prefix . "." . $setting_name . ".txt";
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfilename\" exists.");
+ }
+ print "Opening $memfilename...\n";
+ my $handle = FileHandle->new($memfilename, 'w');
+ push(@memfilenames, $memfilename);
+ # write numregs + IRlen
+ my $word = scalar($this_irlen)<<16;
+ $word = $word + scalar @irs;
+ ### $word = ($word<<16) + pack("L", scalar(@irs));
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# IRlen & numregs \n";
+ #####print $handle "0x" .uc (substr(reverse(join('',unpack("h8", pack("L", scalar($this_irlen))))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar(@irs))))),4,4)) . "\t# IRlen & numregs \n";
+
+ #print "reverse test: " . reverse32bit(0x00000001)."\n";
+ my $initial = 0x00000000;
+ my $crcword = pack("L", reverse32bit($word));
+ my $crc0 = crc32($crcword, $initial);
+ #my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write DEV_ID
+ $word = 0x4D323601;
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# DEV_ID \n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write pointer
+ my $offset = 3*@irs+4;
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $drlen = $drs_length[$reg_i];
+ $word = $offset;
+ #print $handle "0x". uc (substr(reverse(join('',unpack("h8", pack("L", 0)))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar($offset))))),4,4)) . "\t# Pointer + reserved\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# Pointer + reserved \n";
+ $word = $drlen;
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+
+ #print $handle "0x0000". uc (substr(reverse(join('',unpack("h8", pack("L", scalar($drlen))))),4,4)) . "\t# Length\n";
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8",pack("L", $word)))),0,8)) . "\t# Length\n";
+ $offset += floor(($drlen+31)/32);
+ }
+ # write CRC-32
+ #my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+ $crc0_rn = ~reverse32bit($crc0);
+ #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+ my $line_crc = sprintf "%0.8X", $crc0_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ my $crc1 = 0xFFFFFFFF;
+ # write IRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $ir = $irs[$reg_i];
+ #my @words = unpack("L", pack("H*", uc($ir)));
+ $word = unpack("L", pack("h*", (scalar reverse uc($ir)) ."000000"));
+ #print "ir=$ir.IR word: $word\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($ir))).uc($ir) . "\t# IR\n";
+ }
+ # write BYPASSREG IR
+ $word = unpack("L", pack("h*", (scalar reverse uc($bypassreg)) ."000000"));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($bypassreg))).uc($bypassreg) . "\t# IR BYPASS\n";
+
+ # write DRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $length = $drs_length[$reg_i];
+ my $numwords = floor(($length+31)/32);
+ for(my $i=0;$i<$numwords; $i++) {
+ #print "length: $length\n";
+ #print "numwords: $numwords\n";
+
+ $word = unpack("L", pack("h*", (scalar reverse uc(substr($drs[$reg_i],($numwords-$i-1)*8,8)))));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ my $linestr = "0x". substr($drs[$reg_i],($numwords-$i-1)*8,8) . "\t# DR" . $reg_i . "\n";
+ print $handle $linestr;
+ }
+ }
+ #write CRC-32
+ my $crc1_rn = ~reverse32bit($crc1);
+ $line_crc = sprintf "%0.8X", $crc1_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ }
+ }
+ my $numchips_hex = int_to_32bit_hex(scalar @sensors);
+ print "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A\n"; # CMD_STOP
+ my $result = `trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A\n`; # CMD_STOP
+ print "trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex\n"; # ADDR_CONTROL_DATA_REGISTER
+ $result = `trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex\n`; # ADDR_CONTROL_DATA_REGISTER
+ print "trbcmd w $fpga_addr $cmd_reg_addr 0x00000033\n"; # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ $result = `trbcmd w $fpga_addr $cmd_reg_addr 0x00000033\n`; # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ print "set RAM base pointer: \n";
+ print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
+ $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+ # write to configuration RAM
+ print "write max. 256 32-bit-words: \n";
+ print "trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]\n";
+ $result = `trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]`;
+ }
+ print "trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n"; # CMD_START
+ $result = `trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n`; # CMD_START
+ print "\n";
+}
+print $handle_lastprog $initmem_folder;
+# #print "data registers for FPGA $fpga_addr:", map { "$_ => $drs_binary{$_}\n" } keys %drs_binary;
+# $drs_offset{$irs[0]} = 4+(scalar @irs)*2;
+# for (my $i=1;$i<@irs;$i++) {
+# my $dr_length = $drs_length{$irs[$i-1]};
+# $drs_offset{$irs[$i]} = $drs_offset{$irs[$i-1]} + floor(($dr_length*(scalar @sensors)+31)/32) + 2; # add one x 32 bit for CRC, one x 32 bit for IR, integer division rounds down, right?
+# }
+# #open RAMTEXT, ">$memfiles_prefix{$chain}";
+# $num_words = 0;
+# my $ram_fh;
+# my @mem_filenames;
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc (reverse(join('',unpack("h8", pack("L", scalar(@sensors)))))) . "\t# numchips \n"); # numchips; the reverse is done here because apparently internally the unsigned long is stored LSByte first (little endian)
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", 0))))) . "\t# reserved\n"); # reserved
+# for (my $i=0;$i<@irs;$i++) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_offset{$irs[$i]}))))) . "\t# pointer\n"); # pointer
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_length{$irs[$i]}))))) . "\t# length \n"); # length
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# pointer (end of list)\n");
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# length (end of list)\n");
+# for (my $i=0;$i<@irs;$i++) {
+# my $ir=$irs[$i];
+# #print "ir: $ir\n";
+# my $ir_packed = pack("h*", (scalar reverse($ir)).("0"x (7-(length($ir)-1)%8)));
+# my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+# #print "debug ir_packed (h*): ". (scalar reverse($ir)).("0"x (8-length($ir)%32))."\n";
+# #print "debug ir_packed_r (B*): ". scalar reverse unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+# #print "debug2: " . (7-(length($ir)-1)%8) . "\n";
+# #print "debug3: " . $ir . "\n";
+# #print "debug4: " . $ir.("0"x (7-(length($ir)-1)%8)) . "\n";
+# #print "debug5 (B*): ". unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+#
+# my $initial = 0x00000000;
+# my $crc0 = crc32($ir_packed_r, $initial);
+# #printf "CRC0: %X. ~reversed: %X\n", $crc0, $crc0_rn;
+#
+# for(my $i=0; $i<floor((length($drs_binary{$ir})-1)/32)+1;$i++){
+# my $dr_word_packed_r = pack("b*", scalar reverse substr($drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)),($i)*32, 32));
+# $crc0 = crc32($dr_word_packed_r, $crc0);
+# my $crc0_rn = ~reverse32bit($crc0);
+# printf "CRC: 0x%0.8X.\n", $crc0_rn;
+# }
+# my $crc0_rn = ~reverse32bit($crc0);
+# #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+# my $line_crc = sprintf "0x%0.8X\t# CRC-32\n", $crc0_rn;
+# print "debug dr_binary: " . $drs_binary{$ir} . "\n";
+# my $dr_packed = pack("b*", $drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)));
+# $drs{$ir} = unpack('h*', $dr_packed);
+# print "debug drs: " . $drs{$ir} . "\n";
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(8-length($ir))).uc($ir) . "\n");
+# for(my $i=0; $i<floor((length( $drs{$ir}) -1)/8)+1; $i++){
+# #print "dbg: i=$i, len=".length( $drs{$ir})."\n";
+# if(length($drs{$ir}) >= ($i+1)*8) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(substr($drs{$ir}, ($i)*8, 8))) . "\n");
+# }
+# else {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(($i+1)*8-length($drs{$ir}))).uc(reverse(substr($drs{$ir}, ($i)*8, length($drs{$ir})%8))) . "\n");
+# }
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, $line_crc);
+#
+# #print "IR $ir, DR ". $drs{$ir} . "\n";
+# }
+# #close RAMTEXT;
+# $ram_fh->close();
+# #my $result = `cat $memfile{$fpga_addr}`;
+# $ENV{'DAQOPSERVER'}="trb126";
+# for(my $i=0;$i<scalar @mem_filenames;$i++) {
+# # write RAM base pointer
+# my $ihex = int_to_32bit_hex($i);
+# print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
+# my $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+# print "set RAM base pointer: " . $result;
+# # write to configuration RAM
+# print "trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]\n";
+# $result = `trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]`;
+# print "write max. 256 32-bit-words: " . $result;
+# }
+#}
+
+
+# init_writemem:
+# - loop through chains
+# - loop through sensors
+# - test if IR length is the same as for other sensors
+# - loop through DRs
+# - test if DR length is the same as for other sensors
+# - add DR content to chain data register (hexadecimal string)
+# - write contents for JTAG chain controller RAM to text file(s)
+# - execute trbcmd to transfer file(s) to RAM of FPGA configured in chains.ini
+#
+# get_status:
+# get_error_counts:
+# reactivate_sensor:
+# deactivate_sensor:
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use Getopt::Long;
+use POSIX; # for floor
+
+my %chains = ();
+my $namecol = 0; # column of chain name, column counting from zero
+my $chaincol = 1; # column of chain name, column counting from zero
+my $jnrcol = 2; # column of JNR for sorting, column counting from zero
+my $minnumcols = 4;
+
+# in future this could be chain dependent, so should be added to chains.ini
+my $MAX_NUMCHIPS_LD = 3;
+my $RAM_JTAG_REGISTERS_DEPTH = 11;
+
+my $opt_help;
+my $opt_chain;
+my $opt_register;
+my $chain_of_sensor;
+GetOptions ('h|help' => \$opt_help,
+ 'c|chain=s' => \$opt_chain,
+ 'r|register=s' => \$opt_register
+ );
+if($opt_help or not defined($opt_register)) {
+ &help();
+ exit(0);
+}
+
+
+sub help(){
+ print "Usage: write_reg [-c <chain name>] -r <register number>
+
+required:
+ -c|--chain <chain name> : Select only chain <chain name>
+ -r|--register <register number> : Select only Register <register number> and bypass register in
+ other sensors
+ number as string exactly as in sensor*.ini
+ 00 for BIAS_DAC
+"
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ #report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ #report( 'report_detailed' , $result);
+ #report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) { print "command failed. output: $result";}
+ return $result;
+}
+
+
+open(PROTOTYPEDBFILE,"/daq/toolbox/prototype_setup.db") || die("Cannot open file /daq/mvdmon/prototype_setup.db!");
+my @lines_db = <PROTOTYPEDBFILE>;
+close(PROTOTYPEDBFILE);
+my $keydesc = 0;
+foreach my $line (@lines_db) {
+ # skip commented out lines
+ if(substr($line, 0, 1) eq "#") {
+ next;
+ }
+ # if new section begins stop interpreting lines
+ if(substr($line, 0, 3) eq "key") {
+ $keydesc = 0;
+ }
+ if($keydesc == 1) {
+ my @entries = split(/\s+/, $line);
+ if((scalar @entries) < $minnumcols) {
+ if(!($line eq "\n")) {print "Warning: row with too little entries. skipping."};
+ next;
+ }
+ my $sensorname = $entries[$namecol];
+ my $chainname = $entries[$chaincol];
+ my $jnr = $entries[$jnrcol];
+ if(! defined ($chains{$chainname})) {
+ my %sensors = ();
+ $chains{$chainname} = \%sensors;
+ }
+ my %sensors = %{$chains{$chainname}};
+ # only add sensor to chain if JNR matches following regexp
+ if ($jnr =~ /[0-9]+/) {
+ my $jnrname;
+ $jnrname= "JNR".$jnr."_".$sensorname;
+ $sensors{$jnrname} = $sensorname . ".ini";
+ }
+ $chains{$chainname} = \%sensors;
+ }
+ # if desc section begins, start interpreting next line
+ if(substr($line, 0, 8) eq "key jtag") {
+ $keydesc = 1;
+ }
+}
+
+# for each of the possible three chains generate a section with name and sensor-file references in the correct order
+my @chain_names = sort keys (%chains);
+my $ir;
+my $drlength;
+my $dr;
+foreach my $chainname (@chain_names) {
+ if(defined($opt_chain) and not ($chainname eq $opt_chain)) {
+ next;
+ }
+ my %sensors = %{$chains{$chainname}};
+ my $sensornumber;
+ my $sensornumberloop= 0;
+ foreach my $sensorkey (sort keys %sensors) {
+ my $sensorfile=$sensors{$sensorkey};
+ open(SENSORORIGFILE, "/daq/toolbox/sensors/".$sensorfile) || die("Cannot open file ../$sensorfile!");
+ open(SENSOROUTFILE, "> ./".$sensorfile) || die("Cannot open file ../$sensorfile!");
+ my $datasection = 0;
+ while (<SENSORORIGFILE>) {
+
+ if($datasection == 0) {
+ print SENSOROUTFILE $_;
+ }
+ else {
+ if($_ =~ /^[^;]*$opt_register=/) {
+ print SENSOROUTFILE $_;
+ print "found line.\n";
+ ($ir,$drlength,$dr) = split(/,/, $_); # dr is stored MSN first as hexadecimal string
+ last;
+ }
+ } # after the BIAS_DAC register truncate file.
+ if($_ =~ /^\[Data\]/) {
+ $datasection=1;
+ }
+ }
+ close SENSOROUTFILE;
+ close SENSORORIGFILE;
+ $sensornumber = $sensornumberloop;
+ $sensornumberloop++;
+ }
+}
+system("cp ../chains.ini ./chains.ini");
+# program RAM, write once, copy returned value from JTAG register and print it
+foreach my $chainname (@chain_names) {
+ if(defined($opt_chain) and not ($chainname eq $opt_chain)) {
+ next;
+ }
+ my %sensors = %{$chains{$chainname}};
+ # write BIAS_DAC only to RAM of chain
+ system("./ui_writeram.pl -c $chainname");
+ system("./ui.pl -c $chainname -o write_once");
+ system("sleep 0.05");
+ system("./ui.pl -c $chainname -o copy_ram1b1c");
+ system("sleep 0.01");
+}
+foreach my $chainname (@chain_names) {
+ if(defined($opt_chain) and not ($chainname eq $opt_chain)) {
+ next;
+ }
+ my %sensors = %{$chains{$chainname}};
+
+ my $reglen=floor(($drlength+31)/32);
+ for(my $sensornumber=0; $sensornumber < scalar keys %sensors; $sensornumber++) {
+ for(my $i =0; $i<$reglen; $i++) {
+ my $hexaddr = int_to_32bit_hex($sensornumber*(2**($RAM_JTAG_REGISTERS_DEPTH-$MAX_NUMCHIPS_LD))+$i+7); # when one register is programmed only, it starts at address 7.
+ print "sensornr=$sensornumber. reading addr 0x$hexaddr: ";
+ my $regval = execute_shell_command_return("./ui.pl -c $chainname -o read_ram1c_word -a 0x$hexaddr -q");
+ print $regval."\n";
+ }
+ }
+}
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use Getopt::Long;
+use POSIX; # for floor
+
+my %chains = ();
+my $namecol = 0; # column of chain name, column counting from zero
+my $chaincol = 1; # column of chain name, column counting from zero
+my $jnrcol = 2; # column of JNR for sorting, column counting from zero
+my $minnumcols = 4;
+use Sys::Syslog;
+openlog("atomic,onereg_writeonce.pl", "perror", "local1");
+
+# in future this could be chain dependent, so should be added to chains.ini
+my $MAX_NUMCHIPS_LD = 3;
+my $RAM_JTAG_REGISTERS_DEPTH = 11;
+
+my $opt_help;
+my $opt_sensor;
+my $opt_register;
+my $chain_of_sensor;
+GetOptions ('h|help' => \$opt_help,
+ 's|sensor=s' => \$opt_sensor,
+ 'r|register=s' => \$opt_register
+ );
+if($opt_help or not defined($opt_sensor)) {
+ &help();
+ exit(0);
+}
+
+
+sub help(){
+ print "Usage: write_reg_onesensor -s <sensor name> -r <register number>
+
+required:
+ -s|--sensor <sensor name> : Select only chain of sensor <sensor name>
+ -r|--register <register number> : Select only Register <register number> and bypass register in
+ other sensors
+ number as string exactly as in sensor*.ini
+ 00 for BIAS_DAC
+"
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ #report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ #report( 'report_detailed' , $result);
+ #report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) { print "command failed. output: $result";}
+ return $result;
+}
+
+
+open(PROTOTYPEDBFILE,"/daq/toolbox/prototype_setup.db") || die("Cannot open file /daq/mvdmon/prototype_setup.db!");
+my @lines_db = <PROTOTYPEDBFILE>;
+close(PROTOTYPEDBFILE);
+my $keydesc = 0;
+foreach my $line (@lines_db) {
+ # skip commented out lines
+ if(substr($line, 0, 1) eq "#") {
+ next;
+ }
+ # if new section begins stop interpreting lines
+ if(substr($line, 0, 3) eq "key") {
+ $keydesc = 0;
+ }
+ if($keydesc == 1) {
+ my @entries = split(/\s+/, $line);
+ if((scalar @entries) < $minnumcols) {
+ if(!($line eq "\n")) {print "Warning: row with too little entries. skipping."};
+ next;
+ }
+ my $sensorname = $entries[$namecol];
+ my $chainname = $entries[$chaincol];
+ if($sensorname eq $opt_sensor) { $chain_of_sensor = $chainname; }
+ else { print "sensorname: ". $sensorname . "\n"; }
+ my $jnr = $entries[$jnrcol];
+ if(! defined ($chains{$chainname})) {
+ my %sensors = ();
+ $chains{$chainname} = \%sensors;
+ }
+ my %sensors = %{$chains{$chainname}};
+ # only add sensor to chain if JNR matches following regexp
+ if ($jnr =~ /[0-9]+/) {
+ my $jnrname;
+ $jnrname= "JNR".$jnr."_".$sensorname;
+ $sensors{$jnrname} = $sensorname . ".ini";
+ }
+ $chains{$chainname} = \%sensors;
+ }
+ # if desc section begins, start interpreting next line
+ if(substr($line, 0, 8) eq "key jtag") {
+ $keydesc = 1;
+ }
+}
+
+# for each of the possible three chains generate a section with name and sensor-file references in the correct order
+my @chain_names = sort keys (%chains);
+my $ir;
+my $drlength;
+my $dr;
+if(not defined($chains{$chain_of_sensor})) { die ("Chain Name $chain_of_sensor for sensor not found.");}
+my %sensors = %{$chains{$chain_of_sensor}};
+my $sensornumber;
+my $sensornumberloop= 0;
+foreach my $sensorkey (sort keys %sensors) {
+ my $sensorfile=$sensors{$sensorkey};
+ if($sensorfile eq ($opt_sensor.".ini")) {
+ open(SENSORORIGFILE, "/daq/toolbox/sensors/".$sensorfile) || die("Cannot open file ../$sensorfile!");
+ open(SENSOROUTFILE, "> ./".$sensorfile) || die("Cannot open file ../$sensorfile!");
+ my $datasection = 0;
+ while (<SENSORORIGFILE>) {
+
+ if($datasection == 0) {
+ print SENSOROUTFILE $_;
+ }
+ else {
+ if($_ =~ /^[^;]*$opt_register=/) {
+ print SENSOROUTFILE $_;
+ print "found line.\n";
+ ($ir,$drlength,$dr) = split(/,/, $_); # dr is stored MSN first as hexadecimal string
+ last;
+ }
+ } # after the BIAS_DAC register truncate file.
+ if($_ =~ /^\[Data\]/) {
+ $datasection=1;
+ }
+ }
+ close SENSOROUTFILE;
+ close SENSORORIGFILE;
+ $sensornumber = $sensornumberloop;
+ }
+ else {
+ system("cp ./bypass.ini ./$sensorfile")
+ }
+ $sensornumberloop++;
+}
+system("cp ../chains.ini ./chains.ini");
+# write BIAS_DAC only to RAM of chain in which sensor is
+system("./ui_writeram.pl -c $chain_of_sensor");
+syslog("INFO", "write once ".$opt_sensor);
+system("./ui.pl -b board01 -c $chain_of_sensor -o write_once");
+system("sleep 0.05");
+system("./ui.pl -b board01 -c $chain_of_sensor -o copy_ram1b1c");
+my $reglen=floor(($drlength+31)/32);
+for(my $i =0; $i<$reglen; $i++) {
+ my $hexaddr = int_to_32bit_hex($sensornumber*(2**($RAM_JTAG_REGISTERS_DEPTH-$MAX_NUMCHIPS_LD))+$i+7); # when one register is programmed only, it starts at address 7.
+ print "reading addr 0x$hexaddr: ";
+ my $regval = execute_shell_command_return("./ui.pl -b board01 -c $chain_of_sensor -o read_ram1c_word -a 0x$hexaddr -q");
+ print $regval."\n";
+}
--- /dev/null
+#!/usr/bin/perl
+#use strict;
+#use warnings;
+use Config::Abstract::Ini;
+my $chainsfile= 'chains.ini';
+my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+my %allchains = $chainsSettings->get_all_settings;
+
+$ENV{DAQOPSERVER}='trb124';
+
+foreach my $chain (keys %allchains) {
+ my %settings=%{$allchains{$chain}};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_base_addr = $settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ print "trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n"; # CMD_START
+ my $result = `trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n`; # CMD_START
+}
+
--- /dev/null
+cp ../../trb_maps_jtag3/ui/sensor* ./
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+
+$ENV{DAQOPSERVER}='trb124';
+system("mkdir /tmp/jtag_initmem");
+
+#push(@INC, "./BN");
+#use lib "$ENV{PWD}/BN";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+
+use lib "BN/blib/arch";
+use BN::CRC32;
+#use String::CRC32;
+
+#use feature "state";
+use POSIX;
+# for a pure gtk+ glade project
+use Gtk2 -init;
+use Gtk2::GladeXML;
+use Glib qw/TRUE FALSE/;
+
+
+my %chain_defaults = (); #('h_stop', 'h_delay0', 'h_prog_ram', 'h_set_timing_10mhz',,'h_set_inout');
+my %board_defaults = (); #('h_period_0_15s');
+my %chain_defaults2 = (); #('h_start');
+
+# whitespace trimming from http://www.somacon.com/p114.php
+# Declare the subroutines
+sub trim($);
+sub ltrim($);
+sub rtrim($);
+
+# Create a test string
+my $string = " \t Hello world! ";
+
+# Here is how to output the trimmed text "Hello world!"
+#print trim($string)."\n";
+#print ltrim($string)."\n";
+#print rtrim($string)."\n";
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+# Left trim function to remove leading whitespace
+sub ltrim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ return $string;
+}
+# Right trim function to remove trailing whitespace
+sub rtrim($)
+{
+ my $string = shift;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+sub reverse32bit($) {
+ my ($in) = @_;
+ my $result = unpack("L", pack("B*", scalar reverse unpack("B*", pack("L",$in))));
+ return $result;
+ #return 1;
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+my $num_words = 0;
+
+# this subroutine
+# changes parameter 0, which holds the file handle
+sub memfile_writeline($$$$) {
+ my($memfile, $memfilenames, $memfiles_prefix, $line_string)=@_;
+ my $filenum = floor($num_words/256);
+ my $last_filenum = floor(($num_words-1)/256);
+ my $filenum_str = sprintf "%0.2d", $filenum;
+ my $memfilename = $memfiles_prefix.'.'.$filenum_str.".txt";
+
+ if((!defined $_[0])) {
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ elsif($filenum!=$last_filenum) {
+ $memfile->close();
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ my $fh = $_[0];
+ print $fh $line_string;
+ $num_words++;
+}
+my $gladexml = Gtk2::GladeXML->new('gui/design/window3_libglade.glade');
+my $textview_msg = $gladexml->get_widget('textview_msg');
+my $textview_msgdetailed = $gladexml->get_widget('textview_msgdetailed');
+my $logfilehandle = FileHandle->new('gui3log.txt', 'a');
+
+sub report {
+ # log to logfile
+ my $logdate = strftime "%Y%m%d%H%M%S", localtime;
+ print $logfilehandle $logdate . ":". $_[1];
+ # report( $textview, $string );
+
+ my $textfield;
+ if($_[0] eq 'report_detailed') {
+ $textfield = $textview_msgdetailed;
+ }
+ else {
+ $textfield = $textview_msg;
+ }
+ my $buffer = $textfield->get_buffer;
+ my $sw = $textfield->get_parent;
+ my $iter = $buffer->get_end_iter;
+ $buffer->insert($iter,$_[1]);
+
+ my $va = $sw->get_vadjustment;
+ #$va->set_value (($va->upper - $va->page_size) );
+
+ $va->set_value ( $va->upper );
+}
+
+sub init_msg {
+ my $textfield = $textview_msg;
+ my $buffer = $textfield->get_buffer;
+ $buffer->set_text($_[0]."\n");
+ reportd ($_[0]."\n");
+}
+
+sub reportd {
+ report('report_detailed', $_[0]);
+}
+
+
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ open ( SHELL , "$command 2>&1 |" ) || report( 'report_general' , "failed to execute command.");
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {report('report_general', "command failed. output: $result");}
+ return $result;
+}
+
+
+sub generate_h_man_maps_reset {
+ my ($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "manual reset chain " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $resetnormal = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal));
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ }
+}
+
+sub generate_h_maps_start_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "generate MAPS start $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<9)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<9)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_maps_reset_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("MAPS reset signal $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<11)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<11)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ }
+}
+sub generate_h_maps_clk_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("generate MAPS clk $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<13)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<13)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_prog_ram {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_;
+ my @memfilenames = @{$memfilenames_ref};
+ return sub {
+ init_msg("program RAM $chain.");
+ my $numchips_hex = int_to_32bit_hex($numsensors);
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", ""); # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ reportd "set RAM base pointer: \n";
+ execute_shell_command("trbcmd w $fpga_addr $ram_base_addr 0x$ihex", "");
+ # write to configuration RAM
+ reportd "write max. 256 32-bit-words: \n";
+ execute_shell_command("trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]", "");
+ }
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000009", ""); # CMD_START
+ }
+}
+
+sub generate_h_set_timing_10mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 10 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ #reportd $cmdline;
+ #system($cmdline);
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_1mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 1 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_100khz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 100 kHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+
+
+sub generate_h_delay {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
+ return sub {
+ init_msg("Delay $delay $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_waitbeforestart_6us {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 6us.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+sub generate_h_waitbeforestart_1ms {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1ms.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_waitbeforestart_1s {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1s.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_maps_reset {
+ my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
+ return sub {
+ init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ }
+}
+
+
+sub generate_h_trig {
+ my ($board, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr " . $board);
+ # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ }
+}
+sub generate_h_chain_trig {
+ my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
+ # set bit in trigger register correspondig to chain-# $chainnr
+ my $newval;
+ $newval = int_to_32bit_hex(((1<<$chainnr)));
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ }
+}
+
+
+
+sub generate_h_trigger_init_sequence {
+ my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_;
+ return sub {
+ init_msg("Send Trigger $board.");
+ if(!defined($conf_fet_trigger_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # generate trigger
+ execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet
+ }
+}
+
+
+sub generate_h_set_inout {
+ my($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("Set IN/OUT $chain.");
+ if(!defined($conf_signals_addr)){
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ }
+}
+
+sub generate_h_prog_fpga {
+ my($board, $trbhostname, $addonortrb, $staplfilename) = @_;
+ return sub {
+ init_msg("Prog FPGA $board.");
+ if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){
+ report('report_general', "Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"",
+ "------------- Connection accepted -------------
+> return value of command: 0
+> stdout:
+Successful File Execution.
+------------- END OF OUTPUT ------------
+");
+ }
+}
+sub generate_h_start_trbnetd {
+ my($board, $trbhostname) = @_;
+ return sub {
+ init_msg("Start trbnetd $board.");
+ if(!defined($trbhostname)){
+ report('report_general',"Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted -------------
+> return value of command: 0
+------------- END OF OUTPUT ------------
+");
+ }
+}
+
+sub generate_h_set_standard {
+ my %boards_handlers = %{$_[0]};
+ my %chains_handlers = %{$_[1]};
+ return sub {
+ foreach my $board (reverse sort keys %chains_handlers) {
+ my %chains_handlers2 = %{$chains_handlers{$board}};
+ foreach my $chain (reverse sort keys %chains_handlers2) {
+ my %chain_handlers = %{$chains_handlers2{$chain}};
+ foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) {
+ &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ }
+ foreach my $board (reverse sort keys %boards_handlers) {
+ my %board_handlers = %{$boards_handlers{$board}};
+ foreach my $handler_name (@{$board_defaults{$board}}) {
+ &{$board_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ foreach my $board (reverse sort keys %chains_handlers) {
+ my %chains_handlers2 = %{$chains_handlers{$board}};
+ foreach my $chain (reverse sort keys %chains_handlers2) {
+ my %chain_handlers = %{$chains_handlers2{$chain}};
+ foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) {
+ &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ }
+ }
+}
+
+ # outputs/inputs not inverted, but activated, RESET deactivated and inverted (high)
+sub h_reload_boardsini {
+ my ($widget, $data) = @_;
+ init_msg("reload!\n");
+ system("./generate_chainorder.pl");
+ my $boardsfile= 'boards.ini';
+ my $chainsSettings = new Config::Abstract::Ini($boardsfile);
+ my %allboards = $chainsSettings->get_all_settings;
+
+ my $notebook_boards = Gtk2::Notebook->new;
+ my $main_vbox1 = $gladexml->get_widget('vbox1');
+ my @children = $main_vbox1->get_children;
+ $main_vbox1->remove($children[0]);
+ $main_vbox1->pack_start($notebook_boards, TRUE, TRUE, 0);
+ $main_vbox1->reorder_child($notebook_boards,0);
+ $main_vbox1->resize_children();
+# my $testframe = Gtk2::Frame->new;
+# my $testframe2 = Gtk2::Frame->new;
+# $notebook_boards->append_page($testframe, "Test 1");
+# $notebook_boards->append_page($testframe2, "Test 2");
+ my %boards_handlers;
+ my %chains_handlers;
+ foreach my $board (keys %allboards) {
+ my $gladexml3 = Gtk2::GladeXML->new('gui/design/buttons_BM_NP1_board_libglade.glade');
+ my %settings=%{$allboards{$board}};
+ my $chainsini = $settings{'chainsini'};
+ my $trbhostname = $settings{'FPGAboard_hostname'};
+ my $addonortrb = $settings{'FPGAboard_addonortrb'};
+ my $staplfilename = $settings{'FPGAboard_staplfilename'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $conf_period_addr = $settings{'CONFperiod_trbnetAddr'};
+ my $conf_offspillcounter_addr = $settings{'CONFoffspillcounter_trbnetAddr'};
+ my $conf_waitstart_addr = $settings{'CONFwaitstart_trbnetAddr'};
+ my $conf_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+ my @gui_defaults = split (/,/,$settings{'guiBM_NP_defaults'});
+ $board_defaults{$board} = \@gui_defaults;
+
+
+ my $vbox_board_chains = $gladexml3->get_widget('vbox_chains');
+ my $vbox_board_ = $gladexml3->get_widget('vbox_chains');
+
+ $chains_handlers{$board} = reload_chainsini($vbox_board_chains, $chainsini, $board);
+ my %board_handlers = ('h_prog_fpga' => generate_h_prog_fpga($board, $trbhostname, $addonortrb, $staplfilename),
+ 'h_start_trbnetd' => generate_h_start_trbnetd($board, $trbhostname),
+ 'h_waitbeforestart_6us' => generate_h_waitbeforestart_6us($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_waitbeforestart_1ms' => generate_h_waitbeforestart_1ms($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_waitbeforestart_1s' => generate_h_waitbeforestart_1s($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_trigger_init_sequence' => generate_h_trig($board, $fpga_addr, $conf_triginitseq_addr),
+ 'h_maps_reset' => generate_h_trig($board, $fpga_addr, $conf_trigmapsreset_addr),
+ 'h_run_jtag' => generate_h_trig($board, $fpga_addr, $conf_trigrunjtag_addr),
+ 'h_write_once' => generate_h_trig($board, $fpga_addr, $conf_trigwriteonce_addr),
+ 'h_maps_start' => generate_h_trig($board, $fpga_addr, $conf_trigmapsstart_addr)
+
+ );
+ $boards_handlers{$board} = \%board_handlers;
+ $board_handlers{'h_set_standard'} = generate_h_set_standard(\%boards_handlers, \%chains_handlers);
+ $boards_handlers{$board} = \%board_handlers;
+ $gladexml3->signal_autoconnect_all(%board_handlers);
+ my $vbox_board = $gladexml3->get_widget('vbox_top');
+ $vbox_board->reparent($notebook_boards);
+ $notebook_boards->set_tab_label_text($vbox_board, "$board" );
+ }
+ $notebook_boards->show_all;
+}
+
+sub reload_chainsini {
+ my ($vbox_board_chains, $chainsfile, $board) = @_;
+ my %chains_handlers_hash;
+ #my $window = $widget->get_parent_window;
+ my @children = $vbox_board_chains->get_children;
+ $vbox_board_chains->remove($children[0]);
+ my $hbox_chains = Gtk2::HBox->new(FALSE, 2); # homogeneous, spacing 2
+ #$hbox_chains->set_size_request(300,200);
+ $vbox_board_chains->pack_start($hbox_chains, TRUE, TRUE, 0);
+ $vbox_board_chains->reorder_child($hbox_chains,0);
+ $vbox_board_chains->resize_children();
+
+ # START from ui.pl: modified to add GUI elements and to program only when clicked in gui.
+ # my $chainsfile= 'chains.ini';
+ my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+ my %allchains = $chainsSettings->get_all_settings;
+
+ my $date = strftime "%Y%m%d%H%M%S", localtime;
+ my $initmem_folder = "/tmp/jtag_initmem/$date";
+ if(-e $initmem_folder) {
+ die("Error: Folder with the same date already exists!");
+ }
+ mkdir $initmem_folder,0755;
+
+ # File with prefix names files for last programmed values
+ my $lastprogfilename = "/tmp/jtag_initmem/lastprog.txt";
+ my $handle_lastprog = FileHandle->new($lastprogfilename, 'w');
+
+ # loop through chains
+ foreach my $chain (reverse sort keys %allchains) {
+ #GUI stuff BEGIN
+ my $gladexml2 = Gtk2::GladeXML->new('gui/design/buttons_BM_NP1_libglade.glade');
+ my $vbox_top = $gladexml2->get_widget('vbox_top');
+ $vbox_top->reparent($hbox_chains);
+ $hbox_chains->pack_start($vbox_top, TRUE, TRUE, 0); # expand, fill, padding=0
+ # GUI stuff END
+ reportd $chain, ": ";
+ #print join ' ', %{$allchains{$chain}}, "\n";
+ my %settings=%{$allchains{$chain}};
+ my @sensors;
+ my @drs;
+ my @drs_length;
+ my @old_drs;
+ my @old_drs_length;
+ my @irs;
+ my $irlen;
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $conf_signals_addr = $settings{'CONFsignals_trbnetAddr'};
+ my $conf_resetafterfirstwrite_addr = $settings{'CONFresetafterfirstwrite_trbnetAddr'};
+ my $conf_resetbeforeinit_addr = $settings{'CONFresetbeforeinit_trbnetAddr'};
+ my $conf_chain_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_chain_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_chain_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_chain_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_chain_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+ my $chainnr = $settings{'chainnr'};
+ my @gui_defaults1 = split (/,/,$settings{'guiBM_NP_defaults1'});
+ my @gui_defaults2 = split (/,/,$settings{'guiBM_NP_defaults2'});
+ $chain_defaults{$board}{$chain} = \@gui_defaults1;
+ $chain_defaults2{$board}{$chain} = \@gui_defaults2;
+ #my $staplfilename_delay1 = $settings{'FPGAboard_staplfilename_delay1'};
+
+ #my $slowcontrol_hostname = $settings{'TRBNETslowcontrol_hostname'};
+
+ my $memfiles_prefix; # the same prefix is used for the files for one chain
+ # need one file per chip with at maximum 256 32 bit words
+ # that are written at once.
+ # then the RAM base pointer has to be changed for the next chip
+ my @memfilenames=();
+
+ $memfiles_prefix="$initmem_folder/$chain";
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ push(@sensors, $setting_name);
+ @old_drs = @drs;
+ @old_drs_length = @drs_length;
+ @irs = ();
+ @drs = ();
+ @drs_length = ();
+ my $sensorfile = $settings{$setting_name};
+ reportd "loading sensor file: $sensorfile\n";
+ my $sensorSettingsO = new Config::Abstract::Ini("/daq/toolbox/sensors/".$sensorfile);
+ my %sensorSettings = $sensorSettingsO->get_all_settings;
+ my $this_irlen = $sensorSettingsO->get_entry_setting('General', 'IRLEN', '5');
+ my $bypassreg = $sensorSettingsO->get_entry_setting('General', 'BYPASSREG', '1F');
+ if (!defined $irlen ){
+ $irlen = $this_irlen;
+ }
+ elsif($this_irlen != $irlen) {
+ reportd "this_irlen=$this_irlen in $sensorfile differs from previously set irlen=$irlen.\nThis should be supported by this version (trb_maps_jtag3) of the JTAG controller.\n But is it really intended?\n";
+ }
+ #print "irlen: ", $this_irlen, "\n";
+ # loop through data registers
+ my %sensorData = $sensorSettingsO->get_entry('Data');
+ foreach my $data_register_ir (sort keys %sensorData) {
+ my $value = $sensorData{$data_register_ir};
+ my ($ir,$drlength,$dr)= split(/,/, $value); # dr is stored MSN first as hexadecimal string
+ $dr = uc(trim($dr));
+ if(length($dr)%8 != 0) {
+ die("Error: DR string is not multiple of 32 bit (4bytes = 8 nibbles)\n");
+ }
+ if($dr =~ /[^0-9A-F]+/) {
+ die("Error: Invalid hexadecimal string for DR given: \$dr=\"$dr\"\n");
+ }
+ #print "drlength: $drlength\n";
+ push(@drs_length, $drlength);
+ push(@drs, $dr);
+ push(@irs, $ir);
+ # only warning
+ if((defined $old_drs_length[@drs-1]) && ($drlength != $old_drs_length[@drs-1])) {
+ reportd ("Warning: Length of the same DR of two sensors differs.\n");
+ }
+ }
+ my $memfilename = $memfiles_prefix . "." . $setting_name . ".txt";
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfilename\" exists.");
+ }
+ reportd "Opening $memfilename...\n";
+ my $handle = FileHandle->new($memfilename, 'w');
+ push(@memfilenames, $memfilename);
+ # write numregs + IRlen
+ my $word = scalar($this_irlen)<<16;
+ $word = $word + scalar @irs;
+ ### $word = ($word<<16) + pack("L", scalar(@irs));
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# IRlen & numregs \n";
+ #####print $handle "0x" .uc (substr(reverse(join('',unpack("h8", pack("L", scalar($this_irlen))))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar(@irs))))),4,4)) . "\t# IRlen & numregs \n";
+
+ #print "reverse test: " . reverse32bit(0x00000001)."\n";
+ my $initial = 0x00000000;
+ my $crcword = pack("L", reverse32bit($word));
+ my $crc0 = crc32($crcword, $initial);
+ #my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write DEV_ID
+ $word = 0x4D323601;
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# DEV_ID \n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write pointer
+ my $offset = 3*@irs+4;
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $drlen = $drs_length[$reg_i];
+ $word = $offset;
+ #print $handle "0x". uc (substr(reverse(join('',unpack("h8", pack("L", 0)))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar($offset))))),4,4)) . "\t# Pointer + reserved\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# Pointer + reserved \n";
+ $word = $drlen;
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+
+ #print $handle "0x0000". uc (substr(reverse(join('',unpack("h8", pack("L", scalar($drlen))))),4,4)) . "\t# Length\n";
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8",pack("L", $word)))),0,8)) . "\t# Length\n";
+ $offset += floor(($drlen+31)/32);
+ }
+ # write CRC-32
+ #my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+ $crc0_rn = ~reverse32bit($crc0);
+ #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+ my $line_crc = sprintf "%0.8X", $crc0_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ my $crc1 = 0xFFFFFFFF;
+ # write IRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $ir = $irs[$reg_i];
+ #my @words = unpack("L", pack("H*", uc($ir)));
+ $word = unpack("L", pack("h*", (scalar reverse uc($ir)) ."000000"));
+ #print "ir=$ir.IR word: $word\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($ir))).uc($ir) . "\t# IR\n";
+ }
+ # write BYPASSREG IR
+ $word = unpack("L", pack("h*", (scalar reverse uc($bypassreg)) ."000000"));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($bypassreg))).uc($bypassreg) . "\t# IR BYPASS\n";
+
+ # write DRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $length = $drs_length[$reg_i];
+ my $numwords = floor(($length+31)/32);
+ for(my $i=0;$i<$numwords; $i++) {
+ #print "length: $length\n";
+ #print "numwords: $numwords\n";
+
+ $word = unpack("L", pack("h*", (scalar reverse uc(substr($drs[$reg_i],($numwords-$i-1)*8,8)))));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ my $linestr = "0x". substr($drs[$reg_i],($numwords-$i-1)*8,8) . "\t# DR" . $reg_i . "\n";
+ print $handle $linestr;
+ }
+ }
+ #write CRC-32
+ my $crc1_rn = ~reverse32bit($crc1);
+ $line_crc = sprintf "%0.8X", $crc1_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ }
+ }
+ my $ref_h_prog_ram = generate_h_prog_ram($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, scalar @sensors, \@memfilenames);
+ my %handlers_hash = ('h_man_maps_reset'=>generate_h_man_maps_reset($chain, $fpga_addr, $conf_signals_addr),
+ #'h_prog_fpga_delay1' => generate_h_prog_fpga($chain, $trbhostname, $addonortrb, $staplfilename_delay1),
+ 'h_delay0' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 0),
+ 'h_delay1' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 1),
+ 'h_delay2' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 2),
+ 'h_delay3' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 3),
+ 'h_prog_ram' => $ref_h_prog_ram,
+ 'h_set_timing_10mhz' => generate_h_set_timing_10mhz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ 'h_set_timing_1mhz' => generate_h_set_timing_1mhz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ 'h_set_timing_100khz' => generate_h_set_timing_100khz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ #'h_start' => generate_h_start($chain, $fpga_addr,$cmd_reg_addr),
+ #'h_stop' => generate_h_stop($chain, $fpga_addr,$cmd_reg_addr),
+ 'h_set_inout' => generate_h_set_inout($chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_reset_before_on' => generate_h_maps_reset(1,$chain, $chainnr, $fpga_addr, $conf_resetbeforeinit_addr),
+ 'h_maps_reset_before_off' => generate_h_maps_reset(0,$chain, $chainnr, $fpga_addr, $conf_resetbeforeinit_addr),
+ 'h_maps_reset_after_on' => generate_h_maps_reset(1,$chain, $chainnr, $fpga_addr, $conf_resetafterfirstwrite_addr),
+ 'h_maps_reset_after_off' => generate_h_maps_reset(0,$chain, $chainnr, $fpga_addr, $conf_resetafterfirstwrite_addr),
+ #'h_maps_start_on' => generate_h_maps_start(1,$chain, $fpga_addr, $conf_signals_addr),
+ #'h_maps_start_off' => generate_h_maps_start(0,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_clk_on' => generate_h_maps_clk_signal(1,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_clk_off' => generate_h_maps_clk_signal(0,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_trig_init_seq' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_triginitseq_addr),
+ 'h_maps_reset' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigmapsreset_addr),
+ 'h_run_jtag' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigrunjtag_addr),
+ 'h_write_once' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigwriteonce_addr),
+ 'h_maps_start' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigmapsstart_addr)
+ );
+ $gladexml2->signal_autoconnect_all(%handlers_hash);
+ my $label_chainnr = $gladexml2->get_widget('label_chainnr');
+ $label_chainnr->set_label($chain);
+ $chains_handlers_hash{$chain} = \%handlers_hash;
+ reportd "\n";
+ }
+ print $handle_lastprog $initmem_folder;
+
+ $hbox_chains->show_all;
+ return \%chains_handlers_hash;
+
+}
+
+
+# Boris
+sub exitclean{
+ Gtk2->main_quit();
+ exit (0);
+}
+
+
+
+
+$gladexml->signal_autoconnect_from_package('main');
+#$gladexml->signal_autoconnect_all ('h_reload_chainsini'=>\&h_reload_chainsini);
+#$quitbtn = $gladexml->get_widget('Quit');
+my $window1 = $gladexml->get_widget('window1');
+$window1->signal_connect(destroy => \&exitclean); #Boris
+$window1->show_all;
+Gtk2->main;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# #print "data registers for FPGA $fpga_addr:", map { "$_ => $drs_binary{$_}\n" } keys %drs_binary;
+# $drs_offset{$irs[0]} = 4+(scalar @irs)*2;
+# for (my $i=1;$i<@irs;$i++) {
+# my $dr_length = $drs_length{$irs[$i-1]};
+# $drs_offset{$irs[$i]} = $drs_offset{$irs[$i-1]} + floor(($dr_length*(scalar @sensors)+31)/32) + 2; # add one x 32 bit for CRC, one x 32 bit for IR, integer division rounds down, right?
+# }
+# #open RAMTEXT, ">$memfiles_prefix{$chain}";
+# $num_words = 0;
+# my $ram_fh;
+# my @mem_filenames;
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc (reverse(join('',unpack("h8", pack("L", scalar(@sensors)))))) . "\t# numchips \n"); # numchips; the reverse is done here because apparently internally the unsigned long is stored LSByte first (little endian)
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", 0))))) . "\t# reserved\n"); # reserved
+# for (my $i=0;$i<@irs;$i++) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_offset{$irs[$i]}))))) . "\t# pointer\n"); # pointer
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_length{$irs[$i]}))))) . "\t# length \n"); # length
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# pointer (end of list)\n");
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# length (end of list)\n");
+# for (my $i=0;$i<@irs;$i++) {
+# my $ir=$irs[$i];
+# #print "ir: $ir\n";
+# my $ir_packed = pack("h*", (scalar reverse($ir)).("0"x (7-(length($ir)-1)%8)));
+# my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+# #print "debug ir_packed (h*): ". (scalar reverse($ir)).("0"x (8-length($ir)%32))."\n";
+# #print "debug ir_packed_r (B*): ". scalar reverse unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+# #print "debug2: " . (7-(length($ir)-1)%8) . "\n";
+# #print "debug3: " . $ir . "\n";
+# #print "debug4: " . $ir.("0"x (7-(length($ir)-1)%8)) . "\n";
+# #print "debug5 (B*): ". unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+#
+# my $initial = 0x00000000;
+# my $crc0 = crc32($ir_packed_r, $initial);
+# #printf "CRC0: %X. ~reversed: %X\n", $crc0, $crc0_rn;
+#
+# for(my $i=0; $i<floor((length($drs_binary{$ir})-1)/32)+1;$i++){
+# my $dr_word_packed_r = pack("b*", scalar reverse substr($drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)),($i)*32, 32));
+# $crc0 = crc32($dr_word_packed_r, $crc0);
+# my $crc0_rn = ~reverse32bit($crc0);
+# printf "CRC: 0x%0.8X.\n", $crc0_rn;
+# }
+# my $crc0_rn = ~reverse32bit($crc0);
+# #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+# my $line_crc = sprintf "0x%0.8X\t# CRC-32\n", $crc0_rn;
+# print "debug dr_binary: " . $drs_binary{$ir} . "\n";
+# my $dr_packed = pack("b*", $drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)));
+# $drs{$ir} = unpack('h*', $dr_packed);
+# print "debug drs: " . $drs{$ir} . "\n";
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(8-length($ir))).uc($ir) . "\n");
+# for(my $i=0; $i<floor((length( $drs{$ir}) -1)/8)+1; $i++){
+# #print "dbg: i=$i, len=".length( $drs{$ir})."\n";
+# if(length($drs{$ir}) >= ($i+1)*8) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(substr($drs{$ir}, ($i)*8, 8))) . "\n");
+# }
+# else {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(($i+1)*8-length($drs{$ir}))).uc(reverse(substr($drs{$ir}, ($i)*8, length($drs{$ir})%8))) . "\n");
+# }
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, $line_crc);
+#
+# #print "IR $ir, DR ". $drs{$ir} . "\n";
+# }
+# #close RAMTEXT;
+# $ram_fh->close();
+# #my $result = `cat $memfile{$fpga_addr}`;
+# $ENV{'DAQOPSERVER'}="trb126";
+# for(my $i=0;$i<scalar @mem_filenames;$i++) {
+# # write RAM base pointer
+# my $ihex = int_to_32bit_hex($i);
+# print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
+# my $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+# print "set RAM base pointer: " . $result;
+# # write to configuration RAM
+# print "trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]\n";
+# $result = `trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]`;
+# print "write max. 256 32-bit-words: " . $result;
+# }
+#}
+
+
+# init_writemem:
+# - loop through chains
+# - loop through sensors
+# - test if IR length is the same as for other sensors
+# - loop through DRs
+# - test if DR length is the same as for other sensors
+# - add DR content to chain data register (hexadecimal string)
+# - write contents for JTAG chain controller RAM to text file(s)
+# - execute trbcmd to transfer file(s) to RAM of FPGA configured in chains.ini
+#
+# get_status:
+# get_error_counts:
+# reactivate_sensor:
+# deactivate_sensor:
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+
+$ENV{DAQOPSERVER}='trb124';
+if(not( -e "/tmp/jtag_initmem")) {
+ system("mkdir /tmp/jtag_initmem");
+}
+#push(@INC, "./BN");
+#use lib "$ENV{PWD}/BN";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+
+use lib "BN/blib/arch";
+use BN::CRC32;
+#use String::CRC32;
+
+#use feature "state";
+use POSIX;
+# for a pure gtk+ glade project
+use Gtk2 -init;
+use Gtk2::GladeXML;
+use Glib qw/TRUE FALSE/;
+
+
+my %chain_defaults = (); #('h_stop', 'h_delay0', 'h_prog_ram', 'h_set_timing_10mhz',,'h_set_inout');
+my %board_defaults = (); #('h_period_0_15s');
+my %chain_defaults2 = (); #('h_start');
+
+# whitespace trimming from http://www.somacon.com/p114.php
+# Declare the subroutines
+sub trim($);
+sub ltrim($);
+sub rtrim($);
+
+# Create a test string
+my $string = " \t Hello world! ";
+
+# Here is how to output the trimmed text "Hello world!"
+#print trim($string)."\n";
+#print ltrim($string)."\n";
+#print rtrim($string)."\n";
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+# Left trim function to remove leading whitespace
+sub ltrim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ return $string;
+}
+# Right trim function to remove trailing whitespace
+sub rtrim($)
+{
+ my $string = shift;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+sub reverse32bit($) {
+ my ($in) = @_;
+ my $result = unpack("L", pack("B*", scalar reverse unpack("B*", pack("L",$in))));
+ return $result;
+ #return 1;
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+my $num_words = 0;
+
+# this subroutine
+# changes parameter 0, which holds the file handle
+sub memfile_writeline($$$$) {
+ my($memfile, $memfilenames, $memfiles_prefix, $line_string)=@_;
+ my $filenum = floor($num_words/256);
+ my $last_filenum = floor(($num_words-1)/256);
+ my $filenum_str = sprintf "%0.2d", $filenum;
+ my $memfilename = $memfiles_prefix.'.'.$filenum_str.".txt";
+
+ if((!defined $_[0])) {
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ elsif($filenum!=$last_filenum) {
+ $memfile->close();
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ my $fh = $_[0];
+ print $fh $line_string;
+ $num_words++;
+}
+my $gladexml = Gtk2::GladeXML->new('gui/design/window3_libglade.glade');
+my $textview_msg = $gladexml->get_widget('textview_msg');
+my $textview_msgdetailed = $gladexml->get_widget('textview_msgdetailed');
+my $logfilehandle = FileHandle->new('gui3log.txt', 'a');
+
+sub report {
+ # log to logfile
+ my $logdate = strftime "%Y%m%d%H%M%S", localtime;
+ print $logfilehandle $logdate . ":". $_[1];
+ # report( $textview, $string );
+
+ my $textfield;
+ if($_[0] eq 'report_detailed') {
+ $textfield = $textview_msgdetailed;
+ }
+ else {
+ $textfield = $textview_msg;
+ }
+ my $buffer = $textfield->get_buffer;
+ my $sw = $textfield->get_parent;
+ my $iter = $buffer->get_end_iter;
+ $buffer->insert($iter,$_[1]);
+
+ my $va = $sw->get_vadjustment;
+ #$va->set_value (($va->upper - $va->page_size) );
+
+ $va->set_value ( $va->upper );
+}
+
+sub init_msg {
+ my $textfield = $textview_msg;
+ my $buffer = $textfield->get_buffer;
+ $buffer->set_text($_[0]."\n");
+ reportd ($_[0]."\n");
+}
+
+sub reportd {
+ report('report_detailed', $_[0]);
+}
+
+
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ open ( SHELL , "$command 2>&1 |" ) || report( 'report_general' , "failed to execute command.");
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {report('report_general', "command failed. output: $result");}
+ return $result;
+}
+
+
+sub generate_h_man_maps_reset {
+ my ($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "manual reset chain " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $resetnormal = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal));
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ }
+}
+
+sub generate_h_maps_start_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "generate MAPS start $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<9)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<9)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_maps_reset_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("MAPS reset signal $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<11)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<11)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ }
+}
+sub generate_h_maps_clk_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("generate MAPS clk $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<13)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<13)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_prog_ram {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_;
+ my @memfilenames = @{$memfilenames_ref};
+ return sub {
+ init_msg("program RAM $chain.");
+ execute_shell_command("./ui_writeram.pl -c $chain -q", "$chain: done.\n"); # load sensor*.ini
+ }
+}
+
+sub generate_h_set_timing_10mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 10 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ #reportd $cmdline;
+ #system($cmdline);
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_1mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 1 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_100khz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 100 kHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+
+
+sub generate_h_delay {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
+ return sub {
+ init_msg("Delay $delay $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_waitbeforestart_6us {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 6us.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+sub generate_h_waitbeforestart_1ms {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1ms.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_waitbeforestart_1s {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1s.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_maps_reset {
+ my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
+ return sub {
+ init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ }
+}
+
+
+sub generate_h_trig {
+ my ($board, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr " . $board);
+ # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ }
+}
+sub generate_h_chain_trig {
+ my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
+ # set bit in trigger register correspondig to chain-# $chainnr
+ my $newval;
+ $newval = int_to_32bit_hex(((1<<$chainnr)));
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ }
+}
+
+
+
+sub generate_h_trigger_init_sequence {
+ my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_;
+ return sub {
+ init_msg("Send Trigger $board.");
+ if(!defined($conf_fet_trigger_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # generate trigger
+ execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet
+ }
+}
+
+
+sub generate_h_set_inout {
+ my($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("Set IN/OUT $chain.");
+ if(!defined($conf_signals_addr)){
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ }
+}
+
+sub generate_h_prog_fpga {
+ my($board, $trbhostname, $addonortrb, $staplfilename) = @_;
+ return sub {
+ init_msg("Prog FPGA $board.");
+ if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){
+ report('report_general', "Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"",
+ "------------- Connection accepted -------------
+> return value of command: 0
+> stdout:
+Successful File Execution.
+------------- END OF OUTPUT ------------
+");
+ }
+}
+sub generate_h_start_trbnetd {
+ my($board, $trbhostname) = @_;
+ return sub {
+ init_msg("Start trbnetd $board.");
+ if(!defined($trbhostname)){
+ report('report_general',"Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted -------------
+> return value of command: 0
+------------- END OF OUTPUT ------------
+");
+ }
+}
+
+sub generate_h_set_standard {
+ my %boards_handlers = %{$_[0]};
+ my %chains_handlers = %{$_[1]};
+ return sub {
+ foreach my $board (reverse sort keys %chains_handlers) {
+ my %chains_handlers2 = %{$chains_handlers{$board}};
+ foreach my $chain (reverse sort keys %chains_handlers2) {
+ my %chain_handlers = %{$chains_handlers2{$chain}};
+ foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) {
+ &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ }
+ foreach my $board (reverse sort keys %boards_handlers) {
+ my %board_handlers = %{$boards_handlers{$board}};
+ foreach my $handler_name (@{$board_defaults{$board}}) {
+ &{$board_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ foreach my $board (reverse sort keys %chains_handlers) {
+ my %chains_handlers2 = %{$chains_handlers{$board}};
+ foreach my $chain (reverse sort keys %chains_handlers2) {
+ my %chain_handlers = %{$chains_handlers2{$chain}};
+ foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) {
+ &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+ }
+ }
+ }
+ }
+}
+
+ # outputs/inputs not inverted, but activated, RESET deactivated and inverted (high)
+sub h_reload_boardsini {
+ my ($widget, $data) = @_;
+ init_msg("reload!\n");
+ system("./generate_chainorder.pl");
+ my $boardsfile= 'boards.ini';
+ my $chainsSettings = new Config::Abstract::Ini($boardsfile);
+ my %allboards = $chainsSettings->get_all_settings;
+
+ my $notebook_boards = Gtk2::Notebook->new;
+ my $main_vbox1 = $gladexml->get_widget('vbox1');
+ my @children = $main_vbox1->get_children;
+ $main_vbox1->remove($children[0]);
+ $main_vbox1->pack_start($notebook_boards, TRUE, TRUE, 0);
+ $main_vbox1->reorder_child($notebook_boards,0);
+ $main_vbox1->resize_children();
+# my $testframe = Gtk2::Frame->new;
+# my $testframe2 = Gtk2::Frame->new;
+# $notebook_boards->append_page($testframe, "Test 1");
+# $notebook_boards->append_page($testframe2, "Test 2");
+ my %boards_handlers;
+ my %chains_handlers;
+ foreach my $board (keys %allboards) {
+ my $gladexml3 = Gtk2::GladeXML->new('gui/design/buttons_BM_NP1_board_libglade.glade');
+ my %settings=%{$allboards{$board}};
+ my $chainsini = $settings{'chainsini'};
+ my $trbhostname = $settings{'FPGAboard_hostname'};
+ my $addonortrb = $settings{'FPGAboard_addonortrb'};
+ my $staplfilename = $settings{'FPGAboard_staplfilename'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $conf_period_addr = $settings{'CONFperiod_trbnetAddr'};
+ my $conf_offspillcounter_addr = $settings{'CONFoffspillcounter_trbnetAddr'};
+ my $conf_waitstart_addr = $settings{'CONFwaitstart_trbnetAddr'};
+ my $conf_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+ my @gui_defaults = split (/,/,$settings{'guiBM_NP_defaults'});
+ $board_defaults{$board} = \@gui_defaults;
+
+
+ my $vbox_board_chains = $gladexml3->get_widget('vbox_chains');
+ my $vbox_board_ = $gladexml3->get_widget('vbox_chains');
+
+ $chains_handlers{$board} = reload_chainsini($vbox_board_chains, $chainsini, $board);
+ my %board_handlers = ('h_prog_fpga' => generate_h_prog_fpga($board, $trbhostname, $addonortrb, $staplfilename),
+ 'h_start_trbnetd' => generate_h_start_trbnetd($board, $trbhostname),
+ 'h_waitbeforestart_6us' => generate_h_waitbeforestart_6us($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_waitbeforestart_1ms' => generate_h_waitbeforestart_1ms($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_waitbeforestart_1s' => generate_h_waitbeforestart_1s($board, $fpga_addr, $conf_waitstart_addr),
+ 'h_trigger_init_sequence' => generate_h_trig($board, $fpga_addr, $conf_triginitseq_addr),
+ 'h_maps_reset' => generate_h_trig($board, $fpga_addr, $conf_trigmapsreset_addr),
+ 'h_run_jtag' => generate_h_trig($board, $fpga_addr, $conf_trigrunjtag_addr),
+ 'h_write_once' => generate_h_trig($board, $fpga_addr, $conf_trigwriteonce_addr),
+ 'h_maps_start' => generate_h_trig($board, $fpga_addr, $conf_trigmapsstart_addr)
+
+ );
+ $boards_handlers{$board} = \%board_handlers;
+ $board_handlers{'h_set_standard'} = generate_h_set_standard(\%boards_handlers, \%chains_handlers);
+ $boards_handlers{$board} = \%board_handlers;
+ $gladexml3->signal_autoconnect_all(%board_handlers);
+ my $vbox_board = $gladexml3->get_widget('vbox_top');
+ $vbox_board->reparent($notebook_boards);
+ $notebook_boards->set_tab_label_text($vbox_board, "$board" );
+ }
+ $notebook_boards->show_all;
+}
+
+sub reload_chainsini {
+ my ($vbox_board_chains, $chainsfile, $board) = @_;
+ my %chains_handlers_hash;
+ #my $window = $widget->get_parent_window;
+ my @children = $vbox_board_chains->get_children;
+ $vbox_board_chains->remove($children[0]);
+ my $hbox_chains = Gtk2::HBox->new(FALSE, 2); # homogeneous, spacing 2
+ #$hbox_chains->set_size_request(300,200);
+ $vbox_board_chains->pack_start($hbox_chains, TRUE, TRUE, 0);
+ $vbox_board_chains->reorder_child($hbox_chains,0);
+ $vbox_board_chains->resize_children();
+
+ # START from ui.pl: modified to add GUI elements and to program only when clicked in gui.
+ # my $chainsfile= 'chains.ini';
+ my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+ my %allchains = $chainsSettings->get_all_settings;
+
+ my $date = strftime "%Y%m%d%H%M%S", localtime;
+ my $initmem_folder = "/tmp/jtag_initmem/$date";
+ if(-e $initmem_folder) {
+ die("Error: Folder with the same date already exists!");
+ }
+ mkdir $initmem_folder,0755;
+
+ # File with prefix names files for last programmed values
+ my $lastprogfilename = "/tmp/jtag_initmem/lastprog.txt";
+ my $handle_lastprog = FileHandle->new($lastprogfilename, 'w');
+
+ # loop through chains
+ foreach my $chain (reverse sort keys %allchains) {
+ #GUI stuff BEGIN
+ my $gladexml2 = Gtk2::GladeXML->new('gui/design/buttons_BM_NP1_libglade.glade');
+ my $vbox_top = $gladexml2->get_widget('vbox_top');
+ $vbox_top->reparent($hbox_chains);
+ $hbox_chains->pack_start($vbox_top, TRUE, TRUE, 0); # expand, fill, padding=0
+ # GUI stuff END
+ reportd $chain, ": ";
+ #print join ' ', %{$allchains{$chain}}, "\n";
+ my %settings=%{$allchains{$chain}};
+ my @sensors;
+ my @drs;
+ my @drs_length;
+ my @old_drs;
+ my @old_drs_length;
+ my @irs;
+ my $irlen;
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $conf_signals_addr = $settings{'CONFsignals_trbnetAddr'};
+ my $conf_resetafterfirstwrite_addr = $settings{'CONFresetafterfirstwrite_trbnetAddr'};
+ my $conf_resetbeforeinit_addr = $settings{'CONFresetbeforeinit_trbnetAddr'};
+ my $conf_chain_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_chain_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_chain_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_chain_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_chain_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+ my $chainnr = $settings{'chainnr'};
+ my @gui_defaults1 = split (/,/,$settings{'guiBM_NP_defaults1'});
+ my @gui_defaults2 = split (/,/,$settings{'guiBM_NP_defaults2'});
+ $chain_defaults{$board}{$chain} = \@gui_defaults1;
+ $chain_defaults2{$board}{$chain} = \@gui_defaults2;
+ #my $staplfilename_delay1 = $settings{'FPGAboard_staplfilename_delay1'};
+
+ #my $slowcontrol_hostname = $settings{'TRBNETslowcontrol_hostname'};
+
+ my $memfiles_prefix; # the same prefix is used for the files for one chain
+ # need one file per chip with at maximum 256 32 bit words
+ # that are written at once.
+ # then the RAM base pointer has to be changed for the next chip
+ my @memfilenames=();
+
+ $memfiles_prefix="$initmem_folder/$chain";
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ push(@sensors, $setting_name);
+ @old_drs = @drs;
+ @old_drs_length = @drs_length;
+ @irs = ();
+ @drs = ();
+ @drs_length = ();
+ my $sensorfile = $settings{$setting_name};
+ reportd "loading sensor file: $sensorfile\n";
+ my $sensorSettingsO = new Config::Abstract::Ini("/daq/toolbox/sensors/".$sensorfile);
+ my %sensorSettings = $sensorSettingsO->get_all_settings;
+ my $this_irlen = $sensorSettingsO->get_entry_setting('General', 'IRLEN', '5');
+ my $bypassreg = $sensorSettingsO->get_entry_setting('General', 'BYPASSREG', '1F');
+ if (!defined $irlen ){
+ $irlen = $this_irlen;
+ }
+ elsif($this_irlen != $irlen) {
+ reportd "this_irlen=$this_irlen in $sensorfile differs from previously set irlen=$irlen.\nThis should be supported by this version (trb_maps_jtag3) of the JTAG controller.\n But is it really intended?\n";
+ }
+ #print "irlen: ", $this_irlen, "\n";
+ # loop through data registers
+ my %sensorData = $sensorSettingsO->get_entry('Data');
+ foreach my $data_register_ir (sort keys %sensorData) {
+ my $value = $sensorData{$data_register_ir};
+ my ($ir,$drlength,$dr)= split(/,/, $value); # dr is stored MSN first as hexadecimal string
+ $dr = uc(trim($dr));
+ if(length($dr)%8 != 0) {
+ die("Error: DR string is not multiple of 32 bit (4bytes = 8 nibbles)\n");
+ }
+ if($dr =~ /[^0-9A-F]+/) {
+ die("Error: Invalid hexadecimal string for DR given: \$dr=\"$dr\"\n");
+ }
+ #print "drlength: $drlength\n";
+ push(@drs_length, $drlength);
+ push(@drs, $dr);
+ push(@irs, $ir);
+ # only warning
+ if((defined $old_drs_length[@drs-1]) && ($drlength != $old_drs_length[@drs-1])) {
+ reportd ("Warning: Length of the same DR of two sensors differs.\n");
+ }
+ }
+ my $memfilename = $memfiles_prefix . "." . $setting_name . ".txt";
+ if( -e ($memfilename)) {
+ die ("Error: RAM text file \"$memfilename\" exists.");
+ }
+ reportd "Opening $memfilename...\n";
+ my $handle = FileHandle->new($memfilename, 'w');
+ push(@memfilenames, $memfilename);
+ # write numregs + IRlen
+ my $word = scalar($this_irlen)<<16;
+ $word = $word + scalar @irs;
+ ### $word = ($word<<16) + pack("L", scalar(@irs));
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# IRlen & numregs \n";
+ #####print $handle "0x" .uc (substr(reverse(join('',unpack("h8", pack("L", scalar($this_irlen))))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar(@irs))))),4,4)) . "\t# IRlen & numregs \n";
+
+ #print "reverse test: " . reverse32bit(0x00000001)."\n";
+ my $initial = 0x00000000;
+ my $crcword = pack("L", reverse32bit($word));
+ my $crc0 = crc32($crcword, $initial);
+ #my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write DEV_ID
+ $word = 0x4D323601;
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# DEV_ID \n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write pointer
+ my $offset = 3*@irs+4;
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $drlen = $drs_length[$reg_i];
+ $word = $offset;
+ #print $handle "0x". uc (substr(reverse(join('',unpack("h8", pack("L", 0)))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar($offset))))),4,4)) . "\t# Pointer + reserved\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# Pointer + reserved \n";
+ $word = $drlen;
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+
+ #print $handle "0x0000". uc (substr(reverse(join('',unpack("h8", pack("L", scalar($drlen))))),4,4)) . "\t# Length\n";
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8",pack("L", $word)))),0,8)) . "\t# Length\n";
+ $offset += floor(($drlen+31)/32);
+ }
+ # write CRC-32
+ #my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+ $crc0_rn = ~reverse32bit($crc0);
+ #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+ my $line_crc = sprintf "%0.8X", $crc0_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ my $crc1 = 0xFFFFFFFF;
+ # write IRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $ir = $irs[$reg_i];
+ #my @words = unpack("L", pack("H*", uc($ir)));
+ $word = unpack("L", pack("h*", (scalar reverse uc($ir)) ."000000"));
+ #print "ir=$ir.IR word: $word\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($ir))).uc($ir) . "\t# IR\n";
+ }
+ # write BYPASSREG IR
+ $word = unpack("L", pack("h*", (scalar reverse uc($bypassreg)) ."000000"));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($bypassreg))).uc($bypassreg) . "\t# IR BYPASS\n";
+
+ # write DRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $length = $drs_length[$reg_i];
+ my $numwords = floor(($length+31)/32);
+ for(my $i=0;$i<$numwords; $i++) {
+ #print "length: $length\n";
+ #print "numwords: $numwords\n";
+
+ $word = unpack("L", pack("h*", (scalar reverse uc(substr($drs[$reg_i],($numwords-$i-1)*8,8)))));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ my $linestr = "0x". substr($drs[$reg_i],($numwords-$i-1)*8,8) . "\t# DR" . $reg_i . "\n";
+ print $handle $linestr;
+ }
+ }
+ #write CRC-32
+ my $crc1_rn = ~reverse32bit($crc1);
+ $line_crc = sprintf "%0.8X", $crc1_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ }
+ }
+ my $ref_h_prog_ram = generate_h_prog_ram($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, scalar @sensors, \@memfilenames);
+ my %handlers_hash = ('h_man_maps_reset'=>generate_h_man_maps_reset($chain, $fpga_addr, $conf_signals_addr),
+ #'h_prog_fpga_delay1' => generate_h_prog_fpga($chain, $trbhostname, $addonortrb, $staplfilename_delay1),
+ 'h_delay0' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 0),
+ 'h_delay1' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 1),
+ 'h_delay2' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 2),
+ 'h_delay3' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 3),
+ 'h_prog_ram' => $ref_h_prog_ram,
+ 'h_set_timing_10mhz' => generate_h_set_timing_10mhz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ 'h_set_timing_1mhz' => generate_h_set_timing_1mhz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ 'h_set_timing_100khz' => generate_h_set_timing_100khz($chain, $fpga_addr,$cmd_reg_addr, $data_reg_addr),
+ #'h_start' => generate_h_start($chain, $fpga_addr,$cmd_reg_addr),
+ #'h_stop' => generate_h_stop($chain, $fpga_addr,$cmd_reg_addr),
+ 'h_set_inout' => generate_h_set_inout($chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_reset_before_on' => generate_h_maps_reset(1,$chain, $chainnr, $fpga_addr, $conf_resetbeforeinit_addr),
+ 'h_maps_reset_before_off' => generate_h_maps_reset(0,$chain, $chainnr, $fpga_addr, $conf_resetbeforeinit_addr),
+ 'h_maps_reset_after_on' => generate_h_maps_reset(1,$chain, $chainnr, $fpga_addr, $conf_resetafterfirstwrite_addr),
+ 'h_maps_reset_after_off' => generate_h_maps_reset(0,$chain, $chainnr, $fpga_addr, $conf_resetafterfirstwrite_addr),
+ #'h_maps_start_on' => generate_h_maps_start(1,$chain, $fpga_addr, $conf_signals_addr),
+ #'h_maps_start_off' => generate_h_maps_start(0,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_clk_on' => generate_h_maps_clk_signal(1,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_maps_clk_off' => generate_h_maps_clk_signal(0,$chain, $fpga_addr, $conf_signals_addr),
+ 'h_trig_init_seq' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_triginitseq_addr),
+ 'h_maps_reset' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigmapsreset_addr),
+ 'h_run_jtag' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigrunjtag_addr),
+ 'h_write_once' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigwriteonce_addr),
+ 'h_maps_start' => generate_h_chain_trig($chain, $chainnr, $fpga_addr, $conf_chain_trigmapsstart_addr)
+ );
+ $gladexml2->signal_autoconnect_all(%handlers_hash);
+ my $label_chainnr = $gladexml2->get_widget('label_chainnr');
+ $label_chainnr->set_label($chain);
+ $chains_handlers_hash{$chain} = \%handlers_hash;
+ reportd "\n";
+ }
+ print $handle_lastprog $initmem_folder;
+
+ $hbox_chains->show_all;
+ return \%chains_handlers_hash;
+
+}
+
+
+# Boris
+sub exitclean{
+ Gtk2->main_quit();
+ exit (0);
+}
+
+
+
+
+$gladexml->signal_autoconnect_from_package('main');
+#$gladexml->signal_autoconnect_all ('h_reload_chainsini'=>\&h_reload_chainsini);
+#$quitbtn = $gladexml->get_widget('Quit');
+my $window1 = $gladexml->get_widget('window1');
+$window1->signal_connect(destroy => \&exitclean); #Boris
+$window1->show_all;
+Gtk2->main;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# #print "data registers for FPGA $fpga_addr:", map { "$_ => $drs_binary{$_}\n" } keys %drs_binary;
+# $drs_offset{$irs[0]} = 4+(scalar @irs)*2;
+# for (my $i=1;$i<@irs;$i++) {
+# my $dr_length = $drs_length{$irs[$i-1]};
+# $drs_offset{$irs[$i]} = $drs_offset{$irs[$i-1]} + floor(($dr_length*(scalar @sensors)+31)/32) + 2; # add one x 32 bit for CRC, one x 32 bit for IR, integer division rounds down, right?
+# }
+# #open RAMTEXT, ">$memfiles_prefix{$chain}";
+# $num_words = 0;
+# my $ram_fh;
+# my @mem_filenames;
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc (reverse(join('',unpack("h8", pack("L", scalar(@sensors)))))) . "\t# numchips \n"); # numchips; the reverse is done here because apparently internally the unsigned long is stored LSByte first (little endian)
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", 0))))) . "\t# reserved\n"); # reserved
+# for (my $i=0;$i<@irs;$i++) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_offset{$irs[$i]}))))) . "\t# pointer\n"); # pointer
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_length{$irs[$i]}))))) . "\t# length \n"); # length
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# pointer (end of list)\n");
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# length (end of list)\n");
+# for (my $i=0;$i<@irs;$i++) {
+# my $ir=$irs[$i];
+# #print "ir: $ir\n";
+# my $ir_packed = pack("h*", (scalar reverse($ir)).("0"x (7-(length($ir)-1)%8)));
+# my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+# #print "debug ir_packed (h*): ". (scalar reverse($ir)).("0"x (8-length($ir)%32))."\n";
+# #print "debug ir_packed_r (B*): ". scalar reverse unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+# #print "debug2: " . (7-(length($ir)-1)%8) . "\n";
+# #print "debug3: " . $ir . "\n";
+# #print "debug4: " . $ir.("0"x (7-(length($ir)-1)%8)) . "\n";
+# #print "debug5 (B*): ". unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+#
+# my $initial = 0x00000000;
+# my $crc0 = crc32($ir_packed_r, $initial);
+# #printf "CRC0: %X. ~reversed: %X\n", $crc0, $crc0_rn;
+#
+# for(my $i=0; $i<floor((length($drs_binary{$ir})-1)/32)+1;$i++){
+# my $dr_word_packed_r = pack("b*", scalar reverse substr($drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)),($i)*32, 32));
+# $crc0 = crc32($dr_word_packed_r, $crc0);
+# my $crc0_rn = ~reverse32bit($crc0);
+# printf "CRC: 0x%0.8X.\n", $crc0_rn;
+# }
+# my $crc0_rn = ~reverse32bit($crc0);
+# #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+# my $line_crc = sprintf "0x%0.8X\t# CRC-32\n", $crc0_rn;
+# print "debug dr_binary: " . $drs_binary{$ir} . "\n";
+# my $dr_packed = pack("b*", $drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)));
+# $drs{$ir} = unpack('h*', $dr_packed);
+# print "debug drs: " . $drs{$ir} . "\n";
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(8-length($ir))).uc($ir) . "\n");
+# for(my $i=0; $i<floor((length( $drs{$ir}) -1)/8)+1; $i++){
+# #print "dbg: i=$i, len=".length( $drs{$ir})."\n";
+# if(length($drs{$ir}) >= ($i+1)*8) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(substr($drs{$ir}, ($i)*8, 8))) . "\n");
+# }
+# else {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(($i+1)*8-length($drs{$ir}))).uc(reverse(substr($drs{$ir}, ($i)*8, length($drs{$ir})%8))) . "\n");
+# }
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, $line_crc);
+#
+# #print "IR $ir, DR ". $drs{$ir} . "\n";
+# }
+# #close RAMTEXT;
+# $ram_fh->close();
+# #my $result = `cat $memfile{$fpga_addr}`;
+# $ENV{'DAQOPSERVER'}="trb126";
+# for(my $i=0;$i<scalar @mem_filenames;$i++) {
+# # write RAM base pointer
+# my $ihex = int_to_32bit_hex($i);
+# print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
+# my $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+# print "set RAM base pointer: " . $result;
+# # write to configuration RAM
+# print "trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]\n";
+# $result = `trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]`;
+# print "write max. 256 32-bit-words: " . $result;
+# }
+#}
+
+
+# init_writemem:
+# - loop through chains
+# - loop through sensors
+# - test if IR length is the same as for other sensors
+# - loop through DRs
+# - test if DR length is the same as for other sensors
+# - add DR content to chain data register (hexadecimal string)
+# - write contents for JTAG chain controller RAM to text file(s)
+# - execute trbcmd to transfer file(s) to RAM of FPGA configured in chains.ini
+#
+# get_status:
+# get_error_counts:
+# reactivate_sensor:
+# deactivate_sensor:
--- /dev/null
+#!/bin/bash
+
+while true; do
+ trbcmd w 0xf013 0xc003 0x00000001
+ sleep 0.005
+done
--- /dev/null
+#!/bin/bash
+
+while true; do
+ trbcmd w 0xf013 0xc003 0x00000001
+ sleep 0.050
+done
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+use Getopt::Long;
+use Sys::Syslog;
+
+$ENV{DAQOPSERVER}='trb124';
+
+my $opt_help;
+my $opt_chain;
+my $opt_board;
+my $opt_operation;
+my $opt_addr;
+my $opt_quiet;
+my %chain_defaults = (); #('h_stop', 'h_delay0', 'h_prog_ram', 'h_set_timing_10mhz',,'h_set_inout');
+my %board_defaults = (); #('h_period_0_15s');
+my %chain_defaults2 = (); #('h_start');
+openlog("atomic,ui.pl", "perror", "local1");
+
+GetOptions ('h|help' => \$opt_help,
+ 'b|board=s' => \$opt_board,
+ 'c|chain=s' => \$opt_chain,
+ 'o|operation=s' => \$opt_operation,
+ 'a|addr=s' => \$opt_addr,
+ 'q|quiet' => \$opt_quiet
+ );
+if($opt_help or not defined $opt_board) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ syslog("debug", "showing usage information.");
+ print "Usage: ui.pl [-c <chain name> ] [-o <Operation>] [-a <address>]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+ [-b|--board <JTAG board name>] : Select the JTAG/MAIN board for setting signals. (use board01)
+ [-o|--operation <handle name from gui.pl without h_>] : Select operation (on the selected JTAG chain).
+ [-a|--addr <address for operation>] : read_ram1b_word needs address
+ [-q|--quiet ] : suppress informative output
+
+board operations (no chain parameter given):
+ prog_fpga : program FPGA on trb
+ start_trbnetd: start trbnet daemon on trb
+ waitbeforestart_6us: set wait before start time to 6 us
+ waitbeforestart_1ms: set wait before start time to 1 ms
+ waitbeforestart_1s: set wait before start time to 1 s
+ trigger_init_sequence: trigger initialization sequence for all chains,
+ 3xWRITE+1xREAD DEV ID, reset as configured
+ maps_reset: generate RESET pulse, all chains
+ run_jtag: Run 3xWRITE Registers+ 1xRead DEV ID, no reset, all chains
+ write_once: Once write all registers all chains
+ maps_start: generate START pulse, all chains
+
+chain operations (with -c parameter)
+ man_maps_reset: software generated reset pulse
+ delay0: set delay 0 JTAG Clock cycles
+ delay1: set delay 1 JTAG Clock cycles
+ delay2: set delay 2 JTAG Clock cycles
+ delay3: set delay 3 JTAG Clock cycles
+ prog_ram: Write from sensor*.ini to RAM with JTAG registers on FPGA
+ set_timing_10mhz: Set 10 MHz TCK
+ set_timing_1mhz: Set 1 MHz TCK
+ set_timing_100khz: Set 100 kHz TCK
+ set_inout: Initialize I/O pin settings (signals_invert)
+ maps_reset_before_on: set reset before first WRITE on trig_init_seq/trigger_init_sequence
+ maps_reset_before_off: set reset before ... off
+ maps_reset_after_on: set reset after ... on
+ maps_reset_after_off: set reset after ... off
+ maps_clk_on: activate MAPS CLK (80MHz) immediately
+ maps_clk_off: deactivate MAPS CLK (80MHz) immediately
+ trig_init_seq: trigger initialization sequence
+ maps_reset: generate RESET pulse
+ run_jtag: run JTAG (see board operation) this chain
+ write_once: write once all registers
+ maps_start: generate START pulse
+ read_ram1b_word: read 32 bit word at address given with -a option from ram1b CONNECTION REMOVED
+ read_ram1c_word: read 32 bit word at address given with -a option from ram1c
+ copy_ram1b1c: trigger copy of ram1b to ram1c
+
+
+";
+
+
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub report {
+ if(defined($opt_quiet)){
+ if($_[0] eq 'data') { print $_[1]; }
+ }
+ else {
+ print $_[1];
+ }
+}
+sub reportd {
+ if(!defined($opt_quiet)){
+ print "debug:" . $_[0];
+ }
+}
+sub init_msg {
+ if(!defined($opt_quiet)){
+ print $_[0];
+ }
+}
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ if(not open ( SHELL , "$command 2>&1 |" )) {
+ report( 'report_general' , "failed to execute command.");
+ syslog("ERR", "command failed.");
+ }
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ syslog("ERR", "unexpected output: $output.");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {
+ report('report_general', "command failed. output: $result");
+ syslog('ERR', "command failed. output: $result.");
+ }
+ return $result;
+}
+
+
+sub generate_h_read_ram1b_word {
+ my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1baddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1bdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+sub generate_h_read_ram1c_word {
+ my ($chain, $fpga_addr, $debug_ram1caddr, $debug_ram1cdata, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $debug_ram1caddr $addr", "");
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1cdata");
+ report('report_general', "regval: ". substr($regval, 8, 10). "\n");
+ report('data', substr($regval, 8, 10));
+ }
+}
+
+
+sub generate_h_copy_ram1b1c {
+ my ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $addr) = @_;
+ return sub {
+ init_msg( "read ram1b word " . $chain);
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x00000008", ""); # unconditional trigger
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000064", ""); # M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER
+ }
+}
+
+
+sub generate_h_man_maps_reset {
+ my ($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "manual reset chain " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $resetnormal = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal));
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ }
+}
+
+sub generate_h_maps_start_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg( "generate MAPS start $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<9)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<9)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_maps_reset_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("MAPS reset signal $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<11)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<11)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ }
+}
+sub generate_h_maps_clk_signal {
+ my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("generate MAPS clk $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
+
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<13)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<13)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ }
+}
+sub generate_h_prog_ram {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_;
+ my @memfilenames = @{$memfilenames_ref};
+ return sub {
+ init_msg("program RAM $chain.");
+ my $numchips_hex = int_to_32bit_hex($numsensors);
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", ""); # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ reportd "set RAM base pointer: \n";
+ execute_shell_command("trbcmd w $fpga_addr $ram_base_addr 0x$ihex", "");
+ # write to configuration RAM
+ reportd "write max. 256 32-bit-words: \n";
+ execute_shell_command("trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]", "");
+ }
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000009", ""); # CMD_START
+ }
+}
+
+sub generate_h_set_timing_10mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 10 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ #reportd $cmdline;
+ #system($cmdline);
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_1mhz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 1 MHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_set_timing_100khz {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
+ return sub {
+ init_msg("timing 100 kHz $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
+trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
+trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
+trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+
+
+sub generate_h_delay {
+ my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
+ return sub {
+ init_msg("Delay $delay $chain.");
+ my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
+trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
+ execute_shell_command($cmdline, "");
+ }
+}
+
+sub generate_h_waitbeforestart_6us {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 6us.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+sub generate_h_waitbeforestart_1ms {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1ms.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_waitbeforestart_1s {
+
+ my($board, $fpga_addr, $conf_waitstart_addr) = @_;
+ return sub {
+ init_msg("Wait before start $board 1s.");
+ if(!defined($conf_waitstart_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # Set time to wait after finished programming before sending MAPS_start
+ execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+
+ }
+}
+
+sub generate_h_maps_reset {
+ my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
+ return sub {
+ init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
+ # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
+ my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
+ reportd "regval: ". substr($regval, 8, 10). "\n";
+ my $before = substr($regval, 8, 10);
+# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
+ my $newval;
+ if($onoroff == 0) {
+ #off
+ $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
+ }
+ else {
+ #on
+ $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ }
+}
+
+
+sub generate_h_trig {
+ my ($board, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr " . $board);
+ # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ }
+}
+sub generate_h_chain_trig {
+ my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
+ return sub {
+ init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
+ # set bit in trigger register correspondig to chain-# $chainnr
+ my $newval;
+ $newval = int_to_32bit_hex(((1<<$chainnr)));
+ execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ }
+}
+
+
+
+sub generate_h_trigger_init_sequence {
+ my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_;
+ return sub {
+ init_msg("Send Trigger $board.");
+ if(!defined($conf_fet_trigger_addr)) {
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ # generate trigger
+ execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet
+ }
+}
+
+
+sub generate_h_set_inout {
+ my($chain, $fpga_addr, $conf_signals_addr) = @_;
+ return sub {
+ init_msg("Set IN/OUT $chain.");
+ if(!defined($conf_signals_addr)){
+ report('report_general', "TrbNet address missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ }
+}
+
+sub generate_h_prog_fpga {
+ my($board, $trbhostname, $addonortrb, $staplfilename) = @_;
+ return sub {
+ init_msg("Prog FPGA $board.");
+ if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){
+ report('report_general', "Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"",
+ "------------- Connection accepted -------------
+> return value of command: 0
+> stdout:
+Successful File Execution.
+------------- END OF OUTPUT ------------
+");
+ }
+}
+sub generate_h_prog_ram_external {
+ my ($chain) = @_;
+ return sub {
+ my $output = execute_shell_command_return("./ui_writeram.pl -c $chain");
+ #reportd $output;
+ }
+}
+
+
+sub generate_h_start_trbnetd {
+ my($board, $trbhostname) = @_;
+ return sub {
+ init_msg("Start trbnetd $board.");
+ if(!defined($trbhostname)){
+ report('report_general',"Settings missing. Doing nothing.\n");
+ return;
+ }
+ execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted -------------
+> return value of command: 0
+------------- END OF OUTPUT ------------
+");
+ }
+}
+
+# sub generate_h_set_standard {
+# my %boards_handlers = %{$_[0]};
+# my %chains_handlers = %{$_[1]};
+# return sub {
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# foreach my $board (reverse sort keys %boards_handlers) {
+# my %board_handlers = %{$boards_handlers{$board}};
+# foreach my $handler_name (@{$board_defaults{$board}}) {
+# &{$board_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# foreach my $board (reverse sort keys %chains_handlers) {
+# my %chains_handlers2 = %{$chains_handlers{$board}};
+# foreach my $chain (reverse sort keys %chains_handlers2) {
+# my %chain_handlers = %{$chains_handlers2{$chain}};
+# foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) {
+# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash
+# }
+# }
+# }
+# }
+# }
+
+my $boardsfile= 'boards.ini';
+my $boardsSettings = new Config::Abstract::Ini($boardsfile);
+my %allboards = $boardsSettings->get_all_settings;
+foreach my $board (keys %allboards) {
+ my %settings=%{$allboards{$board}};
+ my $chainsini = $settings{'chainsini'};
+ my $trbhostname = $settings{'FPGAboard_hostname'};
+ my $addonortrb = $settings{'FPGAboard_addonortrb'};
+ my $staplfilename = $settings{'FPGAboard_staplfilename'};
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $conf_period_addr = $settings{'CONFperiod_trbnetAddr'};
+ my $conf_offspillcounter_addr = $settings{'CONFoffspillcounter_trbnetAddr'};
+ my $conf_waitstart_addr = $settings{'CONFwaitstart_trbnetAddr'};
+ my $conf_triginitseq_addr = $settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_trigmapsreset_addr = $settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_trigrunjtag_addr = $settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_trigwriteonce_addr = $settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_trigmapsstart_addr = $settings{'CONFtrigmapsstart_trbnetAddr'};
+
+
+ if(defined($opt_board) and not defined($opt_chain)) {
+ # assume board command
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_prog_fpga') {
+ $subr = generate_h_prog_fpga($board, $trbhostname, $addonortrb, $staplfilename)
+ }
+ elsif(("h_".$opt_operation) eq 'h_start_trbnetd'){
+ $subr = generate_h_start_trbnetd($board, $trbhostname);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_6us' ) {
+ $subr = generate_h_waitbeforestart_6us($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1ms' ) {
+ $subr = generate_h_waitbeforestart_1ms($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_waitbeforestart_1s' ) {
+ $subr = generate_h_waitbeforestart_1s($board, $fpga_addr, $conf_waitstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trigger_init_sequence' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_trig($board, $fpga_addr, $conf_trigmapsstart_addr);
+ }
+ if(!defined($opt_quiet)){ print "Starting Board Operation.\n"; }
+ &{$subr}();
+ exit(0);
+ }
+
+
+ my $chainsSettings = new Config::Abstract::Ini($chainsini);
+ my %allchains = $chainsSettings->get_all_settings;
+ if(!defined($allchains{$opt_chain})) { die ("Chain $opt_chain not found.");}
+# foreach my $chain (reverse sort keys %allchains) {
+ my $chain = $opt_chain;
+ my %chain_settings=%{$allchains{$chain}};
+ my $chain_fpga_addr = $chain_settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $chain_settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $chain_settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $chain_settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $chain_settings{'DATAreg_trbnetAddr'};
+ my $conf_signals_addr = $chain_settings{'CONFsignals_trbnetAddr'};
+ my $conf_resetafterfirstwrite_addr = $chain_settings{'CONFresetafterfirstwrite_trbnetAddr'};
+ my $conf_resetbeforeinit_addr = $chain_settings{'CONFresetbeforeinit_trbnetAddr'};
+ my $conf_chain_triginitseq_addr = $chain_settings{'CONFtriginitseq_trbnetAddr'};
+ my $conf_chain_trigmapsreset_addr = $chain_settings{'CONFtrigmapsreset_trbnetAddr'};
+ my $conf_chain_trigrunjtag_addr = $chain_settings{'CONFtrigrunjtag_trbnetAddr'};
+ my $conf_chain_trigwriteonce_addr = $chain_settings{'CONFtrigwriteonce_trbnetAddr'};
+ my $conf_chain_trigmapsstart_addr = $chain_settings{'CONFtrigmapsstart_trbnetAddr'};
+ my $debug_chain_ram1baddr_addr = $chain_settings{'DEBUGram1baddr'};
+ my $debug_chain_ram1bdata_addr = $chain_settings{'DEBUGram1bdata'};
+ my $debug_chain_ram1caddr_addr = $chain_settings{'DEBUGram1caddr'};
+ my $debug_chain_ram1cdata_addr = $chain_settings{'DEBUGram1cdata'};
+ my $chainnr = $chain_settings{'chainnr'};
+ my $subr;
+ if(("h_".$opt_operation) eq 'h_man_maps_reset') {
+ $subr = generate_h_man_maps_reset($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay0' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 0);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay1' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 1);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay2' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 2);
+ }
+ elsif(("h_".$opt_operation) eq 'h_delay3' ) {
+ $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 3);
+ }
+ elsif(("h_".$opt_operation) eq 'h_prog_ram' ) {
+ $subr = generate_h_prog_ram_external($chain);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_10mhz' ) {
+ $subr = generate_h_set_timing_10mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_1mhz' ) {
+ $subr = generate_h_set_timing_1mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_timing_100khz' ) {
+ $subr = generate_h_set_timing_100khz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_set_inout' ) {
+ $subr = generate_h_set_inout($chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_before_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetbeforeinit_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_on' ) {
+ $subr = generate_h_maps_reset(1,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset_after_off' ) {
+ $subr = generate_h_maps_reset(0,$chain, $chainnr, $chain_fpga_addr, $conf_resetafterfirstwrite_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_on' ) {
+ $subr = generate_h_maps_clk_signal(1,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_clk_off' ) {
+ $subr = generate_h_maps_clk_signal(0,$chain, $chain_fpga_addr, $conf_signals_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_trig_init_seq' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_triginitseq_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_reset' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsreset_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_run_jtag' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigrunjtag_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_write_once' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigwriteonce_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_maps_start' ) {
+ $subr = generate_h_chain_trig($chain, $chainnr, $chain_fpga_addr, $conf_chain_trigmapsstart_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1b_word' ) {
+ $subr = generate_h_read_ram1b_word($chain, $chain_fpga_addr, $debug_chain_ram1baddr_addr, $debug_chain_ram1bdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_read_ram1c_word' ) {
+ $subr = generate_h_read_ram1c_word($chain, $chain_fpga_addr, $debug_chain_ram1caddr_addr, $debug_chain_ram1cdata_addr, $opt_addr);
+ }
+ elsif(("h_".$opt_operation) eq 'h_copy_ram1b1c' ) {
+ $subr = generate_h_copy_ram1b1c($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr);
+ }
+
+ if(!defined($opt_quiet)){ print "Starting Chain Operation.\n"; }
+ &{$subr}();
+
+}
--- /dev/null
+./ui_set_standard_settings_board.sh
+./ui_set_standard_settings_chain1.sh
+./ui_set_standard_settings_chain2.sh
+./ui_set_standard_settings_chain3.sh
--- /dev/null
+./ui.pl -b board01 -o waitbeforestart_6us
--- /dev/null
+./ui.pl -b board01 -c chain1 -o "delay1"
+./ui.pl -b board01 -c chain1 -o "prog_ram"
+./ui.pl -b board01 -c chain1 -o "set_timing_10mhz"
+./ui.pl -b board01 -c chain1 -o "set_inout"
+./ui.pl -b board01 -c chain1 -o "maps_reset_before_off"
+./ui.pl -b board01 -c chain1 -o "maps_reset_after_on"
+
--- /dev/null
+./ui.pl -b board01 -c chain2 -o "delay1"
+./ui.pl -b board01 -c chain2 -o "prog_ram"
+./ui.pl -b board01 -c chain2 -o "set_timing_10mhz"
+./ui.pl -b board01 -c chain2 -o "set_inout"
+./ui.pl -b board01 -c chain2 -o "maps_reset_before_off"
+./ui.pl -b board01 -c chain2 -o "maps_reset_after_on"
+
--- /dev/null
+./ui.pl -b board01 -c chain3 -o "delay1"
+./ui.pl -b board01 -c chain3 -o "prog_ram"
+./ui.pl -b board01 -c chain3 -o "set_timing_10mhz"
+./ui.pl -b board01 -c chain3 -o "set_inout"
+./ui.pl -b board01 -c chain3 -o "maps_reset_before_off"
+./ui.pl -b board01 -c chain3 -o "maps_reset_after_on"
+
--- /dev/null
+#!/bin/bash
+./ui.pl -b board01 -o trigger_init_sequence
--- /dev/null
+#!/usr/bin/perl
+use strict;
+use warnings;
+use lib "./libs/";
+use Config::Abstract::Ini;
+use POSIX qw(strftime);
+use FileHandle;
+use Sys::Syslog;
+openlog("atomic,ui_writeram.pl", "", "local1");
+syslog("INFO", "starting ui_writeram.pl");
+
+use Getopt::Long;
+
+my $opt_help;
+my $opt_chain;
+my $opt_quiet;
+GetOptions ('h|help' => \$opt_help,
+ 'c|chain=s' => \$opt_chain,
+ 'q|quiet' => \$opt_quiet
+ );
+if($opt_help) {
+ &help();
+ exit(0);
+}
+
+
+
+sub help(){
+ print "Usage: ui_writeram.pl [-c <chain name> ]
+
+required:
+ [-c|--chain <JTAG chain name>] : Select the JTAG chain (controller) whose RAM should be written.
+ [-q|--quiet] : suppress output
+"
+}
+
+#push(@INC, "./BN");
+#use lib "$ENV{PWD}/BN";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/";
+#use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch";
+
+use lib "BN/blib/arch";
+use BN::CRC32;
+#use String::CRC32;
+
+#use feature "state";
+use POSIX;
+
+# whitespace trimming from http://www.somacon.com/p114.php
+# Declare the subroutines
+sub trim($);
+sub ltrim($);
+sub rtrim($);
+
+# Create a test string
+my $string = " \t Hello world! ";
+
+# Here is how to output the trimmed text "Hello world!"
+#print trim($string)."\n";
+#print ltrim($string)."\n";
+#print rtrim($string)."\n";
+
+# Perl trim function to remove whitespace from the start and end of the string
+sub trim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ $string =~ s/\s+$//;
+ return $string;
+}
+# Left trim function to remove leading whitespace
+sub ltrim($)
+{
+ my $string = shift;
+ $string =~ s/^\s+//;
+ return $string;
+}
+# Right trim function to remove trailing whitespace
+sub rtrim($)
+{
+ my $string = shift;
+ $string =~ s/\s+$//;
+ return $string;
+}
+
+sub reverse32bit($) {
+ my ($in) = @_;
+ my $result = unpack("L", pack("B*", scalar reverse unpack("B*", pack("L",$in))));
+ return $result;
+ #return 1;
+}
+
+sub int_to_32bit_hex($) {
+ my ($in) = @_;
+ my $hex = sprintf("%.8X", $in);
+ return $hex;
+}
+
+sub report {
+ if(defined($opt_quiet)){
+ if($_[0] eq 'data') { print $_[1]; }
+ }
+ else {
+ print $_[1];
+ }
+}
+sub reportd {
+ if(!defined($opt_quiet)){
+ print "debug:" . $_[0];
+ }
+}
+sub execute_shell_command {
+ # input args: $command, $expected_output #, $success_string, $sending_button
+
+ my $success = 0;
+ my $command = $_[0];
+ my $expected = $_[1];
+ my $output = "";
+ #my $success_string = $_[1];
+ #my $sending_button = $_[2];
+
+ #my $message= $sending_button->get_label;
+ #reportd ( 'report_general', "attempting to $message");
+ report( 'report_detailed' , "\nexec $command\n\n");
+ if(not open ( SHELL , "$command 2>&1 |" )) {
+ report( 'report_general' , "failed to execute command.");
+ syslog("ERR", "command failed.");
+ }
+
+ while ( <SHELL> ) {
+ report( 'report_detailed' , $_);
+ $output.=$_;
+# if ( $_ =~ m/$success_string/ ) {
+# report( 'report_general' , " ...success!\n" );
+# my $success = 1;
+# }
+ }
+# if ($success == 0) {
+# report( 'report_general', " ...unclear\n");
+# }
+ if(!($output eq $expected)) {
+ report('report_general', "unexpected output: ".$output."\n");
+ syslog("ERR", "unexpected output: $output.");
+ }
+ report( 'report_detailed' , "\n----------------------------\n");
+}
+
+
+sub execute_shell_command_return {
+ my $command = $_[0];
+ report( 'report_detailed' , "\nexec $command\n\n");
+ my $result = `$command 2>&1`;
+ report( 'report_detailed' , $result);
+ report( 'report_detailed' , "\n----------------------------\n");
+ if($? != 0) {
+ report('report_general', "command failed. output: $result");
+ syslog('ERR', "command failed. output: $result.");
+ }
+ return $result;
+}
+
+
+
+my $num_words = 0;
+
+# this subroutine
+# changes parameter 0, which holds the file handle
+sub memfile_writeline($$$$) {
+ my($memfile, $memfilenames, $memfiles_prefix, $line_string)=@_;
+ my $filenum = floor($num_words/256);
+ my $last_filenum = floor(($num_words-1)/256);
+ my $filenum_str = sprintf "%0.2d", $filenum;
+ my $memfilename = $memfiles_prefix.'.'.$filenum_str.".txt";
+
+ if((!defined $_[0])) {
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ elsif($filenum!=$last_filenum) {
+ $memfile->close();
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfile\" exists.");
+ }
+ $_[0] = FileHandle->new($memfilename, 'w');
+ push(@{$_[1]}, $memfilename);
+ }
+ my $fh = $_[0];
+ print $fh $line_string;
+ $num_words++;
+}
+
+if(not( -e "/tmp/jtag_initmem")) {
+ system("mkdir /tmp/jtag_initmem");
+}
+
+my $chainsfile= 'chains.ini';
+my $chainsSettings = new Config::Abstract::Ini($chainsfile);
+my %allchains = $chainsSettings->get_all_settings;
+
+my $date = strftime "%Y%m%d%H%M%S", localtime;
+#my $initmem_folder = "/tmp/jtag_initmem/$date";
+my $initmem_folder = "/tmp/jtag_initmem/jtag_atomic";
+
+if(-e $initmem_folder) {
+ #die("Error: Folder with the same date already exists!");
+}
+else {
+ mkdir $initmem_folder,0755;
+}
+
+# File with prefix names files for last programmed values
+my $lastprogfilename = "/tmp/jtag_initmem/lastprog.txt";
+my $handle_lastprog = FileHandle->new($lastprogfilename, 'w');
+
+# loop through chains
+foreach my $chain (keys %allchains) {
+ if(defined($opt_chain) && not ($chain eq $opt_chain)) {
+ next;
+ }
+ print $chain, ": ";
+ #print join ' ', %{$allchains{$chain}}, "\n";
+ my %settings=%{$allchains{$chain}};
+ my @sensors;
+ my @drs;
+ my @drs_length;
+ my @old_drs;
+ my @old_drs_length;
+ my @irs;
+ my $irlen;
+ my $fpga_addr = $settings{'FPGAtrbnetAddr'};
+ my $ram_addr = $settings{'RAMtrbnetAddr'};
+ my $cmd_reg_addr = $settings{'CMDreg_trbnetAddr'};
+ my $ram_base_addr = $settings{'RAMbase_trbnetAddr'};
+ my $data_reg_addr = $settings{'DATAreg_trbnetAddr'};
+ my $memfiles_prefix; # the same prefix is used for the files for one chain
+ # need one file per chip with at maximum 256 32 bit words
+ # that are written at once.
+ # then the RAM base pointer has to be changed for the next chip
+ my @memfilenames=();
+
+ $memfiles_prefix="$initmem_folder/$chain";
+ foreach my $setting_name (sort keys %settings) {
+ if ($setting_name =~ /sensor[0-9]+/) {
+ push(@sensors, $setting_name);
+ @old_drs = @drs;
+ @old_drs_length = @drs_length;
+ @irs = ();
+ @drs = ();
+ @drs_length = ();
+ my $sensorfile = $settings{$setting_name};
+ if(not defined($opt_quiet)) { print "loading sensor file: $sensorfile\n"; }
+ my $sensorSettingsO = new Config::Abstract::Ini("/daq/toolbox/sensors/".$sensorfile);
+ my %sensorSettings = $sensorSettingsO->get_all_settings;
+ my $this_irlen = $sensorSettingsO->get_entry_setting('General', 'IRLEN', '5');
+ my $bypassreg = $sensorSettingsO->get_entry_setting('General', 'BYPASSREG', '1F');
+ if (!defined $irlen ){
+ $irlen = $this_irlen;
+ }
+ elsif($this_irlen != $irlen) {
+ print "this_irlen=$this_irlen in $sensorfile differs from previously set irlen=$irlen.\nThis should be supported by this version (trb_maps_jtag3) of the JTAG controller.\n But is it really intended?\n";
+ }
+ #print "irlen: ", $this_irlen, "\n";
+ # loop through data registers
+ my %sensorData = $sensorSettingsO->get_entry('Data');
+ foreach my $data_register_ir (sort keys %sensorData) {
+ my $value = $sensorData{$data_register_ir};
+ my ($ir,$drlength,$dr)= split(/,/, $value); # dr is stored MSN first as hexadecimal string
+ $dr = uc(trim($dr));
+ if(length($dr)%8 != 0) {
+ die("Error: DR string is not multiple of 32 bit (4bytes = 8 nibbles)\n");
+ }
+ if($dr =~ /[^0-9A-F]+/) {
+ die("Error: Invalid hexadecimal string for DR given: \$dr=\"$dr\"\n");
+ }
+ #print "drlength: $drlength\n";
+ push(@drs_length, $drlength);
+ push(@drs, $dr);
+ push(@irs, $ir);
+ # only warning
+ if((defined $old_drs_length[@drs-1]) && ($drlength != $old_drs_length[@drs-1])) {
+ print ("Warning: Length of the same DR of two sensors differs.");
+ }
+ }
+ my $memfilename = $memfiles_prefix . "." . $setting_name . ".txt";
+ if( -e ($memfilename)) {
+ #die ("Error: RAM text file \"$memfilename\" exists.");
+ }
+ if( not defined($opt_quiet)) { print "Opening $memfilename...\n"; }
+ my $handle = FileHandle->new($memfilename, 'w');
+ push(@memfilenames, $memfilename);
+ # write numregs + IRlen
+ my $word = scalar($this_irlen)<<16;
+ $word = $word + scalar @irs;
+ ### $word = ($word<<16) + pack("L", scalar(@irs));
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# IRlen & numregs \n";
+ #####print $handle "0x" .uc (substr(reverse(join('',unpack("h8", pack("L", scalar($this_irlen))))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar(@irs))))),4,4)) . "\t# IRlen & numregs \n";
+
+ #print "reverse test: " . reverse32bit(0x00000001)."\n";
+ my $initial = 0x00000000;
+ my $crcword = pack("L", reverse32bit($word));
+ my $crc0 = crc32($crcword, $initial);
+ #my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write DEV_ID
+ $word = 0x4D323601;
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# DEV_ID \n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ my $crc0_rn = ~reverse32bit($crc0);
+ #printf "crc0: %0.8X, crc0_rn: %0.8X, word: %0.8X\n", $crc0, $crc0_rn, $word;
+ # write pointer
+ my $offset = 3*@irs+4;
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $drlen = $drs_length[$reg_i];
+ $word = $offset;
+ #print $handle "0x". uc (substr(reverse(join('',unpack("h8", pack("L", 0)))),4,4)) . uc (substr(reverse(join('',unpack("h8", pack("L", scalar($offset))))),4,4)) . "\t# Pointer + reserved\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8", pack("L", $word)))),0,8)) . "\t# Pointer + reserved \n";
+ $word = $drlen;
+ $crcword = pack("L", reverse32bit($word));
+ $crc0 = crc32($crcword, $crc0);
+
+ #print $handle "0x0000". uc (substr(reverse(join('',unpack("h8", pack("L", scalar($drlen))))),4,4)) . "\t# Length\n";
+ print $handle "0x" . uc (substr(reverse(join('',unpack("h8",pack("L", $word)))),0,8)) . "\t# Length\n";
+ $offset += floor(($drlen+31)/32);
+ }
+ # write CRC-32
+ #my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+ $crc0_rn = ~reverse32bit($crc0);
+ #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+ my $line_crc = sprintf "%0.8X", $crc0_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ my $crc1 = 0xFFFFFFFF;
+ # write IRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $ir = $irs[$reg_i];
+ #my @words = unpack("L", pack("H*", uc($ir)));
+ $word = unpack("L", pack("h*", (scalar reverse uc($ir)) ."000000"));
+ #print "ir=$ir.IR word: $word\n";
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($ir))).uc($ir) . "\t# IR\n";
+ }
+ # write BYPASSREG IR
+ $word = unpack("L", pack("h*", (scalar reverse uc($bypassreg)) ."000000"));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ print $handle "0x".("0"x(8-length($bypassreg))).uc($bypassreg) . "\t# IR BYPASS\n";
+
+ # write DRs
+ for(my $reg_i=0;$reg_i<@irs;$reg_i++) {
+ my $length = $drs_length[$reg_i];
+ my $numwords = floor(($length+31)/32);
+ for(my $i=0;$i<$numwords; $i++) {
+ #print "length: $length\n";
+ #print "numwords: $numwords\n";
+
+ $word = unpack("L", pack("h*", (scalar reverse uc(substr($drs[$reg_i],($numwords-$i-1)*8,8)))));
+ $crcword = pack("L", reverse32bit($word));
+ $crc1 = crc32($crcword, $crc1);
+ my $linestr = "0x". substr($drs[$reg_i],($numwords-$i-1)*8,8) . "\t# DR" . $reg_i . "\n";
+ print $handle $linestr;
+ }
+ }
+ #write CRC-32
+ my $crc1_rn = ~reverse32bit($crc1);
+ $line_crc = sprintf "%0.8X", $crc1_rn;
+ print $handle "0x". substr($line_crc,length($line_crc)-8,8) . "\t# CRC-32\n";
+
+ }
+ }
+ my $numchips_hex = int_to_32bit_hex(scalar @sensors);
+ #if(not defined($opt_quiet)) { print "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1\n"; } # CMD_STOP
+ #my $result = `trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 \n`; # CMD_STOP
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP
+ #if(not($? == 0)) {syslog("ERR", "trbcmd returned $?. Output: $result.")}
+ #if(not defined($opt_quiet)) { print "trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex\n"; } # ADDR_CONTROL_DATA_REGISTER
+ #$result = `trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex 2>&1\n`; # ADDR_CONTROL_DATA_REGISTER
+ execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER
+ #if(not defined($opt_quiet)) { print "trbcmd w $fpga_addr $cmd_reg_addr 0x00000033\n"; } # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ #$result = `trbcmd w $fpga_addr $cmd_reg_addr 0x00000033\n`; # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", "");
+ for(my $i=0;$i<scalar @memfilenames;$i++) {
+
+ # write RAM base pointer
+ my $ihex = int_to_32bit_hex($i);
+ if(not defined($opt_quiet)) { print "set RAM base pointer: \n"; }
+ #if(not defined($opt_quiet)) { print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n"; }
+ #$result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+ execute_shell_command("trbcmd w $fpga_addr $ram_base_addr 0x$ihex", "");
+ # write to configuration RAM
+ if(not defined($opt_quiet)) { print "write max. 256 32-bit-words: \n"; }
+ #if(not defined($opt_quiet)) { print "trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]\n"; }
+ #$result = `trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]`;
+ execute_shell_command("trbcmd wm $fpga_addr $ram_addr 0 $memfilenames[$i]", "");
+ }
+ #if(not defined($opt_quiet)){ print "trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n"; } # CMD_START
+ #$result = `trbcmd w $fpga_addr $cmd_reg_addr 0x00000009\n`; # CMD_START
+ execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000009", ""); # CMD_START
+
+ if(not defined($opt_quiet)) { print "\n"; }
+ print "done.\n";
+ syslog("INFO", "$chain done.\n");
+}
+print $handle_lastprog $initmem_folder;
+# #print "data registers for FPGA $fpga_addr:", map { "$_ => $drs_binary{$_}\n" } keys %drs_binary;
+# $drs_offset{$irs[0]} = 4+(scalar @irs)*2;
+# for (my $i=1;$i<@irs;$i++) {
+# my $dr_length = $drs_length{$irs[$i-1]};
+# $drs_offset{$irs[$i]} = $drs_offset{$irs[$i-1]} + floor(($dr_length*(scalar @sensors)+31)/32) + 2; # add one x 32 bit for CRC, one x 32 bit for IR, integer division rounds down, right?
+# }
+# #open RAMTEXT, ">$memfiles_prefix{$chain}";
+# $num_words = 0;
+# my $ram_fh;
+# my @mem_filenames;
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc (reverse(join('',unpack("h8", pack("L", scalar(@sensors)))))) . "\t# numchips \n"); # numchips; the reverse is done here because apparently internally the unsigned long is stored LSByte first (little endian)
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", 0))))) . "\t# reserved\n"); # reserved
+# for (my $i=0;$i<@irs;$i++) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_offset{$irs[$i]}))))) . "\t# pointer\n"); # pointer
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_length{$irs[$i]}))))) . "\t# length \n"); # length
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# pointer (end of list)\n");
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# length (end of list)\n");
+# for (my $i=0;$i<@irs;$i++) {
+# my $ir=$irs[$i];
+# #print "ir: $ir\n";
+# my $ir_packed = pack("h*", (scalar reverse($ir)).("0"x (7-(length($ir)-1)%8)));
+# my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
+# #print "debug ir_packed (h*): ". (scalar reverse($ir)).("0"x (8-length($ir)%32))."\n";
+# #print "debug ir_packed_r (B*): ". scalar reverse unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+# #print "debug2: " . (7-(length($ir)-1)%8) . "\n";
+# #print "debug3: " . $ir . "\n";
+# #print "debug4: " . $ir.("0"x (7-(length($ir)-1)%8)) . "\n";
+# #print "debug5 (B*): ". unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
+#
+# my $initial = 0x00000000;
+# my $crc0 = crc32($ir_packed_r, $initial);
+# #printf "CRC0: %X. ~reversed: %X\n", $crc0, $crc0_rn;
+#
+# for(my $i=0; $i<floor((length($drs_binary{$ir})-1)/32)+1;$i++){
+# my $dr_word_packed_r = pack("b*", scalar reverse substr($drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)),($i)*32, 32));
+# $crc0 = crc32($dr_word_packed_r, $crc0);
+# my $crc0_rn = ~reverse32bit($crc0);
+# printf "CRC: 0x%0.8X.\n", $crc0_rn;
+# }
+# my $crc0_rn = ~reverse32bit($crc0);
+# #printf "CRC: %0.8X.\n", $crc0_rn, 1;
+# my $line_crc = sprintf "0x%0.8X\t# CRC-32\n", $crc0_rn;
+# print "debug dr_binary: " . $drs_binary{$ir} . "\n";
+# my $dr_packed = pack("b*", $drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)));
+# $drs{$ir} = unpack('h*', $dr_packed);
+# print "debug drs: " . $drs{$ir} . "\n";
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(8-length($ir))).uc($ir) . "\n");
+# for(my $i=0; $i<floor((length( $drs{$ir}) -1)/8)+1; $i++){
+# #print "dbg: i=$i, len=".length( $drs{$ir})."\n";
+# if(length($drs{$ir}) >= ($i+1)*8) {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(substr($drs{$ir}, ($i)*8, 8))) . "\n");
+# }
+# else {
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(($i+1)*8-length($drs{$ir}))).uc(reverse(substr($drs{$ir}, ($i)*8, length($drs{$ir})%8))) . "\n");
+# }
+# }
+# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, $line_crc);
+#
+# #print "IR $ir, DR ". $drs{$ir} . "\n";
+# }
+# #close RAMTEXT;
+# $ram_fh->close();
+# #my $result = `cat $memfile{$fpga_addr}`;
+# $ENV{'DAQOPSERVER'}="trb126";
+# for(my $i=0;$i<scalar @mem_filenames;$i++) {
+# # write RAM base pointer
+# my $ihex = int_to_32bit_hex($i);
+# print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
+# my $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
+# print "set RAM base pointer: " . $result;
+# # write to configuration RAM
+# print "trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]\n";
+# $result = `trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]`;
+# print "write max. 256 32-bit-words: " . $result;
+# }
+#}
+
+
+# init_writemem:
+# - loop through chains
+# - loop through sensors
+# - test if IR length is the same as for other sensors
+# - loop through DRs
+# - test if DR length is the same as for other sensors
+# - add DR content to chain data register (hexadecimal string)
+# - write contents for JTAG chain controller RAM to text file(s)
+# - execute trbcmd to transfer file(s) to RAM of FPGA configured in chains.ini
+#
+# get_status:
+# get_error_counts:
+# reactivate_sensor:
+# deactivate_sensor:
--- /dev/null
+# Current Setup (reorder by sensor number!!!)
+# connected module position support Deactivated (comma separated) old value
+
+key setup
+
+sensor1 on A down cvd ---- abcd
+sensor2 on A up cvd ---- ----
+sensor3 on B down cvd ---- ----
+sensor4 off B up cvd ---- abcd
+
+sensor8 on D down DUT d d
+sensor7 on D up DUT ---- abcd
+sensor5 on C down DUT ---- abcd
+sensor6 on C up DUT 374 374
+
+sensor9 on E down alu ---- abcd
+sensor10 on E up alu ---- ----
+sensor11 off F down alu ---- abcd
+sensor12 on F up alu ---- ----
+
+============================================================================================================================================
+
+
+
+# Sensor Threshold
+# Nightrun
+
+key thresholds
+sensor1 193 176 139 171
+sensor2 169 210 222 162 0.93/1.03/0.82/1.07
+sensor3 169 193 211 196 65.7/0.84/0.87/0.87 - Block A has always 64 pixel offset due to one damaged row
+sensor4 255 255 255 255 shut down not used
+
+sensor5 108 211 167 210 0.76/0.85/0.88/0.75
+sensor6 184 202 215 192 16.7/17.0/15.2/18.3 used but +8 ADCs
+sensor7 152 181 230 182 5.4/3.8/4.9/4.7 used but +8 ADCs
+sensor8 166 124 183 255 1.04/2.09/0.81 - Block D always noisy, Block B has one dead pixel => 1.09
+
+sensor9 144 117 101 237 13.1/11.2/15.7/13.9 not used
+sensor10 189 237 178 229 0.7/0.63/0.54/0.57
+sensor11 255 255 255 255 not connected not used
+sensor12 185 193 180 211 0.74/0.70/0.80/0.69
+
+
+
+====================================================================
+
+
+
+# Module status (reorder by plane position!!!)
+# shifted angle switched
+
+key module
+
+A no 0 0
+B yes 0 0
+D yes 0 0
+C yes 0 0
+E no 0 0
+F no 0 1
+
+====================================================================
+
+
+
+# Sensor IDs (HEX)
+#
+
+key id
+
+sensor1 aaa0
+sensor2 aaa1
+sensor3 bbb0
+sensor4 bbb1
+
+sensor5 ccc0
+sensor6 ccc1
+sensor7 ddd0
+sensor8 ddd1
+
+sensor9 eee0
+sensor10 eee1
+sensor11 fff0
+sensor12 fff1
+
+=============================
+
+
+
+# JTAG table
+# chain JNR Panel
+
+key jtag
+
+sensor1 chain1 3 1.1
+sensor2 chain1 2 1.2
+sensor3 chain1 1 1.4
+sensor4 chain1 0 1.5
+
+sensor5 chain2 3 1.7
+sensor6 chain2 2 1.8
+sensor7 chain2 1 4.1
+sensor8 chain2 0 4.2
+
+sensor9 chain3 2 4.3
+sensor10 chain3 1 4.4
+sensor11 chain3 F 4.5
+sensor12 chain3 0 4.6
+
+====================================================
+
+
+
+# ROC table
+# ROC Port
+
+key roc
+
+sensor1 0xc001 0
+sensor2 0xc001 1
+sensor3 0xc001 2
+sensor4 0xc001 3
+
+sensor5 0xc002 0
+sensor6 0xc002 1
+sensor7 0xc002 2
+sensor8 0xc002 3
+
+sensor9 0xc003 0
+sensor10 0xc003 1
+sensor11 0xc003 2
+sensor12 0xc003 3
+
+==================================
+
+
+
+
+
+
+# Some notes
+#
+
+key notation
+
+Temperature R L = Sensor 1 2
+ROC sensor 0 1 2 3 = id reg c0_LSB c0_MSB c1_LSB c1_MSB
+
+Coordinates:
+
+(x,y) - flipped coordinates
+
+(1) Standard (1,2,3,4,8,9,10,12) (2) DUT plane D 7,8 - flipped twice (X and Y) (2) DUT plane C 5,6 - just flipped around Y
+
+ |-----------| |-----------| |-----------|
+ |1152 | |576 0,0| | 1152|
+ | |-- --| | --| |
+ | | (1) | | (0) | | (1)
+ | |-- --| | --| |
+ |0,0 576| | 1152| |576 0,0|
+ |-----------| |-----------| |-----------|
+ |-----------| |-----------| |-----------|
+ |1152 | |576 0,0| | 1152|
+ | |-- --| | --| |
+ | | (0) | | (1) | | (0)
+ | |-- --| | --| |
+ |0,0 576| | 1152| |576 0,0|
+ |-----------| |-----------| |-----------|
+
+
+
+
+Boris Threshold FakeHitRate at 1/frame
+sensor1 193 176 139 171
+sensor2 175 218 226 169
+sensor3 200 206 212 196
+sensor4 200 206 212 196
+
+sensor5 114 216 172 214
+sensor6 191 201 219 199
+sensor7 153 176 228 179
+sensor8 174 130 188 247
+
+sensor9 165 129 112 249
+sensor10 189 237 178 229
+sensor11 255 255 255 255
+sensor12 185 193 180 211
+
+Boris Threshold FakeHitRate as before but + 2mv (high threshold)
+sensor1 201 184 147 178
+sensor2 183 226 234 177
+sensor3 208 214 220 204
+sensor4 208 214 220 204
+
+sensor5 122 224 180 222
+sensor6 199 209 227 207
+sensor7 161 184 236 187
+sensor8 182 138 196 255
+
+sensor9 173 137 120 255
+sensor10 197 245 186 237
+sensor11 255 255 255 255
+sensor12 193 201 188 219
+
+Samir threshold +1mV
+sensor1 205 188 151 182
+sensor2 187 230 238 181
+sensor3 212 218 224 208
+sensor4 212 218 224 208
+
+sensor5 126 228 184 226
+sensor6 203 213 231 211
+sensor7 165 188 240 191
+sensor8 186 142 200 255
+
+sensor9 177 141 124 255
+sensor10 201 249 190 241
+sensor11 255 255 255 255
+sensor12 197 205 192 223
+
+------------------
+DUT Tuning 10^6
+
+sensor8 174 132 190 255 gives fakehit rates 0.16/1.18/0.18 for A,B,C but B has always 1 hot pixel
+sensor5 114 217 174 215 gives fakehit rates 0.14/0.12/0.18/0.12 for A,B,C,D
+sensor2 175 218 226 170 0.16/0.16/0.16/0.16
+sensor3 180 199 218 201 36.3/8.3/0.09/0.22 One row is always broken
+sensor10 190 236 177 227 0.23/0.26/0.18/0.27
+sensor12 185 191 178 209 0.13/0.18/0.13/0.19
+
+
+
+High Thresholds:
+sensor1 205 188 151 182
+sensor2 187 230 238 181
+sensor3 212 218 224 208
+sensor4 212 218 224 208
+
+sensor5 126 228 184 226
+sensor6 203 213 231 211
+sensor7 165 188 240 191
+sensor8 186 142 200 255
+
+sensor9 177 141 124 255
+sensor10 201 249 190 241
+sensor11 255 255 255 255
+sensor12 197 205 192 223
+
+
+Setting from night wednsday->thursday
+sensor1 205 188 151 182
+sensor2 175 218 226 170
+sensor3 180 199 218 201
+sensor4 212 218 224 208
+
+sensor5 114 217 174 215
+sensor6 203 213 231 211
+sensor7 165 188 240 191
+sensor8 174 132 190 255
+
+sensor9 177 141 124 255
+sensor10 190 236 177 227
+sensor11 255 255 255 255
+sensor12 185 191 178 209
+
+
+Fakehit Rates 10^5 at DUT cooled to 0 deg
+sensor1 174 161 124 156 15.6/12.5/29.3/13.6 - Block C has always 16 pixel offset => 13.3
+sensor2 161 204 217 155 14.7/11.6/9.8/12.8
+sensor3 160 184 203 186 74.0/16.3/14.9/17.0 - Block A has always 31 pixel offset due to one damaged row
+sensor4 255 255 255 255 shut down
+
+sensor5 099 205 162 203 16.4/11.2/10.5/14.6
+sensor6 176 194 207 184 16.7/17.0/15.2/18.3
+sensor7 146 173 222 174 5.4/3.8/4.9/4.7 - Fakehit Rate varies, seems to be some weird common noise
+sensor8 157 116 174 255 15.7/19.5/13.9 - Block D always noisy
+
+sensor9 144 117 101 237 13.1/11.2/15.7/13.9
+sensor10 174 225 167 217 2.0/2.6/2.3/3.3 - Fakehit Rate varies, seems to be some weird common noise
+sensor11 255 255 255 255 not connected
+sensor12 171 183 168 199 9.3/7.7/5.9/6.8 - Fakehit Rate varies, seems to be some weird common noise
+
+
+Fakehit Rates 10^6 at DUT cooled to 0 deg
+sensor1 174 161 124 156 15.6/12.5/29.3/13.6 not used
+sensor2 169 210 222 162 0.93/1.03/0.82/1.07
+sensor3 169 193 211 196 65.7/0.84/0.87/0.87 - Block A has always 64 pixel offset due to one damaged row
+sensor4 255 255 255 255 shut down not used
+
+sensor5 108 211 167 210 0.76/0.85/0.88/0.75
+sensor6 176 194 207 184 16.7/17.0/15.2/18.3 not used
+sensor7 146 173 222 174 5.4/3.8/4.9/4.7 not used
+sensor8 166 124 183 255 1.04/2.09/0.81 - Block D always noisy, Block B has one dead pixel => 1.09
+
+sensor9 144 117 101 237 13.1/11.2/15.7/13.9 not used
+sensor10 181 230 171 222 0.7/0.63/0.54/0.57
+sensor11 255 255 255 255 not connected not used
+sensor12 178 189 174 206 0.74/0.70/0.80/0.69
+
+
+Boris Optimized for the high datarate run
+sensor1 174 161 124 156 15.6/12.5/29.3/13.6 not used
+sensor2 169 210 222 162 0.93/1.03/0.82/1.07
+sensor3 169 193 211 196 65.7/0.84/0.87/0.87 - Block A has always 64 pixel offset due to one damaged row
+sensor4 255 255 255 255 shut down not used
+
+sensor5 108 211 167 210 0.76/0.85/0.88/0.75
+sensor6 176 194 207 184 16.7/17.0/15.2/18.3 not used
+sensor7 146 173 222 174 5.4/3.8/4.9/4.7 not used
+sensor8 166 124 183 255 1.04/2.09/0.81 - Block D always noisy, Block B has one dead pixel => 1.09
+
+sensor9 144 117 101 237 13.1/11.2/15.7/13.9 not used
+sensor10 181 230 171 222 0.7/0.63/0.54/0.57
+sensor11 255 255 255 255 not connected not used
+sensor12 178 189 174 206 0.74/0.70/0.80/0.69
+
+Boris Optimized for the high datarate run and noise
+sensor1 174 161 124 156 15.6/12.5/29.3/13.6 not used
+sensor2 173 214 226 166 0.31/0.40/0.13/0.42
+sensor3 173 197 215 200 55.5/0.36/0.30/0.30 - Block A has always 64 pixel offset due to one damaged row
+sensor4 255 255 255 255 shut down not used
+
+sensor5 112 215 171 214 0.26/0.17/0.22/0.15
+sensor6 176 194 207 184 16.7/17.0/15.2/18.3 not used
+sensor7 146 173 222 174 5.4/3.8/4.9/4.7 not used
+sensor8 170 128 187 255 0.39/1.35/0.33 - Block D always noisy, Block B has one dead pixel
+
+sensor9 144 117 101 237 13.1/11.2/15.7/13.9 not used
+sensor10 185 234 175 226 0.16/0.10/0.09/0.16
+sensor11 255 255 255 255 not connected not used
+sensor12 182 193 179 210 0.30/0.15/0.16/0.14
+
+
+==============================================================================================
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064C1B08BAB32648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000082 ; RO_MODE0 BORIS TESTMODE
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, Boris
+;02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,00D00008FC00E000 ; CTRL_SUZE_REG: BORIS TESTMODE
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, on the CVD
+09=10,1152,a0a0a0a0a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,a0a0a0a0a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064BDEDB2E532648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064FFFFFFFF32648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064B9C1B4D332648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064B4E48AD732768020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064A9D2DEA232648020280A0A0A0A64
+;00=0F,152,006432202064AFDAE2A932648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; Some column on the broken CVD sensor
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064A9C1D3C432648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064FFFFFFFF32648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,0064322020646CD3A7D232648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064B8CAD7C032648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,00643220206498B5E6B632648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064A67CB7FF32648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, Boris
+;02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, on the CVD
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
--- /dev/null
+[General]
+IRLEN=5
+BYPASSREG=1F
+[Data]
+00=0F,152,006432202064907565ED32648020280A0A0A0A64
+;00=0F,152,006432202064FFFFFFFF32768020280A0A0A0A64
+;00=0F,152,0064322020649ECD74C532768020280A0A0A0A5F Bertrams LAST
+;00=0F,152,006432202064B8E3ADD032768020280A0A0A0A64
+;00=0F,152,006432202064B8E1AECE32768020280A0A0A0A64
+;00=0F,152,006432202064A9BFB1D132768020280A0A0A0A64
+; 18171615141312111009080706050403020100
+01=1E,8,00000002 ; RO_MODE0 en ext start
+;01=1E,8,00000006 ; RO_MODE0 pattern only + en ext start
+;1=1E,8,00000012 ; RO_MODE0, En_LineMarker
+;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1
+02=1D,8,00000000 ; RO_MODE1, basic configuration value
+;02=1D,8,00000001 ; RO_MODE1, EnTestDiscri = 1
+03=13,40,0000000023F00000 ; CTRL_PIX_REG, basic configuration value
+04=12,128,7FFF004001C03C00001C60007FFFFFFF ; changed f->7 boris
+;04=12,128,FFFF004001C03C00001C6000FFFFFFFF ; SEQUENCER_PIX_REG, basic configuration value
+05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit
+;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit)
+;06=17,48,000000D8FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, entestdatadisc, En_scan, En_auto_scan_discri
+06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout (basic configuration value, and fe55)
+;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two
+;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1
+07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value
+08=11,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset slot
+;08=11,1152,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+;08=11,1152,00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI, autoset by create_rawdata.pl!
+09=10,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE0_PATTERN_REG
+10=14,1152,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; LINE1_PATTERN_REG
+;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5
+;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit
+
+
+;00=0F,152,006432202064A6D899D832768020280A0A0A0A64 FPC12_R light on
+;00=0F,152,006432202064ADDE9FE132768020280A0A0A0A64 FPC12_R light off
+
+;00=0F,152,006432202064A280710132768020280A0A0A0A5F FPC12_L light off
+
+;00=0F,152,006432202064B8E183D532768020280A0A0A0A5F FPC13_R recalib manually by BN
+
+
+;00=0F,152,006432202064AED883D132768020280A0A0A0A64 Boris recalib CVD sensor (both on 1 FEB)
\ No newline at end of file
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+
+entity blank_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_BLANK_IN : std_logic;
+ -- RAM
+ RAM_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAM_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAM_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end entity;
+
+
+architecture blank_ram_arch of blank_ram is
+type state_type is (IDLE, BLANKING);
+signal state, state_next : state_type;
+signal ram_a, ram_a_next : std_logic_vector(ram_depth-1 downto 0);
+constant ram_data : std_logic_vector(ram_width-1 downto 0) := (others => '0');
+signal ram_we, ram_we_next : std_logic;
+constant addr_end : std_logic_vector(ram_depth-1 downto 0) := (others => '1'); -- this should be a constant
+begin
+--wordcounter_end <= (others => '1'); -- maximum RAM address
+IDLE_OUT <= '1' when state = IDLE else '0';
+RAM_A_OUT <= ram_a;
+RAM_WR_OUT <= ram_we;
+RAM_D_OUT <= ram_data;
+SYNCHRONOUS: process(CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ state <= idle;
+ ram_a <= (others => '0');
+ ram_we <= '0';
+ else
+ state <= state_next;
+ ram_a <= ram_a_next;
+ ram_we <= ram_we_next;
+ end if;
+ end if;
+end process;
+
+COMB: process (state, TRIGGER_BLANK_IN, ram_a )
+begin
+ ram_a_next <= ram_a;
+ state_next <= state;
+ ram_we_next <= '0';
+
+ case state is
+ when IDLE =>
+ if(TRIGGER_BLANK_IN = '1') then
+ ram_a_next <= (others => '0');
+ ram_we_next <= '1';
+ state_next <= BLANKING;
+ end if;
+ when BLANKING =>
+ -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous??
+ ram_a_next <= std_logic_vector(unsigned(ram_a)+1); -- word 1
+ ram_we_next <= '1';
+ if(ram_a = addr_end) then
+ state_next <= IDLE;
+ end if;
+ end case;
+end process;
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+
+entity copy_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_COPY_IN : std_logic;
+ -- RAM3a
+ RAMA_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMA_D_IN : in std_logic_vector(ram_width-1 downto 0);
+ -- RAM3b
+ RAMB_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMB_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAMB_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end entity;
+
+
+architecture copy_ram_arch of copy_ram is
+type state_type is (IDLE, READ0, READ1, WRITE_I);
+signal state, state_next : state_type;
+signal rama_a, rama_a_next : std_logic_vector(ram_depth-1 downto 0);
+signal ramb_a, ramb_a_next : std_logic_vector(ram_depth-1 downto 0);
+signal ramb_data, ramb_data_next : std_logic_vector(ram_width-1 downto 0);
+signal ramb_we, ramb_we_next : std_logic;
+constant addr_end : std_logic_vector(ram_depth-1 downto 0) := (others => '1'); -- this should be a constant
+begin
+--wordcounter_end <= (others => '1'); -- maximum RAM address
+IDLE_OUT <= '1' when state = idle else '0';
+RAMA_A_OUT <= rama_a;
+RAMB_A_OUT <= ramb_a;
+RAMB_WR_OUT <= ramb_we;
+RAMB_D_OUT <= ramb_data;
+SYNCHRONOUS: process(CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ state <= idle;
+ rama_a <= (others => '0');
+ ramb_a <= (others => '0');
+ ramb_data <= (others => '0');
+ ramb_we <= '0';
+ else
+ state <= state_next;
+ rama_a <= rama_a_next;
+ ramb_a <= ramb_a_next;
+ ramb_data <= ramb_data_next;
+ ramb_we <= ramb_we_next;
+ end if;
+ end if;
+end process;
+
+COMB: process (state, TRIGGER_COPY_IN, RAMA_D_IN, rama_a, ramb_a, ramb_data )
+begin
+ rama_a_next <= rama_a;
+ ramb_a_next <= ramb_a;
+ ramb_data_next <= ramb_data;
+ state_next <= state;
+ ramb_we_next <= '0';
+
+ case state is
+ when IDLE =>
+ if(TRIGGER_COPY_IN = '1') then
+ rama_a_next <= (others => '0');
+ state_next <= READ0;
+ end if;
+ when READ0 =>
+ -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous??
+ rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 1
+ state_next <= READ1;
+ when READ1 =>
+ -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous??
+ rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 2
+ ramb_a_next <= (others => '0'); -- ramb_a should become zero in two clock cycles
+ ramb_data_next <= RAMA_D_IN;
+ ramb_we_next <= '1';
+ state_next <= WRITE_I;
+ when WRITE_I =>
+ rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 3, 4,...
+ -- write word to RAMB
+ ramb_a_next <= std_logic_vector(unsigned(ramb_a)+1);
+ ramb_data_next <= RAMA_D_IN;
+ ramb_we_next <= '1';
+ if(ramb_a = addr_end) then
+ state_next <= IDLE; --last word is written during idle
+ end if;
+ end case;
+end process;
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+library work;
+
+entity CRC_32 is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ CRC_OUT : out std_logic_vector(31 downto 0);
+ CRC_match : out std_logic
+ );
+end entity;
+
+-- architecture CRC32_disabled of CRC32 is
+-- begin
+-- CRC_match <= '1';
+-- CRC_OUT <= (others=>'0');
+-- end architecture;
+
+
+-------------------------------------------------------------------------------
+-- Copyright (C) 2009 OutputLogic.com
+-- This source file may be used and distributed without restriction
+-- provided that this copyright statement is not removed from the file
+-- and that any derivative work contains the original copyright notice
+-- and the associated disclaimer.
+--
+-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+-------------------------------------------------------------------------------
+-- CRC module for data(31:0)
+-- lfsr(31:0)=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture imp_crc32 of CRC_32 is
+ signal lfsr_q: std_logic_vector (31 downto 0);
+ signal lfsr_c: std_logic_vector (31 downto 0);
+begin
+ CRC_OUT <= lfsr_q;
+
+ lfsr_c(0) <= lfsr_q(0) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(12) xor lfsr_q(16) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(12) xor DATA_IN(16) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31);
+ lfsr_c(1) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(28) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(28);
+ lfsr_c(2) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(30) xor DATA_IN(31);
+ lfsr_c(3) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(31);
+ lfsr_c(4) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(15) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(15) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31);
+ lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(28) xor lfsr_q(29) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(28) xor DATA_IN(29);
+ lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(14) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(25) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(14) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(25) xor DATA_IN(29) xor DATA_IN(30);
+ lfsr_c(7) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(28) xor lfsr_q(29) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(28) xor DATA_IN(29);
+ lfsr_c(8) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(17) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(17) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(28) xor DATA_IN(31);
+ lfsr_c(9) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(18) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(29) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(18) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(29);
+ lfsr_c(10) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(19) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(19) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(11) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(20) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(20) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(31);
+ lfsr_c(12) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(30) xor DATA_IN(31);
+ lfsr_c(13) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(22) xor lfsr_q(25) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(22) xor DATA_IN(25) xor DATA_IN(28) xor DATA_IN(31);
+ lfsr_c(14) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(23) xor lfsr_q(26) xor lfsr_q(29) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(23) xor DATA_IN(26) xor DATA_IN(29);
+ lfsr_c(15) <= lfsr_q(3) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(30) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(30);
+ lfsr_c(16) <= lfsr_q(0) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(8) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(0) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(8) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(29) xor DATA_IN(30);
+ lfsr_c(17) <= lfsr_q(1) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(30) xor DATA_IN(31);
+ lfsr_c(18) <= lfsr_q(2) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(2) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(31);
+ lfsr_c(19) <= lfsr_q(3) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(29) xor DATA_IN(3) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(29);
+ lfsr_c(20) <= lfsr_q(4) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(4) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(30);
+ lfsr_c(21) <= lfsr_q(5) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(22) <= lfsr_q(0) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(23) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(24) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(30);
+ lfsr_c(25) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(26) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(10) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(10) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(31);
+ lfsr_c(27) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(11) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor DATA_IN(1) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(11) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29);
+ lfsr_c(28) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(8) xor lfsr_q(12) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(2) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(8) xor DATA_IN(12) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(30);
+ lfsr_c(29) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(3) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31);
+ lfsr_c(30) <= lfsr_q(4) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(4) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30);
+ lfsr_c(31) <= lfsr_q(5) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(5) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31);
+
+ process(lfsr_q) begin
+ if(lfsr_q = 0) then
+ CRC_match <= '1';
+ else
+ CRC_match <= '0';
+ end if;
+ end process;
+
+ process (CLK,RESET) begin
+ if (RESET = '1') then
+ lfsr_q <= b"11111111111111111111111111111111";
+ elsif (rising_edge(CLK)) then
+ if (CLK_EN = '1') then
+ lfsr_q <= lfsr_c;
+ end if;
+ end if;
+ end process;
+end architecture imp_crc32;
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 9.2.04i
+-- \ \ Application : xaw2vhdl
+-- / / Filename : dcm3.vhd
+-- /___/ /\ Timestamp : 06/24/2011 15:30:54
+-- \ \ / \
+-- \___\/\___\
+--
+--Command: xaw2vhdl-intstyle /d/sugar/bneumann/vhdl/jtag_proj/ise9_tempproj/tempproj1/dcm3.xaw -st dcm3.vhd
+--Design Name: dcm3
+--Device: xc4vlx40-10ff1148
+--
+-- Module dcm3
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.018 UI
+-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.222 ns
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity dcm3 is
+ port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end dcm3;
+
+architecture BEHAVIORAL of dcm3 is
+ signal CLKFB_IN : std_logic;
+ signal CLKFX_BUF : std_logic;
+ signal CLK0_BUF : std_logic;
+ signal GND_BIT : std_logic;
+ signal GND_BUS_7 : std_logic_vector (6 downto 0);
+ signal GND_BUS_16 : std_logic_vector (15 downto 0);
+begin
+ GND_BIT <= '0';
+ GND_BUS_7(6 downto 0) <= "0000000";
+ GND_BUS_16(15 downto 0) <= "0000000000000000";
+ CLK0_OUT <= CLKFB_IN;
+ CLKFX_BUFG_INST : BUFG
+ port map (I=>CLKFX_BUF,
+ O=>CLKFX_OUT);
+
+ CLK0_BUFG_INST : BUFG
+ port map (I=>CLK0_BUF,
+ O=>CLKFB_IN);
+
+ DCM_ADV_INST : DCM_ADV
+ generic map( CLK_FEEDBACK => "1X",
+ CLKDV_DIVIDE => 2.0,
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 4,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 10.000,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ DCM_AUTOCALIBRATION => TRUE,
+ DCM_PERFORMANCE_MODE => "MAX_SPEED",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ DFS_FREQUENCY_MODE => "LOW",
+ DLL_FREQUENCY_MODE => "LOW",
+ DUTY_CYCLE_CORRECTION => TRUE,
+ FACTORY_JF => x"F0F0",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map (CLKFB=>CLKFB_IN,
+ CLKIN=>CLKIN_IN,
+ DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
+ DCLK=>GND_BIT,
+ DEN=>GND_BIT,
+ DI(15 downto 0)=>GND_BUS_16(15 downto 0),
+ DWE=>GND_BIT,
+ PSCLK=>GND_BIT,
+ PSEN=>GND_BIT,
+ PSINCDEC=>GND_BIT,
+ RST=>RST_IN,
+ CLKDV=>open,
+ CLKFX=>CLKFX_BUF,
+ CLKFX180=>open,
+ CLK0=>CLK0_BUF,
+ CLK2X=>open,
+ CLK2X180=>open,
+ CLK90=>open,
+ CLK180=>open,
+ CLK270=>open,
+ DO=>open,
+ DRDY=>open,
+ LOCKED=>LOCKED_OUT,
+ PSDONE=>open);
+
+end BEHAVIORAL;
+
+
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+use work.jtag_misc.all;\r
+\r
+entity jtag_bypassreg_testchain_m10 is\r
+ generic (\r
+-- delay : integer := 0; -- this is the same value as in jtag_delay_expected_values\r
+ MAX_NUMCHIPS : integer;\r
+ MAX_NUMCHIPS_LD : integer;\r
+ JTAG_M26_IRLEN : integer;\r
+ \r
+ max_bitcounter_ld : integer;-- set to: MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-- bitcounter counts to ir_fill_ones_length, to zerofill_length aswell as from begin of sending pattern to end of receiving pattern (zerofill_length). should write something like: max(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD, 7)+1.\r
+\r
+ ld_maxdelay : integer := 2; -- floor of ld maxdelay\r
+ pattern_length : integer := 4;\r
+ pattern : std_logic_vector(4-1 downto 0) := "1001";\r
+ zerofill_numzeros_required : integer := 5 -- minimum number of zeros appearing at tdo while first zero filling phase\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ \r
+ BEGIN_JTAGBITCALC_IN : in std_logic;\r
+ TRIGGER_BEGIN_TESTCHAIN_IN : in std_logic;\r
+ IDLE_OUT : out std_logic;\r
+ \r
+ -- length in chips of the chain -- corresponds to the number of bits the\r
+ -- output is shifted compared to the input, because the BYPASS registers\r
+ -- are selected, which are only one bit long\r
+ CHAIN_LENGTH_OUT : out std_logic_vector(max_bitcounter_ld-1 downto 0);\r
+ -- if after feeding in a sufficiently long sequence \r
+ -- the expected output pattern doesnt occur\r
+ CHAIN_BROKEN_OUT : out std_logic;\r
+ \r
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;\r
+ LAST_TCK_CYCLE_OUT : out std_logic;\r
+ TMS_OUT : out std_logic;\r
+ TDI_OUT : out std_logic;\r
+ TDO_IN : in std_logic;\r
+ DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0)\r
+ );\r
+end entity;\r
+\r
+\r
+architecture jtag_bypassreg_testchain_m10_arch of jtag_bypassreg_testchain_m10 is\r
+constant ir_fill_ones_length : integer := MAX_NUMCHIPS*JTAG_M26_IRLEN+100;\r
+constant zerofill_length : integer := MAX_NUMCHIPS + 10;\r
+\r
+signal bitcounter, bitcounter_next : unsigned(max_bitcounter_ld-1 downto 0);\r
+signal nfa_state, nfa_state_next : std_logic_vector (pattern_length-1 downto 0);\r
+signal input_bit : std_logic;\r
+\r
+\r
+-- COPIED FROM jtag_write_m10:\r
+-- this state controls the global behaviour. on reset state idle is entered,\r
+-- on trigger wait_begin_jtagbitcalc is entered\r
+-- when begin_jtagbitcalc is set, state becomes either idle or \r
+-- processing and after finished wait_begin_jtagbitcalc is entered again\r
+type state_type is (IDLE, WAIT_BEGIN_JTAGBITCALC, PROCESSING);\r
+signal state, state_next : state_type;\r
+-- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz.\r
+type substate_type is (none_p1, ir_ones_p1, dr_zeros_p1, dr_pattern_p1, dr_pattern2_p2);\r
+signal substate, substate_next : substate_type;\r
+-- COPIED FROM jtag_write_m10:\r
+-- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": WRITE_DR, operation = "11": none\r
+-- the operation is set on entering processing state, in setup operation is set to none\r
+signal operation, operation_next : unsigned(1 downto 0);\r
+-- COPIED FROM jtag_write_m10, modified\r
+-- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset\r
+-- WRITE_IR: operation_phase = 0000 : set TMS=0 => Run-Test/Idle\r
+-- operation_phase = 0001 : set TMS=1 => Select-DR-Scan\r
+-- operation_phase = 0010 : set TMS=1 => Select-IR-Scan\r
+-- operation_phase = 0011 : set TMS=0 => Capture-IR\r
+-- operation_phase = 0100 : set TMS=0 => Shift-IR\r
+-- operation_phase = 0101 : set TMS=0 => Shift-IR, HERE SHIFTING OF DATA HAPPENS\r
+-- operation_phase = 0110 : set TMS=1 => Exit1-IR, HERE LAST BIT OF IR IS SHIFTED\r
+-- operation_phase = 0111 : set TMS=1 => Update-IR\r
+-- operation_phase = 1000 : set TMS=0 => Run-Test/Idle\r
+-- WRITE_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan\r
+-- operation_phase = 0001 : set TMS=0 => Capture-DR\r
+-- operation_phase = 0010 : set TMS=0 => Shift-DR\r
+-- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, shift zeros\r
+-- operation_phase = 0100 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, shift pattern followed by zeros\r
+-- operation_phase = 0101 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED\r
+-- operation_phase = 0110 : set TMS=1 => Update-DR\r
+-- operation_phase = 0111 : set TMS=0 => Run-Test/Idle\r
+-- warning: operation phase may change during processing (because length of register is retrieved from RAM)\r
+-- but will settle from setOutputs_p8 on\r
+signal operation_phase, operation_phase_next : unsigned(3 downto 0);\r
+\r
+-- helper signals\r
+signal tmp_input_vect : std_logic;\r
+signal pattern_detected : std_logic;\r
+-- other signals\r
+signal last_tck_cycle, last_tck_cycle_next : std_logic;\r
+signal zerocounter, zerocounter_next : unsigned (max_bitcounter_ld-1 downto 0);\r
+signal chain_broken, chain_broken_next : std_logic;\r
+signal chain_length, chain_length_next : std_logic_vector (max_bitcounter_ld-1 downto 0);\r
+-- should a JTAG clock pulse be generated this global_jtag_counter cycle?\r
+signal enable_jtag_clock, enable_jtag_clock_next : std_logic; \r
+-- JTAG output signal: TDI\r
+signal tdi, tdi_next : std_logic;\r
+\r
+-- JTAG output signal: TMS\r
+signal tms, tms_next : std_logic;\r
+\r
+-- INSERTLABEL: signals\r
+begin\r
+-- helper signals\r
+--tmp_input_vect <= (others => input_bit); -- doesn't work\r
+pattern_detected <= nfa_state(pattern_length-1);\r
+input_bit <= TDO_IN;\r
+CHAIN_BROKEN_OUT <= chain_broken;\r
+CHAIN_LENGTH_OUT <= chain_length;\r
+IDLE_OUT <= '1' when state = idle else '0';\r
+ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock;\r
+LAST_TCK_CYCLE_OUT <= last_tck_cycle;\r
+TMS_OUT <= tms;\r
+TDI_OUT <= tdi;\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ bitcounter <= (others =>'0');\r
+ nfa_state <= (others => '0');\r
+ last_tck_cycle <= '0';\r
+ zerocounter <= (others => '0');\r
+ state <= IDLE;\r
+ substate <= none_p1; \r
+ chain_broken <= '1';\r
+ chain_length <= (others => '0');\r
+ enable_jtag_clock <= '0';\r
+ tdi <= '0';\r
+ tms <= '0'; \r
+ operation <= "11";\r
+ operation_phase <= "0000";\r
+ -- INSERTLABEL: SYNCHRONOUS reset\r
+ else\r
+ bitcounter <= bitcounter_next;\r
+ nfa_state <= nfa_state_next;\r
+ last_tck_cycle <= last_tck_cycle_next;\r
+ zerocounter <= zerocounter_next;\r
+ state <= state_next;\r
+ substate <= substate_next; \r
+ chain_broken <= chain_broken_next;\r
+ chain_length <= chain_length_next;\r
+ enable_jtag_clock <= enable_jtag_clock_next;\r
+ tdi <= tdi_next;\r
+ tms <= tms_next;\r
+ operation <= operation_next;\r
+ operation_phase <= operation_phase_next; \r
+ -- INSERTLABEL: SYNCHRONOUS update\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(bitcounter, input_bit, nfa_state,last_tck_cycle,zerocounter,state, TRIGGER_BEGIN_TESTCHAIN_IN, BEGIN_JTAGBITCALC_IN, operation, operation_phase, substate, enable_jtag_clock, chain_broken, chain_length, tdi, tms, pattern_detected, DELAY_IN ) -- INSERTLABEL: sensitivity list\r
+begin\r
+ bitcounter_next <= bitcounter;\r
+ last_tck_cycle_next <= last_tck_cycle;\r
+ zerocounter_next <= zerocounter;\r
+ state_next <= state;\r
+ substate_next <= substate;\r
+ operation_next <= operation;\r
+ operation_phase_next <= operation_phase;\r
+ enable_jtag_clock_next <= enable_jtag_clock;\r
+ nfa_state_next <= nfa_state;\r
+ chain_broken_next <= chain_broken;\r
+ chain_length_next <= chain_length;\r
+ tdi_next <= tdi;\r
+ tms_next <= tms;\r
+ \r
+ -- INSERTLABEL: COMB defaults\r
+ case state is\r
+ when IDLE =>\r
+ if(TRIGGER_BEGIN_TESTCHAIN_IN = '1') then\r
+ state_next <= WAIT_BEGIN_JTAGBITCALC;\r
+ operation_next <= "11"; -- none\r
+ chain_length_next <= (others =>'0');\r
+ chain_broken_next <= '1';\r
+ end if; \r
+ when WAIT_BEGIN_JTAGBITCALC =>\r
+ if(BEGIN_JTAGBITCALC_IN='1') then\r
+ state_next <= PROCESSING;\r
+ operation_phase_next <= operation_phase + 1;\r
+ substate_next <= none_p1; -- do nothing other than output tms=1\r
+ if(operation = "11") then\r
+ -- last operation was none\r
+ operation_next <= "00"; -- JTAG_RESET\r
+ operation_phase_next <= "0000"; -- Bit Nr. 0\r
+ enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation\r
+ elsif(operation = "00") then\r
+ -- last operation was: JTAG_RESET\r
+ if(operation_phase = "0101") then\r
+ operation_next <= "01"; -- WRITE_IR\r
+ operation_phase_next <= "0000";\r
+ bitcounter_next <= (others => '0');\r
+ end if;\r
+ elsif(operation = "01") then\r
+ -- last operation was: WRITE_IR\r
+ if(operation_phase = "0101") then -- Shift-IR\r
+ -- stay in this phase until the instruction registers (of all chips) have been filled with ones\r
+ substate_next <= ir_ones_p1; -- fill ir with ones\r
+ if(to_integer(bitcounter) < ir_fill_ones_length - 1) then \r
+ operation_phase_next <= operation_phase;\r
+ bitcounter_next <= bitcounter + 1;\r
+ else\r
+ operation_phase_next <= operation_phase+1; -- shift last bit\r
+ end if;\r
+ elsif(operation_phase = "1000") then -- Run-Test-Idle\r
+ operation_next <= "10"; -- WRITE_DR\r
+ operation_phase_next <= "0000"; -- Select-DR-Scan\r
+ bitcounter_next <= (others => '0'); -- reset bitcounter\r
+ end if;\r
+ elsif(operation = "10") then\r
+ --last operation was: WRITE_DR\r
+ if(operation_phase = "0010") then -- Shift-DR\r
+ substate_next <= dr_zeros_p1; -- fill dr with zeros\r
+ elsif(operation_phase = "0011") then -- Shift-DR\r
+ -- stay in this phase until the bypass registers (of all chips) have filles with zeros\r
+ bitcounter_next <= bitcounter + 1;\r
+ operation_phase_next <= operation_phase;\r
+ substate_next <= dr_zeros_p1; -- fill dr with zeros\r
+ if(to_integer(bitcounter) +1 >= zerofill_length + to_integer(unsigned(DELAY_IN))) then\r
+ if(to_integer(zerocounter) > zerofill_numzeros_required) then\r
+ -- enough zeros appeared at tdo\r
+ operation_phase_next <= operation_phase + 1;\r
+ bitcounter_next <= (others =>'0');\r
+ substate_next <= dr_pattern_p1; -- write pattern into dr\r
+ else\r
+ operation_phase_next <= operation_phase + 2; -- skip writing pattern, thus yielding CHAIN_BROKEN='1' and CHAIN_LENGTH=0\r
+ bitcounter_next <= (others =>'0');\r
+ end if;\r
+ end if;\r
+ elsif(operation_phase = "0100") then -- Shift-DR: shift pattern\r
+ bitcounter_next <= bitcounter + 1;\r
+ operation_phase_next <= operation_phase;\r
+ substate_next <= dr_pattern_p1; -- write pattern into dr/look for pattern\r
+ if(to_integer(bitcounter) +1 >= zerofill_length + pattern_length + to_integer(unsigned(DELAY_IN))) then\r
+ operation_phase_next <= operation_phase + 1;\r
+ end if;\r
+ elsif(operation_phase = "0110") then -- Update DR\r
+ last_tck_cycle_next <= '1';\r
+ elsif(operation_phase = "0111") then -- Run-Test-Idle\r
+ enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation\r
+ last_tck_cycle_next <= '0';\r
+ state_next <= IDLE; \r
+ end if;\r
+ end if;\r
+ end if;\r
+ when PROCESSING =>\r
+ -- set TMS, copied from jtag_write_m10, modified\r
+ tms_next <= '1'; -- JTAG_RESET if operation = "00"\r
+ if(operation = "01") then -- WRITE_IR\r
+ if(operation_phase = "0001") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0010") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0110") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0111") then\r
+ tms_next <= '1';\r
+ else\r
+ tms_next <= '0';\r
+ end if;\r
+ elsif(operation = "10") then -- WRITE_DR\r
+ if(operation_phase = "0000") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0101") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0110") then\r
+ tms_next <= '1';\r
+ else\r
+ tms_next <= '0';\r
+ end if;\r
+ end if; \r
+ tdi_next <= '0';\r
+ case substate is\r
+ when none_p1 =>\r
+ state_next <= WAIT_BEGIN_JTAGBITCALC;\r
+ when ir_ones_p1 =>\r
+ tdi_next <= '1';\r
+ state_next <= WAIT_BEGIN_JTAGBITCALC;\r
+ when dr_zeros_p1 =>\r
+ tdi_next <= '0';\r
+ -- as the comparison of input_bit always happens in the first processing substate (*_p1),\r
+ -- the delay is fixed (always the same sampling time is used)\r
+ if(input_bit = '1') then\r
+ zerocounter_next <= (others =>'0');\r
+ else\r
+ zerocounter_next <= zerocounter + 1;\r
+ end if;\r
+ state_next <= WAIT_BEGIN_JTAGBITCALC;\r
+ when dr_pattern_p1 =>\r
+ -- as the comparison of input_bit always happens in the first processing substate (*_p1),\r
+ -- the delay is fixed (always the same sampling time is used) \r
+ -- this way: the first bit of the pattern always sets the first bit in nfa_state\r
+ -- nfa_state(i) means the (i+1)'th bit has arrived in a row.\r
+ -- if nfa_state(pattern_length-1) is set, this obviously means the full pattern has been detected.\r
+ nfa_state_next(pattern_length-1 downto 0) <= (nfa_state(pattern_length-2 downto 0) & '1') and std_logic_vector_scalar_compare(pattern, input_bit);\r
+ substate_next <= dr_pattern2_p2;\r
+ --nfa_state_next(pattern_length downto 1) <= nfa_state(pattern_length-1 downto 0) and (pattern = tmp_input_vect);\r
+ when dr_pattern2_p2 =>\r
+ if(pattern_detected = '1') then\r
+ chain_broken_next <= '0';\r
+ chain_length_next <= std_logic_vector(to_unsigned(to_integer(bitcounter)-to_integer(unsigned(DELAY_IN))-pattern_length, max_bitcounter_ld));\r
+ end if;\r
+ if(to_integer(bitcounter) < pattern_length) then\r
+ tdi_next <= pattern(to_integer(bitcounter));\r
+ else\r
+ tdi_next <= '0';\r
+ end if;\r
+ state_next <= WAIT_BEGIN_JTAGBITCALC;\r
+ end case;\r
+ end case;\r
+end process;\r
+\r
+end architecture;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+use work.jtag_constants.all;\r
+\r
+entity jtag_check_crc_ram1a is\r
+ generic (\r
+ RAM_JTAG_REGISTERS_DEPTH : integer;\r
+ MAX_NUMCHIPS : integer;\r
+ MAX_NUMCHIPS_LD : integer;\r
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;\r
+ MAX_REGLEN_PLUS_ONE_LD : integer;\r
+ MAX_REGISTERS_LD : integer\r
+ );\r
+ port (\r
+ CLK_IN : std_logic;\r
+ RESET_IN : std_logic;\r
+ TRIGGER_CHECK_IN : std_logic;\r
+ -- RAM1a\r
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);\r
+ \r
+ NUMCHIPS_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);\r
+ CRC_OK_OUT : out std_logic_vector(MAX_NUMCHIPS-1 downto 0);\r
+ IDLE_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture jtag_check_crc_ram1a_arch of jtag_check_crc_ram1a is\r
+component CRC_32 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(31 downto 0);\r
+ CRC_OUT : out std_logic_vector(31 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+end component;\r
+\r
+type state_type is (idle, prepare_read, readA0, readAi, wait_check, wait_check2, wait_check3);\r
+signal state, state_next : state_type;\r
+signal wordcounter, wordcounter_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);\r
+signal numregs, numregs_next : unsigned(MAX_REGISTERS_LD-1 downto 0);\r
+signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);\r
+signal length, length_next : unsigned(MAX_REGLEN_PLUS_ONE_LD-1 downto 0);\r
+signal wordlength : unsigned(MAX_REGLEN_PLUS_ONE_LD-1-5 downto 0);\r
+\r
+signal ram1a_a, ram1a_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+signal crc32_en, crc32_en_next : std_logic;\r
+signal crc32_data, crc32_data_next : std_logic_vector(31 downto 0);\r
+signal crc32_match : std_logic;\r
+signal crc32_reset, crc32_reset_next : std_logic;\r
+-- is first CRC32 ok? reset on TRIGGER_CHECK_IN\r
+signal crc1_ok, crc1_ok_next : std_logic;\r
+-- is second CRC32 ok? reset on TRIGGER_CHECK_IN\r
+signal crc2_ok, crc2_ok_next : std_logic;\r
+-- are both CRCs ok?\r
+signal crc_ok, crc_ok_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0);\r
+-- check first/second CRC in next clock cycle\r
+signal check_crc1, check_crc1_next, check_crc1_next_next : std_logic;\r
+signal check_crc2, check_crc2_next, check_crc2_next_next : std_logic;\r
+signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);\r
+\r
+begin\r
+\r
+the_crc32 : CRC_32 port map (CLK => CLK_IN, RESET => crc32_reset, CLK_EN => crc32_en, \r
+ DATA_IN => crc32_data, CRC_OUT => open, CRC_match =>crc32_match); \r
+\r
+CRC_OK_OUT <= crc_ok; \r
+IDLE_OUT <= '1' when state = idle else '0';\r
+RAM1A_A_OUT <= ram1a_a;\r
+wordlength <= length(MAX_REGLEN_PLUS_ONE_LD-1 downto 5) when length(4 downto 0) = "00000" else length(MAX_REGLEN_PLUS_ONE_LD-1 downto 5) + 1;\r
+ \r
+SYNCHRONOUS: process(CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ state <= idle;\r
+ ram1a_a <= (others => '0');\r
+ wordcounter <= (others => '0');\r
+ crc32_data <= (others => '0');\r
+ crc32_en <= '0';\r
+ numregs <= (others => '0');\r
+ dr_pointer <= (others => '0');\r
+ length <= (others => '0');\r
+ crc1_ok <= '0';\r
+ crc2_ok <= '0';\r
+ crc_ok <= (others => '0');\r
+ check_crc1 <= '0';\r
+ check_crc2 <= '0'; \r
+ check_crc1_next <= '0';\r
+ check_crc2_next <= '0'; \r
+ chipcounter <= (others => '0');\r
+ crc32_reset <= '0';\r
+ else\r
+ state <= state_next;\r
+ ram1a_a <= ram1a_a_next; \r
+ wordcounter <= wordcounter_next;\r
+ crc32_data <= crc32_data_next;\r
+ crc32_en <= crc32_en_next; \r
+ numregs <= numregs_next;\r
+ dr_pointer <= dr_pointer_next;\r
+ length <= length_next;\r
+ crc1_ok <= crc1_ok_next;\r
+ crc2_ok <= crc2_ok_next;\r
+ crc_ok <= crc_ok_next;\r
+ check_crc1 <= check_crc1_next;\r
+ check_crc2 <= check_crc2_next;\r
+ check_crc1_next <= check_crc1_next_next;\r
+ check_crc2_next <= check_crc2_next_next;\r
+ chipcounter <= chipcounter_next;\r
+ crc32_reset <= crc32_reset_next;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+STATE_COMB: process (state, TRIGGER_CHECK_IN, RAM1A_D_IN, ram1a_a, wordcounter, crc32_data, crc32_match, numregs, dr_pointer, length, crc1_ok, crc2_ok, crc_ok, check_crc1, check_crc2, NUMCHIPS_IN, chipcounter, wordlength)\r
+begin\r
+ ram1a_a_next <= ram1a_a;\r
+ state_next <= state;\r
+ wordcounter_next <= wordcounter;\r
+ crc32_data_next <= crc32_data;\r
+ crc32_en_next <= '0';\r
+ crc32_reset_next <= '0';\r
+ numregs_next <= numregs;\r
+ dr_pointer_next <= dr_pointer;\r
+ length_next <= length;\r
+ crc1_ok_next <= crc1_ok;\r
+ crc2_ok_next <= crc2_ok;\r
+ crc_ok_next <= crc_ok;\r
+ check_crc1_next_next <= '0';\r
+ check_crc2_next_next <= '0';\r
+ chipcounter_next <= chipcounter;\r
+ if(check_crc1 = '1') then\r
+ crc1_ok_next <= crc32_match;\r
+ end if;\r
+ if(check_crc2 = '1') then\r
+ crc2_ok_next <= crc32_match;\r
+ end if;\r
+ case state is \r
+ when idle =>\r
+ if(TRIGGER_CHECK_IN = '1') then\r
+ state_next <= prepare_read;\r
+ chipcounter_next <= (others => '0'); -- reset chipcounter\r
+ end if;\r
+ when prepare_read =>\r
+ state_next <= readA0;\r
+ ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter);\r
+ ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= (others => '0');\r
+ crc1_ok_next <= '0';\r
+ crc2_ok_next <= '0';\r
+ crc32_reset_next <= '1'; -- reset CRC component before processing a new chip (which has independently generated crcs) \r
+ when readA0 =>\r
+ state_next <= readAi;\r
+ ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 1;\r
+ wordcounter_next <= to_unsigned(0,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD);\r
+ numregs_next <= to_unsigned(1,MAX_REGISTERS_LD); -- 1 (because it should't be zero in the next step)\r
+ when readAi =>\r
+ ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(wordcounter + 2); -- word i+2;\r
+ crc32_data_next <= RAM1A_D_IN;\r
+ crc32_en_next <= '1';\r
+ wordcounter_next <= wordcounter + 1;\r
+ if(to_integer(wordcounter) = 0) then\r
+ numregs_next <= unsigned(RAM1A_D_IN(MAX_REGISTERS_LD-1 downto 0));\r
+ end if;\r
+ if(to_integer(wordcounter) = to_integer(2*numregs)) then -- last DR Pointer\r
+ dr_pointer_next <= unsigned(RAM1A_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0));\r
+ elsif(to_integer(wordcounter) = to_integer(2*numregs+1)) then -- last DR length\r
+ length_next <= unsigned(RAM1A_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0));\r
+ elsif(to_integer(wordcounter) = to_integer(2*numregs+2)) then -- first CRC-32\r
+ check_crc1_next_next <= '1';\r
+ elsif(to_integer(wordcounter) > to_integer(2*numregs+2)) then\r
+ -- here the condition dr_pointer+length <= 2*numregs+2 has to be caught\r
+ if(to_integer(dr_pointer+length) <= to_integer(2*numregs+2)) then\r
+ -- abort because CRC, after end of last DR, lies at an invalid location < = 2*numregs+2\r
+ state_next <= idle;\r
+ elsif(to_integer(wordcounter) = to_integer(dr_pointer+wordlength)) then -- second CRC-32\r
+ check_crc2_next_next <= '1';\r
+ state_next <= wait_check;\r
+ end if;\r
+ end if;\r
+ when wait_check =>\r
+ state_next <= wait_check2;\r
+ when wait_check2 =>\r
+ state_next <= wait_check3;\r
+ when wait_check3 =>\r
+ crc_ok_next(to_integer(chipcounter)) <= crc1_ok and crc2_ok;\r
+ if(chipcounter >= unsigned(NUMCHIPS_IN) - 1) then\r
+ state_next <= idle;\r
+ else\r
+ chipcounter_next <= chipcounter + 1;\r
+ state_next <= prepare_read;\r
+ end if;\r
+ end case;\r
+end process;\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.jtag_constants.all;
+use work.jtag_misc.all;
+--use work.minmax.all;
+--use work.monitor_config.all;
+--use debug.fifo32bit;
+
+
+
+
+entity jtag_cmd_m26c is
+ generic(
+ MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
+ MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
+ MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
+ MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
+ MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
+ MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
+ MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
+ MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
+
+ WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
+
+ READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
+
+ JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
+ JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
+ JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
+ JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
+
+ RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit.
+-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
+ JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
+ JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
+ JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2; -- ceil of ld( value plus one)
+ RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz
+);
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_TMS_OUT : out std_logic;
+ JTAG_TCK_OUT : out std_logic;
+ JTAG_TDI_OUT : out std_logic;
+ JTAG_TDO_IN : in std_logic;
+
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+
+ --OFF_SPILL_IN : in std_logic;
+ RUN_REQUEST_IN : in std_logic;
+ WRITE_ONCE_REQUEST_IN : in std_logic;
+ MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ REQUEST_RESET_OUT : out std_logic;
+ IDLE_OUT : out std_logic;
+ PROG_JTAG_FINISHED_OUT:out std_logic;
+ READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ RUN_COUNTER_OUT : out std_logic_vector(31 downto 0);
+
+ STARTED_OUT : out std_logic;
+ LAST_RUN_SUCCESSFUL_OUT : out std_logic;
+ LAST_DATA_CHANGED_OUT : out std_logic;
+ LAST_WRITE_ERRORS_OUT : out std_logic;
+ LAST_READ_ERRORS_OUT : out std_logic;
+ CRC_ERROR_OUT : out std_logic
+
+ --BUS_TIMEOUT_IN : in std_logic;
+ );
+end entity;
+
+
+architecture arch_cmd_m26c of jtag_cmd_m26c is
+
+-- component fifo32bit IS
+-- port (
+-- clk: IN std_logic;
+-- din: IN std_logic_VECTOR(31 downto 0);
+-- rd_en: IN std_logic;
+-- rst: IN std_logic;
+-- wr_en: IN std_logic;
+-- dout: OUT std_logic_VECTOR(31 downto 0);
+-- empty: OUT std_logic;
+-- full: OUT std_logic;
+-- overflow: OUT std_logic;
+-- underflow: OUT std_logic);
+-- end component;
+
+
+component jtag_pulses is
+ generic (
+ time_bits : integer := 10
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ -- input times
+ JTAG_CLOCK_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_CLOCK_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME3_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SET_DATA_TIME_IN: in std_logic_vector(time_bits -1 downto 0);
+
+
+ JTAG_CLOCK_CYCLE_LENGTH_IN: in std_logic_vector(time_bits -1 downto 0);
+
+ -- output pulses
+ BEGIN_JTAGBITCALC_OUT : out std_logic;
+ JTAG_CLOCK_PULSE1_OUT : out std_logic;
+ JTAG_CLOCK_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE1_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE3_OUT : out std_logic;
+ JTAG_SET_DATA_PULSE_OUT : out std_logic
+
+ );
+end component;
+
+component jtag_tck_out_component is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_CLOCK_PULSE1_IN : in std_logic;
+ JTAG_CLOCK_PULSE2_IN : in std_logic;
+ ENABLE_JTAG_TCK_IN : in std_logic;
+
+ TCK_OUT : out std_logic
+ );
+end component;
+
+component jtag_write_m10 is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_LD : integer;
+ MAX_REGLEN_PLUS_ONE_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ -- the zero'th entry points to the first not removed chip
+ -- a value of (others => '1') means that no more non-removed chips follow
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_WRITE_IN : in std_logic;
+ IDLE_OUT : out std_logic;
+
+ IS_DR_BIT_OUT : out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic;
+
+ -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_OUT : out std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0)
+
+
+ );
+end component;
+
+component jtag_tdo_sample is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
+ -- the first sample is taken directly after this pulse
+ SAMPLE_PULSE1_IN : in std_logic;
+ SAMPLE_PULSE2_IN : in std_logic;
+ SAMPLE_PULSE3_IN : in std_logic;
+
+ -- TDO signal, which is to be sampled
+ TDO_IN : in std_logic;
+ -- sampled value of TDO
+ TDO_SAMPLED_OUT : out std_logic;
+ -- sampling error
+ SAMPLING_ERROR_OUT : out std_logic
+ );
+end component;
+
+component jtag_mux_buffer_tms_tdi_out_and_metainfo is
+ generic (
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- pulse when READ/WRITE/... entity's data should be taken and update
+ -- the output values for TMS,TDI
+ JTAG_SET_DATA_IN : in std_logic;
+
+ -- read DEV_ID inputs
+ RD_TMS_IN : in std_logic;
+ RD_TDI_IN : in std_logic;
+ RD_IS_DR_BIT_IN: in std_logic;
+ RD_IS_FIRSTBIT_IN : in std_logic;
+ RD_IS_LASTBIT_IN : in std_logic;
+ RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ RD_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ RD_LAST_TCK_CYCLE_IN : in std_logic;
+ RD_EXPECTED_TDO_OUT : in std_logic;
+
+ -- write registers inputs
+ WR_TMS_IN : in std_logic;
+ WR_TDI_IN : in std_logic;
+ WR_IS_DR_BIT_IN: in std_logic;
+ WR_IS_FIRSTBIT_IN : in std_logic;
+ WR_IS_LASTBIT_IN : in std_logic;
+ WR_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ WR_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ WR_LAST_TCK_CYCLE_IN : in std_logic;
+ WR_EXPECTED_TDO_OUT : in std_logic;
+
+ -- test chain inputs
+ TC_TMS_IN : in std_logic;
+ TC_TDI_IN : in std_logic;
+ TC_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ TC_LAST_TCK_CYCLE_IN : in std_logic;
+
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ IS_DR_BIT_OUT: out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic
+ );
+end component;
+
+component jtag_delay_expected_values is
+ generic (
+-- delay : integer := 0 -- number of whole jtag clock cycles to delay the expected values
+-- -- because of total distance of the tck-line to the last chip and
+-- -- the length of tdo of this chip back to the fpga
+ ld_maxdelay : integer := 2;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE1_IN : in std_logic;
+
+ -- chipcount as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ IS_DR_BIT_IN : in std_logic;
+ -- firstbit signal: reset counters before sampling this bit
+ IS_FIRSTBIT_IN : in std_logic;
+ -- finish signal: dataout => RAM1b, compareout => RAM2
+ IS_LASTBIT_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+
+
+ -- chipcount as unsigned
+ OUT_CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
+ OUT_REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ OUT_IS_DR_BIT_OUT : out std_logic;
+ -- firstbit signal: reset counters before sampling this bit
+ OUT_IS_FIRSTBIT_OUT : out std_logic;
+ -- finish signal: dataout => RAM1b, compareout => RAM2
+ OUT_IS_LASTBIT_OUT : out std_logic;
+
+ OUT_TDO_EXPECTED_OUT : out std_logic;
+ DELAY_IN : in std_logic_vector(ld_maxdelay -1 downto 0)
+
+ );
+end component;
+
+component jtag_tdo_compare_count_m10
+ generic (
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;
+ MAX_REGLEN_LD : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- active chip as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
+
+ ENABLE_COUNTERS_IN : in std_logic;
+ IS_FIRSTBIT_IN : in std_logic;
+ IS_LASTBIT_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ TDO_SAMPLING_ERROR_IN : in std_logic;
+
+
+ -- RAM2
+ RAM_MATCH_DIFF_COUNT_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+ --RAM_MATCH_DIFF_COUNT_D_IN : in std_logic_vector(31 downto 0);
+ RAM_MATCH_DIFF_COUNT_WE_OUT : out std_logic;
+ RAM_MATCH_DIFF_COUNT_D_OUT : out std_logic_vector(31 downto 0)
+
+ ---- internal error out: signals that read/write sampling has been mixed
+ --INTERNAL_ERROR_OUT : out std_logic
+
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+end component;
+
+component jtag_tdo_compare_counttotal_noram_m10
+ generic (
+ numcounts : integer := 3;
+ se_counter_width : integer := 32; -- sampling error counter width
+ diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
+ -- sample_pulse3 delayed by one clock cycle
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?)
+ ENABLE_COUNTERS_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ TDO_SAMPLING_ERROR_IN : in std_logic;
+ BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
+ END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
+
+ -- should be zero if timing is good
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0);
+ COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0);
+ LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0)
+
+
+ );
+end component;
+
+
+component jtag_tdo_data_to_ram_m10
+ generic (
+ enable_ram1b : std_logic := '1';
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_LD : integer;
+ RAM_JTAG_REGISTERS_DEPTH : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- active chip as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ -- dataout => RAM1b
+ ENABLE_DATAOUT_IN : in std_logic;
+ IS_FIRSTBIT_IN : in std_logic;
+ IS_LASTBIT_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ -- RAM1b
+ RAM_JTAG_REGISTERS_READOUT_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_READOUT_D_IN : in std_logic_vector(31 downto 0);
+ RAM_JTAG_REGISTERS_READOUT_WE_OUT : out std_logic;
+ RAM_JTAG_REGISTERS_READOUT_D_OUT : out std_logic_vector(31 downto 0)
+
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+end component;
+
+component jtag_read_m26devid_m10 is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ -- the zero'th entry points to the first not removed chip
+ -- a value of (others => '1') means that no more non-removed chips follow
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_READ_IN : in std_logic;
+
+
+
+ IS_DR_BIT_OUT : out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic;
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component jtag_bypassreg_testchain_m10 is
+ generic (
+-- delay : integer := 0; -- this is the same value as in jtag_delay_expected_values
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ JTAG_M26_IRLEN : integer;
+
+ max_bitcounter_ld : integer;-- set to: MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-- bitcounter counts to ir_fill_ones_length, to zerofill_length aswell as from begin of sending pattern to end of receiving pattern (zerofill_length). should write something like: max(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD, 7)+1.
+
+ ld_maxdelay : integer := 2; -- floor of ld maxdelay
+ pattern_length : integer := 4;
+ pattern : std_logic_vector(4-1 downto 0) := "1001";
+ zerofill_numzeros_required : integer := 5 -- minimum number of zeros appearing at tdo while first zero filling phase
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_TESTCHAIN_IN : in std_logic;
+ IDLE_OUT : out std_logic;
+
+ -- length in chips of the chain -- corresponds to the number of bits the
+ -- output is shifted compared to the input, because the BYPASS registers
+ -- are selected, which are only one bit long
+ CHAIN_LENGTH_OUT : out std_logic_vector(max_bitcounter_ld-1 downto 0);
+ -- if after feeding in a sufficiently long sequence
+ -- the expected output pattern doesnt occur
+ CHAIN_BROKEN_OUT : out std_logic;
+
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ TDO_IN : in std_logic;
+ DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0)
+ );
+end component;
+
+component jtag_update_error_counts_ram3a is
+ generic (
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_PLUS_TWO_LD : integer;
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;
+ RAM_ERROR_COUNTS_DEPTH : integer;
+ WRITE_ERROR_THRESHOLD : integer;
+ READ_ERROR_THRESHOLD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TRIGGER_UPDATE_DATA_CHANGED_IN : in std_logic;
+ TRIGGER_UPDATE_READ_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_WRITE_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_RUN_COUNTER_IN : in std_logic;
+ RUN_COUNTER_IN : in std_logic_vector(31 downto 0);
+ -- RAM2
+ RAM2_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+ RAM2_D_IN : in std_logic_vector(31 downto 0);
+ -- RAM3a
+ RAM3A_A_OUT : out std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+ RAM3A_D_IN : in std_logic_vector(31 downto 0);
+ RAM3A_D_OUT : out std_logic_vector(31 downto 0);
+ RAM3A_WR_OUT :out std_logic;
+
+ REMOVED_CHIPS_IN : in std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+ NUMCHIPS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+ -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ -- if true, there were read errors in last dev_id read
+ READ_ERRORS_OUT : out std_logic;
+ -- if true, there were read errors the last double write to registers (value read the second time didn't equal programmed value)
+ WRITE_ERRORS_OUT : out std_logic;
+ -- if true, the data read from the registers wasn't equal to the data programmed a period before (for example in the last spill break)
+ DATA_CHANGED_OUT : out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+component jtag_init_ram1b is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_INIT_IN : std_logic;
+ -- RAM1a
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);
+ -- RAM1b
+ RAM1B_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1B_D_IN : in std_logic_vector(31 downto 0);
+ RAM1B_WE_OUT : out std_logic;
+ RAM1B_D_OUT : out std_logic_vector(31 downto 0);
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component copy_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_COPY_IN : std_logic;
+ -- RAM3a
+ RAMA_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMA_D_IN : in std_logic_vector(ram_width-1 downto 0);
+ -- RAM3b
+ RAMB_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMB_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAMB_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+component blank_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_BLANK_IN : std_logic;
+ -- RAM
+ RAM_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAM_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAM_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component jtag_check_crc_ram1a is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_CHECK_IN : std_logic;
+ -- RAM1a
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);
+
+ NUMCHIPS_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+ CRC_OK_OUT : out std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component ram_dp is
+ generic(
+ depth : integer := 9;
+ width : integer := 32
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(depth-1 downto 0);
+ dout1 : out std_logic_vector(width-1 downto 0);
+ din1 : in std_logic_vector(width-1 downto 0);
+ a2 : in std_logic_vector(depth-1 downto 0);
+ dout2 : out std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux2to1_readport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : std_logic;
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux4to1_readport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : in std_logic_vector(1 downto 0); -- two bit select input
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+ A2_IN : in std_logic_vector(depth-1 downto 0);
+ D2_OUT : out std_logic_vector(width-1 downto 0);
+ A3_IN : in std_logic_vector(depth-1 downto 0);
+ D3_OUT : out std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux2to1_writeport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : in std_logic;
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ WR0_IN : in std_logic;
+ DIN0_IN : in std_logic_vector(width-1 downto 0);
+
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+ WR1_IN : in std_logic;
+ DIN1_IN : in std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0);
+ RAM_WR_OUT : out std_logic;
+ RAM_DIN_OUT : out std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+
+
+-- component priorityencoder_seq is
+ -- generic ( n : positive;
+ -- ldn:positive -- rounded up ld(n + 1)
+ -- );
+ -- Port ( CLK_IN : in STD_LOGIC;
+ -- RESET_IN : in STD_LOGIC;
+ -- input_vect_IN : in STD_LOGIC_VECTOR (n - 1 downto 0);
+ -- enc_pos_OUT : out STD_LOGIC_VECTOR (ldn - 1 downto 0);
+ -- start_IN : in STD_LOGIC;
+ -- enc_pos_valid_OUT : out STD_LOGIC );
+-- end component;
+
+-- function ld(m:positive) return natural is
+-- variable n : positive;
+-- begin
+-- n = 0;
+-- a: loop
+-- if (2**n >= m) then
+-- return n;
+-- end if;
+-- n = n + 1;
+-- end loop a;
+-- end;
+
+component trb_net16_regio_bus_handler is
+ generic(
+ PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;
+ PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
+ PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
+ DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
+ DAT_READ_ENABLE_IN : in std_logic; -- read pulse
+ DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse
+ DAT_TIMEOUT_IN : in std_logic; -- access timed out
+ DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested
+ DAT_WRITE_ACK_OUT : out std_logic; -- data accepted
+ DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
+
+ BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);
+ BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+
+ BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);
+ BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+
+ STAT_DEBUG : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+constant STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant STATUS_WRITE_ERROR : integer := MAX_NUMCHIPS;
+constant STATUS_WRITE_ERROR2 : integer := 2*MAX_NUMCHIPS;
+constant STATUS_READ_ERROR : integer := 3*MAX_NUMCHIPS;
+constant STATUS_READ_ERROR2 : integer := 4*MAX_NUMCHIPS;
+constant STATUS_DATA_CHANGED : integer := 5*MAX_NUMCHIPS;
+
+constant WRITE_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant WRITE_STATUS_DATA_CHANGED : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant READ_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant READ_STATUS_BIT_ERROR : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+
+constant RAM_MATCH_DIFF_COUNT_DEPTH : integer := MAX_NUMCHIPS_LD + MAX_REGISTERS_PLUS_ONE_LD + 1;--9; -- maximum 32 counts / chip (one for read DEV_ID register, rest for read/write data registers), maximum 16 chips, each count 32 bits
+constant RAM_ERROR_COUNTS_DEPTH : integer := MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD; --10; -- ld(8+4*MAX_REGISTERS)+MAX_NUMCHIPS_LD= MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD
+
+
+
+
+--type BUS_RW_STATE_TYPE is (BUS_RW_STATE_IDLE, BUS_RW_STATE_READ_RAM_WAIT, BUS_RW_STATE_READ_RAM, BUS_RW_STATE_WRITE_RAM, BUS_RW_STATE_RETURN_READ, BUS_RW_STATE_RETURN_WRITE);
+
+--signal bus_rw_state, bus_rw_state_next : BUS_RW_STATE_TYPE;
+--signal dev_state, dev_state_next : DEVICE_STATE_TYPE;
+signal data_register, data_register_next : std_logic_vector(31 downto 0);
+--signal cmd_register, cmd_register_next : std_logic_vector(31 downto 0);
+--signal length_register, length_register_next : std_logic_vector(31 downto 0);
+signal jtag_refresh_active, jtag_refresh_active_next : std_logic;
+signal jtag_check1_active, jtag_check1_active_next : std_logic;
+signal jtag_refresh_active_last, jtag_refresh_active_last_next : std_logic;
+-- has to fit number of 32 bit words needed to represent the status register
+--signal status_register_pos, status_register_pos_next : std_logic_vector(MAX_NUMCHIPS_LD+2+MAX_REGISTERS_LD-5 downto 0);
+--signal status_register_read_running, status_register_read_running_next : std_logic;
+
+-- mostly for debug purposes: status bits
+--signal my_status, my_status_next : std_logic_vector(8 downto 0);
+
+-- status register layout:
+-- bits MAX_NUMCHIPS -1 downto 0 : JTAG ERROR
+-- bits 2*MAX_NUMCHIPS -1 downto MAX_NUMCHIPS : WRITE ERROR
+-- bits 3*MAX_NUMCHIPS -1 downto 2*MAX_NUMCHIPS : WRITE ERROR2
+-- bits 4*MAX_NUMCHIPS -1 downto 3*MAX_NUMCHIPS : READ ERROR
+-- bits 5*MAX_NUMCHIPS -1 downto 4*MAX_NUMCHIPS : READ ERROR2
+-- bits 6*MAX_NUMCHIPS -1 downto 5*MAX_NUMCHIPS : DATA CHANGED
+
+--signal status_register, status_register_next : std_logic_vector(6*MAX_NUMCHIPS-1 downto 0);
+signal crc_status_register, crc_status_register_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+
+--signal status_register_read_error2, status_register_read_error2_next : std_logic;
+
+--signal already_written, already_written_next : std_logic;
+-- contains a "1" at the positions of deactivated sensors
+signal removed_chips, removed_chips_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+signal last_not_removed, last_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
+signal first_not_removed, first_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
+--signal reactivate_sensor, reactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal reactivate_sensor_strobe , reactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal deactivate_sensor, deactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal deactivate_sensor_strobe , deactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+
+--signal disable_write, disable_write_next : std_logic;
+--signal disable_writeerror_for_remove, disable_writeerror_for_remove_next : std_logic;
+--signal disable_remove, disable_remove_next : std_logic;
+--signal debug_one_remove, debug_one_remove_next : std_logic;
+--signal debug_one_remove_strobe, debug_one_remove_strobe_next : std_logic;
+--signal removed_strobe, removed_strobe_next : std_logic;
+--signal m26c_sensor_cand, m26c_sensor_cand_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+
+signal cc_chip_i, cc_chip_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal cc_nextnotremoved_i, cc_nextnotremoved_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal chip_counter_start, chip_counter_start_next : std_logic;
+type CC_STATE_TYPE is (CC_IDLE, CC_COUNT_SENSOR, CC_SETNUMCHIPS);
+signal cc_state, cc_state_next : CC_STATE_TYPE;
+
+
+--type REGISTER_POINTER_TYPE is range MAX_REGISTERS-1 downto 0;
+-- signal status_register_reg_sel, status_register_reg_sel_next : std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
+-- signal status_register_reg_sel_pos, status_register_reg_sel_pos_next : std_logic_vector( (MAX_NUMCHIPS_LD +2 -5)-1 downto 0);
+--signal mux_sel, mux_sel_next : std_logic;
+--signal driver_data_out : std_logic;
+--signal driver_ready_for_cmd : std_logic;
+--signal driver_state_out : std_logic_vector(8 downto 0);
+--signal driver_data_arrived : std_logic;
+--signal driver_data_in : std_logic;
+--signal driver_cmd_in : std_logic_vector(3 downto 0);
+--signal driver_speed , driver_speed_next : std_logic_vector(15 downto 0);
+
+--signal bus_data_out_buffer, bus_data_out_buffer_next : std_logic_vector(31 downto 0);
+--signal bus_dataready, bus_dataready_next : std_logic;
+--signal bus_no_more_data, bus_no_more_data_next : std_logic;
+--signal bus_write_ack, bus_write_ack_next : std_logic;
+--signal bus_unknown_addr, bus_unknown_addr_next : std_logic;
+
+signal ram1a_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1a_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1a_a1_base_addr, ram1a_a1_base_addr_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal ram1a_a1_rel_addr, ram1a_a1_rel_addr_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+signal ram1a_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1a_din1, ram1a_din1_next : std_logic_vector(31 downto 0);
+signal ram1a_wr1, ram1a_wr1_next : std_logic;
+signal ram1a_dout1 : std_logic_vector(31 downto 0);
+
+signal ram1b_a2, ram1b_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1b_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1a_select, ram1a_select_next : std_logic_vector(1 downto 0);
+
+signal ram1b_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1b_din1 : std_logic_vector(31 downto 0);
+signal ram1b_wr1 : std_logic;
+signal ram1b_dout1 : std_logic_vector(31 downto 0);
+signal ram1b_select, ram1b_select_next : std_logic;
+
+signal init_ram1b_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal init_ram1b_ram1a_d : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal init_ram1b_ram1b_dout : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_din : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_wr : std_logic;
+
+signal jtag_data_to_ram_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_data_to_ram_ram1b_dout : std_logic_vector(31 downto 0);
+signal jtag_data_to_ram_ram1b_din : std_logic_vector(31 downto 0);
+signal jtag_data_to_ram_ram1b_wr : std_logic;
+
+signal jtag_check_crc_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_check_crc_ram1a_d : std_logic_vector(31 downto 0);
+
+
+-- ram2 port 2: local flipflops
+--signal ram2_a2, ram2_a2_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+--signal ram2_dout2 : std_logic_vector(31 downto 0);
+-- ram2 port 1: non local flipflops, all connected to components
+signal ram2_a1 : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal ram2_din1 : std_logic_vector(31 downto 0);
+signal ram2_wr1 : std_logic;
+signal ram2_dout1 : std_logic_vector(31 downto 0);
+signal ram2_select, ram2_select_next : std_logic;
+
+-- ram3a port 2: local flipflops
+signal ram3a_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3a_dout2 : std_logic_vector(31 downto 0);
+
+-- ram3a port 1: non local flipflops, all connected to components
+signal ram3a_a1 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3a_din1 : std_logic_vector(31 downto 0);
+signal ram3a_wr1 : std_logic;
+signal ram3a_dout1 : std_logic_vector(31 downto 0);
+
+-- ram3b port 1: non local flipflops, all connected to components
+ -- see jtag_copy_ram3* signals
+-- ram3b port 2: local flipflops
+signal ram3b_a2_base_addr, ram3b_a2_base_addr_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0);
+signal ram3b_a2_rel_addr, ram3b_a2_rel_addr_next : std_logic_vector(3 downto 0);
+signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3b_dout2 : std_logic_vector(31 downto 0);
+
+signal ram3a_select, ram3a_select_next : std_logic;
+signal ram3a_rd_select, ram3a_rd_select_next : std_logic;
+
+signal jtag_tdo_compare_count_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal jtag_tdo_compare_count_ram_dout : std_logic_vector(31 downto 0);
+signal jtag_tdo_compare_count_ram_din : std_logic_vector(31 downto 0);
+signal jtag_tdo_compare_count_ram_wr : std_logic;
+
+--signal jtag_update_error_counts_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+--signal jtag_update_error_counts_ram_d : std_logic_vector(31 downto 0);
+
+
+
+
+
+--signal trigger_counter, trigger_counter_next : std_logic_vector(27 downto 0);
+--signal trigger_counter, trigger_counter_next : std_logic_vector(10 downto 0);
+
+
+
+signal idle_out_signal, idle_out_signal_next : std_logic;
+
+--signal write_status_register : std_logic_vector((3*MAX_NUMCHIPS) * MAX_REGISTERS -1 downto 0);
+--signal write_status_register_or, write_status_register_or_next : std_logic_vector((3*MAX_NUMCHIPS) -1 downto 0);
+--signal write_crc_status_register : std_logic_vector(MAX_REGISTERS - 1 downto 0);
+--signal write_cmd_out : std_logic_vector(3 downto 0);
+--signal write_data_out : std_logic;
+--signal write_idle : std_logic;
+--signal write_trigger, write_trigger_next : std_logic;
+--signal write_idle_last, write_idle_last_next : std_logic;
+--signal write_state_out : std_logic_vector(7 downto 0);
+--type ERROR_COUNTER_TYPE is array (MAX_NUMCHIPS -1 downto 0) of std_logic_vector(9 downto 0);
+--signal write_error_counter, write_error_counter_next : ERROR_COUNTER_TYPE;
+--signal write_error_over_threshold_counter, write_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
+--signal write_data_changed_counter, write_data_changed_counter_next : ERROR_COUNTER_TYPE;
+--constant MAX_ERROR_COUNT : std_logic_vector(9 downto 0) := "1111111111";
+
+--signal read_cmd_out : std_logic_vector(3 downto 0);
+--signal read_data_out : std_logic;
+--signal read_trigger, read_trigger_next : std_logic;
+--signal read_status_register : std_logic_vector(3*MAX_NUMCHIPS -1 downto 0);
+--signal read_idle : std_logic;
+--signal read_idle_last, read_idle_last_next : std_logic;
+--signal read_state_out : std_logic_vector(7 downto 0);
+--signal read_error_counter, read_error_counter_next : ERROR_COUNTER_TYPE;
+--signal read_error_over_threshold_counter, read_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
+
+signal numchips_configured, numchips_configured_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+
+signal debug_m26cs_state, debug_m26cs_state_next : std_logic_vector(7 downto 0);
+signal debug_test, debug_test_next : std_logic_vector(31 downto 0);
+
+signal debug_trigger_counter, debug_trigger_counter_next : unsigned(31 downto 0);
+
+--signal bus2_ram_addr_out : std_logic_vector(7 downto 0);
+signal bus2_ram_addr_out : std_logic_vector(15 downto 0);
+signal bus2_ram_data_out : std_logic_vector(31 downto 0);
+signal bus2_ram_read_enable_out : std_logic;
+signal bus2_ram_write_enable_out : std_logic;
+signal bus2_ram_timeout_out : std_logic;
+
+signal bus2_ram_data_in, bus2_ram_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_ram_dataready_in, bus2_ram_dataready_in_next : std_logic;
+signal bus2_ram_write_ack_in, bus2_ram_write_ack_in_next : std_logic;
+signal bus2_ram_no_more_data_in, bus2_ram_no_more_data_in_next : std_logic;
+signal bus2_ram_unknown_addr_in, bus2_ram_unknown_addr_in_next : std_logic;
+
+--signal bus2_status_addr_out : std_logic_vector(4 downto 0);
+signal bus2_status_addr_out : std_logic_vector(15 downto 0);
+signal bus2_status_data_out : std_logic_vector(31 downto 0);
+signal bus2_status_read_enable_out : std_logic;
+signal bus2_status_write_enable_out : std_logic;
+signal bus2_status_timeout_out : std_logic;
+
+signal bus2_status_data_in, bus2_status_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_status_dataready_in, bus2_status_dataready_in_next : std_logic;
+signal bus2_status_write_ack_in, bus2_status_write_ack_in_next : std_logic;
+signal bus2_status_no_more_data_in, bus2_status_no_more_data_in_next : std_logic;
+signal bus2_status_unknown_addr_in, bus2_status_unknown_addr_in_next : std_logic;
+
+--signal bus2_status2_addr_out : std_logic_vector(4 downto 0);
+signal bus2_status2_addr_out : std_logic_vector(15 downto 0);
+signal bus2_status2_data_out : std_logic_vector(31 downto 0);
+signal bus2_status2_read_enable_out : std_logic;
+signal bus2_status2_write_enable_out : std_logic;
+signal bus2_status2_timeout_out : std_logic;
+
+signal bus2_status2_data_in, bus2_status2_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_status2_dataready_in, bus2_status2_dataready_in_next : std_logic;
+signal bus2_status2_write_ack_in, bus2_status2_write_ack_in_next : std_logic;
+signal bus2_status2_no_more_data_in, bus2_status2_no_more_data_in_next : std_logic;
+signal bus2_status2_unknown_addr_in, bus2_status2_unknown_addr_in_next : std_logic;
+
+signal bus2_status2_read_ram3b, bus2_status2_read_ram3b_next : std_logic;
+signal buf_bus2_status2_read_ram3b, buf_bus2_status2_read_ram3b_next : std_logic;
+
+signal status2_run_counter, status2_run_counter_next : unsigned(31 downto 0);
+
+signal status2_chain_status, status2_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+signal status2_copy_finished: std_logic;
+
+
+--signal bus2_control_addr_out : std_logic_vector(4 downto 0);
+signal bus2_control_addr_out : std_logic_vector(15 downto 0);
+signal bus2_control_data_out : std_logic_vector(31 downto 0);
+signal bus2_control_read_enable_out : std_logic;
+signal bus2_control_write_enable_out : std_logic;
+signal bus2_control_timeout_out : std_logic;
+
+signal bus2_control_data_in, bus2_control_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_control_dataready_in, bus2_control_dataready_in_next : std_logic;
+signal bus2_control_write_ack_in, bus2_control_write_ack_in_next : std_logic;
+signal bus2_control_no_more_data_in, bus2_control_no_more_data_in_next : std_logic;
+signal bus2_control_unknown_addr_in, bus2_control_unknown_addr_in_next : std_logic;
+
+--signal bus2_debug_addr_out : std_logic_vector(4 downto 0);
+signal bus2_debug_addr_out : std_logic_vector(15 downto 0);
+signal bus2_debug_data_out : std_logic_vector(31 downto 0);
+signal bus2_debug_read_enable_out : std_logic;
+signal bus2_debug_write_enable_out : std_logic;
+signal bus2_debug_timeout_out : std_logic;
+
+signal bus2_debug_data_in, bus2_debug_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_debug_dataready_in, bus2_debug_dataready_in_next : std_logic;
+signal bus2_debug_write_ack_in, bus2_debug_write_ack_in_next : std_logic;
+signal bus2_debug_no_more_data_in, bus2_debug_no_more_data_in_next : std_logic;
+signal bus2_debug_unknown_addr_in, bus2_debug_unknown_addr_in_next : std_logic;
+
+signal buf_bus2_ram_read_enable_out, buf_bus2_ram_read_enable_out_next : std_logic;
+signal buf_buf_bus2_ram_read_enable_out, buf_buf_bus2_ram_read_enable_out_next : std_logic;
+-- monitoring
+--signal read_mon_write_out : std_logic;
+-- off_spill timer (htcounter)
+--signal htcounter_next, htcounter : unsigned(26 downto 0); -- 27 bit = approx 1.34 seconds
+--signal have_time_for_write, have_time_for_write_next : std_logic;
+signal prog_jtag_finished, prog_jtag_finished_next : std_logic;
+--signal last_write_successful, last_write_successful_next : std_logic;
+
+-- BEGIN NEW SIGNALS
+signal jtag_next_not_removed, jtag_next_not_removed_next : std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+signal jtag_write_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_write_ram1a_d : std_logic_vector(31 downto 0);
+signal trigger_jtag_write, trigger_jtag_write_next : std_logic;
+signal jtag_write_is_dr_bit : std_logic;
+signal jtag_write_is_firstbit : std_logic;
+signal jtag_write_is_lastbit : std_logic;
+signal jtag_write_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_write_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_write_enable_jtag_clock : std_logic;
+signal jtag_write_last_tck_cycle : std_logic;
+signal jtag_write_tms : std_logic;
+signal jtag_write_tdi : std_logic;
+signal jtag_write_expected_tdo : std_logic;
+signal jtag_write_idle : std_logic;
+signal jtag_write_last_error_code: std_logic_vector(2 downto 0);
+signal jtag_write_numregs_configured : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+signal jtag_read_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_read_ram1a_d : std_logic_vector(31 downto 0);
+signal trigger_jtag_read, trigger_jtag_read_next : std_logic;
+signal jtag_read_is_dr_bit : std_logic;
+signal jtag_read_is_firstbit : std_logic;
+signal jtag_read_is_lastbit : std_logic;
+signal jtag_read_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_read_enable_jtag_clock : std_logic;
+signal jtag_read_last_tck_cycle : std_logic;
+signal jtag_read_tms : std_logic;
+signal jtag_read_tdi : std_logic;
+signal jtag_read_expected_tdo : std_logic;
+signal jtag_read_idle : std_logic;
+
+--signal trigger_bypassreg, trigger_bypassreg_next : std_logic;
+signal jtag_bypassreg_idle : std_logic;
+signal jtag_bypassreg_length : std_logic_vector(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-1 downto 0);
+signal jtag_bypassreg_chain_broken : std_logic;
+signal jtag_bypassreg_enable_jtag_clock : std_logic;
+signal jtag_bypassreg_last_tck_cycle : std_logic;
+signal jtag_bypassreg_tms : std_logic;
+signal jtag_bypassreg_tdi : std_logic;
+-- begin: global_jtag_counter settings
+signal jtag_clock_cycle_length, jtag_clock_cycle_length_next : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us)
+signal jtag_clock_time1, jtag_clock_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_clock_time2, jtag_clock_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time1, jtag_sample_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time2, jtag_sample_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time3, jtag_sample_time3_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_set_data_time, jtag_set_data_time_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+-- begin: periodic pulses, periodic with global_jtag_counter
+signal begin_jtag_bitcalc : std_logic;
+signal jtag_sample_pulse1 : std_logic;
+signal jtag_sample_pulse2 : std_logic;
+signal jtag_sample_pulse3 : std_logic;
+signal jtag_sample_pulse3_d1, jtag_sample_pulse3_d1_next : std_logic;
+signal jtag_set_data_pulse : std_logic;
+-- end: periodic pulses
+
+signal jtag_tdo_sampled : std_logic;
+signal jtag_tdo_sampling_error : std_logic;
+
+signal jtag_tms : std_logic;
+signal jtag_tdi : std_logic;
+signal jtag_enable_clock : std_logic;
+
+signal jtag_meta_is_dr_bit : std_logic;
+signal jtag_meta_is_firstbit : std_logic;
+signal jtag_meta_is_lastbit : std_logic;
+signal jtag_meta_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_meta_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_meta_last_tck_cycle : std_logic;
+signal jtag_meta_expected_tdo : std_logic;
+
+signal jtag_delayed_is_dr_bit : std_logic;
+signal jtag_delayed_is_firstbit : std_logic;
+signal jtag_delayed_is_lastbit : std_logic;
+signal jtag_delayed_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_delayed_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_delayed_tdo_expected : std_logic;
+
+-- jtag_update_error_counts
+signal trigger_juec_update_d_ch, trigger_juec_update_d_ch_next : std_logic;
+signal trigger_juec_update_rd_err, trigger_juec_update_rd_err_next : std_logic;
+signal trigger_juec_update_wr_err, trigger_juec_update_wr_err_next : std_logic;
+signal trigger_juec_update_run_counter, trigger_juec_update_run_counter_next : std_logic;
+signal juec_ram2_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal juec_ram2_dout : std_logic_vector(31 downto 0);
+signal juec_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal juec_ram3a_dout : std_logic_vector(31 downto 0);
+signal juec_ram3a_din : std_logic_vector(31 downto 0);
+signal juec_ram3a_wr : std_logic;
+signal juec_idle : std_logic;
+signal juec_data_changed : std_logic;
+signal juec_read_errors : std_logic;
+signal juec_write_errors : std_logic;
+
+signal jtag_copy_ram3_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_copy_ram3_ram3a_dout : std_logic_vector(31 downto 0);
+signal jtag_copy_ram3_ram3b_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_copy_ram3_ram3b_din : std_logic_vector(31 downto 0);
+signal jtag_copy_ram3_ram3b_wr : std_logic;
+signal jtag_copy_ram3_idle : std_logic;
+
+
+signal trigger_blank_ram3a, trigger_blank_ram3a_next : std_logic;
+signal jtag_blank_ram3a_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_blank_ram3a_ram3a_din : std_logic_vector(31 downto 0);
+signal jtag_blank_ram3a_ram3a_wr : std_logic;
+signal jtag_blank_ram3a_idle : std_logic;
+
+
+type M26CS_STATE_TYPE is (M26CSS_STOPPED, M26CSS_CHECK1_WAIT_FOR_HAVE_TIME, M26CSS_WAIT_FOR_TRIGGER, M26CSS_CHECK_CRC_RAM1A_BEGIN, M26CSS_CHECK_CRC_RAM1A_WAIT, M26CSS_INIT_RAM1B_BEGIN, M26CSS_INIT_RAM1B_WAIT, M26CSS_DATA_CHANGED_BEGIN, M26CSS_DATA_CHANGED_WAIT, M26CSS_BLANK_RAM3A_WAIT, M26CSS_JUEC_DATA_CHANGED_BEGIN, M26CSS_JUEC_DATA_CHANGED_WAIT, M26CSS_COUNT_CHIPS_BEGIN, M26CSS_COUNT_CHIPS_WAIT, M26CSS_BYPASSREG_BEGIN, M26CSS_BYPASSREG_WAIT, M26CSS_READ1_BEGIN, M26CSS_READ1_WAIT, M26CSS_JUEC_READ_BEGIN, M26CSS_JUEC_READ_WAIT, M26CSS_REQUEST_RESET_BEGIN, M26CSS_REQUEST_RESET_WAIT, M26CSS_REQUESTED_RESET_WAIT, M26CSS_WRITE1_BEGIN, M26CSS_WRITE1_WAIT, M26CSS_WRITE2_BEGIN, M26CSS_WRITE2_WAIT, M26CSS_JUEC_WRITE_BEGIN, M26CSS_JUEC_WRITE_WAIT, M26CSS_JUEC_RUN_COUNTER_BEGIN, M26CSS_JUEC_RUN_COUNTER_WAIT,
+M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN, M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT, M26CSS_WRITEONCE_INIT_RAM1B_BEGIN, M26CSS_WRITEONCE_INIT_RAM1B_WAIT, M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN, M26CSS_WRITEONCE_COUNT_CHIPS_WAIT, M26CSS_WRITEONCE_WRITE1_BEGIN, M26CSS_WRITEONCE_WRITE1_WAIT );
+signal m26cs_state, m26cs_state_next : M26CS_STATE_TYPE;
+--signal write_count, write_count_next : std_logic_vector(31 downto 0);
+signal m26cs_stopped : std_logic;
+signal m26cs_firstrun, m26cs_firstrun_next : std_logic;
+signal breakpoint_active, breakpoint_active_next : std_logic_vector(9 downto 0);
+-- chain_status:
+-- bit 0: chain broken
+-- bit 1: CRC_error(s)
+-- bit 2: programmed
+-- bits 3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3: chain length
+signal chain_status, chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+signal trigger_begin_bypassreg, trigger_begin_bypassreg_next : std_logic;
+signal trigger_copy_ram3, trigger_copy_ram3_next : std_logic;
+--signal jtag_tdo_compare_count_internal_error : std_logic;
+signal run_counter, run_counter_next : unsigned(31 downto 0);
+signal jtag_status2_copy_requested, jtag_status2_copy_requested_next : std_logic;
+
+signal jtag_status2_copy_request_strobe, jtag_status2_copy_request_strobe_next : std_logic;
+type CPS2_STATE_TYPE is (CPS2_IDLE, CPS2_COPY_BEGIN, CPS2_COPY_WAIT);
+signal cps2_state, cps2_state_next : CPS2_STATE_TYPE;
+signal jtag_clock_pulse1 : std_logic;
+signal jtag_clock_pulse2 : std_logic;
+signal jtag_tck : std_logic;
+
+signal jtag_pulses_reset, jtag_pulses_reset_next : std_logic;
+signal jtag_pulses_reset_complete : std_logic;
+
+signal jtag_chain_broken_counter, jtag_chain_broken_counter_next : unsigned(JTAG_CHAIN_BROKEN_COUNTER_BITS-1 downto 0);
+
+signal jtag_check_crc_ram1a_crc_ok : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+signal jtag_check_crc_ram1a_idle : std_logic;
+signal trigger_check_crc_ram1a, trigger_check_crc_ram1a_next : std_logic;
+signal trigger_init_ram1b, trigger_init_ram1b_next : std_logic;
+signal jtag_init_ram1b_idle : std_logic;
+
+signal ram1b1c_copy_trigger_strobe, ram1b1c_copy_trigger_strobe_next : std_logic_vector(3 downto 0);
+signal trigger_copy_ram1b1c, trigger_copy_ram1b1c_next : std_logic;
+signal copy_ram1b1c_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal copy_ram1b1c_ram1b_dout : std_logic_vector(31 downto 0);
+signal copy_ram1b1c_ram1c_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal copy_ram1b1c_ram1c_din : std_logic_vector(31 downto 0);
+signal copy_ram1b1c_ram1c_wr : std_logic;
+signal copy_ram1b1c_idle : std_logic;
+
+signal ram1c_a2, ram1c_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1c_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_active_next : std_logic_vector(3 downto 0);
+signal ram1b_copy_requested, ram1b_copy_requested_next : std_logic;
+signal ram1c_run_counter, ram1c_run_counter_next : unsigned(31 downto 0);
+signal ram1c_chain_status, ram1c_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+type CPR1BC_STATE_TYPE is (CPR1BC_IDLE, CPR1BC_COPY_BEGIN, CPR1BC_COPY_WAIT);
+signal cpr1bc_state, cpr1bc_state_next : CPR1BC_STATE_TYPE;
+
+-- DEBUGTDO fifo and control signals
+signal tdodebugsamples : std_logic_vector(31 downto 0);
+signal debugtdo_rd_en : std_logic;
+signal debugtdo_wr_en : std_logic;
+signal debugtdo_dout : std_logic_vector(31 downto 0);
+signal debugtdo_empty : std_logic;
+signal debugtdo_full : std_logic;
+signal debugtdo_overflow : std_logic;
+signal debugtdo_underflow : std_logic;
+signal resetdebugtdo_toffifo : std_logic;
+signal resetdebugtdo_strobe : std_logic;
+signal debugtdo_activate_strobe : std_logic;
+signal debugtdo_active : std_logic;
+signal debugtdo_timeout, debugtdo_timeout_next : std_logic_vector(31 downto 0);
+signal debugtdo_counter : std_logic_vector(31 downto 0);
+signal debugtdo_ran : std_logic;
+
+signal crc_error_on_last_check, crc_error_on_last_check_next : std_logic;
+signal last_run_successful, last_run_successful_next : std_logic;
+signal last_run_successful_tmp, last_run_successful_tmp_next : std_logic;
+signal begin_count_read_errors :std_logic;
+signal begin_count_write_errors :std_logic;
+signal begin_count_data_changed :std_logic;
+signal end_count_read_errors :std_logic;
+signal end_count_write_errors :std_logic;
+signal end_count_data_changed :std_logic;
+signal last_read_error : std_logic;
+signal last_write_error : std_logic;
+signal last_data_changed : std_logic;
+
+signal sREAD_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+signal sWRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+signal sDATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+
+-- INSERTLABEL: signals
+
+signal m26csoptions, m26csoptions_next : std_logic_vector(0 downto 0);
+signal jtag_delay_expvalues, jtag_delay_expvalues_next : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+
+signal request_reset, request_reset_next : std_logic;
+signal reset_wait, reset_wait_next : unsigned(7 downto 0);
+constant reset_wait_zero : unsigned(7 downto 0) := "00000000";
+
+signal run_requested, run_requested_next : std_logic;
+signal write_once_requested, write_once_requested_next : std_logic;
+signal write_once_count, write_once_count_next : unsigned(COUNTER_WIDTHS-1 downto 0);
+
+
+
+begin
+
+--fifo32bit_debugtdo : fifo32bit
+--port map(
+-- clk => CLK_IN,
+-- din => tdodebugsamples(31 downto 0),
+-- rd_en => debugtdo_rd_en,
+-- rst => resetdebugtdo_toffifo,
+-- wr_en => debugtdo_wr_en,
+-- dout => debugtdo_dout(31 downto 0),
+-- empty => debugtdo_empty,
+-- full => debugtdo_full,
+-- overflow => debugtdo_overflow,
+-- underflow => debugtdo_underflow);
+
+
+
+jtag_bypassreg_enable_jtag_clock <= '0';
+
+
+resetdebugtdo_toffifo <= resetdebugtdo_strobe OR RESET_IN;
+debugtdo_wr_en <= '1' when debugtdo_active = '1' and debugtdo_timeout <= debugtdo_counter else '0';
+
+tdodebugsamples(31) <= begin_jtag_bitcalc;
+tdodebugsamples(30) <= jtag_clock_pulse1;
+tdodebugsamples(29) <= jtag_clock_pulse2;
+tdodebugsamples(28) <= jtag_sample_pulse1;
+tdodebugsamples(27) <= jtag_sample_pulse2;
+tdodebugsamples(26) <= jtag_sample_pulse3;
+tdodebugsamples(25) <= jtag_set_data_pulse;
+tdodebugsamples(1) <= JTAG_TDO_IN;
+
+RUN_COUNTER_OUT <= std_logic_vector(run_counter);
+STARTED_OUT <= jtag_refresh_active;
+CRC_ERROR_OUT <= crc_error_on_last_check;
+LAST_RUN_SUCCESSFUL_OUT <= last_run_successful;
+LAST_DATA_CHANGED_OUT <= last_data_changed;
+LAST_WRITE_ERRORS_OUT <= last_write_error;
+LAST_READ_ERRORS_OUT <= last_read_error;
+
+REQUEST_RESET_OUT <= request_reset;
+
+the_bus_handler : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", others => (others => '0')),
+ PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DAT_ADDR_IN(15 downto 9) => "0000000",
+ DAT_ADDR_IN(8 downto 0)=> BUS_ADDR_IN, -- address bus
+ DAT_DATA_IN => BUS_DATA_IN, -- data from TRB endpoint
+ DAT_DATA_OUT => BUS_DATA_OUT, -- data to TRB endpoint
+ DAT_READ_ENABLE_IN => BUS_READ_IN, -- read pulse
+ DAT_WRITE_ENABLE_IN => BUS_WRITE_IN, -- write pulse
+ DAT_TIMEOUT_IN => '0', -- access timed out
+ DAT_DATAREADY_OUT => BUS_DATAREADY_OUT, -- your data, master, as requested
+ DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT, -- data accepted
+ DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT, -- noone here to answer your request
+
+ --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => bus2_ram_addr_out,
+ --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => bus2_status_addr_out,
+ --BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => bus2_control_addr_out,
+ --BUS_ADDR_OUT(3*16+15 downto 3*16+5) => open,
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => bus2_debug_addr_out,
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => bus2_status2_addr_out,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_status_data_out,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_control_data_out,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => bus2_debug_data_out,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => bus2_status2_data_out,
+ BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out,
+ BUS_READ_ENABLE_OUT(1) => bus2_status_read_enable_out,
+ BUS_READ_ENABLE_OUT(2) => bus2_control_read_enable_out,
+ BUS_READ_ENABLE_OUT(3) => bus2_debug_read_enable_out,
+ BUS_READ_ENABLE_OUT(4) => bus2_status2_read_enable_out,
+ BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(1) => bus2_status_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(2) => bus2_control_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(3) => bus2_debug_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(4) => bus2_status2_write_enable_out,
+ BUS_TIMEOUT_OUT(0) => bus2_ram_timeout_out,
+ BUS_TIMEOUT_OUT(1) => bus2_status_timeout_out,
+ BUS_TIMEOUT_OUT(2) => bus2_control_timeout_out,
+ BUS_TIMEOUT_OUT(3) => bus2_debug_timeout_out,
+ BUS_TIMEOUT_OUT(4) => bus2_status2_timeout_out,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in,
+ BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => bus2_control_data_in,
+ BUS_DATA_IN(3*32+31 downto 3*32) => bus2_debug_data_in,
+ BUS_DATA_IN(4*32+31 downto 4*32) => bus2_status2_data_in,
+ BUS_DATAREADY_IN(0) => bus2_ram_dataready_in,
+ BUS_DATAREADY_IN(1) => bus2_status_dataready_in,
+ BUS_DATAREADY_IN(2) => bus2_control_dataready_in,
+ BUS_DATAREADY_IN(3) => bus2_debug_dataready_in,
+ BUS_DATAREADY_IN(4) => bus2_status2_dataready_in,
+ BUS_WRITE_ACK_IN(0) => bus2_ram_write_ack_in,
+ BUS_WRITE_ACK_IN(1) => bus2_status_write_ack_in,
+ BUS_WRITE_ACK_IN(2) => bus2_control_write_ack_in,
+ BUS_WRITE_ACK_IN(3) => bus2_debug_write_ack_in,
+ BUS_WRITE_ACK_IN(4) => bus2_status2_write_ack_in,
+ BUS_NO_MORE_DATA_IN(0) => bus2_ram_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(1) => bus2_status_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(2) => bus2_control_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(3) => bus2_debug_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(4) => bus2_status2_no_more_data_in,
+ BUS_UNKNOWN_ADDR_IN(0) => bus2_ram_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(1) => bus2_status_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(2) => bus2_control_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_unknown_addr_in,
+
+
+
+
+
+
+ STAT_DEBUG => open
+ );
+
+
+
+-- RAM1a holds JTAG registers, written via trbnet
+ram_jtag_registers : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram1a_wr1,
+ a1 => ram1a_a1,
+ dout1 => ram1a_dout1,
+ din1 => ram1a_din1,
+ a2 => ram1a_a2,
+ dout2 => ram1a_dout2
+ );
+ram1a_readport_mux: ram_mux4to1_readport generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map (
+ SELECT_IN => ram1a_select,
+ A0_IN => jtag_read_ram1a_a,
+ D0_OUT => jtag_read_ram1a_d,
+ A1_IN => jtag_write_ram1a_a,
+ D1_OUT => jtag_write_ram1a_d,
+ A2_IN => init_ram1b_ram1a_a,
+ D2_OUT => init_ram1b_ram1a_d,
+ A3_IN => jtag_check_crc_ram1a_a,
+ D3_OUT => jtag_check_crc_ram1a_d,
+
+ RAM_A_OUT => ram1a_a2,
+ RAM_DOUT_IN => ram1a_dout2
+ );
+
+-- RAM1b holds JTAG registers, read from JTAG chain
+ram_jtag_registers_read : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram1b_wr1,
+ a1 => ram1b_a1,
+ dout1 => ram1b_dout1,
+ din1 => ram1b_din1,
+ a2 => copy_ram1b1c_ram1b_a,--ram1b_a2,
+ dout2 => copy_ram1b1c_ram1b_dout--ram1b_dout2
+ );
+
+-- RAM1b holds JTAG registers, read from JTAG chain
+ram_jtag_registers_copy_read : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => copy_ram1b1c_ram1c_wr,
+ a1 => copy_ram1b1c_ram1c_a,
+ dout1 => open,
+ din1 => copy_ram1b1c_ram1c_din,
+ a2 => ram1c_a2,
+ dout2 => ram1c_dout2
+ );
+
+
+ram1b_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram1b_select,
+ A0_IN => init_ram1b_ram1b_a,
+ D0_OUT => init_ram1b_ram1b_dout,
+ WR0_IN => init_ram1b_ram1b_wr,
+ DIN0_IN => init_ram1b_ram1b_din,
+
+ A1_IN => jtag_data_to_ram_ram1b_a,
+ D1_OUT => jtag_data_to_ram_ram1b_dout,
+ WR1_IN => jtag_data_to_ram_ram1b_wr,
+ DIN1_IN => jtag_data_to_ram_ram1b_din,
+
+ RAM_A_OUT => ram1b_a1,
+ RAM_DOUT_IN => ram1b_dout1,
+ RAM_WR_OUT => ram1b_wr1,
+ RAM_DIN_OUT => ram1b_din1
+ );
+
+
+-- RAM2 holds counts of matching/not matching bits of each register of each chip
+ram_match_diff_count : ram_dp generic map(
+ depth => RAM_MATCH_DIFF_COUNT_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram2_wr1,
+ a1 => ram2_a1,
+ dout1 => ram2_dout1,
+ din1 => ram2_din1,
+ a2 => "00000000",--ram2_a2,
+ dout2 => open --ram2_dout2
+ );
+ram2_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_MATCH_DIFF_COUNT_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram2_select,
+ A0_IN => jtag_tdo_compare_count_ram_a,
+ D0_OUT => jtag_tdo_compare_count_ram_dout,
+ WR0_IN => jtag_tdo_compare_count_ram_wr,
+ DIN0_IN => jtag_tdo_compare_count_ram_din,
+
+ A1_IN => juec_ram2_a,
+ D1_OUT => juec_ram2_dout,
+ WR1_IN => '0',
+ DIN1_IN => x"0000_0000",
+
+ RAM_A_OUT => ram2_a1,
+ RAM_DOUT_IN => ram2_dout1,
+ RAM_WR_OUT => ram2_wr1,
+ RAM_DIN_OUT => ram2_din1
+ );
+
+-- RAM3 holds counts of errors and 'error over threshold's of each register of each chip
+ram_error_counts_A : ram_dp generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram3a_wr1,
+ a1 => ram3a_a1,
+ dout1 => ram3a_dout1,
+ din1 => ram3a_din1,
+ a2 => ram3a_a2,
+ dout2 => ram3a_dout2
+ );
+-- ram_error_counts_A : ram_dp generic map(
+-- depth => RAM_ERROR_COUNTS_DEPTH,
+-- width => 32
+-- )
+-- port map ( CLK => CLK_IN,
+-- wr1 => juec_ram3a_wr,
+-- a1 => juec_ram3a_a,
+-- dout1 => juec_ram3a_dout,
+-- din1 => juec_ram3a_din,
+-- a2 => jtag_copy_ram3_ram3a_a,
+-- dout2 => jtag_copy_ram3_ram3a_dout
+-- );
+-- RAM3B is an on demand copy of RAM3A
+ram_error_counts_B : ram_dp generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => jtag_copy_ram3_ram3b_wr,
+ a1 => jtag_copy_ram3_ram3b_a,
+ dout1 => open,
+ din1 => jtag_copy_ram3_ram3b_din,
+ a2 => ram3b_a2,
+ dout2 => ram3b_dout2
+ );
+
+ram3a_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram3a_select,
+ A0_IN => juec_ram3a_a,
+ D0_OUT => juec_ram3a_dout,
+ WR0_IN => juec_ram3a_wr,
+ DIN0_IN => juec_ram3a_din,
+
+ A1_IN => jtag_blank_ram3a_ram3a_a,
+ D1_OUT => open,
+ WR1_IN => jtag_blank_ram3a_ram3a_wr,
+ DIN1_IN => jtag_blank_ram3a_ram3a_din,
+
+ RAM_A_OUT => ram3a_a1,
+ RAM_DOUT_IN => ram3a_dout1,
+ RAM_WR_OUT => ram3a_wr1,
+ RAM_DIN_OUT => ram3a_din1
+ );
+
+ram3a_readport_mux: ram_mux2to1_readport generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map (
+ SELECT_IN => ram3a_rd_select,
+ A0_IN => jtag_copy_ram3_ram3a_a,
+ D0_OUT => jtag_copy_ram3_ram3a_dout,
+ A1_IN => "000000000",
+ D1_OUT => open,
+
+ RAM_A_OUT => ram3a_a2,
+ RAM_DOUT_IN => ram3a_dout2
+ );
+
+
+
+the_jtag_init_ram1b: jtag_init_ram1b generic map(
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+)
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_INIT_IN => trigger_init_ram1b,
+ -- RAM1a
+ RAM1A_A_OUT => init_ram1b_ram1a_a,
+ RAM1A_D_IN => init_ram1b_ram1a_d,
+ -- RAM1b
+ RAM1B_A_OUT => init_ram1b_ram1b_a,
+ RAM1B_D_IN => init_ram1b_ram1b_dout,
+ RAM1B_WE_OUT => init_ram1b_ram1b_wr,
+ RAM1B_D_OUT => init_ram1b_ram1b_din,
+
+ IDLE_OUT => jtag_init_ram1b_idle
+ );
+
+the_jtag_copy_ram1b1c : copy_ram
+ generic map (
+ ram_depth => RAM_JTAG_REGISTERS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_COPY_IN => trigger_copy_ram1b1c,
+ -- RAM3a
+ RAMA_A_OUT => copy_ram1b1c_ram1b_a,
+ RAMA_D_IN => copy_ram1b1c_ram1b_dout,
+ -- RAM3b
+ RAMB_A_OUT => copy_ram1b1c_ram1c_a,
+ RAMB_D_OUT => copy_ram1b1c_ram1c_din,
+ RAMB_WR_OUT => copy_ram1b1c_ram1c_wr,
+
+ IDLE_OUT => copy_ram1b1c_idle
+ );
+
+
+
+the_jtag_copy_ram3 : copy_ram
+ generic map (
+ ram_depth => RAM_ERROR_COUNTS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_COPY_IN => trigger_copy_ram3,
+ -- RAM3a
+ RAMA_A_OUT => jtag_copy_ram3_ram3a_a,
+ RAMA_D_IN => jtag_copy_ram3_ram3a_dout,
+ -- RAM3b
+ RAMB_A_OUT => jtag_copy_ram3_ram3b_a,
+ RAMB_D_OUT => jtag_copy_ram3_ram3b_din,
+ RAMB_WR_OUT => jtag_copy_ram3_ram3b_wr,
+
+ IDLE_OUT => jtag_copy_ram3_idle
+ );
+
+the_jtag_blank_ram3a : blank_ram
+ generic map (
+ ram_depth => RAM_ERROR_COUNTS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_BLANK_IN => trigger_blank_ram3a,
+ -- RAM
+-- RAM_A_OUT => jtag_blank_ram3a_ram3a_a,
+ RAM_A_OUT => open,
+-- RAM_D_OUT => jtag_blank_ram3a_ram3a_din,
+ RAM_D_OUT => open,
+-- RAM_WR_OUT => jtag_blank_ram3a_ram3a_wr, -- disabling blanking ram 29.10.2012
+ RAM_WR_OUT => open,
+
+ IDLE_OUT => jtag_blank_ram3a_idle
+ );
+jtag_blank_ram3a_ram3a_a <= (others => '0');
+jtag_blank_ram3a_ram3a_din <= (others => '0');
+jtag_blank_ram3a_ram3a_wr <= '0';
+
+
+the_jtag_update_error_counts_ram3a : jtag_update_error_counts_ram3a
+ generic map (
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGISTERS_PLUS_TWO_LD => MAX_REGISTERS_PLUS_TWO_LD,
+ RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
+ RAM_ERROR_COUNTS_DEPTH => RAM_ERROR_COUNTS_DEPTH,
+ WRITE_ERROR_THRESHOLD => WRITE_ERROR_THRESHOLD,
+ READ_ERROR_THRESHOLD => READ_ERROR_THRESHOLD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_UPDATE_DATA_CHANGED_IN => trigger_juec_update_d_ch,
+ TRIGGER_UPDATE_READ_ERRORS_IN => trigger_juec_update_rd_err,
+ TRIGGER_UPDATE_WRITE_ERRORS_IN => trigger_juec_update_wr_err,
+ TRIGGER_UPDATE_RUN_COUNTER_IN => trigger_juec_update_run_counter,
+ RUN_COUNTER_IN => std_logic_vector(run_counter),
+ -- RAM2
+ RAM2_A_OUT => juec_ram2_a,
+ RAM2_D_IN => juec_ram2_dout,
+ -- RAM3a
+ RAM3A_A_OUT => juec_ram3a_a,
+ RAM3A_D_IN => juec_ram3a_dout,
+ RAM3A_D_OUT => juec_ram3a_din,
+ RAM3A_WR_OUT => juec_ram3a_wr,
+
+ REMOVED_CHIPS_IN => removed_chips,
+ NUMCHIPS_CONFIGURED_IN => std_logic_vector(numchips_configured),
+ NUMREGS_CONFIGURED_IN => jtag_write_numregs_configured,
+
+ DATA_CHANGED_OUT => juec_data_changed,
+ READ_ERRORS_OUT => juec_read_errors,
+ WRITE_ERRORS_OUT => juec_write_errors,
+
+ IDLE_OUT => juec_idle
+ );
+
+-- the_jtag_bypassreg_testchain_m10: jtag_bypassreg_testchain_m10
+-- generic map (
+-- ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
+-- MAX_NUMCHIPS => MAX_NUMCHIPS,
+-- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+-- JTAG_M26_IRLEN => JTAG_M26_IRLEN,
+-- max_bitcounter_ld => MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7
+-- )
+-- port map(
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+-- TRIGGER_BEGIN_TESTCHAIN_IN => trigger_begin_bypassreg,
+-- IDLE_OUT => jtag_bypassreg_idle,
+-- CHAIN_LENGTH_OUT => jtag_bypassreg_length,
+-- CHAIN_BROKEN_OUT => jtag_bypassreg_chain_broken,
+-- ENABLE_JTAG_CLOCK_OUT => jtag_bypassreg_enable_jtag_clock,
+-- LAST_TCK_CYCLE_OUT => jtag_bypassreg_last_tck_cycle,
+-- TMS_OUT => jtag_bypassreg_tms,
+-- TDI_OUT => jtag_bypassreg_tdi,
+-- TDO_IN => jtag_tdo_sampled,
+-- DELAY_IN => jtag_delay_expvalues
+-- );
+
+the_jtag_read_m26devid_m10: jtag_read_m26devid_m10
+ generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ RAM_JTAG_REGISTERS_A_OUT => jtag_read_ram1a_a,
+ RAM_JTAG_REGISTERS_D_IN => jtag_read_ram1a_d,
+ NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
+ BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+ TRIGGER_BEGIN_READ_IN => trigger_jtag_read,
+ IS_DR_BIT_OUT => jtag_read_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_read_is_firstbit,
+ IS_LASTBIT_OUT => jtag_read_is_lastbit,
+ CHIPNUM_OUT => jtag_read_chipnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_read_enable_jtag_clock,
+ LAST_TCK_CYCLE_OUT => jtag_read_last_tck_cycle,
+ TMS_OUT => jtag_read_tms,
+ TDI_OUT => jtag_read_tdi,
+ EXPECTED_TDO_OUT => jtag_read_expected_tdo,
+ IDLE_OUT => jtag_read_idle
+ );
+
+the_jtag_tdo_data_to_ram_m10 : jtag_tdo_data_to_ram_m10
+ generic map (
+ enable_ram1b => '1',
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGLEN_LD => MAX_REGLEN_LD,
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ CHIPNUM_IN => jtag_delayed_chipnum,
+ REGNUM_IN => jtag_delayed_regnum,
+ ENABLE_DATAOUT_IN => jtag_delayed_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
+ IS_LASTBIT_IN => jtag_delayed_is_lastbit,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ -- RAM1b
+ RAM_JTAG_REGISTERS_READOUT_A_OUT => jtag_data_to_ram_ram1b_a,
+ RAM_JTAG_REGISTERS_READOUT_D_IN => jtag_data_to_ram_ram1b_dout,
+ RAM_JTAG_REGISTERS_READOUT_WE_OUT => jtag_data_to_ram_ram1b_wr,
+ RAM_JTAG_REGISTERS_READOUT_D_OUT => jtag_data_to_ram_ram1b_din
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+
+the_jtag_tdo_compare_count_m10 : jtag_tdo_compare_count_m10
+ generic map (
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
+ MAX_REGLEN_LD => MAX_REGLEN_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ CHIPNUM_IN => jtag_delayed_chipnum,
+ REGNUM_IN => jtag_delayed_regnum,
+ ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
+ IS_LASTBIT_IN => jtag_delayed_is_lastbit,
+ TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
+ RAM_MATCH_DIFF_COUNT_A_OUT => jtag_tdo_compare_count_ram_a,
+ RAM_MATCH_DIFF_COUNT_WE_OUT => jtag_tdo_compare_count_ram_wr,
+ RAM_MATCH_DIFF_COUNT_D_OUT => jtag_tdo_compare_count_ram_din
+ --INTERNAL_ERROR_OUT => jtag_tdo_compare_count_internal_error
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+
+
+the_jtag_tdo_compare_counttotal_noram_m10 : jtag_tdo_compare_counttotal_noram_m10
+ generic map (
+ numcounts => 3,
+ se_counter_width => COUNTER_WIDTHS, -- sampling error counter width
+ diff_counter_width => COUNTER_WIDTHS -- counter width for number of runs in which there were differences
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
+ TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
+ BEGIN_COUNT_I_IN(2) => begin_count_read_errors,
+ BEGIN_COUNT_I_IN(1) => begin_count_write_errors,
+ BEGIN_COUNT_I_IN(0) => begin_count_data_changed,
+
+ END_COUNT_I_IN(2) => end_count_read_errors,
+ END_COUNT_I_IN(1) => end_count_write_errors,
+ END_COUNT_I_IN(0) => end_count_data_changed,
+
+ SAMPLING_ERRORS_COUNT_OUT => SAMPLING_ERRORS_COUNT_OUT,
+ COUNTS_OUT(0*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 0*COUNTER_WIDTHS) => sDATA_CHANGED_COUNT_OUT,
+ COUNTS_OUT(1*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 1*COUNTER_WIDTHS) => sWRITE_ERRORS_COUNT_OUT,
+ COUNTS_OUT(2*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 2*COUNTER_WIDTHS) => sREAD_ID_ERRORS_COUNT_OUT,
+ LAST_VALUES_OUT(2) => last_read_error,
+ LAST_VALUES_OUT(1) => last_write_error,
+ LAST_VALUES_OUT(0) => last_data_changed
+ );
+
+the_jtag_delay_expected_values: jtag_delay_expected_values
+ generic map (
+ ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE1_IN => jtag_sample_pulse1,
+ CHIPNUM_IN => jtag_meta_chipnum,
+ REGNUM_IN => jtag_meta_regnum,
+ IS_DR_BIT_IN => jtag_meta_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_meta_is_firstbit,
+ IS_LASTBIT_IN => jtag_meta_is_lastbit,
+ TDO_EXPECTED_IN => jtag_meta_expected_tdo,
+ OUT_CHIPNUM_OUT => jtag_delayed_chipnum,
+ OUT_REGNUM_OUT => jtag_delayed_regnum,
+ OUT_IS_DR_BIT_OUT => jtag_delayed_is_dr_bit,
+ OUT_IS_FIRSTBIT_OUT => jtag_delayed_is_firstbit,
+ OUT_IS_LASTBIT_OUT => jtag_delayed_is_lastbit,
+ OUT_TDO_EXPECTED_OUT => jtag_delayed_tdo_expected,
+ DELAY_IN => jtag_delay_expvalues
+);
+
+the_jtag_mux_buffer_tms_tdi_out_and_metainfo : jtag_mux_buffer_tms_tdi_out_and_metainfo
+ generic map (
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ JTAG_SET_DATA_IN => jtag_set_data_pulse,
+ -- read DEV_ID inputs
+ RD_TMS_IN => jtag_read_tms,
+ RD_TDI_IN => jtag_read_tdi,
+ RD_IS_DR_BIT_IN => jtag_read_is_dr_bit,
+ RD_IS_FIRSTBIT_IN => jtag_read_is_firstbit,
+ RD_IS_LASTBIT_IN => jtag_read_is_lastbit,
+ RD_CHIPNUM_IN => jtag_read_chipnum,
+ RD_ENABLE_JTAG_CLOCK_IN => jtag_read_enable_jtag_clock,
+ RD_LAST_TCK_CYCLE_IN => jtag_read_last_tck_cycle,
+ RD_EXPECTED_TDO_OUT => jtag_read_expected_tdo,
+ -- write registers inputs
+ WR_TMS_IN => jtag_write_tms,
+ WR_TDI_IN => jtag_write_tdi,
+ WR_IS_DR_BIT_IN => jtag_write_is_dr_bit,
+ WR_IS_FIRSTBIT_IN => jtag_write_is_firstbit,
+ WR_IS_LASTBIT_IN => jtag_write_is_lastbit,
+ WR_CHIPNUM_IN => jtag_write_chipnum,
+ WR_REGNUM_IN => jtag_write_regnum,
+ WR_ENABLE_JTAG_CLOCK_IN => jtag_write_enable_jtag_clock,
+ WR_LAST_TCK_CYCLE_IN => jtag_write_last_tck_cycle,
+ WR_EXPECTED_TDO_OUT => jtag_write_expected_tdo,
+ -- test chain inputs
+ TC_TMS_IN => jtag_bypassreg_tms,
+ TC_TDI_IN => jtag_bypassreg_tdi,
+ TC_ENABLE_JTAG_CLOCK_IN => jtag_bypassreg_enable_jtag_clock,
+ TC_LAST_TCK_CYCLE_IN => jtag_bypassreg_last_tck_cycle,
+
+ TMS_OUT => jtag_tms,
+ TDI_OUT => jtag_tdi,
+ IS_DR_BIT_OUT => jtag_meta_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_meta_is_firstbit,
+ IS_LASTBIT_OUT => jtag_meta_is_lastbit,
+ CHIPNUM_OUT => jtag_meta_chipnum,
+ REGNUM_OUT => jtag_meta_regnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_enable_clock,
+ LAST_TCK_CYCLE_OUT => jtag_meta_last_tck_cycle,
+ EXPECTED_TDO_OUT => jtag_meta_expected_tdo
+ );
+
+the_jtag_tdo_sampler : jtag_tdo_sample port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE1_IN => jtag_sample_pulse1,
+ SAMPLE_PULSE2_IN => jtag_sample_pulse2,
+ SAMPLE_PULSE3_IN => jtag_sample_pulse3,
+ -- TDO signal, which is to be sampled
+ TDO_IN => JTAG_TDO_IN,
+ -- sampled value of TDO
+ TDO_SAMPLED_OUT => jtag_tdo_sampled,
+ -- sampling error
+ SAMPLING_ERROR_OUT => jtag_tdo_sampling_error
+ );
+
+the_jtag_write_m10: jtag_write_m10 generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGLEN_LD => MAX_REGLEN_LD,
+ MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ RAM_JTAG_REGISTERS_A_OUT => jtag_write_ram1a_a,
+ RAM_JTAG_REGISTERS_D_IN => jtag_write_ram1a_d,
+ NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
+ BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+ TRIGGER_BEGIN_WRITE_IN => trigger_jtag_write,
+ IS_DR_BIT_OUT => jtag_write_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_write_is_firstbit,
+ IS_LASTBIT_OUT => jtag_write_is_lastbit,
+ CHIPNUM_OUT => jtag_write_chipnum,
+ REGNUM_OUT => jtag_write_regnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_write_enable_jtag_clock,
+ LAST_TCK_CYCLE_OUT => jtag_write_last_tck_cycle,
+ TMS_OUT => jtag_write_tms,
+ TDI_OUT => jtag_write_tdi,
+ EXPECTED_TDO_OUT => jtag_write_expected_tdo,
+ IDLE_OUT => jtag_write_idle,
+ NUMREGS_CONFIGURED_OUT => jtag_write_numregs_configured,
+ LAST_ERROR_CODE_OUT => jtag_write_last_error_code
+ );
+
+the_jtag_tck_out: jtag_tck_out_component port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ JTAG_CLOCK_PULSE1_IN => jtag_clock_pulse1,
+ JTAG_CLOCK_PULSE2_IN => jtag_clock_pulse2,
+ ENABLE_JTAG_TCK_IN => jtag_enable_clock,
+
+ TCK_OUT => jtag_tck
+ );
+
+the_jtag_pulses : jtag_pulses generic map (
+ time_bits => 10
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => jtag_pulses_reset_complete,
+ -- input times
+ JTAG_CLOCK_TIME1_IN => std_logic_vector(jtag_clock_time1),
+ JTAG_CLOCK_TIME2_IN => std_logic_vector(jtag_clock_time2),
+ JTAG_SAMPLE_TIME1_IN => std_logic_vector(jtag_sample_time1),
+ JTAG_SAMPLE_TIME2_IN => std_logic_vector(jtag_sample_time2),
+ JTAG_SAMPLE_TIME3_IN => std_logic_vector(jtag_sample_time3),
+ JTAG_SET_DATA_TIME_IN => std_logic_vector(jtag_set_data_time),
+
+ JTAG_CLOCK_CYCLE_LENGTH_IN => std_logic_vector(jtag_clock_cycle_length),
+
+ -- output pulses
+ BEGIN_JTAGBITCALC_OUT => begin_jtag_bitcalc,
+ JTAG_CLOCK_PULSE1_OUT => jtag_clock_pulse1,
+ JTAG_CLOCK_PULSE2_OUT => jtag_clock_pulse2,
+ JTAG_SAMPLE_PULSE1_OUT => jtag_sample_pulse1,
+ JTAG_SAMPLE_PULSE2_OUT => jtag_sample_pulse2,
+ JTAG_SAMPLE_PULSE3_OUT => jtag_sample_pulse3,
+ JTAG_SET_DATA_PULSE_OUT => jtag_set_data_pulse
+ );
+
+the_jtag_check_crc_ram1a: jtag_check_crc_ram1a
+ generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_CHECK_IN => trigger_check_crc_ram1a,
+ -- RAM1a
+ RAM1A_A_OUT => jtag_check_crc_ram1a_a,
+ RAM1A_D_IN => jtag_check_crc_ram1a_d,
+ NUMCHIPS_IN => std_logic_vector(numchips_configured),
+ CRC_OK_OUT => jtag_check_crc_ram1a_crc_ok,
+ IDLE_OUT => jtag_check_crc_ram1a_idle
+ );
+
+
+--BUS_DATA_OUT <= bus_data_out_buffer;
+--BUS_DATAREADY_OUT <= bus_dataready;
+--BUS_NO_MORE_DATA_OUT <= bus_no_more_data;
+--BUS_WRITE_ACK_OUT <= bus_write_ack;
+--BUS_UNKNOWN_ADDR_OUT <= bus_unknown_addr;
+MY_STATUS_OUT <= (others => '0'); --my_status;
+JTAG_TCK_OUT <= jtag_tck;
+JTAG_TMS_OUT <= jtag_tms;
+JTAG_TDI_OUT <= jtag_tdi;
+PROG_JTAG_FINISHED_OUT <= prog_jtag_finished;
+READ_ID_ERRORS_COUNT_OUT <= sREAD_ID_ERRORS_COUNT_OUT;
+WRITE_ERRORS_COUNT_OUT <= sWRITE_ERRORS_COUNT_OUT;
+DATA_CHANGED_COUNT_OUT <= sDATA_CHANGED_COUNT_OUT;
+
+
+jtag_pulses_reset_complete <= jtag_pulses_reset or RESET_IN;
+
+m26cs_stopped <= '1' when m26cs_state = M26CSS_STOPPED else '0';
+
+jtag_sample_pulse3_d1_next <= jtag_sample_pulse3;
+
+ram3b_a2 <= ram3b_a2_base_addr & ram3b_a2_rel_addr; -- hope this is the right order (base_addr should be the MSBs)
+
+SEQUENTIAL : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ --bus_rw_state <= BUS_RW_STATE_IDLE;
+ --status_register <= (others => '0');
+ --status_register_read_error2 <= '0';
+ data_register <= x"00000000";
+ --cmd_register <= x"00000000";
+ --bus_data_out_buffer <= x"00000000";
+ --bus_dataready <= '0';
+ --bus_no_more_data <= '0';
+ --bus_write_ack <= '0';
+ --bus_unknown_addr <= '0';
+ --length_register <= x"00000001";
+ jtag_refresh_active <= '0';
+ jtag_check1_active <= '0';
+ jtag_refresh_active_last <= '0';
+ --trigger_counter <= (others => '0');
+ idle_out_signal <= '0';
+ --status_register_pos <= (others => '0');
+ --status_register_read_running <= '0';
+ --ram_base_addr <= (others => '0');
+ crc_status_register <= (others => '0');
+ --write_trigger <= '0';
+ --write_idle_last <= '0';
+ --write_status_register_or <= (others => '0');
+ removed_chips <= (others => '0');
+ --reactivate_sensor <= (others => '0');
+ --reactivate_sensor_strobe <= (others => '0');
+ --deactivate_sensor <= (others => '0');
+ --deactivate_sensor_strobe <= (others => '0');
+ --disable_write <= '0';
+ --disable_writeerror_for_remove <= '0';
+ --disable_remove <= '0';
+ --debug_one_remove <= '0';
+ --debug_one_remove_strobe <= '0';
+ --removed_strobe <= '0';
+ --read_trigger <= '0';
+ numchips_configured <= (others => '0');
+ --my_status <= (others => '0');
+ --m26c_sensor_cand <= (others => '0');
+ chip_counter_start <= '0';
+ --m26c_firstrun <= '0';
+ --m26c_secondrun <= '0';
+ --mux_sel <= '0';
+ --driver_speed <= x"0005";
+ --already_written <= '0';
+ --read_idle_last <= '0';
+ --write_error_counter <= (others => (others => '0'));
+ --write_error_over_threshold_counter <= (others => (others => '0'));
+ --write_data_changed_counter <= (others => (others => '0'));
+ --read_error_counter <= (others => (others => '0'));
+ --read_error_over_threshold_counter <= (others => (others => '0'));
+ debug_test <= (others =>'0');
+ debug_m26cs_state <= (others => '0');
+ bus2_ram_data_in <= (others => '0');
+ bus2_ram_dataready_in <= '0';
+ bus2_ram_write_ack_in <= '0';
+ bus2_ram_no_more_data_in <= '0';
+ bus2_ram_unknown_addr_in <= '0';
+ buf_bus2_ram_read_enable_out <= '0';
+ buf_buf_bus2_ram_read_enable_out <= '0';
+ bus2_status_data_in <= (others =>'0');
+ bus2_status_dataready_in <= '0';
+ bus2_status_write_ack_in <= '0';
+ bus2_status_no_more_data_in <= '0';
+ bus2_status_unknown_addr_in <= '0';
+ bus2_control_data_in <= (others =>'0');
+ bus2_control_dataready_in <= '0';
+ bus2_control_write_ack_in <= '0';
+ bus2_control_no_more_data_in <= '0';
+ bus2_control_unknown_addr_in <= '0';
+ bus2_debug_data_in <= (others =>'0');
+ bus2_debug_dataready_in <= '0';
+ bus2_debug_write_ack_in <= '0';
+ bus2_debug_no_more_data_in <= '0';
+ bus2_debug_unknown_addr_in <= '0';
+ bus2_status2_data_in <= (others =>'0');
+ bus2_status2_dataready_in <= '0';
+ bus2_status2_write_ack_in <= '0';
+ bus2_status2_no_more_data_in <= '0';
+ bus2_status2_unknown_addr_in <= '0';
+ bus2_status2_read_ram3b <= '0';
+ buf_bus2_status2_read_ram3b <= '0';
+ prog_jtag_finished <= '0';
+ --last_write_successful <= '0';
+ -- NEW SIGNALS
+ ram1a_a1_base_addr <= (others =>'0');
+ ram1a_a1_rel_addr <= (others =>'0');
+ ram1a_din1 <= (others =>'0');
+ ram1a_wr1 <= '0';
+ jtag_status2_copy_requested <= '0';
+ jtag_status2_copy_request_strobe <= '0';
+ cps2_state <= CPS2_IDLE;
+ status2_run_counter <= (others =>'0');
+ status2_chain_status <= (others =>'0');
+ jtag_clock_cycle_length <= (others =>'0');
+ jtag_clock_time1 <= (others =>'0');
+ jtag_clock_time2 <= (others =>'0');
+ jtag_sample_time1 <= (others =>'0');
+ jtag_sample_time2 <= (others =>'0');
+ jtag_sample_time3 <= (others =>'0');
+ jtag_set_data_time <= (others => '0');
+ jtag_pulses_reset <= '0';
+ jtag_sample_pulse3_d1 <= '0';
+ breakpoint_active <= (others => '0');
+ ram1b_a2 <= (others => '0');
+ ram3b_a2_rel_addr <= (others => '0');
+ ram3b_a2_base_addr <= (others => '0');
+
+ ram1b_copy_requested <= '0';
+ ram1c_run_counter <= (others => '0');
+ ram1c_chain_status <= (others => '0');
+ cpr1bc_state <= CPR1BC_IDLE;
+ trigger_copy_ram1b1c <= '0';
+ ram1b1c_copy_trigger_active <= (others => '0');
+ ram1c_a2 <= (others => '0');
+ ram1b1c_copy_trigger_strobe <= (others => '0');
+
+ m26csoptions <= (others => '0');
+ jtag_delay_expvalues <= (others => '0');
+
+ crc_error_on_last_check <= '0';
+ last_run_successful <= '0';
+ last_run_successful_tmp <= '0';
+ else
+ --bus_rw_state <= bus_rw_state_next;
+ --status_register <= status_register_next;
+ --status_register_read_error2 <= status_register_read_error2_next;
+ data_register <= data_register_next;
+ --cmd_register <= cmd_register_next;
+ --bus_data_out_buffer <= bus_data_out_buffer_next;
+ --bus_dataready <= bus_dataready_next;
+ --bus_no_more_data <= bus_no_more_data_next;
+ --bus_write_ack <= bus_write_ack_next;
+ --bus_unknown_addr <= bus_unknown_addr_next;
+ --length_register <= length_register_next;
+ jtag_refresh_active <= jtag_refresh_active_next;
+ jtag_check1_active <= jtag_check1_active_next;
+ jtag_refresh_active_last <= jtag_refresh_active_last_next;
+ --trigger_counter <= trigger_counter_next;
+ idle_out_signal <= idle_out_signal_next;
+ --status_register_pos <= status_register_pos_next;
+ --status_register_read_running <= status_register_read_running_next;
+ --ram_base_addr <= ram_base_addr_next;
+ crc_status_register <= crc_status_register_next;
+ --write_trigger <= write_trigger_next;
+ --write_idle_last <= write_idle_last_next;
+ --write_status_register_or <= write_status_register_or_next;
+ removed_chips <= removed_chips_next;
+ --reactivate_sensor <= reactivate_sensor_next;
+ --reactivate_sensor_strobe <= reactivate_sensor_strobe_next;
+ --deactivate_sensor <= deactivate_sensor_next;
+ --deactivate_sensor_strobe <= deactivate_sensor_strobe_next;
+ --disable_write <= disable_write_next;
+ --disable_writeerror_for_remove <= disable_writeerror_for_remove_next;
+ --disable_remove <= disable_remove_next;
+ --debug_one_remove <= debug_one_remove_next;
+ --debug_one_remove_strobe <= debug_one_remove_strobe_next;
+ --removed_strobe <= removed_strobe_next;
+ --read_trigger <= read_trigger_next;
+ numchips_configured <= numchips_configured_next;
+ --my_status <= my_status_next;
+ --m26c_sensor_cand <= m26c_sensor_cand_next;
+ chip_counter_start <= chip_counter_start_next;
+ --m26c_firstrun <= m26c_firstrun_next;
+ --m26c_secondrun <= m26c_secondrun_next;
+ --mux_sel <= mux_sel_next;
+ --driver_speed <= driver_speed_next;
+ --already_written <= already_written_next;
+ --read_idle_last <= read_idle_last_next;
+ --write_error_counter <= write_error_counter_next;
+ --write_error_over_threshold_counter <= write_error_over_threshold_counter_next;
+ --write_data_changed_counter <= write_data_changed_counter_next;
+ --read_error_counter <= read_error_counter_next;
+ --read_error_over_threshold_counter <= read_error_over_threshold_counter_next;
+ --m26c_state <= m26c_state_next;
+ debug_test <= debug_test_next;
+ debug_m26cs_state <= debug_m26cs_state_next;
+ bus2_ram_data_in <= bus2_ram_data_in_next;
+ bus2_ram_dataready_in <= bus2_ram_dataready_in_next;
+ bus2_ram_write_ack_in <= bus2_ram_write_ack_in_next;
+ bus2_ram_no_more_data_in <= bus2_ram_no_more_data_in_next;
+ bus2_ram_unknown_addr_in <= bus2_ram_unknown_addr_in_next;
+ buf_bus2_ram_read_enable_out <= buf_bus2_ram_read_enable_out_next;
+ buf_buf_bus2_ram_read_enable_out <= buf_buf_bus2_ram_read_enable_out_next;
+ bus2_status_data_in <= bus2_status_data_in_next;
+ bus2_status_dataready_in <= bus2_status_dataready_in_next;
+ bus2_status_write_ack_in <= bus2_status_write_ack_in_next;
+ bus2_status_no_more_data_in <= bus2_status_no_more_data_in_next;
+ bus2_status_unknown_addr_in <= bus2_status_unknown_addr_in_next;
+ bus2_control_data_in <= bus2_control_data_in_next;
+ bus2_control_dataready_in <= bus2_control_dataready_in_next;
+ bus2_control_write_ack_in <= bus2_control_write_ack_in_next;
+ bus2_control_no_more_data_in <= bus2_control_no_more_data_in_next;
+ bus2_control_unknown_addr_in <= bus2_control_unknown_addr_in_next;
+ bus2_debug_data_in <= bus2_debug_data_in_next;
+ bus2_debug_dataready_in <= bus2_debug_dataready_in_next;
+ bus2_debug_write_ack_in <= bus2_debug_write_ack_in_next;
+ bus2_debug_no_more_data_in <= bus2_debug_no_more_data_in_next;
+ bus2_debug_unknown_addr_in <= bus2_debug_unknown_addr_in_next;
+ bus2_status2_data_in <= bus2_status2_data_in_next;
+ bus2_status2_dataready_in <= bus2_status2_dataready_in_next;
+ bus2_status2_write_ack_in <= bus2_status2_write_ack_in_next;
+ bus2_status2_no_more_data_in <= bus2_status2_no_more_data_in_next;
+ bus2_status2_unknown_addr_in <= bus2_status2_unknown_addr_in_next;
+ bus2_status2_read_ram3b <= bus2_status2_read_ram3b_next;
+ buf_bus2_status2_read_ram3b <= buf_bus2_status2_read_ram3b_next;
+ prog_jtag_finished <= prog_jtag_finished_next;
+ --last_write_successful <= last_write_successful_next;
+ -- NEW SIGNALS
+ ram1a_a1_base_addr <= ram1a_a1_base_addr_next;
+ ram1a_a1_rel_addr <= ram1a_a1_rel_addr_next;
+ ram1a_din1 <= ram1a_din1_next;
+ ram1a_wr1 <= ram1a_wr1_next;
+ jtag_status2_copy_requested <= jtag_status2_copy_requested_next;
+ jtag_status2_copy_request_strobe <= jtag_status2_copy_request_strobe_next;
+ cps2_state <= cps2_state_next;
+ status2_run_counter <= status2_run_counter_next;
+ status2_chain_status <= status2_chain_status_next;
+ jtag_clock_cycle_length <= jtag_clock_cycle_length_next;
+ jtag_clock_time1 <= jtag_clock_time1_next;
+ jtag_clock_time2 <= jtag_clock_time2_next ;
+ jtag_sample_time1 <= jtag_sample_time1_next;
+ jtag_sample_time2 <= jtag_sample_time2_next;
+ jtag_sample_time3 <= jtag_sample_time3_next;
+ jtag_set_data_time <= jtag_set_data_time_next;
+ jtag_pulses_reset <= jtag_pulses_reset_next;
+ jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next;
+ breakpoint_active <= breakpoint_active_next;
+ ram1b_a2 <= ram1b_a2_next;
+ ram3b_a2_rel_addr <= ram3b_a2_rel_addr_next;
+ ram3b_a2_base_addr <= ram3b_a2_base_addr_next;
+
+ ram1b_copy_requested <= ram1b_copy_requested_next;
+ ram1c_run_counter <= ram1c_run_counter_next;
+ ram1c_chain_status <= ram1c_chain_status_next;
+ cpr1bc_state <= cpr1bc_state_next;
+ trigger_copy_ram1b1c <= trigger_copy_ram1b1c_next;
+ ram1b1c_copy_trigger_active <= ram1b1c_copy_trigger_active_next;
+ ram1c_a2 <= ram1c_a2_next;
+ ram1b1c_copy_trigger_strobe <= ram1b1c_copy_trigger_strobe_next;
+
+ m26csoptions <= m26csoptions_next;
+ jtag_delay_expvalues <= jtag_delay_expvalues_next;
+ crc_error_on_last_check <= crc_error_on_last_check_next;
+ last_run_successful <= last_run_successful_next;
+ last_run_successful_tmp <= last_run_successful_tmp_next;
+ end if;
+ end if;
+end process;
+
+
+SYNCHRONOUS_CHIP_COUNTER : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ cc_state <= CC_IDLE;
+ numchips_active <= (others =>'0');
+ numchips_active_acc <= (others =>'0');
+ cc_chip_i <= (others =>'0');
+ cc_nextnotremoved_i <= (others =>'0');
+ last_not_removed <= (others =>'0');
+ first_not_removed <= (others =>'0');
+ jtag_next_not_removed <= (others =>'0');
+ else
+ cc_state <= cc_state_next;
+ numchips_active <= numchips_active_next;
+ numchips_active_acc <= numchips_active_acc_next;
+ cc_chip_i <= cc_chip_i_next;
+ cc_nextnotremoved_i <= cc_nextnotremoved_i_next;
+ last_not_removed <= last_not_removed_next;
+ first_not_removed <= first_not_removed_next;
+ jtag_next_not_removed <= jtag_next_not_removed_next;
+ end if;
+ end if;
+end process;
+
+COMB_CHIP_COUNTER : process (cc_state, removed_chips, chip_counter_start, numchips_configured, cc_chip_i, cc_nextnotremoved_i, numchips_active, numchips_active_acc, last_not_removed, first_not_removed, jtag_next_not_removed)
+begin
+ cc_state_next <= cc_state;
+ numchips_active_next <= numchips_active;
+ numchips_active_acc_next <= numchips_active_acc;
+ -- index, running through chips
+ cc_chip_i_next <= cc_chip_i;
+ -- index, last not removed sensor
+ cc_nextnotremoved_i_next <= cc_nextnotremoved_i;
+ last_not_removed_next <= last_not_removed;
+ first_not_removed_next <= first_not_removed;
+
+ jtag_next_not_removed_next <= jtag_next_not_removed;
+ case cc_state is
+ when CC_IDLE =>
+ if(chip_counter_start = '1') then
+ -- determine number of chips connected in serial to jtag chain
+ cc_chip_i_next <= (others => '0');
+ cc_nextnotremoved_i_next <= (others => '0'); --position in jtag_next_not_removed,
+ -- with the following initialization no chip will be unremoved, because
+ -- last_not_removed < first_not_removed
+ -- and numchips_active will be set to 0 if really all chips are removed
+ first_not_removed_next <= (others => '1');
+ last_not_removed_next <= (others =>'0');
+ jtag_next_not_removed_next <= (others =>'0');
+ numchips_active_acc_next <= (others => '0');
+ cc_state_next <= CC_COUNT_SENSOR;
+ end if;
+ when CC_COUNT_SENSOR =>
+ if(removed_chips(to_integer(cc_chip_i)) = '0') then
+ numchips_active_acc_next <= numchips_active_acc + 1;
+ last_not_removed_next <= cc_chip_i;
+ -- if first_not_removed unset
+ if(std_logic_vector_all_components_equal_scalar(std_logic_vector(first_not_removed), '1') = '1') then
+ first_not_removed_next <= cc_chip_i;
+ end if;
+ cc_nextnotremoved_i_next <= cc_chip_i + 1; -- next not removed chip after chip i is stored at location (i+1) in jtag_next_not_removed
+ jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD) <=
+ std_logic_vector(cc_chip_i);
+ end if;
+ if(cc_chip_i = numchips_configured - 1) then
+ cc_state_next <= CC_SETNUMCHIPS; -- finished counting active chips
+ else
+ cc_chip_i_next <= cc_chip_i + 1;
+ end if;
+ when CC_SETNUMCHIPS =>
+ jtag_next_not_removed_next((to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '1'); -- set next chip for last chip to invalid
+ numchips_active_next <= numchips_active_acc;
+ cc_state_next <= CC_IDLE;
+ end case;
+end process;
+
+
+-- delay one clock cycle
+jtag_refresh_active_last_next <= jtag_refresh_active;
+
+
+-- monitoring
+--MON_FIFO_WRITE_OUT(0) <= read_mon_write_out;
+--MON_FIFO_WRITE_OUT(1) <= read_mon_write_out;
+--MON_FIFO_WRITE_OUT(2) <= read_mon_write_out;
+-- monitoring debug test
+--MON_FIFO_DATA_OUT(79 downto 64) <= JTAG_M26_DEV_ID(15 downto 0);
+--MON_FIFO_DATA_OUT(111 downto 96) <= JTAG_M26_DEV_ID(31 downto 16);
+--MON_FIFO_WRITE_OUT(2) <= '1';
+--MON_FIFO_WRITE_OUT(3) <= '1';
+
+SYNCHRONOUS_M26_CONTROLLER_SIMPLE : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ m26cs_state <= M26CSS_STOPPED;
+ trigger_begin_bypassreg <= '0';
+ trigger_jtag_read <= '0';
+ trigger_jtag_write <= '0';
+ trigger_copy_ram3 <= '0';
+ trigger_juec_update_d_ch <= '0';
+ trigger_juec_update_rd_err <= '0';
+ trigger_juec_update_wr_err <= '0';
+ trigger_juec_update_run_counter <= '0';
+ trigger_check_crc_ram1a <= '0';
+ trigger_init_ram1b <= '0';
+ trigger_blank_ram3a <= '0';
+ run_counter <= (others =>'0');
+ m26cs_firstrun <= '0';
+ jtag_chain_broken_counter <= (others =>'0');
+ ram1a_select <= (others =>'0');
+ ram1b_select <= '0';
+ ram2_select <= '0';
+ ram3a_select <= '0';
+ ram3a_rd_select <= '0';
+ chain_status <= (others =>'0');
+ request_reset <= '0';
+ reset_wait <= (others =>'0');
+ run_requested <= '0';
+ write_once_requested <= '0';
+ write_once_count <= (others =>'0');
+ -- INSERTLABEL: SYNCHRONOUS reset
+ else
+ m26cs_state <= m26cs_state_next;
+ trigger_begin_bypassreg <= trigger_begin_bypassreg_next;
+ trigger_jtag_read <= trigger_jtag_read_next;
+ trigger_jtag_write <= trigger_jtag_write_next;
+ trigger_copy_ram3 <= trigger_copy_ram3_next;
+ trigger_juec_update_d_ch <= trigger_juec_update_d_ch_next;
+ trigger_juec_update_rd_err <= trigger_juec_update_rd_err_next;
+ trigger_juec_update_wr_err <= trigger_juec_update_wr_err_next;
+ trigger_juec_update_run_counter <= trigger_juec_update_run_counter_next;
+ trigger_check_crc_ram1a <= trigger_check_crc_ram1a_next;
+ trigger_init_ram1b <= trigger_init_ram1b_next;
+ trigger_blank_ram3a <= trigger_blank_ram3a_next;
+ run_counter <= run_counter_next;
+ m26cs_firstrun <= m26cs_firstrun_next;
+ jtag_chain_broken_counter <= jtag_chain_broken_counter_next;
+ ram1a_select <= ram1a_select_next;
+ ram1b_select <= ram1b_select_next;
+ ram2_select <= ram2_select_next;
+ ram3a_select <= ram3a_select_next;
+ ram3a_rd_select <= ram3a_rd_select_next;
+ chain_status <= chain_status_next;
+ request_reset <= request_reset_next;
+ reset_wait <= reset_wait_next;
+ run_requested <= run_requested_next;
+ write_once_requested <= write_once_requested_next;
+ write_once_count <= write_once_count_next;
+ -- INSERTLABEL: SYNCHRONOUS update
+ end if;
+ end if;
+end process;
+
+COMB_M26_CONTROLLER_SIMPLE : process (RUN_REQUEST_IN, WRITE_ONCE_REQUEST_IN, m26cs_state, jtag_bypassreg_last_tck_cycle, jtag_bypassreg_idle, jtag_read_idle, jtag_write_last_tck_cycle, jtag_write_idle, juec_idle, cc_state, breakpoint_active, run_counter, m26cs_firstrun, jtag_status2_copy_requested, jtag_check1_active, jtag_refresh_active, jtag_chain_broken_counter, prog_jtag_finished, ram1a_select, jtag_check_crc_ram1a_idle, jtag_check_crc_ram1a_crc_ok, numchips_configured, ram1a_select, ram1b_select, ram2_select, ram3a_select, ram3a_rd_select, chain_status, jtag_init_ram1b_idle, jtag_bypassreg_chain_broken, jtag_bypassreg_length, crc_status_register, jtag_blank_ram3a_idle, ram1b_copy_requested, jtag_refresh_active_last, m26csoptions, crc_error_on_last_check, last_run_successful, last_run_successful_tmp, last_read_error, last_write_error, request_reset, reset_wait, run_requested, write_once_requested, write_once_count) -- INSERTLABEL: sensitivity list --jtag_read_last_tck_cycle,
+variable output : std_logic;
+variable i : integer;
+begin
+ m26cs_state_next <= m26cs_state;
+ trigger_begin_bypassreg_next <= '0';
+ trigger_jtag_read_next <= '0';
+ trigger_jtag_write_next <= '0';
+ trigger_juec_update_d_ch_next <= '0';
+ trigger_juec_update_rd_err_next <= '0';
+ trigger_juec_update_wr_err_next <= '0';
+ trigger_juec_update_run_counter_next <= '0';
+ trigger_check_crc_ram1a_next <= '0';
+ trigger_init_ram1b_next <= '0';
+ trigger_blank_ram3a_next <= '0';
+ run_counter_next <= run_counter;
+ m26cs_firstrun_next <= m26cs_firstrun;
+ idle_out_signal_next <= '0';
+ jtag_chain_broken_counter_next <= jtag_chain_broken_counter;
+ chip_counter_start_next <= '0';
+ prog_jtag_finished_next <= prog_jtag_finished;
+ chain_status_next <= chain_status;
+ crc_status_register_next <= crc_status_register;
+
+ -- ram multiplexers
+ ram1a_select_next <= ram1a_select;
+ ram1b_select_next <= ram1b_select;
+ ram2_select_next <= ram2_select;
+ ram3a_select_next <= ram3a_select;
+ ram3a_rd_select_next <= ram3a_rd_select;
+
+ crc_error_on_last_check_next <= crc_error_on_last_check;
+ last_run_successful_next <= last_run_successful;
+ last_run_successful_tmp_next <= last_run_successful_tmp;
+ begin_count_read_errors <= '0'; -- added 201210
+ begin_count_write_errors <= '0'; -- added 201210
+ begin_count_data_changed <= '0'; -- added 201210
+ end_count_read_errors <= '0'; -- added 201210
+ end_count_write_errors <= '0'; -- added 201210
+ end_count_data_changed <= '0'; -- added 201210
+ request_reset_next <= request_reset;
+ reset_wait_next <= reset_wait;
+ run_requested_next <= run_requested;
+ write_once_requested_next <= write_once_requested;
+ write_once_count_next <= write_once_count;
+ -- INSERTLABEL: COMB defaults
+
+
+
+ case m26cs_state is
+ when M26CSS_STOPPED =>
+ -- if stopped, start again if jtag_refresh_active is set
+ if(jtag_check1_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
+ m26cs_state_next <= M26CSS_CHECK1_WAIT_FOR_HAVE_TIME;
+ elsif(jtag_refresh_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ -- if just started, reset all counters
+ if(jtag_refresh_active_last = '0') then
+ m26cs_firstrun_next <= '1';
+ end if;
+ end if;
+ when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
+ --if(have_time_for_check) then
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ --end if;
+
+ when M26CSS_WAIT_FOR_TRIGGER =>
+ idle_out_signal_next <= '1';
+ last_run_successful_next <= last_run_successful_tmp;
+ -- if not stopped, test if we should stop
+ if(jtag_refresh_active = '0' or jtag_status2_copy_requested = '1' or ram1b_copy_requested = '1') then
+ ram3a_rd_select_next <= '0'; -- select jtag_copy_ram3_ram3a
+ m26cs_state_next <= M26CSS_STOPPED;
+ else
+ -- if we should not stop, check for off_spill and if we have time for writing
+ if(run_requested = '1') then
+ -- increment run counter (exclusively done here)
+ run_counter_next <= run_counter + 1;
+ prog_jtag_finished_next <= '0';
+ trigger_check_crc_ram1a_next <= '1';
+ ram1a_select_next <= "11"; -- select check_crc_ram1a
+ if(m26cs_firstrun = '1') then
+ trigger_blank_ram3a_next <= '1';
+ ram3a_select_next <= '1'; -- blank_ram3a (at same time)
+ end if;
+ last_run_successful_tmp_next <= '0';
+ m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_BEGIN;
+ elsif(write_once_requested = '1') then
+ trigger_check_crc_ram1a_next <= '1';
+ ram1a_select_next <= "11"; -- select check_crc_ram1a
+ m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN;
+ end if;
+ end if;
+ when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
+ m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_WAIT;
+ when M26CSS_CHECK_CRC_RAM1A_WAIT =>
+ if(jtag_check_crc_ram1a_idle = '1') then
+ crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
+ output := '1';
+ for i in MAX_NUMCHIPS-1 downto 0 loop
+ if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
+ output := '0';
+ end if;
+ end loop;
+ --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
+ if(output = '1') then
+ -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
+ crc_error_on_last_check_next <= '0';
+ trigger_init_ram1b_next <= '1';
+ ram1b_select_next <= '0'; -- select init ram1b
+ ram1a_select_next <= "10"; -- select init ram1b
+ m26cs_state_next <= M26CSS_INIT_RAM1B_BEGIN;
+ else
+ -- crc error in configured chips, don't continue
+ crc_error_on_last_check_next <= '1';
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+ when M26CSS_INIT_RAM1B_BEGIN =>
+ m26cs_state_next <= M26CSS_INIT_RAM1B_WAIT;
+ when M26CSS_INIT_RAM1B_WAIT =>
+ if(jtag_init_ram1b_idle = '1') then
+ if(m26cs_firstrun = '1') then
+ -- skip data changed
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ else
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ ram2_select_next <= '0'; -- tdo_compare_count
+ begin_count_data_changed <= '1';-- added 201210
+ m26cs_state_next <= M26CSS_DATA_CHANGED_BEGIN;
+ end if;
+ end if;
+ when M26CSS_DATA_CHANGED_BEGIN =>
+ m26cs_state_next <= M26CSS_DATA_CHANGED_WAIT;
+ when M26CSS_DATA_CHANGED_WAIT =>
+ if(jtag_write_last_tck_cycle = '1' or jtag_write_idle = '1') then
+ end_count_data_changed <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_BLANK_RAM3A_WAIT;
+ end if;
+ when M26CSS_BLANK_RAM3A_WAIT =>
+ if(jtag_blank_ram3a_idle = '1') then
+ if(breakpoint_active(0) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_d_ch_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_WAIT;
+ when M26CSS_JUEC_DATA_CHANGED_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(1) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ end if;
+ end if;
+
+ when M26CSS_COUNT_CHIPS_BEGIN =>
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ when M26CSS_COUNT_CHIPS_WAIT =>
+ if(cc_state = CC_IDLE) then
+ if(breakpoint_active(2) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+-- if(m26csoptions(0) = '1') then
+ -- skip BYPASSREG CHAIN TEST
+ -- and set CHAIN status to BROKEN
+ chain_status_next(0) <= '1';
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0');
+ -- next state:
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
+-- else
+-- trigger_begin_bypassreg_next <= '1';
+-- m26cs_state_next <= M26CSS_BYPASSREG_BEGIN;
+-- end if;
+ end if;
+ end if;
+ when M26CSS_BYPASSREG_BEGIN =>
+ m26cs_state_next <= M26CSS_BYPASSREG_WAIT;
+ when M26CSS_BYPASSREG_WAIT =>
+ if(jtag_bypassreg_last_tck_cycle = '1' or jtag_bypassreg_idle = '1') then
+ if(breakpoint_active(3) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ chain_status_next(0) <= jtag_bypassreg_chain_broken; -- chain broken
+ if(unsigned(jtag_bypassreg_length) < 2**MAX_NUMCHIPS_PLUS_ONE_LD) then
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= jtag_bypassreg_length(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -- chain length
+ else
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0'); -- chain length: set to zero because to long chain found
+ end if;
+ if(jtag_bypassreg_chain_broken = '1') then
+ jtag_chain_broken_counter_next <= jtag_chain_broken_counter + 1;
+
+ --m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
+ else
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN;
+ end if;
+ end if;
+ end if;
+ when M26CSS_READ1_BEGIN =>
+ m26cs_state_next <= M26CSS_READ1_WAIT;
+ when M26CSS_READ1_WAIT =>
+ if(jtag_read_idle = '1') then -- removed (jtag_read_last_tck_cycle = '1' or ) because writing to RAM needs time
+ end_count_read_errors <= '1'; -- added 201210
+ if(breakpoint_active(4) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_rd_err_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_READ_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_READ_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_READ_WAIT;
+ when M26CSS_JUEC_READ_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(5) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ elsif(jtag_check1_active = '1') then
+ -- in case of check1 set, don't write registers
+ -- in order to save time
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_STOPPED;
+ else
+ -- do the following later!
+ --trigger_jtag_write_next <= '1';
+ --ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ --ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ --ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_REQUEST_RESET_BEGIN;
+ end if;
+ end if;
+ when M26CSS_REQUEST_RESET_BEGIN =>
+ request_reset_next <= '1';
+ m26cs_state_next <= M26CSS_REQUEST_RESET_WAIT;
+ when M26CSS_REQUEST_RESET_WAIT =>
+ reset_wait_next <= RESET_WAIT_DURATION;
+ m26cs_state_next <= M26CSS_REQUESTED_RESET_WAIT;
+ when M26CSS_REQUESTED_RESET_WAIT =>
+ reset_wait_next <= reset_wait - 1;
+ request_reset_next <= '0';
+ if(reset_wait = reset_wait_zero) then
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ if(ram1b_copy_requested = '0') then -- this is a hack, to only change ram1b if not yet data changed triggered copy request
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ else
+ ram1b_select_next <= '0';
+ end if;
+ ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_WRITE1_BEGIN;
+ end if;
+ when M26CSS_WRITE1_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITE1_WAIT;
+ when M26CSS_WRITE1_WAIT =>
+ if(jtag_write_idle = '1') then
+ if(breakpoint_active(6) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_jtag_write_next <= '1';
+ begin_count_write_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_WRITE2_BEGIN;
+ end if;
+ end if;
+ when M26CSS_WRITE2_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITE2_WAIT;
+ when M26CSS_WRITE2_WAIT =>
+ if(jtag_write_idle = '1') then
+ end_count_write_errors <= '1'; -- added 201210
+ if(breakpoint_active(7) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ prog_jtag_finished_next <= '1';
+ trigger_juec_update_wr_err_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_WRITE_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_WRITE_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_WRITE_WAIT;
+ when M26CSS_JUEC_WRITE_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(8) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_run_counter_next <= '1';
+ m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_WAIT;
+ when M26CSS_JUEC_RUN_COUNTER_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(9) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ m26cs_firstrun_next <= '0';
+ last_run_successful_tmp_next <= not (last_read_error or last_write_error); -- added 201210
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+
+
+ -- WRITE_ONCE states
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT;
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
+ if(jtag_check_crc_ram1a_idle = '1') then
+ crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
+ output := '1';
+ for i in MAX_NUMCHIPS-1 downto 0 loop
+ if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
+ output := '0';
+ end if;
+ end loop;
+ --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
+ if(output = '1') then
+ -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
+ crc_error_on_last_check_next <= '0';
+ trigger_init_ram1b_next <= '1';
+ ram1b_select_next <= '0'; -- select init ram1b
+ ram1a_select_next <= "10"; -- select init ram1b
+ m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_BEGIN;
+ else
+ -- crc error in configured chips, don't continue
+ crc_error_on_last_check_next <= '1';
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+ when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_WAIT;
+ when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
+ if(jtag_init_ram1b_idle = '1') then
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN;
+ end if;
+ when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_WAIT;
+ when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_BEGIN;
+ when M26CSS_WRITEONCE_WRITE1_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_WAIT;
+ when M26CSS_WRITEONCE_WRITE1_WAIT =>
+ if(jtag_write_idle = '1') then
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ write_once_count_next <= write_once_count + 1;
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end case;
+ if(RUN_REQUEST_IN = '1') then
+ run_requested_next <= '1';
+ end if;
+ if(WRITE_ONCE_REQUEST_IN = '1') then
+ write_once_requested_next <= '1';
+ end if;
+
+end process;
+
+
+status2_copy_finished <= not jtag_status2_copy_requested and not jtag_status2_copy_request_strobe;
+CP_STATUS2 : process(jtag_status2_copy_requested, jtag_status2_copy_request_strobe, status2_chain_status, status2_run_counter, cps2_state, m26cs_state, jtag_copy_ram3_idle, run_counter, chain_status)
+begin
+ jtag_status2_copy_requested_next <= jtag_status2_copy_requested;
+ -- these are all copies of the registers changed in M26CS
+ status2_run_counter_next <= status2_run_counter;
+ status2_chain_status_next <= status2_chain_status;
+ cps2_state_next <= cps2_state;
+ trigger_copy_ram3_next <= '0';
+ case cps2_state is
+ when CPS2_IDLE =>
+ if(jtag_status2_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
+ trigger_copy_ram3_next <= '1';
+ cps2_state_next <= CPS2_COPY_BEGIN;
+ end if;
+ when CPS2_COPY_BEGIN =>
+ status2_run_counter_next <= run_counter;
+ status2_chain_status_next <= chain_status;
+ cps2_state_next <= CPS2_COPY_WAIT;
+ when CPS2_COPY_WAIT =>
+ if(jtag_copy_ram3_idle = '1') then
+ jtag_status2_copy_requested_next <= '0';
+ cps2_state_next <= CPS2_IDLE;
+ end if;
+ end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
+ if(jtag_status2_copy_request_strobe = '1') then
+ jtag_status2_copy_requested_next <= '1';
+ end if;
+end process;
+
+TRIGGER_CP_RAM1B1C : process(ram1b_copy_requested, ram1c_run_counter, ram1c_chain_status, ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_strobe, copy_ram1b1c_idle, cpr1bc_state, m26cs_state, run_counter, chain_status, juec_read_errors, juec_write_errors, juec_data_changed)
+begin
+ ram1b_copy_requested_next <= ram1b_copy_requested;
+ -- these are all copies of the registers changed in M26CS
+ ram1c_run_counter_next <= ram1c_run_counter;
+ ram1c_chain_status_next <= ram1c_chain_status;
+ cpr1bc_state_next <= cpr1bc_state;
+ trigger_copy_ram1b1c_next <= '0';
+ ram1b1c_copy_trigger_active_next <= ram1b1c_copy_trigger_active or ram1b1c_copy_trigger_strobe;
+ case cpr1bc_state is
+ when CPR1BC_IDLE =>
+ if(ram1b_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
+ trigger_copy_ram1b1c_next <= '1';
+ cpr1bc_state_next <= CPR1BC_COPY_BEGIN;
+ end if;
+ when CPR1BC_COPY_BEGIN =>
+ ram1c_run_counter_next <= run_counter;
+ ram1c_chain_status_next <= chain_status;
+ cpr1bc_state_next <= CPR1BC_COPY_WAIT;
+ when CPR1BC_COPY_WAIT =>
+ if(copy_ram1b1c_idle = '1') then
+ ram1b_copy_requested_next <= '0';
+ cpr1bc_state_next <= CPR1BC_IDLE;
+ end if;
+ end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
+ if(juec_read_errors = '1' and ram1b1c_copy_trigger_active(0) = '1') or
+ (juec_write_errors = '1' and ram1b1c_copy_trigger_active(1) = '1') or
+ (juec_data_changed = '1' and ram1b1c_copy_trigger_active(2) = '1') or
+ (ram1b1c_copy_trigger_active(3) = '1') then
+ ram1b_copy_requested_next <= '1';
+ -- deactivate triggers (copy is requested)
+ ram1b1c_copy_trigger_active_next <= (others => '0');
+ end if;
+end process;
+
+
+
+-- -- OR the status bits of all registers separately for each sensor and (JTAG_ERROR, DATA_CHANGED, DATA CHANGED OVER THRESHOLD)
+-- WRITE_STATUS_REG_OR : process(write_status_register)
+-- variable write_status_reg_acc : std_logic_vector(3*MAX_NUMCHIPS-1 downto 0);
+-- begin
+-- write_status_reg_acc := (others => '0');
+-- for i in 0 to MAX_REGISTERS - 1 loop
+-- write_status_reg_acc := write_status_reg_acc or
+-- write_status_register( i*3*MAX_NUMCHIPS + 3*MAX_NUMCHIPS - 1 downto
+-- i*3*MAX_NUMCHIPS);
+-- end loop;
+-- write_status_register_or_next <= write_status_reg_acc;
+-- end process;
+
+
+-- READ_STATUS_REG_OR : process(status_register)
+-- variable read_error2_acc : std_logic;
+-- begin
+-- read_error2_acc := '0';
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- read_error2_acc := read_error2_acc or status_register(STATUS_READ_ERROR2 + i);
+-- end loop;
+-- status_register_read_error2_next <= read_error2_acc;
+-- end process;
+
+--numchips_configured_next <= std_logic_vector(to_unsigned(3,MAX_NUMCHIPS_LD+1));
+--ram_m26c_a1_next(M26C_RAM_DEPTH-1 downto 8) <= ram_base_addr;
+-- put together ram1a address
+ram1a_a1 <= ram1a_a1_base_addr & ram1a_a1_rel_addr;
+buf_bus2_ram_read_enable_out_next <= bus2_ram_read_enable_out;
+buf_buf_bus2_ram_read_enable_out_next <= buf_bus2_ram_read_enable_out;
+BUS2_RAM_RW : process (bus2_ram_addr_out, bus2_ram_data_out, bus2_ram_read_enable_out, bus2_ram_write_enable_out, buf_buf_bus2_ram_read_enable_out, ram1a_dout1, ram1a_din1, ram1a_a1_rel_addr, bus2_ram_data_in, m26cs_stopped)
+begin
+ ram1a_wr1_next <= '0';
+ ram1a_din1_next <= ram1a_din1;
+ ram1a_a1_rel_addr_next <= ram1a_a1_rel_addr;
+ bus2_ram_data_in_next <= bus2_ram_data_in;
+ bus2_ram_dataready_in_next <= '0';
+ bus2_ram_write_ack_in_next <= '0';
+ bus2_ram_no_more_data_in_next <= '0';
+ bus2_ram_unknown_addr_in_next <= '0';
+ if(bus2_ram_write_enable_out='1') then
+ ram1a_din1_next <= bus2_ram_data_out;
+ ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+ -- only allow ram1a to be changed if stopped!
+ if(m26cs_stopped = '1') then
+ ram1a_wr1_next <= '1';
+ bus2_ram_write_ack_in_next <= '1';
+ else
+ bus2_ram_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_ram_read_enable_out='1') then
+ ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+
+ elsif(buf_buf_bus2_ram_read_enable_out='1') then
+ bus2_ram_data_in_next <= ram1a_dout1;
+ bus2_ram_dataready_in_next <= '1';
+ end if;
+end process;
+
+BUS2_STATUS_R : process (bus2_status_addr_out, crc_status_register, bus2_status_read_enable_out, bus2_status_write_enable_out, bus2_status_data_in)
+variable bus_addr_int : integer range 0 to 31;
+begin
+ bus2_status_data_in_next <= bus2_status_data_in;
+ bus2_status_dataready_in_next <= '0';
+ bus2_status_write_ack_in_next <= '0';
+ bus2_status_no_more_data_in_next <= '0';
+ bus2_status_unknown_addr_in_next <= '0';
+ if(bus2_status_read_enable_out='1') then
+ -- STATUS register layout: 8 bits/chip
+ -- first 32 bits : CRC status
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ bus_addr_int := to_integer(unsigned(bus2_status_addr_out(4 downto 0)));
+ if(bus_addr_int = 0) then
+ bus2_status_data_in_next(31 downto MAX_REGISTERS) <= (others => '0');
+ bus2_status_data_in_next(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0);
+ bus2_status_dataready_in_next <= '1';
+-- elsif(4*(bus_addr_int-1) < MAX_NUMCHIPS) then
+-- -- for i in 0 to MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3) loop
+-- -- bus2_status_data_in_next(8*i+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+7 downto 8*i+6) <= (others => '0');
+-- -- end loop;
+-- -- bus2_status_data_in_next(31 downto 8*(MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3)+1)) <= (others => '0');
+--
+-- bus2_status_data_in_next <= (others => '0');
+-- bus2_status_data_in_next(8*0+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+6) <= removed_chips(4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+7 downto 8*0+7) <= (others => '0');
+-- if(4*(bus_addr_int-1)+1 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*1+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+6) <= removed_chips(4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+7 downto 8*1+7) <= (others => '0');
+-- end if;
+-- if(4*(bus_addr_int-1)+2 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*2+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+6) <= removed_chips(4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+7 downto 8*2+7) <= (others => '0');
+-- end if;
+-- if(4*(bus_addr_int-1)+3 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*3+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+3); bus2_status_data_in_next(8*3+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+6) <= removed_chips(4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+7 downto 8*3+7) <= (others => '0');
+-- end if;
+-- bus2_status_dataready_in_next <= '1';
+ else
+ bus2_status_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+ if(bus2_status_write_enable_out='1') then
+ bus2_status_unknown_addr_in_next <= '1';
+ end if;
+end process;
+
+BUS2_CONTROL_RW : process (bus2_control_addr_out, bus2_control_data_out, bus2_control_read_enable_out, bus2_control_write_enable_out, bus2_control_data_in, jtag_refresh_active, ram1a_a1_base_addr, data_register, jtag_check1_active, numchips_configured, removed_chips, jtag_clock_cycle_length, jtag_clock_time1, jtag_clock_time2,
+jtag_sample_time1, jtag_sample_time2, jtag_sample_time3, jtag_set_data_time, breakpoint_active, run_counter, debug_trigger_counter, last_not_removed, m26cs_stopped, numchips_active, m26csoptions, jtag_delay_expvalues
+)
+begin
+ bus2_control_data_in_next <= bus2_control_data_in;
+ bus2_control_dataready_in_next <= '0';
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '0';
+ bus2_control_unknown_addr_in_next <= '0';
+ jtag_refresh_active_next <= jtag_refresh_active;
+ ram1a_a1_base_addr_next <= ram1a_a1_base_addr;
+ data_register_next <= data_register;
+ jtag_status2_copy_request_strobe_next <= '0';
+ jtag_check1_active_next <= jtag_check1_active;
+ numchips_configured_next <= numchips_configured;
+ removed_chips_next <= removed_chips;
+ jtag_clock_cycle_length_next <= jtag_clock_cycle_length;
+ jtag_clock_time1_next <= jtag_clock_time1;
+ jtag_clock_time2_next <= jtag_clock_time2;
+ jtag_sample_time1_next <= jtag_sample_time1;
+ jtag_sample_time2_next <= jtag_sample_time2;
+ jtag_sample_time3_next <= jtag_sample_time3;
+ jtag_set_data_time_next <= jtag_set_data_time;
+ jtag_pulses_reset_next <= '0';
+ breakpoint_active_next <= breakpoint_active;
+ ram1b1c_copy_trigger_strobe_next <= (others => '0');
+ m26csoptions_next <= m26csoptions;
+ jtag_delay_expvalues_next <= jtag_delay_expvalues;
+
+ --driver_speed_next <= driver_speed;
+ --deactivate_sensor_strobe_next <= (others => '0');
+ --reactivate_sensor_strobe_next <= (others => '0');
+ --disable_write_next <= disable_write;
+ --disable_writeerror_for_remove_next <= disable_writeerror_for_remove;
+ --disable_remove_next <= disable_remove;
+ --debug_one_remove_strobe_next <= '0';
+ if(bus2_control_write_enable_out='1') then
+ -- CONTROL registers layout:
+ -- ADDR_CONTROL_CMD
+ -- ADDR_CONTROL_RAM_BASEADDR
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
+ bus2_control_write_ack_in_next <= '1';
+ if(bus2_control_data_out(7 downto 0) = M26C_CMD_START) then
+ jtag_refresh_active_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) =M26C_CMD_START_CHECK1) then
+ jtag_check1_active_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_STOP) then
+ jtag_refresh_active_next <= '0';
+ jtag_check1_active_next <= '0';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REMOVE_SENSOR ) then
+ -- only signal ack if really written
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '1';
+ -- only allowed to change removed chips when not writing to JTAG interface!
+ if(m26cs_stopped = '1') then
+ if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+ removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+ bus2_control_write_ack_in_next <= '1';
+ bus2_control_no_more_data_in_next <= '0';
+ end if;
+ end if;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_INSERT_SENSOR ) then
+ -- only signal ack if really written
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '1';
+ -- only allowed to change removed chips when not writing to JTAG interface!
+ if(jtag_refresh_active = '0' and jtag_check1_active = '0') then
+ if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+ removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '0';
+ bus2_control_write_ack_in_next <= '1';
+ bus2_control_no_more_data_in_next <= '0';
+ end if;
+ end if;
+ --elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_SPEED) then
+ --driver_speed_next <= data_register(15 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_SPEED) then
+-- data_register_next(31 downto 16) <= (others => '0');
+-- data_register_next(15 downto 0) <= driver_speed;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REACTIVATE_SENSOR) then
+-- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+-- reactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+-- end if;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_DEACTIVATE_SENSOR) then
+-- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+-- deactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+-- end if;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_CONFIGURED) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_ACTIVE) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_TRIGGER_COUNT) then
+ data_register_next <= std_logic_vector(debug_trigger_counter);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DISABLE_WRITE) then
+-- data_register_next(31 downto 1) <= (others => '0');
+-- data_register_next(0) <= disable_write;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DISABLE_WRITE) then
+-- disable_write_next <= data_register(0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_LAST_NOT_REMOVED) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED) then
+ data_register_next(31 downto 1) <= (others => '0');
+ data_register_next(0) <= removed_chips(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED32) then
+ data_register_next(31 downto MYMIN(MAX_NUMCHIPS-1, 31)) <= (others => '0');
+ data_register_next(MYMIN(MAX_NUMCHIPS-1, 31) downto 0) <= removed_chips(MYMIN(MAX_NUMCHIPS-1, 31) downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REACTIVATE_SENSOR32) then
+-- data_register_next(31 downto 0) <= reactivate_sensor(31 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DEACTIVATE_SENSOR32) then
+-- data_register_next(31 downto 0) <= deactivate_sensor(31 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_M26_DEV_ID) then
+-- data_register_next <= JTAG_M26_DEV_ID;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_NUMCHIPS_CONFIGURED) then
+ numchips_configured_next <= unsigned(data_register(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0));
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS) then
+-- data_register_next(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= std_logic_vector(numchips_configured);
+-- data_register_next(31 downto MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_BREAKPOINTS) then
+ breakpoint_active_next <= data_register(9 downto 0);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_BREAKPOINTS) then
+ data_register_next(9 downto 0) <= breakpoint_active;
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH) then
+ jtag_clock_cycle_length_next <= unsigned(data_register(9 downto 0));
+ jtag_pulses_reset_next <= '1'; -- reset counter (because maximum value of counter could be exceeded)
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME1) then
+ jtag_clock_time1_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME1) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time1);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME2) then
+ jtag_clock_time2_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME2) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time2);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME1) then
+ jtag_sample_time1_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME1) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time1);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME2) then
+ jtag_sample_time2_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME2) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time2);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME3) then
+ jtag_sample_time3_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME3) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time3);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SET_DATA_TIME) then
+ jtag_set_data_time_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SET_DATA_TIME) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_set_data_time);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_RUN_COUNT) then
+ data_register_next(31 downto 0) <= std_logic_vector(run_counter);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_TO_STATUS2) then
+ jtag_status2_copy_request_strobe_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER) then
+ ram1b1c_copy_trigger_strobe_next(3 downto 0) <= data_register(3 downto 0); -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR) then
+ ram1b1c_copy_trigger_strobe_next(0) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR) then
+ ram1b1c_copy_trigger_strobe_next(1) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED) then
+ ram1b1c_copy_trigger_strobe_next(2) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW) then
+ ram1b1c_copy_trigger_strobe_next(3) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_CSOPTIONS) then
+ m26csoptions_next(0 downto 0) <= data_register(0 downto 0); -- bit 0 => skip bypassreg chaintest
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_CSOPTIONS) then
+ data_register_next(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest
+ data_register_next(31 downto 0+1) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DELAY_EXPECTED_VALUES) then
+ jtag_delay_expvalues_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= data_register(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DELAY_EXPECTED_VALUES) then
+ data_register_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+ data_register_next(31 downto JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_ACTIVITY) then
+ data_register_next(0) <= jtag_refresh_active;
+ data_register_next(1) <= jtag_check1_active;
+ data_register_next(31 downto 2) <= (others => '0');
+ else
+ -- revoke write_ack, which was set preliminary before "if"
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
+ ram1a_a1_base_addr_next <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0);
+ bus2_control_write_ack_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
+ data_register_next <= bus2_control_data_out;
+ bus2_control_write_ack_in_next <= '1';
+ else
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_control_read_enable_out='1') then
+ if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
+ bus2_control_data_in_next <= (others => '0');
+ bus2_control_dataready_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
+ bus2_control_data_in_next(31 downto RAM_JTAG_REGISTERS_DEPTH-8) <= (others => '0');
+ bus2_control_data_in_next(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr;
+ bus2_control_dataready_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
+ bus2_control_data_in_next <= data_register;
+ bus2_control_dataready_in_next <= '1';
+ else
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+BUS2_DEBUG_R : process (bus2_debug_addr_out, bus2_debug_read_enable_out, bus2_debug_write_enable_out, bus2_debug_data_in, debug_m26cs_state, debug_trigger_counter, debug_test, ram1b_a2, ram1b_dout2, bus2_debug_data_out, ram1c_a2, ram1c_dout2, ram1c_chain_status, ram1c_run_counter, debugtdo_timeout, debugtdo_underflow, debugtdo_overflow, debugtdo_full, debugtdo_empty, debugtdo_dout, write_once_count)
+begin
+ bus2_debug_data_in_next <= bus2_debug_data_in;
+ bus2_debug_dataready_in_next <= '0';
+ bus2_debug_write_ack_in_next <= '0';
+ bus2_debug_no_more_data_in_next <= '0';
+ bus2_debug_unknown_addr_in_next <= '0';
+ debug_test_next <= debug_test;
+ ram1b_a2_next <= ram1b_a2;
+ ram1c_a2_next <= ram1c_a2;
+ debugtdo_activate_strobe <= '0';
+ debugtdo_timeout_next <= debugtdo_timeout;
+ debugtdo_rd_en <= '0';
+ resetdebugtdo_strobe <= '0';
+ if(bus2_debug_write_enable_out='1') then
+ if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
+ debug_test_next <= bus2_debug_data_out;
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1BADDR) then
+ ram1b_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1CADDR) then
+ ram1c_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
+ debugtdo_timeout_next <= bus2_debug_data_out(31 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_ACTIVATE) then
+ if( bus2_debug_data_out(0) = '1') then
+ debugtdo_activate_strobe <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ end if;
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_CONTROLFIFO) then
+ if( bus2_debug_data_out(0) = '1') then
+ debugtdo_rd_en <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ elsif( bus2_debug_data_out(4) = '1') then
+ resetdebugtdo_strobe <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ end if;
+ else
+ bus2_debug_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_debug_read_enable_out='1') then
+ if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
+ bus2_debug_data_in_next <= debug_test;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26CS_STATE) then
+ bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+ bus2_debug_data_in_next(7 downto 0) <= debug_m26cs_state;
+ bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_READ_STATE) then
+-- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+-- bus2_debug_data_in_next(7 downto 0) <= read_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_WRITE_STATE) then
+-- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+-- bus2_debug_data_in_next(7 downto 0) <= write_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_JTAG_DRIVER_STATE) then
+-- bus2_debug_data_in_next(31 downto 9) <= (others => '0');
+-- bus2_debug_data_in_next(8 downto 0) <= driver_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TRIGGER_COUNT) then
+ bus2_debug_data_in_next <= std_logic_vector(debug_trigger_counter);
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_VERSION) then
+ bus2_debug_data_in_next <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
+ bus2_debug_dataready_in_next <= '1';
+ bus2_debug_unknown_addr_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1B_DATA) then
+ bus2_debug_data_in_next <= ram1b_dout2;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_DATA) then
+ bus2_debug_data_in_next <= ram1c_dout2;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_RUN_COUNTER) then
+ bus2_debug_data_in_next <= std_logic_vector(ram1c_run_counter);
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_CHAIN_STATUS) then
+ bus2_debug_data_in_next(31 downto 3+MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
+ bus2_debug_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= ram1c_chain_status;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_SAMPLES) then
+ bus2_debug_data_in_next(31 downto 0) <= debugtdo_dout;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_GETFIFOSTATUS) then
+ bus2_debug_data_in_next(0) <= debugtdo_full;
+ bus2_debug_data_in_next(1) <= debugtdo_empty;
+ bus2_debug_data_in_next(2) <= debugtdo_overflow;
+ bus2_debug_data_in_next(3) <= debugtdo_underflow;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
+ bus2_debug_data_in_next(31 downto 0) <= debugtdo_timeout_next;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_WRONCE_COUNT) then
+ bus2_debug_data_in_next(31 downto COUNTER_WIDTHS) <= (others => '0');
+ bus2_debug_data_in_next(COUNTER_WIDTHS-1 downto 0) <= std_logic_vector(write_once_count);
+ bus2_debug_dataready_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+buf_bus2_status2_read_ram3b_next <= bus2_status2_read_ram3b;
+BUS2_STATUS2_R : process (bus2_status2_addr_out, bus2_status2_data_out, bus2_status2_read_enable_out, bus2_status2_write_enable_out, bus2_status2_data_in, status2_copy_finished, status2_chain_status, status2_run_counter, bus2_status_addr_out, buf_bus2_status2_read_ram3b, jtag_refresh_active, ram3b_dout2, ram3b_a2_rel_addr, ram3b_a2_base_addr)
+variable bus_addr_int : integer range 0 to 31;
+begin
+ bus2_status2_data_in_next <= bus2_status2_data_in;
+ bus2_status2_dataready_in_next <= '0';
+ bus2_status2_write_ack_in_next <= '0';
+ bus2_status2_no_more_data_in_next <= '0';
+ bus2_status2_unknown_addr_in_next <= '0';
+ bus2_status2_read_ram3b_next <= '0';
+ ram3b_a2_base_addr_next <= ram3b_a2_base_addr;
+ ram3b_a2_rel_addr_next <= ram3b_a2_rel_addr;
+ if(buf_bus2_status2_read_ram3b = '1') then
+ bus2_status2_data_in_next <= ram3b_dout2;
+ bus2_status2_dataready_in_next <= '1';
+ end if;
+ if(bus2_status2_read_enable_out='1') then
+ -- STATUS register layout: 8 bits/chip
+ -- first 32 bits : CRC status
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ if(bus2_status2_addr_out(4) = '1') then -- ram3b
+ ram3b_a2_rel_addr_next <= bus2_status_addr_out(3 downto 0);
+ bus2_status2_read_ram3b_next <= '1';
+ -- dataready delayed
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_TRIGGERCOUNTER_COPY) then
+ bus2_status2_data_in_next <= std_logic_vector(status2_run_counter);
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_CHAIN_STATUS_COPY) then
+ bus2_status2_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status;
+ bus2_status2_data_in_next(31 downto 8) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_UPDATING) then
+ bus2_status2_data_in_next(0) <= not status2_copy_finished;
+ bus2_status2_data_in_next(31 downto 1) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
+ bus2_status2_data_in_next(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0) <= ram3b_a2_base_addr;
+ bus2_status2_data_in_next(31 downto RAM_ERROR_COUNTS_DEPTH-4 ) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_STARTED) then
+ bus2_status2_data_in_next(0) <= jtag_refresh_active;
+ bus2_status2_data_in_next(31 downto 1) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ else
+ bus2_status2_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+ if(bus2_status2_write_enable_out='1') then
+ if(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
+ ram3b_a2_base_addr_next <= bus2_status2_data_out(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0);
+ bus2_status2_write_ack_in_next <= '1';
+ else
+ bus2_status2_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+--trigger_process : process (trigger_counter)
+--begin
+ --trigger_counter_next <= trigger_counter + 1;
+ --jtag_refresh_start_next <= '0';
+ --if(trigger_counter = "00000000000") then
+ -- jtag_refresh_start_next <= '1';
+ --end if;
+--end process;
+
+-- reactivate_sensor_wait : process (reactivate_sensor, reactivate_sensor_strobe, removed_chips)
+-- begin
+-- reactivate_sensor_next <= reactivate_sensor;
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- if(reactivate_sensor_strobe(i) = '1') then
+-- reactivate_sensor_next(i) <= '1';
+-- elsif(removed_chips(i) = '0') then
+-- reactivate_sensor_next(i) <= '0';
+-- end if;
+-- end loop;
+-- end process;
+-- deactivate_sensor_wait : process (deactivate_sensor, deactivate_sensor_strobe, removed_chips)
+-- begin
+-- deactivate_sensor_next <= deactivate_sensor;
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- if(deactivate_sensor_strobe(i) = '1') then
+-- deactivate_sensor_next(i) <= '1';
+-- elsif(removed_chips(i) = '1') then
+-- deactivate_sensor_next(i) <= '0';
+-- end if;
+-- end loop;
+-- end process;
+--
+-- one_remove_wait : process (debug_one_remove_strobe, removed_strobe)
+-- begin
+-- debug_one_remove_next <= debug_one_remove;
+-- if(removed_strobe = '1') then
+-- debug_one_remove_next <= '0';
+-- elsif(debug_one_remove_strobe = '1') then
+-- debug_one_remove_next <= '1';
+-- end if;
+-- end process;
+
+debug_m26cs_state_process : process (m26cs_state)
+begin
+ case m26cs_state is
+ when M26CSS_WAIT_FOR_TRIGGER =>
+ debug_m26cs_state_next <= x"00";
+ when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
+ debug_m26cs_state_next <= x"20";
+ when M26CSS_CHECK_CRC_RAM1A_WAIT =>
+ debug_m26cs_state_next <= x"21";
+ when M26CSS_INIT_RAM1B_BEGIN =>
+ debug_m26cs_state_next <= x"22";
+ when M26CSS_INIT_RAM1B_WAIT =>
+ debug_m26cs_state_next <= x"23";
+ when M26CSS_DATA_CHANGED_BEGIN =>
+ debug_m26cs_state_next <= x"01";
+ when M26CSS_DATA_CHANGED_WAIT =>
+ debug_m26cs_state_next <= x"02";
+ when M26CSS_BLANK_RAM3A_WAIT =>
+ debug_m26cs_state_next <= x"24";
+ when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
+ debug_m26cs_state_next <= x"03";
+ when M26CSS_JUEC_DATA_CHANGED_WAIT =>
+ debug_m26cs_state_next <= x"04";
+ when M26CSS_COUNT_CHIPS_BEGIN =>
+ debug_m26cs_state_next <= x"05";
+ when M26CSS_COUNT_CHIPS_WAIT =>
+ debug_m26cs_state_next <= x"06";
+ when M26CSS_BYPASSREG_BEGIN =>
+ debug_m26cs_state_next <= x"07";
+ when M26CSS_BYPASSREG_WAIT =>
+ debug_m26cs_state_next <= x"08";
+ when M26CSS_READ1_BEGIN =>
+ debug_m26cs_state_next <= x"09";
+ when M26CSS_READ1_WAIT =>
+ debug_m26cs_state_next <= x"0a";
+ when M26CSS_JUEC_READ_BEGIN =>
+ debug_m26cs_state_next <= x"0b";
+ when M26CSS_JUEC_READ_WAIT =>
+ debug_m26cs_state_next <= x"0c";
+ when M26CSS_WRITE1_BEGIN =>
+ debug_m26cs_state_next <= x"0d";
+ when M26CSS_WRITE1_WAIT =>
+ debug_m26cs_state_next <= x"0e";
+ when M26CSS_WRITE2_BEGIN =>
+ debug_m26cs_state_next <= x"0f";
+ when M26CSS_WRITE2_WAIT =>
+ debug_m26cs_state_next <= x"10";
+ when M26CSS_JUEC_WRITE_BEGIN =>
+ debug_m26cs_state_next <= x"11";
+ when M26CSS_JUEC_WRITE_WAIT =>
+ debug_m26cs_state_next <= x"12";
+ when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
+ debug_m26cs_state_next <= x"13";
+ when M26CSS_STOPPED =>
+ debug_m26cs_state_next <= x"14";
+ when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
+ debug_m26cs_state_next <= x"15";
+ when M26CSS_JUEC_RUN_COUNTER_WAIT =>
+ debug_m26cs_state_next <= x"16";
+ when M26CSS_REQUEST_RESET_BEGIN =>
+ debug_m26cs_state_next <= x"17";
+ when M26CSS_REQUEST_RESET_WAIT =>
+ debug_m26cs_state_next <= x"18";
+ when M26CSS_REQUESTED_RESET_WAIT =>
+ debug_m26cs_state_next <= x"19";
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
+ debug_m26cs_state_next <= x"1a";
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
+ debug_m26cs_state_next <= x"1b";
+ when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
+ debug_m26cs_state_next <= x"1c";
+ when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
+ debug_m26cs_state_next <= x"1d";
+ when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
+ debug_m26cs_state_next <= x"1e";
+ when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
+ debug_m26cs_state_next <= x"1f";
+ when M26CSS_WRITEONCE_WRITE1_BEGIN =>
+ debug_m26cs_state_next <= x"25";
+ when M26CSS_WRITEONCE_WRITE1_WAIT =>
+ debug_m26cs_state_next <= x"26";
+
+ end case;
+end process;
+
+
+IDLE_OUT <= idle_out_signal;
+--write_idle_last_next <= write_idle;
+--read_idle_last_next <= read_idle;
+--SEQ_have_time_COUNTER : process(CLK_IN)
+--begin
+-- if(rising_edge(CLK_IN)) then
+-- if(RESET_IN ='1') then
+-- htcounter <= (others => '0');
+-- have_time_for_write <= '0';
+-- debug_trigger_counter <= (others => '0');
+-- else
+-- htcounter <= htcounter_next;
+-- have_time_for_write <= have_time_for_write_next;
+-- debug_trigger_counter <= debug_trigger_counter_next;
+-- end if;
+-- end if;
+--end process;
+
+---- process for counter and to decide when it's still ok to start a jtag write
+--COMB_have_time_COUNTER : process(htcounter, OFF_SPILL_IN, debug_trigger_counter)
+--begin
+-- htcounter_next <= htcounter + 1;
+-- debug_trigger_counter_next <= debug_trigger_counter;
+-- if(OFF_SPILL_IN = '1') then
+-- htcounter_next <= (others => '0');
+-- debug_trigger_counter_next <= debug_trigger_counter + 1;
+-- end if;
+-- if(to_integer(unsigned(htcounter)) >= 8388608) then -- (about 8/100 seconds = 80ms)
+-- have_time_for_write_next <= '0';
+-- else
+-- have_time_for_write_next <= '1';
+-- end if;
+--end process;
+
+ALL_debugtdo : process( CLK_IN)
+begin
+ if(rising_edge(CLK_IN)) then
+ debugtdo_timeout <= debugtdo_timeout_next;
+ -- COUNTER
+ debugtdo_counter <= std_logic_vector(unsigned(debugtdo_counter) + 1);
+ -- reset counter in idle/stopped states => counter times the elapsed time since start of m26cs state machine
+ -- also clear debugtdo_active
+ if(m26cs_state = M26CSS_WAIT_FOR_TRIGGER or m26cs_state = M26CSS_STOPPED) then
+ debugtdo_counter <= (others => '0');
+ if(debugtdo_ran = '1') then
+ debugtdo_active <= '0';
+ end if;
+ debugtdo_ran <= '0';
+ else
+ debugtdo_ran <= '1';
+ end if;
+ if(debugtdo_activate_strobe = '1') then
+ debugtdo_active <= '1';
+ end if;
+
+ -- RESET
+ if(RESET_IN= '1') then
+ debugtdo_counter <= (others => '0');
+ debugtdo_active <= '0';
+ debugtdo_ran <= '0';
+ end if;
+ end if;
+end process;
+end architecture;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.jtag_constants.all;
+use work.jtag_misc.all;
+--use work.minmax.all;
+--use work.monitor_config.all;
+--use debug.fifo32bit;
+
+
+
+
+entity jtag_cmd_m26c is
+ generic(
+ MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
+ MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
+ MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
+ MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
+ MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
+ MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
+ MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
+ MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
+
+ WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
+
+ READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
+
+ JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
+ JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
+ JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
+ JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
+
+ RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit.
+-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
+ JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
+ JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
+ JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2; -- ceil of ld( value plus one)
+ RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz
+);
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_TMS_OUT : out std_logic;
+ JTAG_TCK_OUT : out std_logic;
+ JTAG_TDI_OUT : out std_logic;
+ JTAG_TDO_IN : in std_logic;
+
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+
+ --OFF_SPILL_IN : in std_logic;
+ RUN_REQUEST_IN : in std_logic;
+ WRITE_ONCE_REQUEST_IN : in std_logic;
+ MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ REQUEST_RESET_OUT : out std_logic;
+ IDLE_OUT : out std_logic;
+ PROG_JTAG_FINISHED_OUT:out std_logic;
+ READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ RUN_COUNTER_OUT : out std_logic_vector(31 downto 0);
+
+ STARTED_OUT : out std_logic;
+ LAST_RUN_SUCCESSFUL_OUT : out std_logic;
+ LAST_DATA_CHANGED_OUT : out std_logic;
+ LAST_WRITE_ERRORS_OUT : out std_logic;
+ LAST_READ_ERRORS_OUT : out std_logic;
+ CRC_ERROR_OUT : out std_logic
+
+ --BUS_TIMEOUT_IN : in std_logic;
+ );
+end entity;
+
+
+architecture arch_cmd_m26c of jtag_cmd_m26c is
+
+-- component fifo32bit IS
+-- port (
+-- clk: IN std_logic;
+-- din: IN std_logic_VECTOR(31 downto 0);
+-- rd_en: IN std_logic;
+-- rst: IN std_logic;
+-- wr_en: IN std_logic;
+-- dout: OUT std_logic_VECTOR(31 downto 0);
+-- empty: OUT std_logic;
+-- full: OUT std_logic;
+-- overflow: OUT std_logic;
+-- underflow: OUT std_logic);
+-- end component;
+
+
+component jtag_pulses is
+ generic (
+ time_bits : integer := 10
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ -- input times
+ JTAG_CLOCK_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_CLOCK_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME3_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SET_DATA_TIME_IN: in std_logic_vector(time_bits -1 downto 0);
+
+
+ JTAG_CLOCK_CYCLE_LENGTH_IN: in std_logic_vector(time_bits -1 downto 0);
+
+ -- output pulses
+ BEGIN_JTAGBITCALC_OUT : out std_logic;
+ JTAG_CLOCK_PULSE1_OUT : out std_logic;
+ JTAG_CLOCK_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE1_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE3_OUT : out std_logic;
+ JTAG_SET_DATA_PULSE_OUT : out std_logic
+
+ );
+end component;
+
+component jtag_tck_out_component is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_CLOCK_PULSE1_IN : in std_logic;
+ JTAG_CLOCK_PULSE2_IN : in std_logic;
+ ENABLE_JTAG_TCK_IN : in std_logic;
+
+ TCK_OUT : out std_logic
+ );
+end component;
+
+component jtag_write_m10 is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_LD : integer;
+ MAX_REGLEN_PLUS_ONE_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ -- the zero'th entry points to the first not removed chip
+ -- a value of (others => '1') means that no more non-removed chips follow
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_WRITE_IN : in std_logic;
+ IDLE_OUT : out std_logic;
+
+ IS_DR_BIT_OUT : out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic;
+
+ -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_OUT : out std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0)
+
+
+ );
+end component;
+
+component jtag_tdo_sample is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
+ -- the first sample is taken directly after this pulse
+ SAMPLE_PULSE1_IN : in std_logic;
+ SAMPLE_PULSE2_IN : in std_logic;
+ SAMPLE_PULSE3_IN : in std_logic;
+
+ -- TDO signal, which is to be sampled
+ TDO_IN : in std_logic;
+ -- sampled value of TDO
+ TDO_SAMPLED_OUT : out std_logic;
+ -- sampling error
+ SAMPLING_ERROR_OUT : out std_logic
+ );
+end component;
+
+component jtag_mux_buffer_tms_tdi_out_and_metainfo is
+ generic (
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- pulse when READ/WRITE/... entity's data should be taken and update
+ -- the output values for TMS,TDI
+ JTAG_SET_DATA_IN : in std_logic;
+
+ -- read DEV_ID inputs
+ RD_TMS_IN : in std_logic;
+ RD_TDI_IN : in std_logic;
+ RD_IS_DR_BIT_IN: in std_logic;
+ RD_IS_FIRSTBIT_IN : in std_logic;
+ RD_IS_LASTBIT_IN : in std_logic;
+ RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ RD_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ RD_LAST_TCK_CYCLE_IN : in std_logic;
+ RD_EXPECTED_TDO_OUT : in std_logic;
+
+ -- write registers inputs
+ WR_TMS_IN : in std_logic;
+ WR_TDI_IN : in std_logic;
+ WR_IS_DR_BIT_IN: in std_logic;
+ WR_IS_FIRSTBIT_IN : in std_logic;
+ WR_IS_LASTBIT_IN : in std_logic;
+ WR_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ WR_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ WR_LAST_TCK_CYCLE_IN : in std_logic;
+ WR_EXPECTED_TDO_OUT : in std_logic;
+
+ -- test chain inputs
+ TC_TMS_IN : in std_logic;
+ TC_TDI_IN : in std_logic;
+ TC_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ TC_LAST_TCK_CYCLE_IN : in std_logic;
+
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ IS_DR_BIT_OUT: out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic
+ );
+end component;
+
+component jtag_delay_expected_values is
+ generic (
+-- delay : integer := 0 -- number of whole jtag clock cycles to delay the expected values
+-- -- because of total distance of the tck-line to the last chip and
+-- -- the length of tdo of this chip back to the fpga
+ ld_maxdelay : integer := 2;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE1_IN : in std_logic;
+
+ -- chipcount as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ IS_DR_BIT_IN : in std_logic;
+ -- firstbit signal: reset counters before sampling this bit
+ IS_FIRSTBIT_IN : in std_logic;
+ -- finish signal: dataout => RAM1b, compareout => RAM2
+ IS_LASTBIT_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+
+
+ -- chipcount as unsigned
+ OUT_CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
+ OUT_REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ OUT_IS_DR_BIT_OUT : out std_logic;
+ -- firstbit signal: reset counters before sampling this bit
+ OUT_IS_FIRSTBIT_OUT : out std_logic;
+ -- finish signal: dataout => RAM1b, compareout => RAM2
+ OUT_IS_LASTBIT_OUT : out std_logic;
+
+ OUT_TDO_EXPECTED_OUT : out std_logic;
+ DELAY_IN : in std_logic_vector(ld_maxdelay -1 downto 0)
+
+ );
+end component;
+
+component jtag_tdo_compare_count_m10
+ generic (
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;
+ MAX_REGLEN_LD : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- active chip as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
+
+ ENABLE_COUNTERS_IN : in std_logic;
+ IS_FIRSTBIT_IN : in std_logic;
+ IS_LASTBIT_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ TDO_SAMPLING_ERROR_IN : in std_logic;
+
+
+ -- RAM2
+ RAM_MATCH_DIFF_COUNT_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+ --RAM_MATCH_DIFF_COUNT_D_IN : in std_logic_vector(31 downto 0);
+ RAM_MATCH_DIFF_COUNT_WE_OUT : out std_logic;
+ RAM_MATCH_DIFF_COUNT_D_OUT : out std_logic_vector(31 downto 0)
+
+ ---- internal error out: signals that read/write sampling has been mixed
+ --INTERNAL_ERROR_OUT : out std_logic
+
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+end component;
+
+component jtag_tdo_compare_counttotal_noram_m10
+ generic (
+ numcounts : integer := 3;
+ se_counter_width : integer := 32; -- sampling error counter width
+ diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
+ -- sample_pulse3 delayed by one clock cycle
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?)
+ ENABLE_COUNTERS_IN : in std_logic;
+
+ TDO_EXPECTED_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ TDO_SAMPLING_ERROR_IN : in std_logic;
+ BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
+ END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
+
+ -- should be zero if timing is good
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0);
+ COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0);
+ LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0)
+
+
+ );
+end component;
+
+
+component jtag_tdo_data_to_ram_m10
+ generic (
+ enable_ram1b : std_logic := '1';
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_LD : integer;
+ RAM_JTAG_REGISTERS_DEPTH : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SAMPLE_PULSE3_D1_IN : in std_logic;
+ -- active chip as unsigned
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+ -- dataout => RAM1b
+ ENABLE_DATAOUT_IN : in std_logic;
+ IS_FIRSTBIT_IN : in std_logic;
+ IS_LASTBIT_IN : in std_logic;
+ TDO_SAMPLED_IN : in std_logic;
+ -- RAM1b
+ RAM_JTAG_REGISTERS_READOUT_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_READOUT_D_IN : in std_logic_vector(31 downto 0);
+ RAM_JTAG_REGISTERS_READOUT_WE_OUT : out std_logic;
+ RAM_JTAG_REGISTERS_READOUT_D_OUT : out std_logic_vector(31 downto 0)
+
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+end component;
+
+component jtag_read_m26devid_m10 is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ -- the zero'th entry points to the first not removed chip
+ -- a value of (others => '1') means that no more non-removed chips follow
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_READ_IN : in std_logic;
+
+
+
+ IS_DR_BIT_OUT : out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic;
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component jtag_bypassreg_testchain_m10 is
+ generic (
+-- delay : integer := 0; -- this is the same value as in jtag_delay_expected_values
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ JTAG_M26_IRLEN : integer;
+
+ max_bitcounter_ld : integer;-- set to: MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-- bitcounter counts to ir_fill_ones_length, to zerofill_length aswell as from begin of sending pattern to end of receiving pattern (zerofill_length). should write something like: max(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD, 7)+1.
+
+ ld_maxdelay : integer := 2; -- floor of ld maxdelay
+ pattern_length : integer := 4;
+ pattern : std_logic_vector(4-1 downto 0) := "1001";
+ zerofill_numzeros_required : integer := 5 -- minimum number of zeros appearing at tdo while first zero filling phase
+ );
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_TESTCHAIN_IN : in std_logic;
+ IDLE_OUT : out std_logic;
+
+ -- length in chips of the chain -- corresponds to the number of bits the
+ -- output is shifted compared to the input, because the BYPASS registers
+ -- are selected, which are only one bit long
+ CHAIN_LENGTH_OUT : out std_logic_vector(max_bitcounter_ld-1 downto 0);
+ -- if after feeding in a sufficiently long sequence
+ -- the expected output pattern doesnt occur
+ CHAIN_BROKEN_OUT : out std_logic;
+
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ TDO_IN : in std_logic;
+ DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0)
+ );
+end component;
+
+component jtag_update_error_counts_ram3a is
+ generic (
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_PLUS_TWO_LD : integer;
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;
+ RAM_ERROR_COUNTS_DEPTH : integer;
+ WRITE_ERROR_THRESHOLD : integer;
+ READ_ERROR_THRESHOLD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TRIGGER_UPDATE_DATA_CHANGED_IN : in std_logic;
+ TRIGGER_UPDATE_READ_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_WRITE_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_RUN_COUNTER_IN : in std_logic;
+ RUN_COUNTER_IN : in std_logic_vector(31 downto 0);
+ -- RAM2
+ RAM2_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+ RAM2_D_IN : in std_logic_vector(31 downto 0);
+ -- RAM3a
+ RAM3A_A_OUT : out std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+ RAM3A_D_IN : in std_logic_vector(31 downto 0);
+ RAM3A_D_OUT : out std_logic_vector(31 downto 0);
+ RAM3A_WR_OUT :out std_logic;
+
+ REMOVED_CHIPS_IN : in std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+ NUMCHIPS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+ -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ -- if true, there were read errors in last dev_id read
+ READ_ERRORS_OUT : out std_logic;
+ -- if true, there were read errors the last double write to registers (value read the second time didn't equal programmed value)
+ WRITE_ERRORS_OUT : out std_logic;
+ -- if true, the data read from the registers wasn't equal to the data programmed a period before (for example in the last spill break)
+ DATA_CHANGED_OUT : out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+component jtag_init_ram1b is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_INIT_IN : std_logic;
+ -- RAM1a
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);
+ -- RAM1b
+ RAM1B_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1B_D_IN : in std_logic_vector(31 downto 0);
+ RAM1B_WE_OUT : out std_logic;
+ RAM1B_D_OUT : out std_logic_vector(31 downto 0);
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component copy_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_COPY_IN : std_logic;
+ -- RAM3a
+ RAMA_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMA_D_IN : in std_logic_vector(ram_width-1 downto 0);
+ -- RAM3b
+ RAMB_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAMB_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAMB_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+component blank_ram is
+ generic (
+ ram_depth : integer;
+ ram_width : integer := 32
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_BLANK_IN : std_logic;
+ -- RAM
+ RAM_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
+ RAM_D_OUT : out std_logic_vector(ram_width-1 downto 0);
+ RAM_WR_OUT :out std_logic;
+
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component jtag_check_crc_ram1a is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ TRIGGER_CHECK_IN : std_logic;
+ -- RAM1a
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);
+
+ NUMCHIPS_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+ CRC_OK_OUT : out std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+ IDLE_OUT : out std_logic
+ );
+end component;
+
+
+component ram_dp is
+ generic(
+ depth : integer := 9;
+ width : integer := 32
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(depth-1 downto 0);
+ dout1 : out std_logic_vector(width-1 downto 0);
+ din1 : in std_logic_vector(width-1 downto 0);
+ a2 : in std_logic_vector(depth-1 downto 0);
+ dout2 : out std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux2to1_readport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : std_logic;
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux4to1_readport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : in std_logic_vector(1 downto 0); -- two bit select input
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+ A2_IN : in std_logic_vector(depth-1 downto 0);
+ D2_OUT : out std_logic_vector(width-1 downto 0);
+ A3_IN : in std_logic_vector(depth-1 downto 0);
+ D3_OUT : out std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+component ram_mux2to1_writeport is
+ generic (
+ depth : integer;
+ width : integer := 32
+ );
+ port (
+ SELECT_IN : in std_logic;
+ A0_IN : in std_logic_vector(depth-1 downto 0);
+ D0_OUT : out std_logic_vector(width-1 downto 0);
+ WR0_IN : in std_logic;
+ DIN0_IN : in std_logic_vector(width-1 downto 0);
+
+ A1_IN : in std_logic_vector(depth-1 downto 0);
+ D1_OUT : out std_logic_vector(width-1 downto 0);
+ WR1_IN : in std_logic;
+ DIN1_IN : in std_logic_vector(width-1 downto 0);
+
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0);
+ RAM_WR_OUT : out std_logic;
+ RAM_DIN_OUT : out std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+
+
+-- component priorityencoder_seq is
+ -- generic ( n : positive;
+ -- ldn:positive -- rounded up ld(n + 1)
+ -- );
+ -- Port ( CLK_IN : in STD_LOGIC;
+ -- RESET_IN : in STD_LOGIC;
+ -- input_vect_IN : in STD_LOGIC_VECTOR (n - 1 downto 0);
+ -- enc_pos_OUT : out STD_LOGIC_VECTOR (ldn - 1 downto 0);
+ -- start_IN : in STD_LOGIC;
+ -- enc_pos_valid_OUT : out STD_LOGIC );
+-- end component;
+
+-- function ld(m:positive) return natural is
+-- variable n : positive;
+-- begin
+-- n = 0;
+-- a: loop
+-- if (2**n >= m) then
+-- return n;
+-- end if;
+-- n = n + 1;
+-- end loop a;
+-- end;
+
+component trb_net16_regio_bus_handler is
+ generic(
+ PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;
+ PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
+ PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
+ DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
+ DAT_READ_ENABLE_IN : in std_logic; -- read pulse
+ DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse
+ DAT_TIMEOUT_IN : in std_logic; -- access timed out
+ DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested
+ DAT_WRITE_ACK_OUT : out std_logic; -- data accepted
+ DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
+
+ BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);
+ BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
+
+ BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);
+ BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+ BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
+
+ STAT_DEBUG : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+constant STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant STATUS_WRITE_ERROR : integer := MAX_NUMCHIPS;
+constant STATUS_WRITE_ERROR2 : integer := 2*MAX_NUMCHIPS;
+constant STATUS_READ_ERROR : integer := 3*MAX_NUMCHIPS;
+constant STATUS_READ_ERROR2 : integer := 4*MAX_NUMCHIPS;
+constant STATUS_DATA_CHANGED : integer := 5*MAX_NUMCHIPS;
+
+constant WRITE_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant WRITE_STATUS_DATA_CHANGED : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant READ_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
+constant READ_STATUS_BIT_ERROR : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+
+constant RAM_MATCH_DIFF_COUNT_DEPTH : integer := MAX_NUMCHIPS_LD + MAX_REGISTERS_PLUS_ONE_LD + 1;--9; -- maximum 32 counts / chip (one for read DEV_ID register, rest for read/write data registers), maximum 16 chips, each count 32 bits
+constant RAM_ERROR_COUNTS_DEPTH : integer := MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD; --10; -- ld(8+4*MAX_REGISTERS)+MAX_NUMCHIPS_LD= MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD
+
+
+
+
+--type BUS_RW_STATE_TYPE is (BUS_RW_STATE_IDLE, BUS_RW_STATE_READ_RAM_WAIT, BUS_RW_STATE_READ_RAM, BUS_RW_STATE_WRITE_RAM, BUS_RW_STATE_RETURN_READ, BUS_RW_STATE_RETURN_WRITE);
+
+--signal bus_rw_state, bus_rw_state_next : BUS_RW_STATE_TYPE;
+--signal dev_state, dev_state_next : DEVICE_STATE_TYPE;
+signal data_register, data_register_next : std_logic_vector(31 downto 0);
+--signal cmd_register, cmd_register_next : std_logic_vector(31 downto 0);
+--signal length_register, length_register_next : std_logic_vector(31 downto 0);
+signal jtag_refresh_active, jtag_refresh_active_next : std_logic;
+signal jtag_check1_active, jtag_check1_active_next : std_logic;
+signal jtag_refresh_active_last, jtag_refresh_active_last_next : std_logic;
+-- has to fit number of 32 bit words needed to represent the status register
+--signal status_register_pos, status_register_pos_next : std_logic_vector(MAX_NUMCHIPS_LD+2+MAX_REGISTERS_LD-5 downto 0);
+--signal status_register_read_running, status_register_read_running_next : std_logic;
+
+-- mostly for debug purposes: status bits
+--signal my_status, my_status_next : std_logic_vector(8 downto 0);
+
+-- status register layout:
+-- bits MAX_NUMCHIPS -1 downto 0 : JTAG ERROR
+-- bits 2*MAX_NUMCHIPS -1 downto MAX_NUMCHIPS : WRITE ERROR
+-- bits 3*MAX_NUMCHIPS -1 downto 2*MAX_NUMCHIPS : WRITE ERROR2
+-- bits 4*MAX_NUMCHIPS -1 downto 3*MAX_NUMCHIPS : READ ERROR
+-- bits 5*MAX_NUMCHIPS -1 downto 4*MAX_NUMCHIPS : READ ERROR2
+-- bits 6*MAX_NUMCHIPS -1 downto 5*MAX_NUMCHIPS : DATA CHANGED
+
+--signal status_register, status_register_next : std_logic_vector(6*MAX_NUMCHIPS-1 downto 0);
+signal crc_status_register, crc_status_register_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+
+--signal status_register_read_error2, status_register_read_error2_next : std_logic;
+
+--signal already_written, already_written_next : std_logic;
+-- contains a "1" at the positions of deactivated sensors
+signal removed_chips, removed_chips_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+signal last_not_removed, last_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
+signal first_not_removed, first_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
+--signal reactivate_sensor, reactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal reactivate_sensor_strobe , reactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal deactivate_sensor, deactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+--signal deactivate_sensor_strobe , deactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+
+--signal disable_write, disable_write_next : std_logic;
+--signal disable_writeerror_for_remove, disable_writeerror_for_remove_next : std_logic;
+--signal disable_remove, disable_remove_next : std_logic;
+--signal debug_one_remove, debug_one_remove_next : std_logic;
+--signal debug_one_remove_strobe, debug_one_remove_strobe_next : std_logic;
+--signal removed_strobe, removed_strobe_next : std_logic;
+--signal m26c_sensor_cand, m26c_sensor_cand_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+
+signal cc_chip_i, cc_chip_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal cc_nextnotremoved_i, cc_nextnotremoved_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal chip_counter_start, chip_counter_start_next : std_logic;
+type CC_STATE_TYPE is (CC_IDLE, CC_COUNT_SENSOR, CC_SETNUMCHIPS);
+signal cc_state, cc_state_next : CC_STATE_TYPE;
+
+
+--type REGISTER_POINTER_TYPE is range MAX_REGISTERS-1 downto 0;
+-- signal status_register_reg_sel, status_register_reg_sel_next : std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
+-- signal status_register_reg_sel_pos, status_register_reg_sel_pos_next : std_logic_vector( (MAX_NUMCHIPS_LD +2 -5)-1 downto 0);
+--signal mux_sel, mux_sel_next : std_logic;
+--signal driver_data_out : std_logic;
+--signal driver_ready_for_cmd : std_logic;
+--signal driver_state_out : std_logic_vector(8 downto 0);
+--signal driver_data_arrived : std_logic;
+--signal driver_data_in : std_logic;
+--signal driver_cmd_in : std_logic_vector(3 downto 0);
+--signal driver_speed , driver_speed_next : std_logic_vector(15 downto 0);
+
+--signal bus_data_out_buffer, bus_data_out_buffer_next : std_logic_vector(31 downto 0);
+--signal bus_dataready, bus_dataready_next : std_logic;
+--signal bus_no_more_data, bus_no_more_data_next : std_logic;
+--signal bus_write_ack, bus_write_ack_next : std_logic;
+--signal bus_unknown_addr, bus_unknown_addr_next : std_logic;
+
+signal ram1a_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1a_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1a_a1_base_addr, ram1a_a1_base_addr_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal ram1a_a1_rel_addr, ram1a_a1_rel_addr_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+signal ram1a_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1a_din1, ram1a_din1_next : std_logic_vector(31 downto 0);
+signal ram1a_wr1, ram1a_wr1_next : std_logic;
+signal ram1a_dout1 : std_logic_vector(31 downto 0);
+
+signal ram1b_a2, ram1b_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1b_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1a_select, ram1a_select_next : std_logic_vector(1 downto 0);
+
+signal ram1b_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1b_din1 : std_logic_vector(31 downto 0);
+signal ram1b_wr1 : std_logic;
+signal ram1b_dout1 : std_logic_vector(31 downto 0);
+signal ram1b_select, ram1b_select_next : std_logic;
+
+signal init_ram1b_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal init_ram1b_ram1a_d : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal init_ram1b_ram1b_dout : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_din : std_logic_vector(31 downto 0);
+signal init_ram1b_ram1b_wr : std_logic;
+
+signal jtag_data_to_ram_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_data_to_ram_ram1b_dout : std_logic_vector(31 downto 0);
+signal jtag_data_to_ram_ram1b_din : std_logic_vector(31 downto 0);
+signal jtag_data_to_ram_ram1b_wr : std_logic;
+
+signal jtag_check_crc_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_check_crc_ram1a_d : std_logic_vector(31 downto 0);
+
+
+-- ram2 port 2: local flipflops
+--signal ram2_a2, ram2_a2_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+--signal ram2_dout2 : std_logic_vector(31 downto 0);
+-- ram2 port 1: non local flipflops, all connected to components
+signal ram2_a1 : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal ram2_din1 : std_logic_vector(31 downto 0);
+signal ram2_wr1 : std_logic;
+signal ram2_dout1 : std_logic_vector(31 downto 0);
+signal ram2_select, ram2_select_next : std_logic;
+
+-- ram3a port 2: local flipflops
+signal ram3a_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3a_dout2 : std_logic_vector(31 downto 0);
+
+-- ram3a port 1: non local flipflops, all connected to components
+signal ram3a_a1 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3a_din1 : std_logic_vector(31 downto 0);
+signal ram3a_wr1 : std_logic;
+signal ram3a_dout1 : std_logic_vector(31 downto 0);
+
+-- ram3b port 1: non local flipflops, all connected to components
+ -- see jtag_copy_ram3* signals
+-- ram3b port 2: local flipflops
+signal ram3b_a2_base_addr, ram3b_a2_base_addr_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0);
+signal ram3b_a2_rel_addr, ram3b_a2_rel_addr_next : std_logic_vector(3 downto 0);
+signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3b_dout2 : std_logic_vector(31 downto 0);
+
+signal ram3a_select, ram3a_select_next : std_logic;
+signal ram3a_rd_select, ram3a_rd_select_next : std_logic;
+
+signal jtag_tdo_compare_count_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal jtag_tdo_compare_count_ram_dout : std_logic_vector(31 downto 0);
+signal jtag_tdo_compare_count_ram_din : std_logic_vector(31 downto 0);
+signal jtag_tdo_compare_count_ram_wr : std_logic;
+
+--signal jtag_update_error_counts_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+--signal jtag_update_error_counts_ram_d : std_logic_vector(31 downto 0);
+
+
+
+
+
+--signal trigger_counter, trigger_counter_next : std_logic_vector(27 downto 0);
+--signal trigger_counter, trigger_counter_next : std_logic_vector(10 downto 0);
+
+
+
+signal idle_out_signal, idle_out_signal_next : std_logic;
+
+--signal write_status_register : std_logic_vector((3*MAX_NUMCHIPS) * MAX_REGISTERS -1 downto 0);
+--signal write_status_register_or, write_status_register_or_next : std_logic_vector((3*MAX_NUMCHIPS) -1 downto 0);
+--signal write_crc_status_register : std_logic_vector(MAX_REGISTERS - 1 downto 0);
+--signal write_cmd_out : std_logic_vector(3 downto 0);
+--signal write_data_out : std_logic;
+--signal write_idle : std_logic;
+--signal write_trigger, write_trigger_next : std_logic;
+--signal write_idle_last, write_idle_last_next : std_logic;
+--signal write_state_out : std_logic_vector(7 downto 0);
+--type ERROR_COUNTER_TYPE is array (MAX_NUMCHIPS -1 downto 0) of std_logic_vector(9 downto 0);
+--signal write_error_counter, write_error_counter_next : ERROR_COUNTER_TYPE;
+--signal write_error_over_threshold_counter, write_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
+--signal write_data_changed_counter, write_data_changed_counter_next : ERROR_COUNTER_TYPE;
+--constant MAX_ERROR_COUNT : std_logic_vector(9 downto 0) := "1111111111";
+
+--signal read_cmd_out : std_logic_vector(3 downto 0);
+--signal read_data_out : std_logic;
+--signal read_trigger, read_trigger_next : std_logic;
+--signal read_status_register : std_logic_vector(3*MAX_NUMCHIPS -1 downto 0);
+--signal read_idle : std_logic;
+--signal read_idle_last, read_idle_last_next : std_logic;
+--signal read_state_out : std_logic_vector(7 downto 0);
+--signal read_error_counter, read_error_counter_next : ERROR_COUNTER_TYPE;
+--signal read_error_over_threshold_counter, read_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
+
+signal numchips_configured, numchips_configured_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+
+signal debug_m26cs_state, debug_m26cs_state_next : std_logic_vector(7 downto 0);
+signal debug_test, debug_test_next : std_logic_vector(31 downto 0);
+
+signal debug_trigger_counter, debug_trigger_counter_next : unsigned(31 downto 0);
+
+--signal bus2_ram_addr_out : std_logic_vector(7 downto 0);
+signal bus2_ram_addr_out : std_logic_vector(15 downto 0);
+signal bus2_ram_data_out : std_logic_vector(31 downto 0);
+signal bus2_ram_read_enable_out : std_logic;
+signal bus2_ram_write_enable_out : std_logic;
+signal bus2_ram_timeout_out : std_logic;
+
+signal bus2_ram_data_in, bus2_ram_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_ram_dataready_in, bus2_ram_dataready_in_next : std_logic;
+signal bus2_ram_write_ack_in, bus2_ram_write_ack_in_next : std_logic;
+signal bus2_ram_no_more_data_in, bus2_ram_no_more_data_in_next : std_logic;
+signal bus2_ram_unknown_addr_in, bus2_ram_unknown_addr_in_next : std_logic;
+
+--signal bus2_status_addr_out : std_logic_vector(4 downto 0);
+signal bus2_status_addr_out : std_logic_vector(15 downto 0);
+signal bus2_status_data_out : std_logic_vector(31 downto 0);
+signal bus2_status_read_enable_out : std_logic;
+signal bus2_status_write_enable_out : std_logic;
+signal bus2_status_timeout_out : std_logic;
+
+signal bus2_status_data_in, bus2_status_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_status_dataready_in, bus2_status_dataready_in_next : std_logic;
+signal bus2_status_write_ack_in, bus2_status_write_ack_in_next : std_logic;
+signal bus2_status_no_more_data_in, bus2_status_no_more_data_in_next : std_logic;
+signal bus2_status_unknown_addr_in, bus2_status_unknown_addr_in_next : std_logic;
+
+--signal bus2_status2_addr_out : std_logic_vector(4 downto 0);
+signal bus2_status2_addr_out : std_logic_vector(15 downto 0);
+signal bus2_status2_data_out : std_logic_vector(31 downto 0);
+signal bus2_status2_read_enable_out : std_logic;
+signal bus2_status2_write_enable_out : std_logic;
+signal bus2_status2_timeout_out : std_logic;
+
+signal bus2_status2_data_in, bus2_status2_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_status2_dataready_in, bus2_status2_dataready_in_next : std_logic;
+signal bus2_status2_write_ack_in, bus2_status2_write_ack_in_next : std_logic;
+signal bus2_status2_no_more_data_in, bus2_status2_no_more_data_in_next : std_logic;
+signal bus2_status2_unknown_addr_in, bus2_status2_unknown_addr_in_next : std_logic;
+
+signal bus2_status2_read_ram3b, bus2_status2_read_ram3b_next : std_logic;
+signal buf_bus2_status2_read_ram3b, buf_bus2_status2_read_ram3b_next : std_logic;
+
+signal status2_run_counter, status2_run_counter_next : unsigned(31 downto 0);
+
+signal status2_chain_status, status2_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+signal status2_copy_finished: std_logic;
+
+
+--signal bus2_control_addr_out : std_logic_vector(4 downto 0);
+signal bus2_control_addr_out : std_logic_vector(15 downto 0);
+signal bus2_control_data_out : std_logic_vector(31 downto 0);
+signal bus2_control_read_enable_out : std_logic;
+signal bus2_control_write_enable_out : std_logic;
+signal bus2_control_timeout_out : std_logic;
+
+signal bus2_control_data_in, bus2_control_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_control_dataready_in, bus2_control_dataready_in_next : std_logic;
+signal bus2_control_write_ack_in, bus2_control_write_ack_in_next : std_logic;
+signal bus2_control_no_more_data_in, bus2_control_no_more_data_in_next : std_logic;
+signal bus2_control_unknown_addr_in, bus2_control_unknown_addr_in_next : std_logic;
+
+--signal bus2_debug_addr_out : std_logic_vector(4 downto 0);
+signal bus2_debug_addr_out : std_logic_vector(15 downto 0);
+signal bus2_debug_data_out : std_logic_vector(31 downto 0);
+signal bus2_debug_read_enable_out : std_logic;
+signal bus2_debug_write_enable_out : std_logic;
+signal bus2_debug_timeout_out : std_logic;
+
+signal bus2_debug_data_in, bus2_debug_data_in_next : std_logic_vector(31 downto 0);
+signal bus2_debug_dataready_in, bus2_debug_dataready_in_next : std_logic;
+signal bus2_debug_write_ack_in, bus2_debug_write_ack_in_next : std_logic;
+signal bus2_debug_no_more_data_in, bus2_debug_no_more_data_in_next : std_logic;
+signal bus2_debug_unknown_addr_in, bus2_debug_unknown_addr_in_next : std_logic;
+
+signal buf_bus2_ram_read_enable_out, buf_bus2_ram_read_enable_out_next : std_logic;
+signal buf_buf_bus2_ram_read_enable_out, buf_buf_bus2_ram_read_enable_out_next : std_logic;
+-- monitoring
+--signal read_mon_write_out : std_logic;
+-- off_spill timer (htcounter)
+--signal htcounter_next, htcounter : unsigned(26 downto 0); -- 27 bit = approx 1.34 seconds
+--signal have_time_for_write, have_time_for_write_next : std_logic;
+signal prog_jtag_finished, prog_jtag_finished_next : std_logic;
+--signal last_write_successful, last_write_successful_next : std_logic;
+
+-- BEGIN NEW SIGNALS
+signal jtag_next_not_removed, jtag_next_not_removed_next : std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+signal jtag_write_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_write_ram1a_d : std_logic_vector(31 downto 0);
+signal trigger_jtag_write, trigger_jtag_write_next : std_logic;
+signal jtag_write_is_dr_bit : std_logic;
+signal jtag_write_is_firstbit : std_logic;
+signal jtag_write_is_lastbit : std_logic;
+signal jtag_write_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_write_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_write_enable_jtag_clock : std_logic;
+signal jtag_write_last_tck_cycle : std_logic;
+signal jtag_write_tms : std_logic;
+signal jtag_write_tdi : std_logic;
+signal jtag_write_expected_tdo : std_logic;
+signal jtag_write_idle : std_logic;
+signal jtag_write_last_error_code: std_logic_vector(2 downto 0);
+signal jtag_write_numregs_configured : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+signal jtag_read_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal jtag_read_ram1a_d : std_logic_vector(31 downto 0);
+signal trigger_jtag_read, trigger_jtag_read_next : std_logic;
+signal jtag_read_is_dr_bit : std_logic;
+signal jtag_read_is_firstbit : std_logic;
+signal jtag_read_is_lastbit : std_logic;
+signal jtag_read_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_read_enable_jtag_clock : std_logic;
+signal jtag_read_last_tck_cycle : std_logic;
+signal jtag_read_tms : std_logic;
+signal jtag_read_tdi : std_logic;
+signal jtag_read_expected_tdo : std_logic;
+signal jtag_read_idle : std_logic;
+
+--signal trigger_bypassreg, trigger_bypassreg_next : std_logic;
+signal jtag_bypassreg_idle : std_logic;
+signal jtag_bypassreg_length : std_logic_vector(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-1 downto 0);
+signal jtag_bypassreg_chain_broken : std_logic;
+signal jtag_bypassreg_enable_jtag_clock : std_logic;
+signal jtag_bypassreg_last_tck_cycle : std_logic;
+signal jtag_bypassreg_tms : std_logic;
+signal jtag_bypassreg_tdi : std_logic;
+-- begin: global_jtag_counter settings
+signal jtag_clock_cycle_length, jtag_clock_cycle_length_next : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us)
+signal jtag_clock_time1, jtag_clock_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_clock_time2, jtag_clock_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time1, jtag_sample_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time2, jtag_sample_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_sample_time3, jtag_sample_time3_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+signal jtag_set_data_time, jtag_set_data_time_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
+-- begin: periodic pulses, periodic with global_jtag_counter
+signal begin_jtag_bitcalc : std_logic;
+signal jtag_sample_pulse1 : std_logic;
+signal jtag_sample_pulse2 : std_logic;
+signal jtag_sample_pulse3 : std_logic;
+signal jtag_sample_pulse3_d1, jtag_sample_pulse3_d1_next : std_logic;
+signal jtag_set_data_pulse : std_logic;
+-- end: periodic pulses
+
+signal jtag_tdo_sampled : std_logic;
+signal jtag_tdo_sampling_error : std_logic;
+
+signal jtag_tms : std_logic;
+signal jtag_tdi : std_logic;
+signal jtag_enable_clock : std_logic;
+
+signal jtag_meta_is_dr_bit : std_logic;
+signal jtag_meta_is_firstbit : std_logic;
+signal jtag_meta_is_lastbit : std_logic;
+signal jtag_meta_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_meta_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_meta_last_tck_cycle : std_logic;
+signal jtag_meta_expected_tdo : std_logic;
+
+signal jtag_delayed_is_dr_bit : std_logic;
+signal jtag_delayed_is_firstbit : std_logic;
+signal jtag_delayed_is_lastbit : std_logic;
+signal jtag_delayed_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+signal jtag_delayed_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+signal jtag_delayed_tdo_expected : std_logic;
+
+-- jtag_update_error_counts
+signal trigger_juec_update_d_ch, trigger_juec_update_d_ch_next : std_logic;
+signal trigger_juec_update_rd_err, trigger_juec_update_rd_err_next : std_logic;
+signal trigger_juec_update_wr_err, trigger_juec_update_wr_err_next : std_logic;
+signal trigger_juec_update_run_counter, trigger_juec_update_run_counter_next : std_logic;
+signal juec_ram2_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal juec_ram2_dout : std_logic_vector(31 downto 0);
+signal juec_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal juec_ram3a_dout : std_logic_vector(31 downto 0);
+signal juec_ram3a_din : std_logic_vector(31 downto 0);
+signal juec_ram3a_wr : std_logic;
+signal juec_idle : std_logic;
+signal juec_data_changed : std_logic;
+signal juec_read_errors : std_logic;
+signal juec_write_errors : std_logic;
+
+signal jtag_copy_ram3_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_copy_ram3_ram3a_dout : std_logic_vector(31 downto 0);
+signal jtag_copy_ram3_ram3b_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_copy_ram3_ram3b_din : std_logic_vector(31 downto 0);
+signal jtag_copy_ram3_ram3b_wr : std_logic;
+signal jtag_copy_ram3_idle : std_logic;
+
+
+signal trigger_blank_ram3a, trigger_blank_ram3a_next : std_logic;
+signal jtag_blank_ram3a_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal jtag_blank_ram3a_ram3a_din : std_logic_vector(31 downto 0);
+signal jtag_blank_ram3a_ram3a_wr : std_logic;
+signal jtag_blank_ram3a_idle : std_logic;
+
+
+type M26CS_STATE_TYPE is (M26CSS_STOPPED, M26CSS_CHECK1_WAIT_FOR_HAVE_TIME, M26CSS_WAIT_FOR_TRIGGER, M26CSS_CHECK_CRC_RAM1A_BEGIN, M26CSS_CHECK_CRC_RAM1A_WAIT, M26CSS_INIT_RAM1B_BEGIN, M26CSS_INIT_RAM1B_WAIT, M26CSS_DATA_CHANGED_BEGIN, M26CSS_DATA_CHANGED_WAIT, M26CSS_BLANK_RAM3A_WAIT, M26CSS_JUEC_DATA_CHANGED_BEGIN, M26CSS_JUEC_DATA_CHANGED_WAIT, M26CSS_COUNT_CHIPS_BEGIN, M26CSS_COUNT_CHIPS_WAIT, M26CSS_BYPASSREG_BEGIN, M26CSS_BYPASSREG_WAIT, M26CSS_READ1_BEGIN, M26CSS_READ1_WAIT, M26CSS_JUEC_READ_BEGIN, M26CSS_JUEC_READ_WAIT, M26CSS_REQUEST_RESET_BEGIN, M26CSS_REQUEST_RESET_WAIT, M26CSS_REQUESTED_RESET_WAIT, M26CSS_WRITE1_BEGIN, M26CSS_WRITE1_WAIT, M26CSS_WRITE2_BEGIN, M26CSS_WRITE2_WAIT, M26CSS_JUEC_WRITE_BEGIN, M26CSS_JUEC_WRITE_WAIT, M26CSS_JUEC_RUN_COUNTER_BEGIN, M26CSS_JUEC_RUN_COUNTER_WAIT,
+M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN, M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT, M26CSS_WRITEONCE_INIT_RAM1B_BEGIN, M26CSS_WRITEONCE_INIT_RAM1B_WAIT, M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN, M26CSS_WRITEONCE_COUNT_CHIPS_WAIT, M26CSS_WRITEONCE_WRITE1_BEGIN, M26CSS_WRITEONCE_WRITE1_WAIT );
+signal m26cs_state, m26cs_state_next : M26CS_STATE_TYPE;
+--signal write_count, write_count_next : std_logic_vector(31 downto 0);
+signal m26cs_stopped : std_logic;
+signal m26cs_firstrun, m26cs_firstrun_next : std_logic;
+signal breakpoint_active, breakpoint_active_next : std_logic_vector(9 downto 0);
+-- chain_status:
+-- bit 0: chain broken
+-- bit 1: CRC_error(s)
+-- bit 2: programmed
+-- bits 3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3: chain length
+signal chain_status, chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+signal trigger_begin_bypassreg, trigger_begin_bypassreg_next : std_logic;
+signal trigger_copy_ram3, trigger_copy_ram3_next : std_logic;
+--signal jtag_tdo_compare_count_internal_error : std_logic;
+signal run_counter, run_counter_next : unsigned(31 downto 0);
+signal jtag_status2_copy_requested, jtag_status2_copy_requested_next : std_logic;
+
+signal jtag_status2_copy_request_strobe, jtag_status2_copy_request_strobe_next : std_logic;
+type CPS2_STATE_TYPE is (CPS2_IDLE, CPS2_COPY_BEGIN, CPS2_COPY_WAIT);
+signal cps2_state, cps2_state_next : CPS2_STATE_TYPE;
+signal jtag_clock_pulse1 : std_logic;
+signal jtag_clock_pulse2 : std_logic;
+signal jtag_tck : std_logic;
+
+signal jtag_pulses_reset, jtag_pulses_reset_next : std_logic;
+signal jtag_pulses_reset_complete : std_logic;
+
+signal jtag_chain_broken_counter, jtag_chain_broken_counter_next : unsigned(JTAG_CHAIN_BROKEN_COUNTER_BITS-1 downto 0);
+
+signal jtag_check_crc_ram1a_crc_ok : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
+signal jtag_check_crc_ram1a_idle : std_logic;
+signal trigger_check_crc_ram1a, trigger_check_crc_ram1a_next : std_logic;
+signal trigger_init_ram1b, trigger_init_ram1b_next : std_logic;
+signal jtag_init_ram1b_idle : std_logic;
+
+signal ram1b1c_copy_trigger_strobe, ram1b1c_copy_trigger_strobe_next : std_logic_vector(3 downto 0);
+signal trigger_copy_ram1b1c, trigger_copy_ram1b1c_next : std_logic;
+signal copy_ram1b1c_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal copy_ram1b1c_ram1b_dout : std_logic_vector(31 downto 0);
+signal copy_ram1b1c_ram1c_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal copy_ram1b1c_ram1c_din : std_logic_vector(31 downto 0);
+signal copy_ram1b1c_ram1c_wr : std_logic;
+signal copy_ram1b1c_idle : std_logic;
+
+signal ram1c_a2, ram1c_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram1c_dout2 : std_logic_vector(31 downto 0);
+
+signal ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_active_next : std_logic_vector(3 downto 0);
+signal ram1b_copy_requested, ram1b_copy_requested_next : std_logic;
+signal ram1c_run_counter, ram1c_run_counter_next : unsigned(31 downto 0);
+signal ram1c_chain_status, ram1c_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+type CPR1BC_STATE_TYPE is (CPR1BC_IDLE, CPR1BC_COPY_BEGIN, CPR1BC_COPY_WAIT);
+signal cpr1bc_state, cpr1bc_state_next : CPR1BC_STATE_TYPE;
+
+-- DEBUGTDO fifo and control signals
+signal tdodebugsamples : std_logic_vector(31 downto 0);
+signal debugtdo_rd_en : std_logic;
+signal debugtdo_wr_en : std_logic;
+signal debugtdo_dout : std_logic_vector(31 downto 0);
+signal debugtdo_empty : std_logic;
+signal debugtdo_full : std_logic;
+signal debugtdo_overflow : std_logic;
+signal debugtdo_underflow : std_logic;
+signal resetdebugtdo_toffifo : std_logic;
+signal resetdebugtdo_strobe : std_logic;
+signal debugtdo_activate_strobe : std_logic;
+signal debugtdo_active : std_logic;
+signal debugtdo_timeout, debugtdo_timeout_next : std_logic_vector(31 downto 0);
+signal debugtdo_counter : std_logic_vector(31 downto 0);
+signal debugtdo_ran : std_logic;
+
+signal crc_error_on_last_check, crc_error_on_last_check_next : std_logic;
+signal last_run_successful, last_run_successful_next : std_logic;
+signal last_run_successful_tmp, last_run_successful_tmp_next : std_logic;
+signal begin_count_read_errors :std_logic;
+signal begin_count_write_errors :std_logic;
+signal begin_count_data_changed :std_logic;
+signal end_count_read_errors :std_logic;
+signal end_count_write_errors :std_logic;
+signal end_count_data_changed :std_logic;
+signal last_read_error : std_logic;
+signal last_write_error : std_logic;
+signal last_data_changed : std_logic;
+
+signal sREAD_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+signal sWRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+signal sDATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+
+-- INSERTLABEL: signals
+
+signal m26csoptions, m26csoptions_next : std_logic_vector(0 downto 0);
+signal jtag_delay_expvalues, jtag_delay_expvalues_next : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+
+signal request_reset, request_reset_next : std_logic;
+signal reset_wait, reset_wait_next : unsigned(7 downto 0);
+constant reset_wait_zero : unsigned(7 downto 0) := "00000000";
+
+signal run_requested, run_requested_next : std_logic;
+signal write_once_requested, write_once_requested_next : std_logic;
+signal write_once_count, write_once_count_next : unsigned(COUNTER_WIDTHS-1 downto 0);
+
+
+
+begin
+
+--fifo32bit_debugtdo : fifo32bit
+--port map(
+-- clk => CLK_IN,
+-- din => tdodebugsamples(31 downto 0),
+-- rd_en => debugtdo_rd_en,
+-- rst => resetdebugtdo_toffifo,
+-- wr_en => debugtdo_wr_en,
+-- dout => debugtdo_dout(31 downto 0),
+-- empty => debugtdo_empty,
+-- full => debugtdo_full,
+-- overflow => debugtdo_overflow,
+-- underflow => debugtdo_underflow);
+
+
+
+jtag_bypassreg_enable_jtag_clock <= '0';
+
+
+resetdebugtdo_toffifo <= resetdebugtdo_strobe OR RESET_IN;
+debugtdo_wr_en <= '1' when debugtdo_active = '1' and debugtdo_timeout <= debugtdo_counter else '0';
+
+tdodebugsamples(31) <= begin_jtag_bitcalc;
+tdodebugsamples(30) <= jtag_clock_pulse1;
+tdodebugsamples(29) <= jtag_clock_pulse2;
+tdodebugsamples(28) <= jtag_sample_pulse1;
+tdodebugsamples(27) <= jtag_sample_pulse2;
+tdodebugsamples(26) <= jtag_sample_pulse3;
+tdodebugsamples(25) <= jtag_set_data_pulse;
+tdodebugsamples(1) <= JTAG_TDO_IN;
+
+RUN_COUNTER_OUT <= std_logic_vector(run_counter);
+STARTED_OUT <= jtag_refresh_active;
+CRC_ERROR_OUT <= crc_error_on_last_check;
+LAST_RUN_SUCCESSFUL_OUT <= last_run_successful;
+LAST_DATA_CHANGED_OUT <= last_data_changed;
+LAST_WRITE_ERRORS_OUT <= last_write_error;
+LAST_READ_ERRORS_OUT <= last_read_error;
+
+REQUEST_RESET_OUT <= request_reset;
+
+the_bus_handler : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", others => (others => '0')),
+ PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DAT_ADDR_IN(15 downto 9) => "0000000",
+ DAT_ADDR_IN(8 downto 0)=> BUS_ADDR_IN, -- address bus
+ DAT_DATA_IN => BUS_DATA_IN, -- data from TRB endpoint
+ DAT_DATA_OUT => BUS_DATA_OUT, -- data to TRB endpoint
+ DAT_READ_ENABLE_IN => BUS_READ_IN, -- read pulse
+ DAT_WRITE_ENABLE_IN => BUS_WRITE_IN, -- write pulse
+ DAT_TIMEOUT_IN => '0', -- access timed out
+ DAT_DATAREADY_OUT => BUS_DATAREADY_OUT, -- your data, master, as requested
+ DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT, -- data accepted
+ DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT, -- noone here to answer your request
+
+ --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => bus2_ram_addr_out,
+ --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => bus2_status_addr_out,
+ --BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => bus2_control_addr_out,
+ --BUS_ADDR_OUT(3*16+15 downto 3*16+5) => open,
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => bus2_debug_addr_out,
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => bus2_status2_addr_out,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_status_data_out,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_control_data_out,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => bus2_debug_data_out,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => bus2_status2_data_out,
+ BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out,
+ BUS_READ_ENABLE_OUT(1) => bus2_status_read_enable_out,
+ BUS_READ_ENABLE_OUT(2) => bus2_control_read_enable_out,
+ BUS_READ_ENABLE_OUT(3) => bus2_debug_read_enable_out,
+ BUS_READ_ENABLE_OUT(4) => bus2_status2_read_enable_out,
+ BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(1) => bus2_status_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(2) => bus2_control_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(3) => bus2_debug_write_enable_out,
+ BUS_WRITE_ENABLE_OUT(4) => bus2_status2_write_enable_out,
+ BUS_TIMEOUT_OUT(0) => bus2_ram_timeout_out,
+ BUS_TIMEOUT_OUT(1) => bus2_status_timeout_out,
+ BUS_TIMEOUT_OUT(2) => bus2_control_timeout_out,
+ BUS_TIMEOUT_OUT(3) => bus2_debug_timeout_out,
+ BUS_TIMEOUT_OUT(4) => bus2_status2_timeout_out,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in,
+ BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => bus2_control_data_in,
+ BUS_DATA_IN(3*32+31 downto 3*32) => bus2_debug_data_in,
+ BUS_DATA_IN(4*32+31 downto 4*32) => bus2_status2_data_in,
+ BUS_DATAREADY_IN(0) => bus2_ram_dataready_in,
+ BUS_DATAREADY_IN(1) => bus2_status_dataready_in,
+ BUS_DATAREADY_IN(2) => bus2_control_dataready_in,
+ BUS_DATAREADY_IN(3) => bus2_debug_dataready_in,
+ BUS_DATAREADY_IN(4) => bus2_status2_dataready_in,
+ BUS_WRITE_ACK_IN(0) => bus2_ram_write_ack_in,
+ BUS_WRITE_ACK_IN(1) => bus2_status_write_ack_in,
+ BUS_WRITE_ACK_IN(2) => bus2_control_write_ack_in,
+ BUS_WRITE_ACK_IN(3) => bus2_debug_write_ack_in,
+ BUS_WRITE_ACK_IN(4) => bus2_status2_write_ack_in,
+ BUS_NO_MORE_DATA_IN(0) => bus2_ram_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(1) => bus2_status_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(2) => bus2_control_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(3) => bus2_debug_no_more_data_in,
+ BUS_NO_MORE_DATA_IN(4) => bus2_status2_no_more_data_in,
+ BUS_UNKNOWN_ADDR_IN(0) => bus2_ram_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(1) => bus2_status_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(2) => bus2_control_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_unknown_addr_in,
+ BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_unknown_addr_in,
+
+
+
+
+
+
+ STAT_DEBUG => open
+ );
+
+
+
+-- RAM1a holds JTAG registers, written via trbnet
+ram_jtag_registers : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram1a_wr1,
+ a1 => ram1a_a1,
+ dout1 => ram1a_dout1,
+ din1 => ram1a_din1,
+ a2 => ram1a_a2,
+ dout2 => ram1a_dout2
+ );
+ram1a_readport_mux: ram_mux4to1_readport generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map (
+ SELECT_IN => ram1a_select,
+ A0_IN => jtag_read_ram1a_a,
+ D0_OUT => jtag_read_ram1a_d,
+ A1_IN => jtag_write_ram1a_a,
+ D1_OUT => jtag_write_ram1a_d,
+ A2_IN => init_ram1b_ram1a_a,
+ D2_OUT => init_ram1b_ram1a_d,
+ A3_IN => jtag_check_crc_ram1a_a,
+ D3_OUT => jtag_check_crc_ram1a_d,
+
+ RAM_A_OUT => ram1a_a2,
+ RAM_DOUT_IN => ram1a_dout2
+ );
+
+-- RAM1b holds JTAG registers, read from JTAG chain
+ram_jtag_registers_read : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram1b_wr1,
+ a1 => ram1b_a1,
+ dout1 => ram1b_dout1,
+ din1 => ram1b_din1,
+ a2 => copy_ram1b1c_ram1b_a,--ram1b_a2,
+ dout2 => copy_ram1b1c_ram1b_dout--ram1b_dout2
+ );
+
+-- RAM1b holds JTAG registers, read from JTAG chain
+ram_jtag_registers_copy_read : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => copy_ram1b1c_ram1c_wr,
+ a1 => copy_ram1b1c_ram1c_a,
+ dout1 => open,
+ din1 => copy_ram1b1c_ram1c_din,
+ a2 => ram1c_a2,
+ dout2 => ram1c_dout2
+ );
+
+
+ram1b_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram1b_select,
+ A0_IN => init_ram1b_ram1b_a,
+ D0_OUT => init_ram1b_ram1b_dout,
+ WR0_IN => init_ram1b_ram1b_wr,
+ DIN0_IN => init_ram1b_ram1b_din,
+
+ A1_IN => jtag_data_to_ram_ram1b_a,
+ D1_OUT => jtag_data_to_ram_ram1b_dout,
+ WR1_IN => jtag_data_to_ram_ram1b_wr,
+ DIN1_IN => jtag_data_to_ram_ram1b_din,
+
+ RAM_A_OUT => ram1b_a1,
+ RAM_DOUT_IN => ram1b_dout1,
+ RAM_WR_OUT => ram1b_wr1,
+ RAM_DIN_OUT => ram1b_din1
+ );
+
+
+-- RAM2 holds counts of matching/not matching bits of each register of each chip
+ram_match_diff_count : ram_dp generic map(
+ depth => RAM_MATCH_DIFF_COUNT_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram2_wr1,
+ a1 => ram2_a1,
+ dout1 => ram2_dout1,
+ din1 => ram2_din1,
+ a2 => "00000000",--ram2_a2,
+ dout2 => open --ram2_dout2
+ );
+ram2_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_MATCH_DIFF_COUNT_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram2_select,
+ A0_IN => jtag_tdo_compare_count_ram_a,
+ D0_OUT => jtag_tdo_compare_count_ram_dout,
+ WR0_IN => jtag_tdo_compare_count_ram_wr,
+ DIN0_IN => jtag_tdo_compare_count_ram_din,
+
+ A1_IN => juec_ram2_a,
+ D1_OUT => juec_ram2_dout,
+ WR1_IN => '0',
+ DIN1_IN => x"0000_0000",
+
+ RAM_A_OUT => ram2_a1,
+ RAM_DOUT_IN => ram2_dout1,
+ RAM_WR_OUT => ram2_wr1,
+ RAM_DIN_OUT => ram2_din1
+ );
+
+-- RAM3 holds counts of errors and 'error over threshold's of each register of each chip
+ram_error_counts_A : ram_dp generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => ram3a_wr1,
+ a1 => ram3a_a1,
+ dout1 => ram3a_dout1,
+ din1 => ram3a_din1,
+ a2 => ram3a_a2,
+ dout2 => ram3a_dout2
+ );
+-- ram_error_counts_A : ram_dp generic map(
+-- depth => RAM_ERROR_COUNTS_DEPTH,
+-- width => 32
+-- )
+-- port map ( CLK => CLK_IN,
+-- wr1 => juec_ram3a_wr,
+-- a1 => juec_ram3a_a,
+-- dout1 => juec_ram3a_dout,
+-- din1 => juec_ram3a_din,
+-- a2 => jtag_copy_ram3_ram3a_a,
+-- dout2 => jtag_copy_ram3_ram3a_dout
+-- );
+-- RAM3B is an on demand copy of RAM3A
+ram_error_counts_B : ram_dp generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( CLK => CLK_IN,
+ wr1 => jtag_copy_ram3_ram3b_wr,
+ a1 => jtag_copy_ram3_ram3b_a,
+ dout1 => open,
+ din1 => jtag_copy_ram3_ram3b_din,
+ a2 => ram3b_a2,
+ dout2 => ram3b_dout2
+ );
+
+ram3a_mux2to1_writeport : ram_mux2to1_writeport generic map (
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map ( SELECT_IN => ram3a_select,
+ A0_IN => juec_ram3a_a,
+ D0_OUT => juec_ram3a_dout,
+ WR0_IN => juec_ram3a_wr,
+ DIN0_IN => juec_ram3a_din,
+
+ A1_IN => jtag_blank_ram3a_ram3a_a,
+ D1_OUT => open,
+ WR1_IN => jtag_blank_ram3a_ram3a_wr,
+ DIN1_IN => jtag_blank_ram3a_ram3a_din,
+
+ RAM_A_OUT => ram3a_a1,
+ RAM_DOUT_IN => ram3a_dout1,
+ RAM_WR_OUT => ram3a_wr1,
+ RAM_DIN_OUT => ram3a_din1
+ );
+
+ram3a_readport_mux: ram_mux2to1_readport generic map(
+ depth => RAM_ERROR_COUNTS_DEPTH,
+ width => 32
+ )
+ port map (
+ SELECT_IN => ram3a_rd_select,
+ A0_IN => jtag_copy_ram3_ram3a_a,
+ D0_OUT => jtag_copy_ram3_ram3a_dout,
+ A1_IN => "000000000",
+ D1_OUT => open,
+
+ RAM_A_OUT => ram3a_a2,
+ RAM_DOUT_IN => ram3a_dout2
+ );
+
+
+
+the_jtag_init_ram1b: jtag_init_ram1b generic map(
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+)
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_INIT_IN => trigger_init_ram1b,
+ -- RAM1a
+ RAM1A_A_OUT => init_ram1b_ram1a_a,
+ RAM1A_D_IN => init_ram1b_ram1a_d,
+ -- RAM1b
+ RAM1B_A_OUT => init_ram1b_ram1b_a,
+ RAM1B_D_IN => init_ram1b_ram1b_dout,
+ RAM1B_WE_OUT => init_ram1b_ram1b_wr,
+ RAM1B_D_OUT => init_ram1b_ram1b_din,
+
+ IDLE_OUT => jtag_init_ram1b_idle
+ );
+
+the_jtag_copy_ram1b1c : copy_ram
+ generic map (
+ ram_depth => RAM_JTAG_REGISTERS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_COPY_IN => trigger_copy_ram1b1c,
+ -- RAM3a
+ RAMA_A_OUT => copy_ram1b1c_ram1b_a,
+ RAMA_D_IN => copy_ram1b1c_ram1b_dout,
+ -- RAM3b
+ RAMB_A_OUT => copy_ram1b1c_ram1c_a,
+ RAMB_D_OUT => copy_ram1b1c_ram1c_din,
+ RAMB_WR_OUT => copy_ram1b1c_ram1c_wr,
+
+ IDLE_OUT => copy_ram1b1c_idle
+ );
+
+
+
+the_jtag_copy_ram3 : copy_ram
+ generic map (
+ ram_depth => RAM_ERROR_COUNTS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_COPY_IN => trigger_copy_ram3,
+ -- RAM3a
+ RAMA_A_OUT => jtag_copy_ram3_ram3a_a,
+ RAMA_D_IN => jtag_copy_ram3_ram3a_dout,
+ -- RAM3b
+ RAMB_A_OUT => jtag_copy_ram3_ram3b_a,
+ RAMB_D_OUT => jtag_copy_ram3_ram3b_din,
+ RAMB_WR_OUT => jtag_copy_ram3_ram3b_wr,
+
+ IDLE_OUT => jtag_copy_ram3_idle
+ );
+
+the_jtag_blank_ram3a : blank_ram
+ generic map (
+ ram_depth => RAM_ERROR_COUNTS_DEPTH,
+ ram_width => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_BLANK_IN => trigger_blank_ram3a,
+ -- RAM
+-- RAM_A_OUT => jtag_blank_ram3a_ram3a_a,
+ RAM_A_OUT => open,
+-- RAM_D_OUT => jtag_blank_ram3a_ram3a_din,
+ RAM_D_OUT => open,
+-- RAM_WR_OUT => jtag_blank_ram3a_ram3a_wr, -- disabling blanking ram 29.10.2012
+ RAM_WR_OUT => open,
+
+ IDLE_OUT => jtag_blank_ram3a_idle
+ );
+jtag_blank_ram3a_ram3a_a <= (others => '0');
+jtag_blank_ram3a_ram3a_din <= (others => '0');
+jtag_blank_ram3a_ram3a_wr <= '0';
+
+
+the_jtag_update_error_counts_ram3a : jtag_update_error_counts_ram3a
+ generic map (
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGISTERS_PLUS_TWO_LD => MAX_REGISTERS_PLUS_TWO_LD,
+ RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
+ RAM_ERROR_COUNTS_DEPTH => RAM_ERROR_COUNTS_DEPTH,
+ WRITE_ERROR_THRESHOLD => WRITE_ERROR_THRESHOLD,
+ READ_ERROR_THRESHOLD => READ_ERROR_THRESHOLD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_UPDATE_DATA_CHANGED_IN => trigger_juec_update_d_ch,
+ TRIGGER_UPDATE_READ_ERRORS_IN => trigger_juec_update_rd_err,
+ TRIGGER_UPDATE_WRITE_ERRORS_IN => trigger_juec_update_wr_err,
+ TRIGGER_UPDATE_RUN_COUNTER_IN => trigger_juec_update_run_counter,
+ RUN_COUNTER_IN => std_logic_vector(run_counter),
+ -- RAM2
+ RAM2_A_OUT => juec_ram2_a,
+ RAM2_D_IN => juec_ram2_dout,
+ -- RAM3a
+ RAM3A_A_OUT => juec_ram3a_a,
+ RAM3A_D_IN => juec_ram3a_dout,
+ RAM3A_D_OUT => juec_ram3a_din,
+ RAM3A_WR_OUT => juec_ram3a_wr,
+
+ REMOVED_CHIPS_IN => removed_chips,
+ NUMCHIPS_CONFIGURED_IN => std_logic_vector(numchips_configured),
+ NUMREGS_CONFIGURED_IN => jtag_write_numregs_configured,
+
+ DATA_CHANGED_OUT => juec_data_changed,
+ READ_ERRORS_OUT => juec_read_errors,
+ WRITE_ERRORS_OUT => juec_write_errors,
+
+ IDLE_OUT => juec_idle
+ );
+
+-- the_jtag_bypassreg_testchain_m10: jtag_bypassreg_testchain_m10
+-- generic map (
+-- ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
+-- MAX_NUMCHIPS => MAX_NUMCHIPS,
+-- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+-- JTAG_M26_IRLEN => JTAG_M26_IRLEN,
+-- max_bitcounter_ld => MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7
+-- )
+-- port map(
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+-- TRIGGER_BEGIN_TESTCHAIN_IN => trigger_begin_bypassreg,
+-- IDLE_OUT => jtag_bypassreg_idle,
+-- CHAIN_LENGTH_OUT => jtag_bypassreg_length,
+-- CHAIN_BROKEN_OUT => jtag_bypassreg_chain_broken,
+-- ENABLE_JTAG_CLOCK_OUT => jtag_bypassreg_enable_jtag_clock,
+-- LAST_TCK_CYCLE_OUT => jtag_bypassreg_last_tck_cycle,
+-- TMS_OUT => jtag_bypassreg_tms,
+-- TDI_OUT => jtag_bypassreg_tdi,
+-- TDO_IN => jtag_tdo_sampled,
+-- DELAY_IN => jtag_delay_expvalues
+-- );
+
+the_jtag_read_m26devid_m10: jtag_read_m26devid_m10
+ generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ RAM_JTAG_REGISTERS_A_OUT => jtag_read_ram1a_a,
+ RAM_JTAG_REGISTERS_D_IN => jtag_read_ram1a_d,
+ NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
+ BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+ TRIGGER_BEGIN_READ_IN => trigger_jtag_read,
+ IS_DR_BIT_OUT => jtag_read_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_read_is_firstbit,
+ IS_LASTBIT_OUT => jtag_read_is_lastbit,
+ CHIPNUM_OUT => jtag_read_chipnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_read_enable_jtag_clock,
+ LAST_TCK_CYCLE_OUT => jtag_read_last_tck_cycle,
+ TMS_OUT => jtag_read_tms,
+ TDI_OUT => jtag_read_tdi,
+ EXPECTED_TDO_OUT => jtag_read_expected_tdo,
+ IDLE_OUT => jtag_read_idle
+ );
+
+the_jtag_tdo_data_to_ram_m10 : jtag_tdo_data_to_ram_m10
+ generic map (
+ enable_ram1b => '1',
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGLEN_LD => MAX_REGLEN_LD,
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ CHIPNUM_IN => jtag_delayed_chipnum,
+ REGNUM_IN => jtag_delayed_regnum,
+ ENABLE_DATAOUT_IN => jtag_delayed_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
+ IS_LASTBIT_IN => jtag_delayed_is_lastbit,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ -- RAM1b
+ RAM_JTAG_REGISTERS_READOUT_A_OUT => jtag_data_to_ram_ram1b_a,
+ RAM_JTAG_REGISTERS_READOUT_D_IN => jtag_data_to_ram_ram1b_dout,
+ RAM_JTAG_REGISTERS_READOUT_WE_OUT => jtag_data_to_ram_ram1b_wr,
+ RAM_JTAG_REGISTERS_READOUT_D_OUT => jtag_data_to_ram_ram1b_din
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+
+the_jtag_tdo_compare_count_m10 : jtag_tdo_compare_count_m10
+ generic map (
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
+ MAX_REGLEN_LD => MAX_REGLEN_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ CHIPNUM_IN => jtag_delayed_chipnum,
+ REGNUM_IN => jtag_delayed_regnum,
+ ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
+ IS_LASTBIT_IN => jtag_delayed_is_lastbit,
+ TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
+ RAM_MATCH_DIFF_COUNT_A_OUT => jtag_tdo_compare_count_ram_a,
+ RAM_MATCH_DIFF_COUNT_WE_OUT => jtag_tdo_compare_count_ram_wr,
+ RAM_MATCH_DIFF_COUNT_D_OUT => jtag_tdo_compare_count_ram_din
+ --INTERNAL_ERROR_OUT => jtag_tdo_compare_count_internal_error
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ );
+
+
+the_jtag_tdo_compare_counttotal_noram_m10 : jtag_tdo_compare_counttotal_noram_m10
+ generic map (
+ numcounts => 3,
+ se_counter_width => COUNTER_WIDTHS, -- sampling error counter width
+ diff_counter_width => COUNTER_WIDTHS -- counter width for number of runs in which there were differences
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
+ ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
+ TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
+ TDO_SAMPLED_IN => jtag_tdo_sampled,
+ TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
+ BEGIN_COUNT_I_IN(2) => begin_count_read_errors,
+ BEGIN_COUNT_I_IN(1) => begin_count_write_errors,
+ BEGIN_COUNT_I_IN(0) => begin_count_data_changed,
+
+ END_COUNT_I_IN(2) => end_count_read_errors,
+ END_COUNT_I_IN(1) => end_count_write_errors,
+ END_COUNT_I_IN(0) => end_count_data_changed,
+
+ SAMPLING_ERRORS_COUNT_OUT => SAMPLING_ERRORS_COUNT_OUT,
+ COUNTS_OUT(0*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 0*COUNTER_WIDTHS) => sDATA_CHANGED_COUNT_OUT,
+ COUNTS_OUT(1*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 1*COUNTER_WIDTHS) => sWRITE_ERRORS_COUNT_OUT,
+ COUNTS_OUT(2*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 2*COUNTER_WIDTHS) => sREAD_ID_ERRORS_COUNT_OUT,
+ LAST_VALUES_OUT(2) => last_read_error,
+ LAST_VALUES_OUT(1) => last_write_error,
+ LAST_VALUES_OUT(0) => last_data_changed
+ );
+
+the_jtag_delay_expected_values: jtag_delay_expected_values
+ generic map (
+ ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD
+ )
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE1_IN => jtag_sample_pulse1,
+ CHIPNUM_IN => jtag_meta_chipnum,
+ REGNUM_IN => jtag_meta_regnum,
+ IS_DR_BIT_IN => jtag_meta_is_dr_bit,
+ IS_FIRSTBIT_IN => jtag_meta_is_firstbit,
+ IS_LASTBIT_IN => jtag_meta_is_lastbit,
+ TDO_EXPECTED_IN => jtag_meta_expected_tdo,
+ OUT_CHIPNUM_OUT => jtag_delayed_chipnum,
+ OUT_REGNUM_OUT => jtag_delayed_regnum,
+ OUT_IS_DR_BIT_OUT => jtag_delayed_is_dr_bit,
+ OUT_IS_FIRSTBIT_OUT => jtag_delayed_is_firstbit,
+ OUT_IS_LASTBIT_OUT => jtag_delayed_is_lastbit,
+ OUT_TDO_EXPECTED_OUT => jtag_delayed_tdo_expected,
+ DELAY_IN => jtag_delay_expvalues
+);
+
+the_jtag_mux_buffer_tms_tdi_out_and_metainfo : jtag_mux_buffer_tms_tdi_out_and_metainfo
+ generic map (
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ JTAG_SET_DATA_IN => jtag_set_data_pulse,
+ -- read DEV_ID inputs
+ RD_TMS_IN => jtag_read_tms,
+ RD_TDI_IN => jtag_read_tdi,
+ RD_IS_DR_BIT_IN => jtag_read_is_dr_bit,
+ RD_IS_FIRSTBIT_IN => jtag_read_is_firstbit,
+ RD_IS_LASTBIT_IN => jtag_read_is_lastbit,
+ RD_CHIPNUM_IN => jtag_read_chipnum,
+ RD_ENABLE_JTAG_CLOCK_IN => jtag_read_enable_jtag_clock,
+ RD_LAST_TCK_CYCLE_IN => jtag_read_last_tck_cycle,
+ RD_EXPECTED_TDO_OUT => jtag_read_expected_tdo,
+ -- write registers inputs
+ WR_TMS_IN => jtag_write_tms,
+ WR_TDI_IN => jtag_write_tdi,
+ WR_IS_DR_BIT_IN => jtag_write_is_dr_bit,
+ WR_IS_FIRSTBIT_IN => jtag_write_is_firstbit,
+ WR_IS_LASTBIT_IN => jtag_write_is_lastbit,
+ WR_CHIPNUM_IN => jtag_write_chipnum,
+ WR_REGNUM_IN => jtag_write_regnum,
+ WR_ENABLE_JTAG_CLOCK_IN => jtag_write_enable_jtag_clock,
+ WR_LAST_TCK_CYCLE_IN => jtag_write_last_tck_cycle,
+ WR_EXPECTED_TDO_OUT => jtag_write_expected_tdo,
+ -- test chain inputs
+ TC_TMS_IN => jtag_bypassreg_tms,
+ TC_TDI_IN => jtag_bypassreg_tdi,
+ TC_ENABLE_JTAG_CLOCK_IN => jtag_bypassreg_enable_jtag_clock,
+ TC_LAST_TCK_CYCLE_IN => jtag_bypassreg_last_tck_cycle,
+
+ TMS_OUT => jtag_tms,
+ TDI_OUT => jtag_tdi,
+ IS_DR_BIT_OUT => jtag_meta_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_meta_is_firstbit,
+ IS_LASTBIT_OUT => jtag_meta_is_lastbit,
+ CHIPNUM_OUT => jtag_meta_chipnum,
+ REGNUM_OUT => jtag_meta_regnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_enable_clock,
+ LAST_TCK_CYCLE_OUT => jtag_meta_last_tck_cycle,
+ EXPECTED_TDO_OUT => jtag_meta_expected_tdo
+ );
+
+the_jtag_tdo_sampler : jtag_tdo_sample port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SAMPLE_PULSE1_IN => jtag_sample_pulse1,
+ SAMPLE_PULSE2_IN => jtag_sample_pulse2,
+ SAMPLE_PULSE3_IN => jtag_sample_pulse3,
+ -- TDO signal, which is to be sampled
+ TDO_IN => JTAG_TDO_IN,
+ -- sampled value of TDO
+ TDO_SAMPLED_OUT => jtag_tdo_sampled,
+ -- sampling error
+ SAMPLING_ERROR_OUT => jtag_tdo_sampling_error
+ );
+
+the_jtag_write_m10: jtag_write_m10 generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD,
+ MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
+ MAX_REGLEN_LD => MAX_REGLEN_LD,
+ MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ RAM_JTAG_REGISTERS_A_OUT => jtag_write_ram1a_a,
+ RAM_JTAG_REGISTERS_D_IN => jtag_write_ram1a_d,
+ NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
+ BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
+ TRIGGER_BEGIN_WRITE_IN => trigger_jtag_write,
+ IS_DR_BIT_OUT => jtag_write_is_dr_bit,
+ IS_FIRSTBIT_OUT => jtag_write_is_firstbit,
+ IS_LASTBIT_OUT => jtag_write_is_lastbit,
+ CHIPNUM_OUT => jtag_write_chipnum,
+ REGNUM_OUT => jtag_write_regnum,
+ ENABLE_JTAG_CLOCK_OUT => jtag_write_enable_jtag_clock,
+ LAST_TCK_CYCLE_OUT => jtag_write_last_tck_cycle,
+ TMS_OUT => jtag_write_tms,
+ TDI_OUT => jtag_write_tdi,
+ EXPECTED_TDO_OUT => jtag_write_expected_tdo,
+ IDLE_OUT => jtag_write_idle,
+ NUMREGS_CONFIGURED_OUT => jtag_write_numregs_configured,
+ LAST_ERROR_CODE_OUT => jtag_write_last_error_code
+ );
+
+the_jtag_tck_out: jtag_tck_out_component port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ JTAG_CLOCK_PULSE1_IN => jtag_clock_pulse1,
+ JTAG_CLOCK_PULSE2_IN => jtag_clock_pulse2,
+ ENABLE_JTAG_TCK_IN => jtag_enable_clock,
+
+ TCK_OUT => jtag_tck
+ );
+
+the_jtag_pulses : jtag_pulses generic map (
+ time_bits => 10
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => jtag_pulses_reset_complete,
+ -- input times
+ JTAG_CLOCK_TIME1_IN => std_logic_vector(jtag_clock_time1),
+ JTAG_CLOCK_TIME2_IN => std_logic_vector(jtag_clock_time2),
+ JTAG_SAMPLE_TIME1_IN => std_logic_vector(jtag_sample_time1),
+ JTAG_SAMPLE_TIME2_IN => std_logic_vector(jtag_sample_time2),
+ JTAG_SAMPLE_TIME3_IN => std_logic_vector(jtag_sample_time3),
+ JTAG_SET_DATA_TIME_IN => std_logic_vector(jtag_set_data_time),
+
+ JTAG_CLOCK_CYCLE_LENGTH_IN => std_logic_vector(jtag_clock_cycle_length),
+
+ -- output pulses
+ BEGIN_JTAGBITCALC_OUT => begin_jtag_bitcalc,
+ JTAG_CLOCK_PULSE1_OUT => jtag_clock_pulse1,
+ JTAG_CLOCK_PULSE2_OUT => jtag_clock_pulse2,
+ JTAG_SAMPLE_PULSE1_OUT => jtag_sample_pulse1,
+ JTAG_SAMPLE_PULSE2_OUT => jtag_sample_pulse2,
+ JTAG_SAMPLE_PULSE3_OUT => jtag_sample_pulse3,
+ JTAG_SET_DATA_PULSE_OUT => jtag_set_data_pulse
+ );
+
+the_jtag_check_crc_ram1a: jtag_check_crc_ram1a
+ generic map (
+ RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
+ MAX_NUMCHIPS => MAX_NUMCHIPS,
+ MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
+ MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
+ MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD,
+ MAX_REGISTERS_LD => MAX_REGISTERS_LD
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_CHECK_IN => trigger_check_crc_ram1a,
+ -- RAM1a
+ RAM1A_A_OUT => jtag_check_crc_ram1a_a,
+ RAM1A_D_IN => jtag_check_crc_ram1a_d,
+ NUMCHIPS_IN => std_logic_vector(numchips_configured),
+ CRC_OK_OUT => jtag_check_crc_ram1a_crc_ok,
+ IDLE_OUT => jtag_check_crc_ram1a_idle
+ );
+
+
+--BUS_DATA_OUT <= bus_data_out_buffer;
+--BUS_DATAREADY_OUT <= bus_dataready;
+--BUS_NO_MORE_DATA_OUT <= bus_no_more_data;
+--BUS_WRITE_ACK_OUT <= bus_write_ack;
+--BUS_UNKNOWN_ADDR_OUT <= bus_unknown_addr;
+MY_STATUS_OUT <= (others => '0'); --my_status;
+JTAG_TCK_OUT <= jtag_tck;
+JTAG_TMS_OUT <= jtag_tms;
+JTAG_TDI_OUT <= jtag_tdi;
+PROG_JTAG_FINISHED_OUT <= prog_jtag_finished;
+READ_ID_ERRORS_COUNT_OUT <= sREAD_ID_ERRORS_COUNT_OUT;
+WRITE_ERRORS_COUNT_OUT <= sWRITE_ERRORS_COUNT_OUT;
+DATA_CHANGED_COUNT_OUT <= sDATA_CHANGED_COUNT_OUT;
+
+
+jtag_pulses_reset_complete <= jtag_pulses_reset or RESET_IN;
+
+m26cs_stopped <= '1' when m26cs_state = M26CSS_STOPPED else '0';
+
+jtag_sample_pulse3_d1_next <= jtag_sample_pulse3;
+
+ram3b_a2 <= ram3b_a2_base_addr & ram3b_a2_rel_addr; -- hope this is the right order (base_addr should be the MSBs)
+
+SEQUENTIAL : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ --bus_rw_state <= BUS_RW_STATE_IDLE;
+ --status_register <= (others => '0');
+ --status_register_read_error2 <= '0';
+ data_register <= x"00000000";
+ --cmd_register <= x"00000000";
+ --bus_data_out_buffer <= x"00000000";
+ --bus_dataready <= '0';
+ --bus_no_more_data <= '0';
+ --bus_write_ack <= '0';
+ --bus_unknown_addr <= '0';
+ --length_register <= x"00000001";
+ jtag_refresh_active <= '0';
+ jtag_check1_active <= '0';
+ jtag_refresh_active_last <= '0';
+ --trigger_counter <= (others => '0');
+ idle_out_signal <= '0';
+ --status_register_pos <= (others => '0');
+ --status_register_read_running <= '0';
+ --ram_base_addr <= (others => '0');
+ crc_status_register <= (others => '0');
+ --write_trigger <= '0';
+ --write_idle_last <= '0';
+ --write_status_register_or <= (others => '0');
+ removed_chips <= (others => '0');
+ --reactivate_sensor <= (others => '0');
+ --reactivate_sensor_strobe <= (others => '0');
+ --deactivate_sensor <= (others => '0');
+ --deactivate_sensor_strobe <= (others => '0');
+ --disable_write <= '0';
+ --disable_writeerror_for_remove <= '0';
+ --disable_remove <= '0';
+ --debug_one_remove <= '0';
+ --debug_one_remove_strobe <= '0';
+ --removed_strobe <= '0';
+ --read_trigger <= '0';
+ numchips_configured <= (others => '0');
+ --my_status <= (others => '0');
+ --m26c_sensor_cand <= (others => '0');
+ chip_counter_start <= '0';
+ --m26c_firstrun <= '0';
+ --m26c_secondrun <= '0';
+ --mux_sel <= '0';
+ --driver_speed <= x"0005";
+ --already_written <= '0';
+ --read_idle_last <= '0';
+ --write_error_counter <= (others => (others => '0'));
+ --write_error_over_threshold_counter <= (others => (others => '0'));
+ --write_data_changed_counter <= (others => (others => '0'));
+ --read_error_counter <= (others => (others => '0'));
+ --read_error_over_threshold_counter <= (others => (others => '0'));
+ debug_test <= (others =>'0');
+ debug_m26cs_state <= (others => '0');
+ bus2_ram_data_in <= (others => '0');
+ bus2_ram_dataready_in <= '0';
+ bus2_ram_write_ack_in <= '0';
+ bus2_ram_no_more_data_in <= '0';
+ bus2_ram_unknown_addr_in <= '0';
+ buf_bus2_ram_read_enable_out <= '0';
+ buf_buf_bus2_ram_read_enable_out <= '0';
+ bus2_status_data_in <= (others =>'0');
+ bus2_status_dataready_in <= '0';
+ bus2_status_write_ack_in <= '0';
+ bus2_status_no_more_data_in <= '0';
+ bus2_status_unknown_addr_in <= '0';
+ bus2_control_data_in <= (others =>'0');
+ bus2_control_dataready_in <= '0';
+ bus2_control_write_ack_in <= '0';
+ bus2_control_no_more_data_in <= '0';
+ bus2_control_unknown_addr_in <= '0';
+ bus2_debug_data_in <= (others =>'0');
+ bus2_debug_dataready_in <= '0';
+ bus2_debug_write_ack_in <= '0';
+ bus2_debug_no_more_data_in <= '0';
+ bus2_debug_unknown_addr_in <= '0';
+ bus2_status2_data_in <= (others =>'0');
+ bus2_status2_dataready_in <= '0';
+ bus2_status2_write_ack_in <= '0';
+ bus2_status2_no_more_data_in <= '0';
+ bus2_status2_unknown_addr_in <= '0';
+ bus2_status2_read_ram3b <= '0';
+ buf_bus2_status2_read_ram3b <= '0';
+ prog_jtag_finished <= '0';
+ --last_write_successful <= '0';
+ -- NEW SIGNALS
+ ram1a_a1_base_addr <= (others =>'0');
+ ram1a_a1_rel_addr <= (others =>'0');
+ ram1a_din1 <= (others =>'0');
+ ram1a_wr1 <= '0';
+ jtag_status2_copy_requested <= '0';
+ jtag_status2_copy_request_strobe <= '0';
+ cps2_state <= CPS2_IDLE;
+ status2_run_counter <= (others =>'0');
+ status2_chain_status <= (others =>'0');
+ jtag_clock_cycle_length <= (others =>'0');
+ jtag_clock_time1 <= (others =>'0');
+ jtag_clock_time2 <= (others =>'0');
+ jtag_sample_time1 <= (others =>'0');
+ jtag_sample_time2 <= (others =>'0');
+ jtag_sample_time3 <= (others =>'0');
+ jtag_set_data_time <= (others => '0');
+ jtag_pulses_reset <= '0';
+ jtag_sample_pulse3_d1 <= '0';
+ breakpoint_active <= (others => '0');
+ ram1b_a2 <= (others => '0');
+ ram3b_a2_rel_addr <= (others => '0');
+ ram3b_a2_base_addr <= (others => '0');
+
+ ram1b_copy_requested <= '0';
+ ram1c_run_counter <= (others => '0');
+ ram1c_chain_status <= (others => '0');
+ cpr1bc_state <= CPR1BC_IDLE;
+ trigger_copy_ram1b1c <= '0';
+ ram1b1c_copy_trigger_active <= (others => '0');
+ ram1c_a2 <= (others => '0');
+ ram1b1c_copy_trigger_strobe <= (others => '0');
+
+ m26csoptions <= (others => '0');
+ jtag_delay_expvalues <= (others => '0');
+
+ crc_error_on_last_check <= '0';
+ last_run_successful <= '0';
+ last_run_successful_tmp <= '0';
+ else
+ --bus_rw_state <= bus_rw_state_next;
+ --status_register <= status_register_next;
+ --status_register_read_error2 <= status_register_read_error2_next;
+ data_register <= data_register_next;
+ --cmd_register <= cmd_register_next;
+ --bus_data_out_buffer <= bus_data_out_buffer_next;
+ --bus_dataready <= bus_dataready_next;
+ --bus_no_more_data <= bus_no_more_data_next;
+ --bus_write_ack <= bus_write_ack_next;
+ --bus_unknown_addr <= bus_unknown_addr_next;
+ --length_register <= length_register_next;
+ jtag_refresh_active <= jtag_refresh_active_next;
+ jtag_check1_active <= jtag_check1_active_next;
+ jtag_refresh_active_last <= jtag_refresh_active_last_next;
+ --trigger_counter <= trigger_counter_next;
+ idle_out_signal <= idle_out_signal_next;
+ --status_register_pos <= status_register_pos_next;
+ --status_register_read_running <= status_register_read_running_next;
+ --ram_base_addr <= ram_base_addr_next;
+ crc_status_register <= crc_status_register_next;
+ --write_trigger <= write_trigger_next;
+ --write_idle_last <= write_idle_last_next;
+ --write_status_register_or <= write_status_register_or_next;
+ removed_chips <= removed_chips_next;
+ --reactivate_sensor <= reactivate_sensor_next;
+ --reactivate_sensor_strobe <= reactivate_sensor_strobe_next;
+ --deactivate_sensor <= deactivate_sensor_next;
+ --deactivate_sensor_strobe <= deactivate_sensor_strobe_next;
+ --disable_write <= disable_write_next;
+ --disable_writeerror_for_remove <= disable_writeerror_for_remove_next;
+ --disable_remove <= disable_remove_next;
+ --debug_one_remove <= debug_one_remove_next;
+ --debug_one_remove_strobe <= debug_one_remove_strobe_next;
+ --removed_strobe <= removed_strobe_next;
+ --read_trigger <= read_trigger_next;
+ numchips_configured <= numchips_configured_next;
+ --my_status <= my_status_next;
+ --m26c_sensor_cand <= m26c_sensor_cand_next;
+ chip_counter_start <= chip_counter_start_next;
+ --m26c_firstrun <= m26c_firstrun_next;
+ --m26c_secondrun <= m26c_secondrun_next;
+ --mux_sel <= mux_sel_next;
+ --driver_speed <= driver_speed_next;
+ --already_written <= already_written_next;
+ --read_idle_last <= read_idle_last_next;
+ --write_error_counter <= write_error_counter_next;
+ --write_error_over_threshold_counter <= write_error_over_threshold_counter_next;
+ --write_data_changed_counter <= write_data_changed_counter_next;
+ --read_error_counter <= read_error_counter_next;
+ --read_error_over_threshold_counter <= read_error_over_threshold_counter_next;
+ --m26c_state <= m26c_state_next;
+ debug_test <= debug_test_next;
+ debug_m26cs_state <= debug_m26cs_state_next;
+ bus2_ram_data_in <= bus2_ram_data_in_next;
+ bus2_ram_dataready_in <= bus2_ram_dataready_in_next;
+ bus2_ram_write_ack_in <= bus2_ram_write_ack_in_next;
+ bus2_ram_no_more_data_in <= bus2_ram_no_more_data_in_next;
+ bus2_ram_unknown_addr_in <= bus2_ram_unknown_addr_in_next;
+ buf_bus2_ram_read_enable_out <= buf_bus2_ram_read_enable_out_next;
+ buf_buf_bus2_ram_read_enable_out <= buf_buf_bus2_ram_read_enable_out_next;
+ bus2_status_data_in <= bus2_status_data_in_next;
+ bus2_status_dataready_in <= bus2_status_dataready_in_next;
+ bus2_status_write_ack_in <= bus2_status_write_ack_in_next;
+ bus2_status_no_more_data_in <= bus2_status_no_more_data_in_next;
+ bus2_status_unknown_addr_in <= bus2_status_unknown_addr_in_next;
+ bus2_control_data_in <= bus2_control_data_in_next;
+ bus2_control_dataready_in <= bus2_control_dataready_in_next;
+ bus2_control_write_ack_in <= bus2_control_write_ack_in_next;
+ bus2_control_no_more_data_in <= bus2_control_no_more_data_in_next;
+ bus2_control_unknown_addr_in <= bus2_control_unknown_addr_in_next;
+ bus2_debug_data_in <= bus2_debug_data_in_next;
+ bus2_debug_dataready_in <= bus2_debug_dataready_in_next;
+ bus2_debug_write_ack_in <= bus2_debug_write_ack_in_next;
+ bus2_debug_no_more_data_in <= bus2_debug_no_more_data_in_next;
+ bus2_debug_unknown_addr_in <= bus2_debug_unknown_addr_in_next;
+ bus2_status2_data_in <= bus2_status2_data_in_next;
+ bus2_status2_dataready_in <= bus2_status2_dataready_in_next;
+ bus2_status2_write_ack_in <= bus2_status2_write_ack_in_next;
+ bus2_status2_no_more_data_in <= bus2_status2_no_more_data_in_next;
+ bus2_status2_unknown_addr_in <= bus2_status2_unknown_addr_in_next;
+ bus2_status2_read_ram3b <= bus2_status2_read_ram3b_next;
+ buf_bus2_status2_read_ram3b <= buf_bus2_status2_read_ram3b_next;
+ prog_jtag_finished <= prog_jtag_finished_next;
+ --last_write_successful <= last_write_successful_next;
+ -- NEW SIGNALS
+ ram1a_a1_base_addr <= ram1a_a1_base_addr_next;
+ ram1a_a1_rel_addr <= ram1a_a1_rel_addr_next;
+ ram1a_din1 <= ram1a_din1_next;
+ ram1a_wr1 <= ram1a_wr1_next;
+ jtag_status2_copy_requested <= jtag_status2_copy_requested_next;
+ jtag_status2_copy_request_strobe <= jtag_status2_copy_request_strobe_next;
+ cps2_state <= cps2_state_next;
+ status2_run_counter <= status2_run_counter_next;
+ status2_chain_status <= status2_chain_status_next;
+ jtag_clock_cycle_length <= jtag_clock_cycle_length_next;
+ jtag_clock_time1 <= jtag_clock_time1_next;
+ jtag_clock_time2 <= jtag_clock_time2_next ;
+ jtag_sample_time1 <= jtag_sample_time1_next;
+ jtag_sample_time2 <= jtag_sample_time2_next;
+ jtag_sample_time3 <= jtag_sample_time3_next;
+ jtag_set_data_time <= jtag_set_data_time_next;
+ jtag_pulses_reset <= jtag_pulses_reset_next;
+ jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next;
+ breakpoint_active <= breakpoint_active_next;
+ ram1b_a2 <= ram1b_a2_next;
+ ram3b_a2_rel_addr <= ram3b_a2_rel_addr_next;
+ ram3b_a2_base_addr <= ram3b_a2_base_addr_next;
+
+ ram1b_copy_requested <= ram1b_copy_requested_next;
+ ram1c_run_counter <= ram1c_run_counter_next;
+ ram1c_chain_status <= ram1c_chain_status_next;
+ cpr1bc_state <= cpr1bc_state_next;
+ trigger_copy_ram1b1c <= trigger_copy_ram1b1c_next;
+ ram1b1c_copy_trigger_active <= ram1b1c_copy_trigger_active_next;
+ ram1c_a2 <= ram1c_a2_next;
+ ram1b1c_copy_trigger_strobe <= ram1b1c_copy_trigger_strobe_next;
+
+ m26csoptions <= m26csoptions_next;
+ jtag_delay_expvalues <= jtag_delay_expvalues_next;
+ crc_error_on_last_check <= crc_error_on_last_check_next;
+ last_run_successful <= last_run_successful_next;
+ last_run_successful_tmp <= last_run_successful_tmp_next;
+ end if;
+ end if;
+end process;
+
+
+SYNCHRONOUS_CHIP_COUNTER : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ cc_state <= CC_IDLE;
+ numchips_active <= (others =>'0');
+ numchips_active_acc <= (others =>'0');
+ cc_chip_i <= (others =>'0');
+ cc_nextnotremoved_i <= (others =>'0');
+ last_not_removed <= (others =>'0');
+ first_not_removed <= (others =>'0');
+ jtag_next_not_removed <= (others =>'0');
+ else
+ cc_state <= cc_state_next;
+ numchips_active <= numchips_active_next;
+ numchips_active_acc <= numchips_active_acc_next;
+ cc_chip_i <= cc_chip_i_next;
+ cc_nextnotremoved_i <= cc_nextnotremoved_i_next;
+ last_not_removed <= last_not_removed_next;
+ first_not_removed <= first_not_removed_next;
+ jtag_next_not_removed <= jtag_next_not_removed_next;
+ end if;
+ end if;
+end process;
+
+COMB_CHIP_COUNTER : process (cc_state, removed_chips, chip_counter_start, numchips_configured, cc_chip_i, cc_nextnotremoved_i, numchips_active, numchips_active_acc, last_not_removed, first_not_removed, jtag_next_not_removed)
+begin
+ cc_state_next <= cc_state;
+ numchips_active_next <= numchips_active;
+ numchips_active_acc_next <= numchips_active_acc;
+ -- index, running through chips
+ cc_chip_i_next <= cc_chip_i;
+ -- index, last not removed sensor
+ cc_nextnotremoved_i_next <= cc_nextnotremoved_i;
+ last_not_removed_next <= last_not_removed;
+ first_not_removed_next <= first_not_removed;
+
+ jtag_next_not_removed_next <= jtag_next_not_removed;
+ case cc_state is
+ when CC_IDLE =>
+ if(chip_counter_start = '1') then
+ -- determine number of chips connected in serial to jtag chain
+ cc_chip_i_next <= (others => '0');
+ cc_nextnotremoved_i_next <= (others => '0');
+ -- with the following initialization no chip will be unremoved, because
+ -- last_not_removed < first_not_removed
+ -- and numchips_active will be set to 0 if really all chips are removed
+ first_not_removed_next <= (others => '1');
+ last_not_removed_next <= (others =>'0');
+ jtag_next_not_removed_next <= (others =>'0');
+ numchips_active_acc_next <= (others => '0');
+ cc_state_next <= CC_COUNT_SENSOR;
+ end if;
+ when CC_COUNT_SENSOR =>
+ if(removed_chips(to_integer(cc_chip_i)) = '0') then
+ numchips_active_acc_next <= numchips_active_acc + 1;
+ last_not_removed_next <= cc_chip_i;
+ -- if first_not_removed unset
+ if(std_logic_vector_all_components_equal_scalar(std_logic_vector(first_not_removed), '1') = '1') then
+ first_not_removed_next <= cc_chip_i;
+ end if;
+ cc_nextnotremoved_i_next <= cc_chip_i + 1; -- next not removed chip after chip i is stored at location (i+1) in jtag_next_not_removed
+ jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_LD) <=
+ std_logic_vector(cc_chip_i);
+ end if;
+ if(cc_chip_i = numchips_configured - 1) then
+ jtag_next_not_removed_next((to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto (to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_LD) <= (others => '1'); -- set next chip for last chip to invalid
+ cc_state_next <= CC_SETNUMCHIPS; -- finished counting active chips
+ else
+ cc_chip_i_next <= cc_chip_i + 1;
+ end if;
+ when CC_SETNUMCHIPS =>
+ numchips_active_next <= numchips_active_acc;
+ cc_state_next <= CC_IDLE;
+ end case;
+end process;
+
+
+-- delay one clock cycle
+jtag_refresh_active_last_next <= jtag_refresh_active;
+
+
+-- monitoring
+--MON_FIFO_WRITE_OUT(0) <= read_mon_write_out;
+--MON_FIFO_WRITE_OUT(1) <= read_mon_write_out;
+--MON_FIFO_WRITE_OUT(2) <= read_mon_write_out;
+-- monitoring debug test
+--MON_FIFO_DATA_OUT(79 downto 64) <= JTAG_M26_DEV_ID(15 downto 0);
+--MON_FIFO_DATA_OUT(111 downto 96) <= JTAG_M26_DEV_ID(31 downto 16);
+--MON_FIFO_WRITE_OUT(2) <= '1';
+--MON_FIFO_WRITE_OUT(3) <= '1';
+
+SYNCHRONOUS_M26_CONTROLLER_SIMPLE : process (CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ m26cs_state <= M26CSS_STOPPED;
+ trigger_begin_bypassreg <= '0';
+ trigger_jtag_read <= '0';
+ trigger_jtag_write <= '0';
+ trigger_copy_ram3 <= '0';
+ trigger_juec_update_d_ch <= '0';
+ trigger_juec_update_rd_err <= '0';
+ trigger_juec_update_wr_err <= '0';
+ trigger_juec_update_run_counter <= '0';
+ trigger_check_crc_ram1a <= '0';
+ trigger_init_ram1b <= '0';
+ trigger_blank_ram3a <= '0';
+ run_counter <= (others =>'0');
+ m26cs_firstrun <= '0';
+ jtag_chain_broken_counter <= (others =>'0');
+ ram1a_select <= (others =>'0');
+ ram1b_select <= '0';
+ ram2_select <= '0';
+ ram3a_select <= '0';
+ ram3a_rd_select <= '0';
+ chain_status <= (others =>'0');
+ request_reset <= '0';
+ reset_wait <= (others =>'0');
+ run_requested <= '0';
+ write_once_requested <= '0';
+ write_once_count <= (others =>'0');
+ -- INSERTLABEL: SYNCHRONOUS reset
+ else
+ m26cs_state <= m26cs_state_next;
+ trigger_begin_bypassreg <= trigger_begin_bypassreg_next;
+ trigger_jtag_read <= trigger_jtag_read_next;
+ trigger_jtag_write <= trigger_jtag_write_next;
+ trigger_copy_ram3 <= trigger_copy_ram3_next;
+ trigger_juec_update_d_ch <= trigger_juec_update_d_ch_next;
+ trigger_juec_update_rd_err <= trigger_juec_update_rd_err_next;
+ trigger_juec_update_wr_err <= trigger_juec_update_wr_err_next;
+ trigger_juec_update_run_counter <= trigger_juec_update_run_counter_next;
+ trigger_check_crc_ram1a <= trigger_check_crc_ram1a_next;
+ trigger_init_ram1b <= trigger_init_ram1b_next;
+ trigger_blank_ram3a <= trigger_blank_ram3a_next;
+ run_counter <= run_counter_next;
+ m26cs_firstrun <= m26cs_firstrun_next;
+ jtag_chain_broken_counter <= jtag_chain_broken_counter_next;
+ ram1a_select <= ram1a_select_next;
+ ram1b_select <= ram1b_select_next;
+ ram2_select <= ram2_select_next;
+ ram3a_select <= ram3a_select_next;
+ ram3a_rd_select <= ram3a_rd_select_next;
+ chain_status <= chain_status_next;
+ request_reset <= request_reset_next;
+ reset_wait <= reset_wait_next;
+ run_requested <= run_requested_next;
+ write_once_requested <= write_once_requested_next;
+ write_once_count <= write_once_count_next;
+ -- INSERTLABEL: SYNCHRONOUS update
+ end if;
+ end if;
+end process;
+
+COMB_M26_CONTROLLER_SIMPLE : process (RUN_REQUEST_IN, WRITE_ONCE_REQUEST_IN, m26cs_state, jtag_bypassreg_last_tck_cycle, jtag_bypassreg_idle, jtag_read_idle, jtag_write_last_tck_cycle, jtag_write_idle, juec_idle, cc_state, breakpoint_active, run_counter, m26cs_firstrun, jtag_status2_copy_requested, jtag_check1_active, jtag_refresh_active, jtag_chain_broken_counter, prog_jtag_finished, ram1a_select, jtag_check_crc_ram1a_idle, jtag_check_crc_ram1a_crc_ok, numchips_configured, ram1a_select, ram1b_select, ram2_select, ram3a_select, ram3a_rd_select, chain_status, jtag_init_ram1b_idle, jtag_bypassreg_chain_broken, jtag_bypassreg_length, crc_status_register, jtag_blank_ram3a_idle, ram1b_copy_requested, jtag_refresh_active_last, m26csoptions, crc_error_on_last_check, last_run_successful, last_run_successful_tmp, last_read_error, last_write_error, request_reset, reset_wait, run_requested, write_once_requested, write_once_count) -- INSERTLABEL: sensitivity list --jtag_read_last_tck_cycle,
+variable output : std_logic;
+variable i : integer;
+begin
+ m26cs_state_next <= m26cs_state;
+ trigger_begin_bypassreg_next <= '0';
+ trigger_jtag_read_next <= '0';
+ trigger_jtag_write_next <= '0';
+ trigger_juec_update_d_ch_next <= '0';
+ trigger_juec_update_rd_err_next <= '0';
+ trigger_juec_update_wr_err_next <= '0';
+ trigger_juec_update_run_counter_next <= '0';
+ trigger_check_crc_ram1a_next <= '0';
+ trigger_init_ram1b_next <= '0';
+ trigger_blank_ram3a_next <= '0';
+ run_counter_next <= run_counter;
+ m26cs_firstrun_next <= m26cs_firstrun;
+ idle_out_signal_next <= '0';
+ jtag_chain_broken_counter_next <= jtag_chain_broken_counter;
+ chip_counter_start_next <= '0';
+ prog_jtag_finished_next <= prog_jtag_finished;
+ chain_status_next <= chain_status;
+ crc_status_register_next <= crc_status_register;
+
+ -- ram multiplexers
+ ram1a_select_next <= ram1a_select;
+ ram1b_select_next <= ram1b_select;
+ ram2_select_next <= ram2_select;
+ ram3a_select_next <= ram3a_select;
+ ram3a_rd_select_next <= ram3a_rd_select;
+
+ crc_error_on_last_check_next <= crc_error_on_last_check;
+ last_run_successful_next <= last_run_successful;
+ last_run_successful_tmp_next <= last_run_successful_tmp;
+ begin_count_read_errors <= '0'; -- added 201210
+ begin_count_write_errors <= '0'; -- added 201210
+ begin_count_data_changed <= '0'; -- added 201210
+ end_count_read_errors <= '0'; -- added 201210
+ end_count_write_errors <= '0'; -- added 201210
+ end_count_data_changed <= '0'; -- added 201210
+ request_reset_next <= request_reset;
+ reset_wait_next <= reset_wait;
+ run_requested_next <= run_requested;
+ write_once_requested_next <= write_once_requested;
+ write_once_count_next <= write_once_count;
+ -- INSERTLABEL: COMB defaults
+
+
+
+ case m26cs_state is
+ when M26CSS_STOPPED =>
+ -- if stopped, start again if jtag_refresh_active is set
+ if(jtag_check1_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
+ m26cs_state_next <= M26CSS_CHECK1_WAIT_FOR_HAVE_TIME;
+ elsif(jtag_refresh_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ -- if just started, reset all counters
+ if(jtag_refresh_active_last = '0') then
+ m26cs_firstrun_next <= '1';
+ end if;
+ end if;
+ when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
+ --if(have_time_for_check) then
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ --end if;
+
+ when M26CSS_WAIT_FOR_TRIGGER =>
+ idle_out_signal_next <= '1';
+ last_run_successful_next <= last_run_successful_tmp;
+ -- if not stopped, test if we should stop
+ if(jtag_refresh_active = '0' or jtag_status2_copy_requested = '1' or ram1b_copy_requested = '1') then
+ ram3a_rd_select_next <= '0'; -- select jtag_copy_ram3_ram3a
+ m26cs_state_next <= M26CSS_STOPPED;
+ else
+ -- if we should not stop, check for off_spill and if we have time for writing
+ if(run_requested = '1') then
+ -- increment run counter (exclusively done here)
+ run_counter_next <= run_counter + 1;
+ prog_jtag_finished_next <= '0';
+ trigger_check_crc_ram1a_next <= '1';
+ ram1a_select_next <= "11"; -- select check_crc_ram1a
+ if(m26cs_firstrun = '1') then
+ trigger_blank_ram3a_next <= '1';
+ ram3a_select_next <= '1'; -- blank_ram3a (at same time)
+ end if;
+ last_run_successful_tmp_next <= '0';
+ m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_BEGIN;
+ elsif(write_once_requested = '1') then
+ trigger_check_crc_ram1a_next <= '1';
+ ram1a_select_next <= "11"; -- select check_crc_ram1a
+ m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN;
+ end if;
+ end if;
+ when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
+ m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_WAIT;
+ when M26CSS_CHECK_CRC_RAM1A_WAIT =>
+ if(jtag_check_crc_ram1a_idle = '1') then
+ crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
+ output := '1';
+ for i in MAX_NUMCHIPS-1 downto 0 loop
+ if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
+ output := '0';
+ end if;
+ end loop;
+ --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
+ if(output = '1') then
+ -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
+ crc_error_on_last_check_next <= '0';
+ trigger_init_ram1b_next <= '1';
+ ram1b_select_next <= '0'; -- select init ram1b
+ ram1a_select_next <= "10"; -- select init ram1b
+ m26cs_state_next <= M26CSS_INIT_RAM1B_BEGIN;
+ else
+ -- crc error in configured chips, don't continue
+ crc_error_on_last_check_next <= '1';
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+ when M26CSS_INIT_RAM1B_BEGIN =>
+ m26cs_state_next <= M26CSS_INIT_RAM1B_WAIT;
+ when M26CSS_INIT_RAM1B_WAIT =>
+ if(jtag_init_ram1b_idle = '1') then
+ if(m26cs_firstrun = '1') then
+ -- skip data changed
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ else
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ ram2_select_next <= '0'; -- tdo_compare_count
+ begin_count_data_changed <= '1';-- added 201210
+ m26cs_state_next <= M26CSS_DATA_CHANGED_BEGIN;
+ end if;
+ end if;
+ when M26CSS_DATA_CHANGED_BEGIN =>
+ m26cs_state_next <= M26CSS_DATA_CHANGED_WAIT;
+ when M26CSS_DATA_CHANGED_WAIT =>
+ if(jtag_write_last_tck_cycle = '1' or jtag_write_idle = '1') then
+ end_count_data_changed <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_BLANK_RAM3A_WAIT;
+ end if;
+ when M26CSS_BLANK_RAM3A_WAIT =>
+ if(jtag_blank_ram3a_idle = '1') then
+ if(breakpoint_active(0) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_d_ch_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_WAIT;
+ when M26CSS_JUEC_DATA_CHANGED_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(1) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
+ end if;
+ end if;
+
+ when M26CSS_COUNT_CHIPS_BEGIN =>
+ m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ when M26CSS_COUNT_CHIPS_WAIT =>
+ if(cc_state = CC_IDLE) then
+ if(breakpoint_active(2) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+-- if(m26csoptions(0) = '1') then
+ -- skip BYPASSREG CHAIN TEST
+ -- and set CHAIN status to BROKEN
+ chain_status_next(0) <= '1';
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0');
+ -- next state:
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
+-- else
+-- trigger_begin_bypassreg_next <= '1';
+-- m26cs_state_next <= M26CSS_BYPASSREG_BEGIN;
+-- end if;
+ end if;
+ end if;
+ when M26CSS_BYPASSREG_BEGIN =>
+ m26cs_state_next <= M26CSS_BYPASSREG_WAIT;
+ when M26CSS_BYPASSREG_WAIT =>
+ if(jtag_bypassreg_last_tck_cycle = '1' or jtag_bypassreg_idle = '1') then
+ if(breakpoint_active(3) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ chain_status_next(0) <= jtag_bypassreg_chain_broken; -- chain broken
+ if(unsigned(jtag_bypassreg_length) < 2**MAX_NUMCHIPS_PLUS_ONE_LD) then
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= jtag_bypassreg_length(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -- chain length
+ else
+ chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0'); -- chain length: set to zero because to long chain found
+ end if;
+ if(jtag_bypassreg_chain_broken = '1') then
+ jtag_chain_broken_counter_next <= jtag_chain_broken_counter + 1;
+
+ --m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
+ else
+ ram2_select_next <= '0'; -- tdo_compare_count
+ ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ trigger_jtag_read_next <= '1';
+ begin_count_read_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_READ1_BEGIN;
+ end if;
+ end if;
+ end if;
+ when M26CSS_READ1_BEGIN =>
+ m26cs_state_next <= M26CSS_READ1_WAIT;
+ when M26CSS_READ1_WAIT =>
+ if(jtag_read_idle = '1') then -- removed (jtag_read_last_tck_cycle = '1' or ) because writing to RAM needs time
+ end_count_read_errors <= '1'; -- added 201210
+ if(breakpoint_active(4) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_rd_err_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_READ_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_READ_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_READ_WAIT;
+ when M26CSS_JUEC_READ_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(5) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ elsif(jtag_check1_active = '1') then
+ -- in case of check1 set, don't write registers
+ -- in order to save time
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_STOPPED;
+ else
+ -- do the following later!
+ --trigger_jtag_write_next <= '1';
+ --ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ --ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ --ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_REQUEST_RESET_BEGIN;
+ end if;
+ end if;
+ when M26CSS_REQUEST_RESET_BEGIN =>
+ request_reset_next <= '1';
+ m26cs_state_next <= M26CSS_REQUEST_RESET_WAIT;
+ when M26CSS_REQUEST_RESET_WAIT =>
+ reset_wait_next <= RESET_WAIT_DURATION;
+ m26cs_state_next <= M26CSS_REQUESTED_RESET_WAIT;
+ when M26CSS_REQUESTED_RESET_WAIT =>
+ reset_wait_next <= reset_wait - 1;
+ request_reset_next <= '0';
+ if(reset_wait = reset_wait_zero) then
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ if(ram1b_copy_requested = '0') then -- this is a hack, to only change ram1b if not yet data changed triggered copy request
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ else
+ ram1b_select_next <= '0';
+ end if;
+ ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_WRITE1_BEGIN;
+ end if;
+ when M26CSS_WRITE1_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITE1_WAIT;
+ when M26CSS_WRITE1_WAIT =>
+ if(jtag_write_idle = '1') then
+ if(breakpoint_active(6) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_jtag_write_next <= '1';
+ begin_count_write_errors <= '1'; -- added 201210
+ m26cs_state_next <= M26CSS_WRITE2_BEGIN;
+ end if;
+ end if;
+ when M26CSS_WRITE2_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITE2_WAIT;
+ when M26CSS_WRITE2_WAIT =>
+ if(jtag_write_idle = '1') then
+ end_count_write_errors <= '1'; -- added 201210
+ if(breakpoint_active(7) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ prog_jtag_finished_next <= '1';
+ trigger_juec_update_wr_err_next <= '1';
+ ram2_select_next <= '1'; -- juec
+ ram3a_select_next <= '0'; -- juec
+ m26cs_state_next <= M26CSS_JUEC_WRITE_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_WRITE_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_WRITE_WAIT;
+ when M26CSS_JUEC_WRITE_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(8) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ trigger_juec_update_run_counter_next <= '1';
+ m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_BEGIN;
+ end if;
+ end if;
+ when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
+ m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_WAIT;
+ when M26CSS_JUEC_RUN_COUNTER_WAIT =>
+ if(juec_idle = '1') then
+ if(breakpoint_active(9) = '1') then
+ --stay in state
+ --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
+ else
+ m26cs_firstrun_next <= '0';
+ last_run_successful_tmp_next <= not (last_read_error or last_write_error); -- added 201210
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+
+
+ -- WRITE_ONCE states
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT;
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
+ if(jtag_check_crc_ram1a_idle = '1') then
+ crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
+ output := '1';
+ for i in MAX_NUMCHIPS-1 downto 0 loop
+ if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
+ output := '0';
+ end if;
+ end loop;
+ --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
+ if(output = '1') then
+ -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
+ crc_error_on_last_check_next <= '0';
+ trigger_init_ram1b_next <= '1';
+ ram1b_select_next <= '0'; -- select init ram1b
+ ram1a_select_next <= "10"; -- select init ram1b
+ m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_BEGIN;
+ else
+ -- crc error in configured chips, don't continue
+ crc_error_on_last_check_next <= '1';
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end if;
+ when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_WAIT;
+ when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
+ if(jtag_init_ram1b_idle = '1') then
+ chip_counter_start_next <= '1';
+ m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN;
+ end if;
+ when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_WAIT;
+ when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
+ trigger_jtag_write_next <= '1';
+ ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
+ ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
+ ram2_select_next <= '0'; -- tdo_compare_count
+ m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_BEGIN;
+ when M26CSS_WRITEONCE_WRITE1_BEGIN =>
+ m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_WAIT;
+ when M26CSS_WRITEONCE_WRITE1_WAIT =>
+ if(jtag_write_idle = '1') then
+ -- clear requests
+ run_requested_next <= '0';
+ write_once_requested_next <= '0';
+ write_once_count_next <= write_once_count + 1;
+ m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
+ end if;
+ end case;
+ if(RUN_REQUEST_IN = '1') then
+ run_requested_next <= '1';
+ end if;
+ if(WRITE_ONCE_REQUEST_IN = '1') then
+ write_once_requested_next <= '1';
+ end if;
+
+end process;
+
+
+status2_copy_finished <= not jtag_status2_copy_requested and not jtag_status2_copy_request_strobe;
+CP_STATUS2 : process(jtag_status2_copy_requested, jtag_status2_copy_request_strobe, status2_chain_status, status2_run_counter, cps2_state, m26cs_state, jtag_copy_ram3_idle, run_counter, chain_status)
+begin
+ jtag_status2_copy_requested_next <= jtag_status2_copy_requested;
+ -- these are all copies of the registers changed in M26CS
+ status2_run_counter_next <= status2_run_counter;
+ status2_chain_status_next <= status2_chain_status;
+ cps2_state_next <= cps2_state;
+ trigger_copy_ram3_next <= '0';
+ case cps2_state is
+ when CPS2_IDLE =>
+ if(jtag_status2_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
+ trigger_copy_ram3_next <= '1';
+ cps2_state_next <= CPS2_COPY_BEGIN;
+ end if;
+ when CPS2_COPY_BEGIN =>
+ status2_run_counter_next <= run_counter;
+ status2_chain_status_next <= chain_status;
+ cps2_state_next <= CPS2_COPY_WAIT;
+ when CPS2_COPY_WAIT =>
+ if(jtag_copy_ram3_idle = '1') then
+ jtag_status2_copy_requested_next <= '0';
+ cps2_state_next <= CPS2_IDLE;
+ end if;
+ end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
+ if(jtag_status2_copy_request_strobe = '1') then
+ jtag_status2_copy_requested_next <= '1';
+ end if;
+end process;
+
+TRIGGER_CP_RAM1B1C : process(ram1b_copy_requested, ram1c_run_counter, ram1c_chain_status, ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_strobe, copy_ram1b1c_idle, cpr1bc_state, m26cs_state, run_counter, chain_status, juec_read_errors, juec_write_errors, juec_data_changed)
+begin
+ ram1b_copy_requested_next <= ram1b_copy_requested;
+ -- these are all copies of the registers changed in M26CS
+ ram1c_run_counter_next <= ram1c_run_counter;
+ ram1c_chain_status_next <= ram1c_chain_status;
+ cpr1bc_state_next <= cpr1bc_state;
+ trigger_copy_ram1b1c_next <= '0';
+ ram1b1c_copy_trigger_active_next <= ram1b1c_copy_trigger_active or ram1b1c_copy_trigger_strobe;
+ case cpr1bc_state is
+ when CPR1BC_IDLE =>
+ if(ram1b_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
+ trigger_copy_ram1b1c_next <= '1';
+ cpr1bc_state_next <= CPR1BC_COPY_BEGIN;
+ end if;
+ when CPR1BC_COPY_BEGIN =>
+ ram1c_run_counter_next <= run_counter;
+ ram1c_chain_status_next <= chain_status;
+ cpr1bc_state_next <= CPR1BC_COPY_WAIT;
+ when CPR1BC_COPY_WAIT =>
+ if(copy_ram1b1c_idle = '1') then
+ ram1b_copy_requested_next <= '0';
+ cpr1bc_state_next <= CPR1BC_IDLE;
+ end if;
+ end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
+ if(juec_read_errors = '1' and ram1b1c_copy_trigger_active(0) = '1') or
+ (juec_write_errors = '1' and ram1b1c_copy_trigger_active(1) = '1') or
+ (juec_data_changed = '1' and ram1b1c_copy_trigger_active(2) = '1') or
+ (ram1b1c_copy_trigger_active(3) = '1') then
+ ram1b_copy_requested_next <= '1';
+ -- deactivate triggers (copy is requested)
+ ram1b1c_copy_trigger_active_next <= (others => '0');
+ end if;
+end process;
+
+
+
+-- -- OR the status bits of all registers separately for each sensor and (JTAG_ERROR, DATA_CHANGED, DATA CHANGED OVER THRESHOLD)
+-- WRITE_STATUS_REG_OR : process(write_status_register)
+-- variable write_status_reg_acc : std_logic_vector(3*MAX_NUMCHIPS-1 downto 0);
+-- begin
+-- write_status_reg_acc := (others => '0');
+-- for i in 0 to MAX_REGISTERS - 1 loop
+-- write_status_reg_acc := write_status_reg_acc or
+-- write_status_register( i*3*MAX_NUMCHIPS + 3*MAX_NUMCHIPS - 1 downto
+-- i*3*MAX_NUMCHIPS);
+-- end loop;
+-- write_status_register_or_next <= write_status_reg_acc;
+-- end process;
+
+
+-- READ_STATUS_REG_OR : process(status_register)
+-- variable read_error2_acc : std_logic;
+-- begin
+-- read_error2_acc := '0';
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- read_error2_acc := read_error2_acc or status_register(STATUS_READ_ERROR2 + i);
+-- end loop;
+-- status_register_read_error2_next <= read_error2_acc;
+-- end process;
+
+--numchips_configured_next <= std_logic_vector(to_unsigned(3,MAX_NUMCHIPS_LD+1));
+--ram_m26c_a1_next(M26C_RAM_DEPTH-1 downto 8) <= ram_base_addr;
+-- put together ram1a address
+ram1a_a1 <= ram1a_a1_base_addr & ram1a_a1_rel_addr;
+buf_bus2_ram_read_enable_out_next <= bus2_ram_read_enable_out;
+buf_buf_bus2_ram_read_enable_out_next <= buf_bus2_ram_read_enable_out;
+BUS2_RAM_RW : process (bus2_ram_addr_out, bus2_ram_data_out, bus2_ram_read_enable_out, bus2_ram_write_enable_out, buf_buf_bus2_ram_read_enable_out, ram1a_dout1, ram1a_din1, ram1a_a1_rel_addr, bus2_ram_data_in, m26cs_stopped)
+begin
+ ram1a_wr1_next <= '0';
+ ram1a_din1_next <= ram1a_din1;
+ ram1a_a1_rel_addr_next <= ram1a_a1_rel_addr;
+ bus2_ram_data_in_next <= bus2_ram_data_in;
+ bus2_ram_dataready_in_next <= '0';
+ bus2_ram_write_ack_in_next <= '0';
+ bus2_ram_no_more_data_in_next <= '0';
+ bus2_ram_unknown_addr_in_next <= '0';
+ if(bus2_ram_write_enable_out='1') then
+ ram1a_din1_next <= bus2_ram_data_out;
+ ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+ -- only allow ram1a to be changed if stopped!
+ if(m26cs_stopped = '1') then
+ ram1a_wr1_next <= '1';
+ bus2_ram_write_ack_in_next <= '1';
+ else
+ bus2_ram_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_ram_read_enable_out='1') then
+ ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+
+ elsif(buf_buf_bus2_ram_read_enable_out='1') then
+ bus2_ram_data_in_next <= ram1a_dout1;
+ bus2_ram_dataready_in_next <= '1';
+ end if;
+end process;
+
+BUS2_STATUS_R : process (bus2_status_addr_out, crc_status_register, bus2_status_read_enable_out, bus2_status_write_enable_out, bus2_status_data_in)
+variable bus_addr_int : integer range 0 to 31;
+begin
+ bus2_status_data_in_next <= bus2_status_data_in;
+ bus2_status_dataready_in_next <= '0';
+ bus2_status_write_ack_in_next <= '0';
+ bus2_status_no_more_data_in_next <= '0';
+ bus2_status_unknown_addr_in_next <= '0';
+ if(bus2_status_read_enable_out='1') then
+ -- STATUS register layout: 8 bits/chip
+ -- first 32 bits : CRC status
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ bus_addr_int := to_integer(unsigned(bus2_status_addr_out(4 downto 0)));
+ if(bus_addr_int = 0) then
+ bus2_status_data_in_next(31 downto MAX_REGISTERS) <= (others => '0');
+ bus2_status_data_in_next(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0);
+ bus2_status_dataready_in_next <= '1';
+-- elsif(4*(bus_addr_int-1) < MAX_NUMCHIPS) then
+-- -- for i in 0 to MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3) loop
+-- -- bus2_status_data_in_next(8*i+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+i);
+-- -- bus2_status_data_in_next(8*i+7 downto 8*i+6) <= (others => '0');
+-- -- end loop;
+-- -- bus2_status_data_in_next(31 downto 8*(MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3)+1)) <= (others => '0');
+--
+-- bus2_status_data_in_next <= (others => '0');
+-- bus2_status_data_in_next(8*0+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+6) <= removed_chips(4*(bus_addr_int-1)+0);
+-- bus2_status_data_in_next(8*0+7 downto 8*0+7) <= (others => '0');
+-- if(4*(bus_addr_int-1)+1 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*1+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+6) <= removed_chips(4*(bus_addr_int-1)+1);
+-- bus2_status_data_in_next(8*1+7 downto 8*1+7) <= (others => '0');
+-- end if;
+-- if(4*(bus_addr_int-1)+2 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*2+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+6) <= removed_chips(4*(bus_addr_int-1)+2);
+-- bus2_status_data_in_next(8*2+7 downto 8*2+7) <= (others => '0');
+-- end if;
+-- if(4*(bus_addr_int-1)+3 < MAX_NUMCHIPS) then
+-- bus2_status_data_in_next(8*3+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+3); bus2_status_data_in_next(8*3+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+6) <= removed_chips(4*(bus_addr_int-1)+3);
+-- bus2_status_data_in_next(8*3+7 downto 8*3+7) <= (others => '0');
+-- end if;
+-- bus2_status_dataready_in_next <= '1';
+ else
+ bus2_status_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+ if(bus2_status_write_enable_out='1') then
+ bus2_status_unknown_addr_in_next <= '1';
+ end if;
+end process;
+
+BUS2_CONTROL_RW : process (bus2_control_addr_out, bus2_control_data_out, bus2_control_read_enable_out, bus2_control_write_enable_out, bus2_control_data_in, jtag_refresh_active, ram1a_a1_base_addr, data_register, jtag_check1_active, numchips_configured, removed_chips, jtag_clock_cycle_length, jtag_clock_time1, jtag_clock_time2,
+jtag_sample_time1, jtag_sample_time2, jtag_sample_time3, jtag_set_data_time, breakpoint_active, run_counter, debug_trigger_counter, last_not_removed, m26cs_stopped, numchips_active, m26csoptions, jtag_delay_expvalues
+)
+begin
+ bus2_control_data_in_next <= bus2_control_data_in;
+ bus2_control_dataready_in_next <= '0';
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '0';
+ bus2_control_unknown_addr_in_next <= '0';
+ jtag_refresh_active_next <= jtag_refresh_active;
+ ram1a_a1_base_addr_next <= ram1a_a1_base_addr;
+ data_register_next <= data_register;
+ jtag_status2_copy_request_strobe_next <= '0';
+ jtag_check1_active_next <= jtag_check1_active;
+ numchips_configured_next <= numchips_configured;
+ removed_chips_next <= removed_chips;
+ jtag_clock_cycle_length_next <= jtag_clock_cycle_length;
+ jtag_clock_time1_next <= jtag_clock_time1;
+ jtag_clock_time2_next <= jtag_clock_time2;
+ jtag_sample_time1_next <= jtag_sample_time1;
+ jtag_sample_time2_next <= jtag_sample_time2;
+ jtag_sample_time3_next <= jtag_sample_time3;
+ jtag_set_data_time_next <= jtag_set_data_time;
+ jtag_pulses_reset_next <= '0';
+ breakpoint_active_next <= breakpoint_active;
+ ram1b1c_copy_trigger_strobe_next <= (others => '0');
+ m26csoptions_next <= m26csoptions;
+ jtag_delay_expvalues_next <= jtag_delay_expvalues;
+
+ --driver_speed_next <= driver_speed;
+ --deactivate_sensor_strobe_next <= (others => '0');
+ --reactivate_sensor_strobe_next <= (others => '0');
+ --disable_write_next <= disable_write;
+ --disable_writeerror_for_remove_next <= disable_writeerror_for_remove;
+ --disable_remove_next <= disable_remove;
+ --debug_one_remove_strobe_next <= '0';
+ if(bus2_control_write_enable_out='1') then
+ -- CONTROL registers layout:
+ -- ADDR_CONTROL_CMD
+ -- ADDR_CONTROL_RAM_BASEADDR
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
+ bus2_control_write_ack_in_next <= '1';
+ if(bus2_control_data_out(7 downto 0) = M26C_CMD_START) then
+ jtag_refresh_active_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) =M26C_CMD_START_CHECK1) then
+ jtag_check1_active_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_STOP) then
+ jtag_refresh_active_next <= '0';
+ jtag_check1_active_next <= '0';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REMOVE_SENSOR ) then
+ -- only signal ack if really written
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '1';
+ -- only allowed to change removed chips when not writing to JTAG interface!
+ if(m26cs_stopped = '1') then
+ if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+ removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+ bus2_control_write_ack_in_next <= '1';
+ bus2_control_no_more_data_in_next <= '0';
+ end if;
+ end if;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_INSERT_SENSOR ) then
+ -- only signal ack if really written
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_no_more_data_in_next <= '1';
+ -- only allowed to change removed chips when not writing to JTAG interface!
+ if(jtag_refresh_active = '0' and jtag_check1_active = '0') then
+ if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+ removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '0';
+ bus2_control_write_ack_in_next <= '1';
+ bus2_control_no_more_data_in_next <= '0';
+ end if;
+ end if;
+ --elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_SPEED) then
+ --driver_speed_next <= data_register(15 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_SPEED) then
+-- data_register_next(31 downto 16) <= (others => '0');
+-- data_register_next(15 downto 0) <= driver_speed;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REACTIVATE_SENSOR) then
+-- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+-- reactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+-- end if;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_DEACTIVATE_SENSOR) then
+-- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
+-- deactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
+-- end if;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_CONFIGURED) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_ACTIVE) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_TRIGGER_COUNT) then
+ data_register_next <= std_logic_vector(debug_trigger_counter);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DISABLE_WRITE) then
+-- data_register_next(31 downto 1) <= (others => '0');
+-- data_register_next(0) <= disable_write;
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DISABLE_WRITE) then
+-- disable_write_next <= data_register(0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_LAST_NOT_REMOVED) then
+ data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
+ data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED) then
+ data_register_next(31 downto 1) <= (others => '0');
+ data_register_next(0) <= removed_chips(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED32) then
+ data_register_next(31 downto MYMIN(MAX_NUMCHIPS-1, 31)) <= (others => '0');
+ data_register_next(MYMIN(MAX_NUMCHIPS-1, 31) downto 0) <= removed_chips(MYMIN(MAX_NUMCHIPS-1, 31) downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REACTIVATE_SENSOR32) then
+-- data_register_next(31 downto 0) <= reactivate_sensor(31 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DEACTIVATE_SENSOR32) then
+-- data_register_next(31 downto 0) <= deactivate_sensor(31 downto 0);
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_M26_DEV_ID) then
+-- data_register_next <= JTAG_M26_DEV_ID;
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_NUMCHIPS_CONFIGURED) then
+ numchips_configured_next <= unsigned(data_register(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0));
+-- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS) then
+-- data_register_next(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= std_logic_vector(numchips_configured);
+-- data_register_next(31 downto MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_BREAKPOINTS) then
+ breakpoint_active_next <= data_register(9 downto 0);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_BREAKPOINTS) then
+ data_register_next(9 downto 0) <= breakpoint_active;
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH) then
+ jtag_clock_cycle_length_next <= unsigned(data_register(9 downto 0));
+ jtag_pulses_reset_next <= '1'; -- reset counter (because maximum value of counter could be exceeded)
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME1) then
+ jtag_clock_time1_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME1) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time1);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME2) then
+ jtag_clock_time2_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME2) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time2);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME1) then
+ jtag_sample_time1_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME1) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time1);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME2) then
+ jtag_sample_time2_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME2) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time2);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME3) then
+ jtag_sample_time3_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME3) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time3);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SET_DATA_TIME) then
+ jtag_set_data_time_next <= unsigned(data_register(9 downto 0));
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SET_DATA_TIME) then
+ data_register_next(9 downto 0) <= std_logic_vector(jtag_set_data_time);
+ data_register_next(31 downto 10) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_RUN_COUNT) then
+ data_register_next(31 downto 0) <= std_logic_vector(run_counter);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_TO_STATUS2) then
+ jtag_status2_copy_request_strobe_next <= '1';
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER) then
+ ram1b1c_copy_trigger_strobe_next(3 downto 0) <= data_register(3 downto 0); -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR) then
+ ram1b1c_copy_trigger_strobe_next(0) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR) then
+ ram1b1c_copy_trigger_strobe_next(1) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED) then
+ ram1b1c_copy_trigger_strobe_next(2) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW) then
+ ram1b1c_copy_trigger_strobe_next(3) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_CSOPTIONS) then
+ m26csoptions_next(0 downto 0) <= data_register(0 downto 0); -- bit 0 => skip bypassreg chaintest
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_CSOPTIONS) then
+ data_register_next(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest
+ data_register_next(31 downto 0+1) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DELAY_EXPECTED_VALUES) then
+ jtag_delay_expvalues_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= data_register(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DELAY_EXPECTED_VALUES) then
+ data_register_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
+ data_register_next(31 downto JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD) <= (others => '0');
+ elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_ACTIVITY) then
+ data_register_next(0) <= jtag_refresh_active;
+ data_register_next(1) <= jtag_check1_active;
+ data_register_next(31 downto 2) <= (others => '0');
+ else
+ -- revoke write_ack, which was set preliminary before "if"
+ bus2_control_write_ack_in_next <= '0';
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
+ ram1a_a1_base_addr_next <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0);
+ bus2_control_write_ack_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
+ data_register_next <= bus2_control_data_out;
+ bus2_control_write_ack_in_next <= '1';
+ else
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_control_read_enable_out='1') then
+ if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
+ bus2_control_data_in_next <= (others => '0');
+ bus2_control_dataready_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
+ bus2_control_data_in_next(31 downto RAM_JTAG_REGISTERS_DEPTH-8) <= (others => '0');
+ bus2_control_data_in_next(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr;
+ bus2_control_dataready_in_next <= '1';
+ elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
+ bus2_control_data_in_next <= data_register;
+ bus2_control_dataready_in_next <= '1';
+ else
+ bus2_control_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+BUS2_DEBUG_R : process (bus2_debug_addr_out, bus2_debug_read_enable_out, bus2_debug_write_enable_out, bus2_debug_data_in, debug_m26cs_state, debug_trigger_counter, debug_test, ram1b_a2, ram1b_dout2, bus2_debug_data_out, ram1c_a2, ram1c_dout2, ram1c_chain_status, ram1c_run_counter, debugtdo_timeout, debugtdo_underflow, debugtdo_overflow, debugtdo_full, debugtdo_empty, debugtdo_dout, write_once_count)
+begin
+ bus2_debug_data_in_next <= bus2_debug_data_in;
+ bus2_debug_dataready_in_next <= '0';
+ bus2_debug_write_ack_in_next <= '0';
+ bus2_debug_no_more_data_in_next <= '0';
+ bus2_debug_unknown_addr_in_next <= '0';
+ debug_test_next <= debug_test;
+ ram1b_a2_next <= ram1b_a2;
+ ram1c_a2_next <= ram1c_a2;
+ debugtdo_activate_strobe <= '0';
+ debugtdo_timeout_next <= debugtdo_timeout;
+ debugtdo_rd_en <= '0';
+ resetdebugtdo_strobe <= '0';
+ if(bus2_debug_write_enable_out='1') then
+ if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
+ debug_test_next <= bus2_debug_data_out;
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1BADDR) then
+ ram1b_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1CADDR) then
+ ram1c_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
+ debugtdo_timeout_next <= bus2_debug_data_out(31 downto 0);
+ bus2_debug_write_ack_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_ACTIVATE) then
+ if( bus2_debug_data_out(0) = '1') then
+ debugtdo_activate_strobe <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ end if;
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_CONTROLFIFO) then
+ if( bus2_debug_data_out(0) = '1') then
+ debugtdo_rd_en <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ elsif( bus2_debug_data_out(4) = '1') then
+ resetdebugtdo_strobe <= '1';
+ bus2_debug_write_ack_in_next <= '1';
+ end if;
+ else
+ bus2_debug_unknown_addr_in_next <= '1';
+ end if;
+ elsif(bus2_debug_read_enable_out='1') then
+ if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
+ bus2_debug_data_in_next <= debug_test;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26CS_STATE) then
+ bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+ bus2_debug_data_in_next(7 downto 0) <= debug_m26cs_state;
+ bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_READ_STATE) then
+-- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+-- bus2_debug_data_in_next(7 downto 0) <= read_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_WRITE_STATE) then
+-- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
+-- bus2_debug_data_in_next(7 downto 0) <= write_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+-- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_JTAG_DRIVER_STATE) then
+-- bus2_debug_data_in_next(31 downto 9) <= (others => '0');
+-- bus2_debug_data_in_next(8 downto 0) <= driver_state_out;
+-- bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TRIGGER_COUNT) then
+ bus2_debug_data_in_next <= std_logic_vector(debug_trigger_counter);
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_VERSION) then
+ bus2_debug_data_in_next <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
+ bus2_debug_dataready_in_next <= '1';
+ bus2_debug_unknown_addr_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1B_DATA) then
+ bus2_debug_data_in_next <= ram1b_dout2;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_DATA) then
+ bus2_debug_data_in_next <= ram1c_dout2;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_RUN_COUNTER) then
+ bus2_debug_data_in_next <= std_logic_vector(ram1c_run_counter);
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_CHAIN_STATUS) then
+ bus2_debug_data_in_next(31 downto 3+MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
+ bus2_debug_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= ram1c_chain_status;
+ bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_SAMPLES) then
+ bus2_debug_data_in_next(31 downto 0) <= debugtdo_dout;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_GETFIFOSTATUS) then
+ bus2_debug_data_in_next(0) <= debugtdo_full;
+ bus2_debug_data_in_next(1) <= debugtdo_empty;
+ bus2_debug_data_in_next(2) <= debugtdo_overflow;
+ bus2_debug_data_in_next(3) <= debugtdo_underflow;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
+ bus2_debug_data_in_next(31 downto 0) <= debugtdo_timeout_next;
+ bus2_debug_dataready_in_next <= '1';
+ elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_WRONCE_COUNT) then
+ bus2_debug_data_in_next(31 downto COUNTER_WIDTHS) <= (others => '0');
+ bus2_debug_data_in_next(COUNTER_WIDTHS-1 downto 0) <= std_logic_vector(write_once_count);
+ bus2_debug_dataready_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+buf_bus2_status2_read_ram3b_next <= bus2_status2_read_ram3b;
+BUS2_STATUS2_R : process (bus2_status2_addr_out, bus2_status2_data_out, bus2_status2_read_enable_out, bus2_status2_write_enable_out, bus2_status2_data_in, status2_copy_finished, status2_chain_status, status2_run_counter, bus2_status_addr_out, buf_bus2_status2_read_ram3b, jtag_refresh_active, ram3b_dout2, ram3b_a2_rel_addr, ram3b_a2_base_addr)
+variable bus_addr_int : integer range 0 to 31;
+begin
+ bus2_status2_data_in_next <= bus2_status2_data_in;
+ bus2_status2_dataready_in_next <= '0';
+ bus2_status2_write_ack_in_next <= '0';
+ bus2_status2_no_more_data_in_next <= '0';
+ bus2_status2_unknown_addr_in_next <= '0';
+ bus2_status2_read_ram3b_next <= '0';
+ ram3b_a2_base_addr_next <= ram3b_a2_base_addr;
+ ram3b_a2_rel_addr_next <= ram3b_a2_rel_addr;
+ if(buf_bus2_status2_read_ram3b = '1') then
+ bus2_status2_data_in_next <= ram3b_dout2;
+ bus2_status2_dataready_in_next <= '1';
+ end if;
+ if(bus2_status2_read_enable_out='1') then
+ -- STATUS register layout: 8 bits/chip
+ -- first 32 bits : CRC status
+ -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
+ -- 5: DATA_CHANGED, 6: reserved, 7: reserved
+ if(bus2_status2_addr_out(4) = '1') then -- ram3b
+ ram3b_a2_rel_addr_next <= bus2_status_addr_out(3 downto 0);
+ bus2_status2_read_ram3b_next <= '1';
+ -- dataready delayed
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_TRIGGERCOUNTER_COPY) then
+ bus2_status2_data_in_next <= std_logic_vector(status2_run_counter);
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_CHAIN_STATUS_COPY) then
+ bus2_status2_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status;
+ bus2_status2_data_in_next(31 downto 8) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_UPDATING) then
+ bus2_status2_data_in_next(0) <= not status2_copy_finished;
+ bus2_status2_data_in_next(31 downto 1) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
+ bus2_status2_data_in_next(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0) <= ram3b_a2_base_addr;
+ bus2_status2_data_in_next(31 downto RAM_ERROR_COUNTS_DEPTH-4 ) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_STARTED) then
+ bus2_status2_data_in_next(0) <= jtag_refresh_active;
+ bus2_status2_data_in_next(31 downto 1) <= (others => '0');
+ bus2_status2_dataready_in_next <= '1';
+ else
+ bus2_status2_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+ if(bus2_status2_write_enable_out='1') then
+ if(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
+ ram3b_a2_base_addr_next <= bus2_status2_data_out(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0);
+ bus2_status2_write_ack_in_next <= '1';
+ else
+ bus2_status2_unknown_addr_in_next <= '1';
+ end if;
+ end if;
+end process;
+
+--trigger_process : process (trigger_counter)
+--begin
+ --trigger_counter_next <= trigger_counter + 1;
+ --jtag_refresh_start_next <= '0';
+ --if(trigger_counter = "00000000000") then
+ -- jtag_refresh_start_next <= '1';
+ --end if;
+--end process;
+
+-- reactivate_sensor_wait : process (reactivate_sensor, reactivate_sensor_strobe, removed_chips)
+-- begin
+-- reactivate_sensor_next <= reactivate_sensor;
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- if(reactivate_sensor_strobe(i) = '1') then
+-- reactivate_sensor_next(i) <= '1';
+-- elsif(removed_chips(i) = '0') then
+-- reactivate_sensor_next(i) <= '0';
+-- end if;
+-- end loop;
+-- end process;
+-- deactivate_sensor_wait : process (deactivate_sensor, deactivate_sensor_strobe, removed_chips)
+-- begin
+-- deactivate_sensor_next <= deactivate_sensor;
+-- for i in 0 to MAX_NUMCHIPS-1 loop
+-- if(deactivate_sensor_strobe(i) = '1') then
+-- deactivate_sensor_next(i) <= '1';
+-- elsif(removed_chips(i) = '1') then
+-- deactivate_sensor_next(i) <= '0';
+-- end if;
+-- end loop;
+-- end process;
+--
+-- one_remove_wait : process (debug_one_remove_strobe, removed_strobe)
+-- begin
+-- debug_one_remove_next <= debug_one_remove;
+-- if(removed_strobe = '1') then
+-- debug_one_remove_next <= '0';
+-- elsif(debug_one_remove_strobe = '1') then
+-- debug_one_remove_next <= '1';
+-- end if;
+-- end process;
+
+debug_m26cs_state_process : process (m26cs_state)
+begin
+ case m26cs_state is
+ when M26CSS_WAIT_FOR_TRIGGER =>
+ debug_m26cs_state_next <= x"00";
+ when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
+ debug_m26cs_state_next <= x"20";
+ when M26CSS_CHECK_CRC_RAM1A_WAIT =>
+ debug_m26cs_state_next <= x"21";
+ when M26CSS_INIT_RAM1B_BEGIN =>
+ debug_m26cs_state_next <= x"22";
+ when M26CSS_INIT_RAM1B_WAIT =>
+ debug_m26cs_state_next <= x"23";
+ when M26CSS_DATA_CHANGED_BEGIN =>
+ debug_m26cs_state_next <= x"01";
+ when M26CSS_DATA_CHANGED_WAIT =>
+ debug_m26cs_state_next <= x"02";
+ when M26CSS_BLANK_RAM3A_WAIT =>
+ debug_m26cs_state_next <= x"24";
+ when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
+ debug_m26cs_state_next <= x"03";
+ when M26CSS_JUEC_DATA_CHANGED_WAIT =>
+ debug_m26cs_state_next <= x"04";
+ when M26CSS_COUNT_CHIPS_BEGIN =>
+ debug_m26cs_state_next <= x"05";
+ when M26CSS_COUNT_CHIPS_WAIT =>
+ debug_m26cs_state_next <= x"06";
+ when M26CSS_BYPASSREG_BEGIN =>
+ debug_m26cs_state_next <= x"07";
+ when M26CSS_BYPASSREG_WAIT =>
+ debug_m26cs_state_next <= x"08";
+ when M26CSS_READ1_BEGIN =>
+ debug_m26cs_state_next <= x"09";
+ when M26CSS_READ1_WAIT =>
+ debug_m26cs_state_next <= x"0a";
+ when M26CSS_JUEC_READ_BEGIN =>
+ debug_m26cs_state_next <= x"0b";
+ when M26CSS_JUEC_READ_WAIT =>
+ debug_m26cs_state_next <= x"0c";
+ when M26CSS_WRITE1_BEGIN =>
+ debug_m26cs_state_next <= x"0d";
+ when M26CSS_WRITE1_WAIT =>
+ debug_m26cs_state_next <= x"0e";
+ when M26CSS_WRITE2_BEGIN =>
+ debug_m26cs_state_next <= x"0f";
+ when M26CSS_WRITE2_WAIT =>
+ debug_m26cs_state_next <= x"10";
+ when M26CSS_JUEC_WRITE_BEGIN =>
+ debug_m26cs_state_next <= x"11";
+ when M26CSS_JUEC_WRITE_WAIT =>
+ debug_m26cs_state_next <= x"12";
+ when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
+ debug_m26cs_state_next <= x"13";
+ when M26CSS_STOPPED =>
+ debug_m26cs_state_next <= x"14";
+ when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
+ debug_m26cs_state_next <= x"15";
+ when M26CSS_JUEC_RUN_COUNTER_WAIT =>
+ debug_m26cs_state_next <= x"16";
+ when M26CSS_REQUEST_RESET_BEGIN =>
+ debug_m26cs_state_next <= x"17";
+ when M26CSS_REQUEST_RESET_WAIT =>
+ debug_m26cs_state_next <= x"18";
+ when M26CSS_REQUESTED_RESET_WAIT =>
+ debug_m26cs_state_next <= x"19";
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
+ debug_m26cs_state_next <= x"1a";
+ when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
+ debug_m26cs_state_next <= x"1b";
+ when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
+ debug_m26cs_state_next <= x"1c";
+ when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
+ debug_m26cs_state_next <= x"1d";
+ when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
+ debug_m26cs_state_next <= x"1e";
+ when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
+ debug_m26cs_state_next <= x"1f";
+ when M26CSS_WRITEONCE_WRITE1_BEGIN =>
+ debug_m26cs_state_next <= x"25";
+ when M26CSS_WRITEONCE_WRITE1_WAIT =>
+ debug_m26cs_state_next <= x"26";
+
+ end case;
+end process;
+
+
+IDLE_OUT <= idle_out_signal;
+--write_idle_last_next <= write_idle;
+--read_idle_last_next <= read_idle;
+--SEQ_have_time_COUNTER : process(CLK_IN)
+--begin
+-- if(rising_edge(CLK_IN)) then
+-- if(RESET_IN ='1') then
+-- htcounter <= (others => '0');
+-- have_time_for_write <= '0';
+-- debug_trigger_counter <= (others => '0');
+-- else
+-- htcounter <= htcounter_next;
+-- have_time_for_write <= have_time_for_write_next;
+-- debug_trigger_counter <= debug_trigger_counter_next;
+-- end if;
+-- end if;
+--end process;
+
+---- process for counter and to decide when it's still ok to start a jtag write
+--COMB_have_time_COUNTER : process(htcounter, OFF_SPILL_IN, debug_trigger_counter)
+--begin
+-- htcounter_next <= htcounter + 1;
+-- debug_trigger_counter_next <= debug_trigger_counter;
+-- if(OFF_SPILL_IN = '1') then
+-- htcounter_next <= (others => '0');
+-- debug_trigger_counter_next <= debug_trigger_counter + 1;
+-- end if;
+-- if(to_integer(unsigned(htcounter)) >= 8388608) then -- (about 8/100 seconds = 80ms)
+-- have_time_for_write_next <= '0';
+-- else
+-- have_time_for_write_next <= '1';
+-- end if;
+--end process;
+
+ALL_debugtdo : process( CLK_IN)
+begin
+ if(rising_edge(CLK_IN)) then
+ debugtdo_timeout <= debugtdo_timeout_next;
+ -- COUNTER
+ debugtdo_counter <= std_logic_vector(unsigned(debugtdo_counter) + 1);
+ -- reset counter in idle/stopped states => counter times the elapsed time since start of m26cs state machine
+ -- also clear debugtdo_active
+ if(m26cs_state = M26CSS_WAIT_FOR_TRIGGER or m26cs_state = M26CSS_STOPPED) then
+ debugtdo_counter <= (others => '0');
+ if(debugtdo_ran = '1') then
+ debugtdo_active <= '0';
+ end if;
+ debugtdo_ran <= '0';
+ else
+ debugtdo_ran <= '1';
+ end if;
+ if(debugtdo_activate_strobe = '1') then
+ debugtdo_active <= '1';
+ end if;
+
+ -- RESET
+ if(RESET_IN= '1') then
+ debugtdo_counter <= (others => '0');
+ debugtdo_active <= '0';
+ debugtdo_ran <= '0';
+ end if;
+ end if;
+end process;
+end architecture;
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+package jtag_constants is
+
+constant CMD_NONE : std_logic_vector (3 downto 0) := x"0";
+constant CMD_SELECT_DR : std_logic_vector (3 downto 0) := x"1";
+constant CMD_SELECT_IR : std_logic_vector (3 downto 0) := x"2";
+constant CMD_SHIFT_DR : std_logic_vector (3 downto 0) := x"3";
+constant CMD_SHIFT_IR : std_logic_vector (3 downto 0) := x"4";
+constant CMD_UPDATE_IR : std_logic_vector (3 downto 0) := x"5";
+constant CMD_UPDATE_DR : std_logic_vector (3 downto 0) := x"6";
+constant CMD_RESET_JTAG : std_logic_vector (3 downto 0) := x"7";
+constant CMD_READ_TDO : std_logic_vector (3 downto 0) := x"8";
+constant M26C_CMD_NONE : std_logic_vector (7 downto 0) := x"00";
+constant M26C_CMD_START : std_logic_vector (7 downto 0) := x"09";
+constant M26C_CMD_STOP : std_logic_vector (7 downto 0) := x"0A";
+constant M26C_CMD_REMOVE_SENSOR : std_logic_vector (7 downto 0) := x"10";
+constant M26C_CMD_INSERT_SENSOR : std_logic_vector (7 downto 0) := x"11";
+--constant M26C_CMD_REACTIVATE_SENSOR : std_logic_vector (7 downto 0) := x"10";
+--constant M26C_CMD_DEACTIVATE_SENSOR : std_logic_vector (7 downto 0) := x"11";
+constant M26C_CMD_GET_NUMCHIPS_CONFIGURED:std_logic_vector (7 downto 0) := x"12";
+constant M26C_CMD_GET_NUMCHIPS_ACTIVE : std_logic_vector (7 downto 0) := x"13";
+constant M26C_CMD_GET_TRIGGER_COUNT : std_logic_vector (7 downto 0) := x"14";
+--constant M26C_CMD_GET_DISABLE_WRITE : std_logic_vector (7 downto 0) := x"15";
+--constant M26C_CMD_SET_DISABLE_WRITE : std_logic_vector (7 downto 0) := x"16";
+--constant M26C_CMD_GET_DISABLE_WRITEERROR_FOR_REMOVE : std_logic_vector (7 downto 0) := x"17";
+--constant M26C_CMD_SET_DISABLE_WRITEERROR_FOR_REMOVE : std_logic_vector (7 downto 0) := x"18";
+--constant M26C_CMD_GET_DISABLE_REMOVE : std_logic_vector (7 downto 0) := x"19";
+--constant M26C_CMD_SET_DISABLE_REMOVE : std_logic_vector (7 downto 0) := x"1a";
+--constant M26C_CMD_DEBUG_ONE_REMOVE : std_logic_vector (7 downto 0) := x"1b";
+-- constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"1c";
+--constant M26C_CMD_GET_REACTIVATE_SENSOR32 : std_logic_vector (7 downto 0) := x"1d";
+--constant M26C_CMD_GET_DEACTIVATE_SENSOR32 : std_logic_vector (7 downto 0) := x"1e";
+constant M26C_CMD_GET_REMOVED : std_logic_vector (7 downto 0) := x"1d";
+constant M26C_CMD_GET_REMOVED32 : std_logic_vector (7 downto 0) := x"1e";
+constant M26C_CMD_GET_WRITE_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"20";
+constant M26C_CMD_GET_WRITE_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"21";
+constant M26C_CMD_GET_WRITE_DATA_CHANGED_COUNTER :std_logic_vector (7 downto 0) := x"22";
+constant M26C_CMD_GET_READ_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"23";
+constant M26C_CMD_GET_READ_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"24";
+constant M26C_CMD_GET_JTAG_M26_DEV_ID :std_logic_vector (7 downto 0) := x"30";
+--constant M26C_CMD_GET_NUMCHIPS : std_logic_vector (7 downto 0) := x"32";
+constant M26C_CMD_SET_NUMCHIPS_CONFIGURED : std_logic_vector (7 downto 0) := x"33";
+constant M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"40";
+constant M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"41";
+constant M26C_CMD_SET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"42";
+constant M26C_CMD_GET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"43";
+constant M26C_CMD_SET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"44";
+constant M26C_CMD_GET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"45";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"46";
+constant M26C_CMD_GET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"47";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"48";
+constant M26C_CMD_GET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"49";
+constant M26C_CMD_SET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4a";
+constant M26C_CMD_GET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4b";
+constant M26C_CMD_SET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4c";
+constant M26C_CMD_GET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4d";
+constant M26C_CMD_GET_RUN_COUNT : std_logic_vector(7 downto 0) := x"50";
+constant M26C_CMD_GET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"52";
+constant M26C_CMD_SET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"53";
+constant M26C_CMD_START_CHECK1 : std_logic_vector (7 downto 0) := x"60";
+constant M26C_CMD_COPY_TO_STATUS2 : std_logic_vector (7 downto 0) := x"63";
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER : std_logic_vector (7 downto 0) := x"64"; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR : std_logic_vector (7 downto 0) := x"6a"; --
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR : std_logic_vector (7 downto 0) := x"6b"; --
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED : std_logic_vector (7 downto 0) := x"6c"; --
+constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW : std_logic_vector (7 downto 0) := x"6d"; --
+constant M26C_CMD_SET_CSOPTIONS : std_logic_vector (7 downto 0) := x"65"; -- bit 0 => skip BYPASS CHAINTEST
+constant M26C_CMD_GET_CSOPTIONS : std_logic_vector (7 downto 0) := x"66"; -- bit 0 => skip BYPASS CHAINTEST
+constant M26C_CMD_SET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"67"; -- bits 1 downto 0 as unsigned number of TCK clocks expected values are delayed
+constant M26C_CMD_GET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"68";
+constant M26C_CMD_GET_ACTIVITY : std_logic_vector (7 downto 0) := x"69"; -- bit 0 => jtag_refresh_active, bit 1 => jtag_check1_active.
+--constant M26C_CMD_REG_GET_STATUS : std_logic_vector (3 downto 0) := x"B";
+--constant M26C_CMD_CRC_GET_STATUS : std_logic_vector (3 downto 0) := x"C";
+--constant M26C_CMD_SET_RAM_BASE_ADDR : std_logic_vector (3 downto 0) := x"D";
+
+-- 0xb100 - 0xb2ff
+-- RAM: 0xb000 - 0xb0ff
+-- Status registers: 0xb100 - 0xb11f
+-- Control registers: 0xb120 - 0xb13f
+-- Debug registers: 0xb140 - 0xb15f
+constant ADDR_RAM : std_logic_vector (15 downto 0) := x"b000";
+constant ADDR_STATUS : std_logic_vector (15 downto 0) := x"b100";
+constant ADDR_CONTROL : std_logic_vector (15 downto 0) := x"b120";
+constant ADDR_DEBUG : std_logic_vector (15 downto 0) := x"b140";
+constant ADDR_STATUS2 : std_logic_vector (15 downto 0) := x"b160";
+
+constant ADDR_CONTROL_CMD : std_logic_vector (4 downto 0) := "00000";
+constant ADDR_CONTROL_RAM_BASEADDR : std_logic_vector (4 downto 0) := "00001";
+constant ADDR_CONTROL_DATA_REGISTER : std_logic_vector (4 downto 0) := "00010";
+
+constant ADDR_DEBUG_TEST : std_logic_vector(4 downto 0) := "00000";
+constant ADDR_DEBUG_M26CS_STATE : std_logic_vector(4 downto 0) := "00001";
+constant ADDR_DEBUG_M26C_READ_STATE : std_logic_vector(4 downto 0) := "00010";
+constant ADDR_DEBUG_M26C_WRITE_STATE : std_logic_vector(4 downto 0) := "00011";
+constant ADDR_DEBUG_JTAG_DRIVER_STATE : std_logic_vector(4 downto 0) := "00100";
+constant ADDR_DEBUG_TRIGGER_COUNT : std_logic_vector(4 downto 0) := "00101";
+constant ADDR_DEBUG_VERSION : std_logic_vector(4 downto 0) := "00110";
+constant ADDR_DEBUG_RAM1BADDR : std_logic_vector(4 downto 0) := "00111";
+constant ADDR_DEBUG_RAM1B_DATA : std_logic_vector(4 downto 0) := "01000";
+constant ADDR_DEBUG_RAM1CADDR : std_logic_vector(4 downto 0) := "01001";
+constant ADDR_DEBUG_RAM1C_DATA : std_logic_vector(4 downto 0) := "01010";
+constant ADDR_DEBUG_RAM1C_RUN_COUNTER : std_logic_vector(4 downto 0) := "01011";
+constant ADDR_DEBUG_RAM1C_CHAIN_STATUS : std_logic_vector(4 downto 0) := "01100";
+constant ADDR_DEBUG_DEBUGTDO_SAMPLES : std_logic_vector(4 downto 0) := "01101";
+constant ADDR_DEBUG_DEBUGTDO_GETFIFOSTATUS : std_logic_vector(4 downto 0) := "01110";
+constant ADDR_DEBUG_DEBUGTDO_TIMEOUT : std_logic_vector(4 downto 0) := "01111";
+constant ADDR_DEBUG_DEBUGTDO_ACTIVATE : std_logic_vector(4 downto 0) := "10000";
+constant ADDR_DEBUG_DEBUGTDO_CONTROLFIFO : std_logic_vector(4 downto 0) := "10001";
+constant ADDR_DEBUG_WRONCE_COUNT : std_logic_vector(4 downto 0) := "10010";
+
+
+constant ADDR_STATUS_VERSION : std_logic_vector(4 downto 0) := "00110";
+
+constant ADDR_STATUS2_TRIGGERCOUNTER_COPY : std_logic_vector(4 downto 0) := "00000";
+constant ADDR_STATUS2_CHAIN_STATUS_COPY : std_logic_vector(4 downto 0) := "00001";
+constant ADDR_STATUS2_UPDATING : std_logic_vector(4 downto 0) := "00010";
+constant ADDR_STATUS2_RAM3B_BASEADDR : std_logic_vector(4 downto 0) := "00011";
+constant ADDR_STATUS2_STARTED : std_logic_vector(4 downto 0) := "00100";
+constant ADDR_STATUS2_RAM3B_BEGIN : std_logic_vector(4 downto 0) := "10000"; -- lower 4 bits used as address into ram3b from baseaddr
+
+
+
+--constant ADDR_DATA : std_logic_vector (8 downto 0) := "000000001";
+--constant ADDR_LENGTH : std_logic_vector (8 downto 0) := "000000010";
+
+
+constant STATUS_OK : std_logic_vector (15 downto 0) := x"0000";
+constant STATUS_INVALID_COMMAND : std_logic_vector (15 downto 0) := x"FFFF";
+
+-- constraint: MAX_NUMCHIPS can be at most 2**MAX_NUMCHIPS_LD
+-- if MAX_NUMCHIPS is 2^n-1 then the number of chips can be stored in n bits, thats the reason to choose this odd max. number
+
+constant COUNTER_WIDTHS : integer := 16; -- width of counters for jtag_cmd_m26c entity port, must be static.
+
+end package jtag_constants;
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+use work.jtag_constants.all;\r
+\r
+entity jtag_delay_expected_values is\r
+ generic (\r
+-- delay : integer := 0 -- number of whole jtag clock cycles to delay the expected values\r
+-- -- because of total distance of the tck-line to the last chip and\r
+-- -- the length of tdo of this chip back to the fpga\r
+ ld_maxdelay : integer := 2; -- floor of ld maxdelay\r
+ MAX_NUMCHIPS_LD : integer;\r
+ MAX_REGISTERS_PLUS_ONE_LD : integer\r
+ );\r
+ port (\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SAMPLE_PULSE1_IN : in std_logic;\r
+ \r
+ -- chipcount as unsigned\r
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);\r
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10\r
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);\r
+ \r
+ IS_DR_BIT_IN : in std_logic;\r
+ -- firstbit signal: reset counters before sampling this bit\r
+ IS_FIRSTBIT_IN : in std_logic;\r
+ -- finish signal: dataout => RAM1b, compareout => RAM2\r
+ IS_LASTBIT_IN : in std_logic;\r
+ \r
+ TDO_EXPECTED_IN : in std_logic;\r
+ \r
+ \r
+ -- chipcount as unsigned\r
+ OUT_CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);\r
+ -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10\r
+ OUT_REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);\r
+ \r
+ OUT_IS_DR_BIT_OUT : out std_logic;\r
+ -- firstbit signal: reset counters before sampling this bit\r
+ OUT_IS_FIRSTBIT_OUT : out std_logic;\r
+ -- finish signal: dataout => RAM1b, compareout => RAM2\r
+ OUT_IS_LASTBIT_OUT : out std_logic;\r
+ \r
+ OUT_TDO_EXPECTED_OUT : out std_logic;\r
+\r
+ DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0)\r
+\r
+\r
+ \r
+ );\r
+end entity;\r
+architecture jtag_delay_expected_values_arch of jtag_delay_expected_values is\r
+type REGNUM_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);\r
+ signal regnum_buf, regnum_buf_next : REGNUM_BUF_TYPE;\r
+type CHIPNUM_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);\r
+ signal chipnum_buf, chipnum_buf_next : CHIPNUM_BUF_TYPE;\r
+type STD_LOGIC_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic;\r
+ signal is_dr_bit_buf, is_dr_bit_buf_next : STD_LOGIC_BUF_TYPE;\r
+ signal is_firstbit_buf, is_firstbit_buf_next : STD_LOGIC_BUF_TYPE;\r
+ signal is_lastbit_buf, is_lastbit_buf_next : STD_LOGIC_BUF_TYPE;\r
+ signal tdo_expected_buf, tdo_expected_buf_next : STD_LOGIC_BUF_TYPE;\r
+begin\r
+OUT_CHIPNUM_OUT <= chipnum_buf(to_integer(unsigned(DELAY_IN)));\r
+OUT_REGNUM_OUT <= regnum_buf(to_integer(unsigned(DELAY_IN)));\r
+OUT_IS_DR_BIT_OUT <= is_dr_bit_buf(to_integer(unsigned(DELAY_IN)));\r
+OUT_IS_FIRSTBIT_OUT <= is_firstbit_buf(to_integer(unsigned(DELAY_IN)));\r
+OUT_IS_LASTBIT_OUT <= is_lastbit_buf(to_integer(unsigned(DELAY_IN)));\r
+OUT_TDO_EXPECTED_OUT <= tdo_expected_buf(to_integer(unsigned(DELAY_IN)));\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ is_dr_bit_buf <= (others => '0');\r
+ is_firstbit_buf <= (others => '0');\r
+ is_lastbit_buf <= (others => '0');\r
+ tdo_expected_buf <= (others => '0'); \r
+ regnum_buf <= (others => (others => '0'));\r
+ chipnum_buf <= (others => (others => '0')); \r
+ else\r
+ is_dr_bit_buf <= is_dr_bit_buf_next;\r
+ is_firstbit_buf <= is_firstbit_buf_next;\r
+ is_lastbit_buf <= is_lastbit_buf_next;\r
+ tdo_expected_buf <= tdo_expected_buf_next; \r
+ regnum_buf <= regnum_buf_next;\r
+ chipnum_buf <= chipnum_buf_next;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(SAMPLE_PULSE1_IN, IS_LASTBIT_IN, IS_DR_BIT_IN, IS_FIRSTBIT_IN, TDO_EXPECTED_IN, REGNUM_IN, CHIPNUM_IN, is_lastbit_buf, is_dr_bit_buf, is_firstbit_buf, tdo_expected_buf, regnum_buf, chipnum_buf)\r
+begin\r
+ is_lastbit_buf_next <= is_lastbit_buf;\r
+ is_dr_bit_buf_next <= is_dr_bit_buf;\r
+ is_firstbit_buf_next <= is_firstbit_buf;\r
+ tdo_expected_buf_next <= tdo_expected_buf;\r
+ regnum_buf_next <= regnum_buf;\r
+ chipnum_buf_next <= chipnum_buf;\r
+ -- shift registers\r
+ if(SAMPLE_PULSE1_IN = '1') then\r
+ if(2**ld_maxdelay-1 >= 1) then\r
+ is_lastbit_buf_next(2**ld_maxdelay-1 downto 1) <= is_lastbit_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ is_dr_bit_buf_next(2**ld_maxdelay-1 downto 1) <= is_dr_bit_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ is_firstbit_buf_next(2**ld_maxdelay-1 downto 1) <= is_firstbit_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ tdo_expected_buf_next(2**ld_maxdelay-1 downto 1) <= tdo_expected_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ regnum_buf_next(2**ld_maxdelay-1 downto 1) <= regnum_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ chipnum_buf_next(2**ld_maxdelay-1 downto 1) <= chipnum_buf(2**ld_maxdelay-1 -1 downto 0);\r
+ end if;\r
+ is_lastbit_buf_next(0) <= IS_LASTBIT_IN;\r
+ is_dr_bit_buf_next(0) <= IS_DR_BIT_IN;\r
+ is_firstbit_buf_next(0) <= IS_FIRSTBIT_IN;\r
+ tdo_expected_buf_next(0) <= TDO_EXPECTED_IN;\r
+ regnum_buf_next(0) <= REGNUM_IN;\r
+ chipnum_buf_next(0) <= CHIPNUM_IN;\r
+ end if;\r
+end process;\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+\r
+use work.jtag_constants.all;\r
+use work.jtag_misc.all;\r
+\r
+entity jtag_init_ram1b is\r
+ generic (\r
+ RAM_JTAG_REGISTERS_DEPTH : integer;\r
+ MAX_NUMCHIPS_LD : integer;\r
+ MAX_REGISTERS_LD : integer\r
+ );\r
+ port (\r
+ CLK_IN : std_logic;\r
+ RESET_IN : std_logic;\r
+ TRIGGER_INIT_IN : std_logic;\r
+ -- RAM1a\r
+ RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ RAM1A_D_IN : in std_logic_vector(31 downto 0);\r
+ -- RAM1b\r
+ RAM1B_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ RAM1B_D_IN : in std_logic_vector(31 downto 0);\r
+ RAM1B_WE_OUT : out std_logic;\r
+ RAM1B_D_OUT : out std_logic_vector(31 downto 0);\r
+ \r
+ IDLE_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture jtag_init_ram1b_arch of jtag_init_ram1b is\r
+type state_type is (idle, read_numregs0, read_numregs1, write_i, nextchip);\r
+signal state, state_next : state_type;\r
+signal wordcounter, wordcounter_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0);\r
+signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);\r
+constant chipcounter_end : unsigned(MAX_NUMCHIPS_LD-1 downto 0) := (others => '1');\r
+signal ram1a_a, ram1a_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0);\r
+signal ram1b_a, ram1b_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0);\r
+signal ram1b_data, ram1b_data_next : std_logic_vector(31 downto 0);\r
+signal ram1b_we, ram1b_we_next : std_logic;\r
+signal numregs, numregs_next : unsigned(MAX_REGISTERS_LD-1 downto 0);\r
+constant wordcounter_end : unsigned(RAM_JTAG_REGISTERS_DEPTH-1 downto 0) := (others => '1'); -- this should be a constant\r
+begin\r
+--wordcounter_end <= (others => '1'); -- maximum RAM address\r
+IDLE_OUT <= '1' when state = idle else '0';\r
+RAM1A_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD+1) <= std_logic_vector(chipcounter);\r
+RAM1A_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0) <= ram1a_a;\r
+RAM1B_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD+1) <= std_logic_vector(chipcounter);\r
+RAM1B_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0) <= ram1b_a;\r
+RAM1B_WE_OUT <= ram1b_we;\r
+RAM1B_D_OUT <= ram1b_data;\r
+SYNCHRONOUS: process(CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ state <= idle;\r
+ ram1a_a <= (others => '0');\r
+ ram1b_a <= (others => '0');\r
+ ram1b_data <= (others => '0');\r
+ ram1b_we <= '0';\r
+ wordcounter <= (others => '0');\r
+ chipcounter <= (others => '0');\r
+ numregs <= (others => '0');\r
+ else\r
+ state <= state_next;\r
+ ram1a_a <= ram1a_a_next;\r
+ ram1b_a <= ram1b_a_next;\r
+ ram1b_data <= ram1b_data_next; \r
+ ram1b_we <= ram1b_we_next; \r
+ wordcounter <= wordcounter_next;\r
+ chipcounter <= chipcounter_next;\r
+ numregs <= numregs_next;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB: process (state, TRIGGER_INIT_IN, RAM1A_D_IN, numregs, ram1a_a, ram1b_a, ram1b_data, wordcounter, chipcounter )\r
+begin\r
+ ram1a_a_next <= ram1a_a;\r
+ ram1b_a_next <= ram1b_a;\r
+ ram1b_data_next <= ram1b_data;\r
+ state_next <= state;\r
+ wordcounter_next <= wordcounter;\r
+ chipcounter_next <= chipcounter;\r
+ ram1b_we_next <= '0';\r
+ numregs_next <= numregs;\r
+ \r
+ case state is\r
+ when IDLE =>\r
+ if(TRIGGER_INIT_IN = '1') then\r
+ chipcounter_next <= (others => '0');\r
+ ram1a_a_next <= (others => '0'); -- numregs\r
+ state_next <= READ_NUMREGS0;\r
+ end if;\r
+ when READ_NUMREGS0 =>\r
+ ram1a_a_next <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 1\r
+ state_next <= READ_NUMREGS1;\r
+ when READ_NUMREGS1 =>\r
+ ram1a_a_next <= std_logic_vector(to_unsigned(2,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 2\r
+ numregs_next <= unsigned(RAM1A_D_IN(MAX_REGISTERS_LD-1 downto 0));\r
+ wordcounter_next <= to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD); -- which word to write in next step\r
+ -- write word to RAM1b\r
+ ram1b_a_next <= (others => '0'); -- numregs\r
+ ram1b_data_next <= RAM1A_D_IN;\r
+ ram1b_we_next <= '1';\r
+ state_next <= WRITE_I;\r
+ when WRITE_I =>\r
+ wordcounter_next <= wordcounter + 1;\r
+ ram1b_a_next <= std_logic_vector(wordcounter);\r
+ ram1b_we_next <= '1';\r
+ -- the following block guarantees that the DEV_ID at wordcounter=1 in ram1a is not copied to ram1b \r
+ if(wordcounter < 2*numregs+2) then \r
+ ram1a_a_next <= std_logic_vector(to_unsigned(to_integer(wordcounter)+2,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- might need next word\r
+ if(to_integer(wordcounter) = 1) then\r
+ -- write zeros to reserved (for DEV_ID)\r
+ ram1b_data_next <= (others => '0');\r
+ else\r
+ -- write Ptr/Length fields to RAM1b\r
+ ram1b_data_next <= RAM1A_D_IN;\r
+ end if;\r
+ else\r
+ -- blank rest of RAM\r
+ ram1b_data_next <= (others => '0'); \r
+ end if;\r
+ if(std_logic_vector_all_components_equal_scalar(std_logic_vector(wordcounter), '1') = '1') then\r
+ state_next <= NEXTCHIP;\r
+ end if;\r
+ when NEXTCHIP =>\r
+ if(chipcounter /= chipcounter_end) then\r
+ chipcounter_next <= chipcounter + 1;\r
+ ram1a_a_next <= (others => '0'); -- numregs \r
+ state_next <= READ_NUMREGS0;\r
+ else\r
+ state_next <= IDLE;\r
+ end if;\r
+ end case;\r
+end process;\r
+\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+library work;
+
+package jtag_misc is
+ function MYMIN(x : integer; y : integer) return integer;
+ function std_logic_vector_scalar_compare(vect: std_logic_vector; scalar : std_logic) return std_logic_vector;
+ function std_logic_vector_all_components_equal_scalar(vect: std_logic_vector; scalar : std_logic) return std_logic;
+end package jtag_misc;
+
+package body jtag_misc is
+
+function MYMIN(x : integer; y : integer)
+ return integer is
+ begin
+ if x > y then
+ return y;
+ else
+ return x;
+ end if;
+ end MYMIN;
+
+function std_logic_vector_scalar_compare(vect: std_logic_vector; scalar : std_logic) return std_logic_vector is
+variable output : std_logic_vector(vect'range);
+variable i : integer;
+begin
+ for i in vect'range loop
+ if(vect(i) = scalar) then
+ output(i) := '1';
+ else
+ output(i) := '0';
+ end if;
+ end loop;
+ return output;
+end std_logic_vector_scalar_compare;
+
+function std_logic_vector_all_components_equal_scalar(vect: std_logic_vector; scalar : std_logic) return std_logic is
+variable output : std_logic;
+variable i : integer;
+begin
+ output := '1';
+ for i in vect'range loop
+ if(vect(i) /= scalar) then
+ output := '0';
+ end if;
+ end loop;
+ return output;
+end std_logic_vector_all_components_equal_scalar;
+end package body jtag_misc;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+--use work.version.all;
+use work.jtag_constants.all;
+-- this entity is a multiplexer, based on which *_ENABLE_JTAG_CLOCK_IN signal is '1' on a pulse on JTAG_SET_DATA_IN, it loads the corresponding input values for TMS, TDI, IS_DR_BIT, ... into the buffers
+entity jtag_mux_buffer_tms_tdi_out_and_metainfo is
+ generic (
+ MAX_NUMCHIPS_LD : integer;
+ MAX_REGISTERS_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- pulse when READ/WRITE/... entity's data should be taken and update
+ -- the output values for TMS,TDI
+ JTAG_SET_DATA_IN : in std_logic;
+
+ -- read DEV_ID inputs
+ RD_TMS_IN : in std_logic;
+ RD_TDI_IN : in std_logic;
+ RD_IS_DR_BIT_IN: in std_logic;
+ RD_IS_FIRSTBIT_IN : in std_logic;
+ RD_IS_LASTBIT_IN : in std_logic;
+ RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ RD_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ RD_LAST_TCK_CYCLE_IN : in std_logic;
+ RD_EXPECTED_TDO_OUT : in std_logic;
+
+ -- write registers inputs
+ WR_TMS_IN : in std_logic;
+ WR_TDI_IN : in std_logic;
+ WR_IS_DR_BIT_IN: in std_logic;
+ WR_IS_FIRSTBIT_IN : in std_logic;
+ WR_IS_LASTBIT_IN : in std_logic;
+ WR_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ WR_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ WR_LAST_TCK_CYCLE_IN : in std_logic;
+ WR_EXPECTED_TDO_OUT : in std_logic;
+
+ -- test chain inputs
+ TC_TMS_IN : in std_logic;
+ TC_TDI_IN : in std_logic;
+ TC_ENABLE_JTAG_CLOCK_IN : in std_logic;
+ TC_LAST_TCK_CYCLE_IN : in std_logic;
+
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ IS_DR_BIT_OUT: out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic
+ );
+end entity;
+
+architecture jtag_mux_buffer_tms_tdi_out_and_metainfo_arch of jtag_mux_buffer_tms_tdi_out_and_metainfo is
+-- buffers
+signal tms, tms_next : std_logic;
+signal tdi, tdi_next : std_logic;
+signal is_dr_bit, is_dr_bit_next : std_logic;
+signal is_firstbit, is_firstbit_next : std_logic;
+signal is_lastbit, is_lastbit_next : std_logic;
+signal chipnum, chipnum_next : unsigned (MAX_NUMCHIPS_LD-1 downto 0);
+signal regnum, regnum_next : unsigned (MAX_REGISTERS_LD-1 downto 0);
+
+signal enable_jtag_clock, enable_jtag_clock_next : std_logic;
+signal last_tck_cycle, last_tck_cycle_next : std_logic;
+signal expected_tdo, expected_tdo_next : std_logic;
+-- INSERTLABEL: signals
+begin
+TMS_OUT <= tms;
+TDI_OUT <= tdi;
+IS_DR_BIT_OUT <= is_dr_bit;
+IS_FIRSTBIT_OUT <= is_firstbit;
+IS_LASTBIT_OUT <= is_lastbit;
+CHIPNUM_OUT <= std_logic_vector(chipnum);
+REGNUM_OUT <= std_logic_vector(regnum);
+ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock;
+LAST_TCK_CYCLE_OUT <= last_tck_cycle;
+EXPECTED_TDO_OUT <= expected_tdo;
+SYNCHRONOUS_MAIN: process(CLK_IN)
+begin
+ if(rising_edge(CLK_IN)) then
+ if(RESET_IN='1') then
+ tms <= '1';
+ tdi <= '0';
+ is_dr_bit <= '0';
+ is_firstbit <= '0';
+ is_lastbit <= '0';
+ chipnum <= (others => '0');
+ regnum <= (others => '0');
+ enable_jtag_clock <= '0';
+ last_tck_cycle <= '0';
+ expected_tdo <= '0';
+ -- INSERTLABEL: SYNCHRONOUS reset
+ else
+ tms <= tms_next;
+ tdi <= tdi_next;
+ is_dr_bit <= is_dr_bit_next;
+ is_firstbit <= is_firstbit_next;
+ is_lastbit <= is_lastbit_next;
+ chipnum <= chipnum_next;
+ regnum <= regnum_next;
+ enable_jtag_clock <= enable_jtag_clock_next;
+ last_tck_cycle <= last_tck_cycle_next;
+ expected_tdo <= expected_tdo_next;
+ -- INSERTLABEL: SYNCHRONOUS update
+ end if;
+ end if;
+end process;
+
+COMB_MAIN: process(JTAG_SET_DATA_IN, RD_ENABLE_JTAG_CLOCK_IN, WR_ENABLE_JTAG_CLOCK_IN, TC_ENABLE_JTAG_CLOCK_IN, RD_TMS_IN, RD_TDI_IN, RD_IS_DR_BIT_IN, RD_IS_FIRSTBIT_IN, RD_IS_LASTBIT_IN, RD_CHIPNUM_IN, RD_LAST_TCK_CYCLE_IN, RD_EXPECTED_TDO_OUT, WR_TMS_IN, WR_TDI_IN, WR_IS_DR_BIT_IN, WR_IS_FIRSTBIT_IN, WR_IS_LASTBIT_IN, WR_CHIPNUM_IN, WR_REGNUM_IN, WR_LAST_TCK_CYCLE_IN, WR_EXPECTED_TDO_OUT, TC_TMS_IN, TC_TDI_IN, TC_LAST_TCK_CYCLE_IN, tdi, tms,is_dr_bit,is_firstbit,is_lastbit,chipnum,regnum,enable_jtag_clock,last_tck_cycle,expected_tdo) -- INSERTLABEL: sensitivity list
+begin
+ tms_next <= tms;
+ tdi_next <= tdi;
+ is_dr_bit_next <= is_dr_bit;
+ is_firstbit_next <= is_firstbit;
+ is_lastbit_next <= is_lastbit;
+ chipnum_next <= chipnum;
+ regnum_next <= regnum;
+ enable_jtag_clock_next <= enable_jtag_clock;
+ last_tck_cycle_next <= last_tck_cycle;
+ expected_tdo_next <= expected_tdo;
+ -- INSERTLABEL: COMB defaults
+ if(JTAG_SET_DATA_IN = '1') then
+ if(RD_ENABLE_JTAG_CLOCK_IN = '1') then
+ tms_next <= RD_TMS_IN;
+ tdi_next <= RD_TDI_IN;
+ is_dr_bit_next <= RD_IS_DR_BIT_IN;
+ is_firstbit_next <= RD_IS_FIRSTBIT_IN;
+ is_lastbit_next <= RD_IS_LASTBIT_IN;
+ chipnum_next <= unsigned(RD_CHIPNUM_IN);
+ -- read dev_id is treated as register 0
+ regnum_next <= (others => '0');
+ enable_jtag_clock_next <= RD_ENABLE_JTAG_CLOCK_IN;
+ last_tck_cycle_next <= RD_LAST_TCK_CYCLE_IN;
+ expected_tdo_next <= RD_EXPECTED_TDO_OUT;
+ elsif(WR_ENABLE_JTAG_CLOCK_IN = '1') then
+ tms_next <= WR_TMS_IN;
+ tdi_next <= WR_TDI_IN;
+ is_dr_bit_next <= WR_IS_DR_BIT_IN;
+ is_firstbit_next <= WR_IS_FIRSTBIT_IN;
+ is_lastbit_next <= WR_IS_LASTBIT_IN;
+ chipnum_next <= unsigned(WR_CHIPNUM_IN);
+ -- read dev_id is stored as register 0, the write registers are stored as WR_REGNUM+1
+ regnum_next <= unsigned(WR_REGNUM_IN) + 1;
+ enable_jtag_clock_next <= WR_ENABLE_JTAG_CLOCK_IN;
+ last_tck_cycle_next <= WR_LAST_TCK_CYCLE_IN;
+ expected_tdo_next <= WR_EXPECTED_TDO_OUT;
+ elsif(TC_ENABLE_JTAG_CLOCK_IN = '1') then
+ tms_next <= TC_TMS_IN;
+ tdi_next <= TC_TDI_IN;
+ is_dr_bit_next <= '0';
+ is_firstbit_next <= '0';
+ is_lastbit_next <= '0';
+ chipnum_next <= (others =>'0');
+ regnum_next <= (others =>'0');
+ enable_jtag_clock_next <= TC_ENABLE_JTAG_CLOCK_IN;
+ last_tck_cycle_next <= TC_LAST_TCK_CYCLE_IN;
+ expected_tdo_next <= '0';
+ else
+ tms_next <= '1';
+ tdi_next <= '0';
+ is_dr_bit_next <= '0';
+ is_firstbit_next <= '0';
+ is_lastbit_next <= '0';
+ chipnum_next <= (others =>'0');
+ regnum_next <= (others =>'0');
+ enable_jtag_clock_next <= '0';
+ last_tck_cycle_next <= '0';
+ expected_tdo_next <= '0';
+ end if;
+ end if;
+end process;
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+library work;
+
+use work.jtag_constants.all;
+use work.jtag_misc.all;
+
+entity jtag_pulses is
+ generic (
+ time_bits : integer := 10
+ );
+ port (
+ CLK_IN : std_logic;
+ RESET_IN : std_logic;
+ -- input times
+ JTAG_CLOCK_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_CLOCK_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SAMPLE_TIME3_IN: in std_logic_vector(time_bits -1 downto 0);
+ JTAG_SET_DATA_TIME_IN: in std_logic_vector(time_bits -1 downto 0);
+
+ JTAG_CLOCK_CYCLE_LENGTH_IN: in std_logic_vector(time_bits -1 downto 0);
+
+ -- output pulses
+ BEGIN_JTAGBITCALC_OUT : out std_logic;
+ JTAG_CLOCK_PULSE1_OUT : out std_logic;
+ JTAG_CLOCK_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE1_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE2_OUT : out std_logic;
+ JTAG_SAMPLE_PULSE3_OUT : out std_logic;
+ JTAG_SET_DATA_PULSE_OUT : out std_logic
+
+ );
+end entity;
+
+architecture jtag_pulses_arch of jtag_pulses is
+signal jtag_counter, jtag_counter_next : unsigned(time_bits-1 downto 0);
+signal begin_jtagbitcalc, begin_jtagbitcalc_next : std_logic;
+signal jtag_clock_pulse1, jtag_clock_pulse1_next : std_logic;
+signal jtag_clock_pulse2, jtag_clock_pulse2_next : std_logic;
+signal jtag_sample_pulse1, jtag_sample_pulse1_next : std_logic;
+signal jtag_sample_pulse2, jtag_sample_pulse2_next : std_logic;
+signal jtag_sample_pulse3, jtag_sample_pulse3_next : std_logic;
+signal jtag_set_data_pulse, jtag_set_data_pulse_next : std_logic;
+begin
+--wordcounter_end <= (others => '1'); -- maximum RAM address
+ BEGIN_JTAGBITCALC_OUT <= begin_jtagbitcalc;
+ JTAG_CLOCK_PULSE1_OUT <= jtag_clock_pulse1;
+ JTAG_CLOCK_PULSE2_OUT <= jtag_clock_pulse2;
+ JTAG_SAMPLE_PULSE1_OUT <= jtag_sample_pulse1;
+ JTAG_SAMPLE_PULSE2_OUT <= jtag_sample_pulse2;
+ JTAG_SAMPLE_PULSE3_OUT <= jtag_sample_pulse3;
+ JTAG_SET_DATA_PULSE_OUT <= jtag_set_data_pulse;
+SYNCHRONOUS: process(CLK_IN, RESET_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ begin_jtagbitcalc <= '0';
+ jtag_clock_pulse1 <= '0';
+ jtag_clock_pulse2 <= '0';
+ jtag_sample_pulse1 <= '0';
+ jtag_sample_pulse2 <= '0';
+ jtag_sample_pulse3 <= '0';
+ jtag_set_data_pulse <= '0';
+ jtag_counter <= (others => '0');
+ else
+ begin_jtagbitcalc <= begin_jtagbitcalc_next;
+ jtag_clock_pulse1 <= jtag_clock_pulse1_next;
+ jtag_clock_pulse2 <= jtag_clock_pulse2_next;
+ jtag_sample_pulse1 <= jtag_sample_pulse1_next;
+ jtag_sample_pulse2 <= jtag_sample_pulse2_next;
+ jtag_sample_pulse3 <= jtag_sample_pulse3_next;
+ jtag_set_data_pulse <= jtag_set_data_pulse_next;
+ jtag_counter <= jtag_counter_next;
+ end if;
+ end if;
+end process;
+
+
+
+COMB: process (jtag_counter, JTAG_CLOCK_CYCLE_LENGTH_IN, JTAG_CLOCK_TIME1_IN, JTAG_CLOCK_TIME2_IN, JTAG_SAMPLE_TIME1_IN, JTAG_SAMPLE_TIME2_IN, JTAG_SAMPLE_TIME3_IN, JTAG_SET_DATA_TIME_IN )
+begin
+jtag_counter_next <= jtag_counter + 1;
+begin_jtagbitcalc_next <= '0';
+jtag_clock_pulse1_next <= '0';
+jtag_clock_pulse2_next <= '0';
+jtag_sample_pulse1_next <= '0';
+jtag_sample_pulse2_next <= '0';
+jtag_sample_pulse3_next <= '0';
+jtag_set_data_pulse_next <= '0';
+ if(jtag_counter = unsigned(JTAG_CLOCK_CYCLE_LENGTH_IN)-1) then
+ begin_jtagbitcalc_next <= '1';
+ jtag_counter_next <= (others => '0'); -- reset counter
+ end if;
+
+ if(jtag_counter = unsigned(JTAG_CLOCK_TIME1_IN)) then
+ jtag_clock_pulse1_next <= '1';
+ end if;
+ if(jtag_counter = unsigned(JTAG_CLOCK_TIME2_IN)) then
+ jtag_clock_pulse2_next <= '1';
+ end if;
+ if(jtag_counter = unsigned(JTAG_SAMPLE_TIME1_IN)) then
+ jtag_sample_pulse1_next <= '1';
+ end if;
+ if(jtag_counter = unsigned(JTAG_SAMPLE_TIME2_IN)) then
+ jtag_sample_pulse2_next <= '1';
+ end if;
+ if(jtag_counter = unsigned(JTAG_SAMPLE_TIME3_IN)) then
+ jtag_sample_pulse3_next <= '1';
+ end if;
+ if(jtag_counter = unsigned(JTAG_SET_DATA_TIME_IN)) then
+ jtag_set_data_pulse_next <= '1';
+ end if;
+end process;
+
+
+end architecture;
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+use work.jtag_misc.all;\r
+\r
+entity jtag_read_m26devid_m10 is\r
+ generic (\r
+ RAM_JTAG_REGISTERS_DEPTH : integer;\r
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;\r
+ MAX_NUMCHIPS : integer;\r
+ MAX_NUMCHIPS_LD : integer\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);\r
+\r
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is\r
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD) \r
+ -- which should be interpreted as unsigned\r
+ -- the zero'th entry points to the first not removed chip\r
+ -- a value of (others => '1') means that no more non-removed chips follow\r
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);\r
+ \r
+ BEGIN_JTAGBITCALC_IN : in std_logic;\r
+ TRIGGER_BEGIN_READ_IN : in std_logic;\r
+ \r
+\r
+ \r
+ IS_DR_BIT_OUT : out std_logic;\r
+ IS_FIRSTBIT_OUT : out std_logic;\r
+ IS_LASTBIT_OUT : out std_logic;\r
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);\r
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;\r
+ LAST_TCK_CYCLE_OUT : out std_logic;\r
+ TMS_OUT : out std_logic;\r
+ TDI_OUT : out std_logic;\r
+ EXPECTED_TDO_OUT : out std_logic;\r
+ IDLE_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+\r
+architecture jtag_read_m26devid_m10_arch of jtag_read_m26devid_m10 is\r
+-- 32 bit dev_id\r
+signal bitcounter, bitcounter_next : unsigned(5-1 downto 0);\r
+\r
+-- COPIED FROM jtag_write_m10:\r
+-- this state controls the global behaviour. on reset state idle is entered,\r
+-- on trigger wait_begin_jtagbitcalc is entered\r
+-- when begin_jtagbitcalc is set, state becomes either idle or \r
+-- processing and after finished wait_begin_jtagbitcalc is entered again\r
+type state_type is (idle, wait_begin_jtagbitcalc, processing);\r
+signal state, state_next : state_type;\r
+-- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz.\r
+type substate_type is (none_p1, dr_read_p1 ,dr_read_p2, dr_read_p3, dr_read_p4);\r
+signal substate, substate_next : substate_type;\r
+-- COPIED FROM jtag_write_m10:\r
+-- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": SCAN_DR, operation = "11": none\r
+-- the operation is set on entering processing state, in setup operation is set to none\r
+signal operation, operation_next : unsigned(1 downto 0);\r
+-- COPIED FROM jtag_write_m10, modified\r
+-- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset\r
+-- operation_phase = 0110 : set TMS=0 => Run-Test/Idle\r
+-- WRITE_IR: this state should never be reached\r
+-- SCAN_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan\r
+-- operation_phase = 0001 : set TMS=0 => Capture-DR\r
+-- operation_phase = 0010 : set TMS=0 => Shift-DR\r
+-- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, \r
+-- operation_phase = 0100 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED\r
+-- operation_phase = 0101 : set TMS=1 => Update-DR\r
+-- operation_phase = 0110 : set TMS=0 => Run-Test/Idle\r
+-- warning: operation phase may change during processing (because length of register is retrieved from RAM)\r
+-- but will settle from setOutputs_p8 on\r
+signal operation_phase, operation_phase_next : unsigned(3 downto 0);\r
+\r
+\r
+-- other signals\r
+signal last_tck_cycle, last_tck_cycle_next : std_logic;\r
+signal chipcounter, chipcounter_next : unsigned (MAX_NUMCHIPS_LD-1 downto 0);\r
+-- should a JTAG clock pulse be generated this global_jtag_counter cycle?\r
+signal enable_jtag_clock, enable_jtag_clock_next : std_logic; \r
+-- JTAG output signal: TDI\r
+signal tdi, tdi_next : std_logic;\r
+\r
+-- JTAG output signal: TMS\r
+signal tms, tms_next : std_logic;\r
+\r
+signal is_dr_bit, is_dr_bit_next : std_logic;\r
+signal is_firstbit, is_firstbit_next : std_logic;\r
+signal is_lastbit, is_lastbit_next : std_logic;\r
+signal expected_tdo, expected_tdo_next : std_logic;\r
+\r
+signal ram_jtag_registers_a, ram_jtag_registers_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+-- the correct slice from NEXT_NOT_REMOVED_IN, depending on the current value of chipcounter\r
+signal nxt_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); \r
+signal first_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);\r
+constant invalid_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) := (others => '1');\r
+signal dev_id, dev_id_next : std_logic_vector(31 downto 0);\r
+-- INSERTLABEL: signals\r
+begin\r
+-- helper signals\r
+--tmp_input_vect <= (others => input_bit); -- doesn't work\r
+IDLE_OUT <= '1' when state = idle else '0';\r
+ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock;\r
+LAST_TCK_CYCLE_OUT <= last_tck_cycle;\r
+TMS_OUT <= tms;\r
+TDI_OUT <= tdi;\r
+IS_DR_BIT_OUT <= '1' when operation = "10" and (operation_phase = "0011" or operation_phase = "0100") else '0';\r
+IS_FIRSTBIT_OUT <= '1' when to_integer(bitcounter) = 0 else '0';\r
+IS_LASTBIT_OUT <= '1' when to_integer(bitcounter)+1 = 32 else '0';\r
+CHIPNUM_OUT <= std_logic_vector(chipcounter);\r
+EXPECTED_TDO_OUT <= expected_tdo;\r
+RAM_JTAG_REGISTERS_A_OUT <= ram_jtag_registers_a;\r
+nxt_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN((to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD)); -- first entry points to first not removed chip\r
+first_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN(MAX_NUMCHIPS_PLUS_ONE_LD - 1 downto 0));\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ bitcounter <= (others =>'0');\r
+ chipcounter <= (others =>'0');\r
+ last_tck_cycle <= '0';\r
+ state <= idle;\r
+ substate <= none_p1; \r
+ enable_jtag_clock <= '0';\r
+ tdi <= '0';\r
+ tms <= '0'; \r
+ operation <= "11";\r
+ operation_phase <= "0000";\r
+ is_dr_bit <= '0';\r
+ is_firstbit <= '0';\r
+ is_lastbit <= '0';\r
+ expected_tdo <= '0';\r
+ ram_jtag_registers_a <= (others => '0');\r
+ dev_id <= (others => '0');\r
+ -- INSERTLABEL: SYNCHRONOUS reset\r
+ else\r
+ bitcounter <= bitcounter_next;\r
+ chipcounter <= chipcounter_next;\r
+ last_tck_cycle <= last_tck_cycle_next;\r
+ state <= state_next;\r
+ substate <= substate_next; \r
+ enable_jtag_clock <= enable_jtag_clock_next;\r
+ tdi <= tdi_next;\r
+ tms <= tms_next;\r
+ operation <= operation_next;\r
+ operation_phase <= operation_phase_next;\r
+ is_dr_bit <= is_dr_bit_next;\r
+ is_firstbit <= is_firstbit_next;\r
+ is_lastbit <= is_lastbit_next;\r
+ expected_tdo <= expected_tdo_next;\r
+ ram_jtag_registers_a <= ram_jtag_registers_a_next;\r
+ dev_id <= dev_id_next;\r
+ -- INSERTLABEL: SYNCHRONOUS update\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(bitcounter, chipcounter, dev_id, last_tck_cycle, state, TRIGGER_BEGIN_READ_IN, BEGIN_JTAGBITCALC_IN, operation, operation_phase, substate, enable_jtag_clock, tdi, tms, RAM_JTAG_REGISTERS_D_IN, expected_tdo, first_not_removed_chip, nxt_not_removed_chip, ram_jtag_registers_a, is_lastbit, is_firstbit, is_dr_bit) -- INSERTLABEL: sensitivity list\r
+begin\r
+ bitcounter_next <= bitcounter;\r
+ last_tck_cycle_next <= last_tck_cycle;\r
+ state_next <= state;\r
+ substate_next <= substate;\r
+ operation_next <= operation;\r
+ operation_phase_next <= operation_phase;\r
+ enable_jtag_clock_next <= enable_jtag_clock;\r
+ tdi_next <= tdi;\r
+ tms_next <= tms;\r
+ chipcounter_next <= chipcounter;\r
+ dev_id_next <= dev_id;\r
+ expected_tdo_next <= expected_tdo;\r
+ is_dr_bit_next <= is_dr_bit;\r
+ is_firstbit_next <= is_firstbit;\r
+ is_lastbit_next <= is_lastbit;\r
+ ram_jtag_registers_a_next <= ram_jtag_registers_a;\r
+ \r
+ -- INSERTLABEL: COMB defaults\r
+ case state is\r
+ when idle =>\r
+ if(TRIGGER_BEGIN_READ_IN = '1') then\r
+ state_next <= wait_begin_jtagbitcalc;\r
+ operation_next <= "11"; -- none\r
+ \r
+ end if; \r
+ when wait_begin_jtagbitcalc =>\r
+ if(BEGIN_JTAGBITCALC_IN='1') then\r
+ state_next <= processing;\r
+ operation_phase_next <= operation_phase + 1;\r
+ substate_next <= none_p1; -- do nothing other than output tms=1\r
+ if(operation = "11") then\r
+ -- last operation was none\r
+ operation_next <= "00"; -- JTAG_RESET\r
+ operation_phase_next <= "0000"; -- Bit Nr. 0\r
+ enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation\r
+ elsif(operation = "00") then\r
+ -- last operation was: JTAG_RESET\r
+ if(operation_phase = "0110") then\r
+ operation_next <= "10"; -- skip WRITE_IR, because after JTAG_RESET, DEV_ID register is selected automatically\r
+ operation_phase_next <= "0000";\r
+ bitcounter_next <= (others => '0');\r
+ chipcounter_next <= first_not_removed_chip;\r
+ end if;\r
+ elsif(operation = "01") then\r
+ -- this state should never be reached\r
+ state_next <= idle;\r
+ elsif(operation = "10") then\r
+ --last operation was: WRITE_DR\r
+ if(operation_phase = "0010") then -- Shift-DR\r
+ substate_next <= dr_read_p1; \r
+ elsif(operation_phase = "0011") then -- Shift-DR\r
+ -- stay in this phase until the dr of all chips is read out\r
+ bitcounter_next <= bitcounter + 1;\r
+ operation_phase_next <= operation_phase;\r
+ substate_next <= dr_read_p1; -- fill dr with zeros\r
+ -- assume 32-bit DEV_ID per chip\r
+ if(nxt_not_removed_chip /= invalid_chip) then\r
+ if(to_integer(bitcounter) >= 31) then\r
+ chipcounter_next <= nxt_not_removed_chip;\r
+ bitcounter_next <= (others => '0');\r
+ substate_next <= dr_read_p1;\r
+ end if;\r
+ else\r
+ if (to_integer(bitcounter) >= 30) then\r
+ -- if the current chip is the last chip and we finish the register with the next bit\r
+ operation_phase_next <= operation_phase + 1;\r
+ -- bitcounter_next <= bitcounter + 1;\r
+ end if;\r
+ end if;\r
+ elsif(operation_phase = "0101") then -- Update DR\r
+ last_tck_cycle_next <= '1';\r
+ elsif(operation_phase = "0110") then -- Run-Test-Idle\r
+ enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation\r
+ last_tck_cycle_next <= '0';\r
+ elsif(operation_phase = "0111") then -- Wait for Data to be written to RAM\r
+ state_next <= idle; \r
+ end if;\r
+ end if;\r
+ end if;\r
+ when processing =>\r
+ -- set TMS, copied from jtag_write_m10, modified\r
+ tms_next <= '1'; -- JTAG_RESET if operation = "00"\r
+ if(operation = "00") then \r
+ if(operation_phase = "0110") then -- go into Run-Test/Idle\r
+ tms_next <= '0';\r
+ end if;\r
+ elsif(operation = "10") then -- Scan DR\r
+ if(operation_phase = "0000") then\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0100") then -- enter Exit1-DR\r
+ tms_next <= '1';\r
+ elsif(operation_phase = "0101") then -- enter Update-DR\r
+ tms_next <= '1';\r
+ else\r
+ tms_next <= '0';\r
+ end if;\r
+ end if; \r
+ tdi_next <= '0';\r
+ case substate is\r
+ when none_p1 =>\r
+ state_next <= wait_begin_jtagbitcalc;\r
+ when dr_read_p1 =>\r
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address\r
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1, RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- DEV_ID\r
+ tdi_next <= '0';\r
+ substate_next <= dr_read_p2;\r
+ when dr_read_p2 =>\r
+ -- wait one clock cycle \r
+ substate_next <= dr_read_p3;\r
+ when dr_read_p3 =>\r
+ dev_id_next <= RAM_JTAG_REGISTERS_D_IN;\r
+ substate_next <= dr_read_p4;\r
+ when dr_read_p4 =>\r
+ expected_tdo_next <= dev_id(to_integer(bitcounter));\r
+ state_next <= wait_begin_jtagbitcalc;\r
+ end case;\r
+ end case;\r
+end process;\r
+\r
+end architecture;\r
+\r
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+--use work.version.all;
+use work.jtag_constants.all;
+
+entity jtag_tck_out_component is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_CLOCK_PULSE1_IN : in std_logic;
+ JTAG_CLOCK_PULSE2_IN : in std_logic;
+ ENABLE_JTAG_TCK_IN : in std_logic;
+
+ TCK_OUT : out std_logic
+ );
+end entity;
+
+architecture jtag_tck_out_component_arch of jtag_tck_out_component is
+signal tck, tck_next : std_logic;
+begin
+TCK_OUT <= tck;
+
+process(CLK_IN)
+begin
+ if(rising_edge(CLK_IN)) then
+ if(RESET_IN='1') then
+ tck <= '0';
+ else
+ tck <= tck_next;
+ end if;
+ end if;
+end process;
+
+COMB_MAIN: process(ENABLE_JTAG_TCK_IN, JTAG_CLOCK_PULSE1_IN, JTAG_CLOCK_PULSE2_IN, tck)
+begin
+ tck_next <= tck;
+ if((JTAG_CLOCK_PULSE1_IN = '1') and (ENABLE_JTAG_TCK_IN = '1')) then
+ tck_next <= '1';
+ elsif(JTAG_CLOCK_PULSE2_IN = '1') then
+ tck_next <= '0';
+ end if;
+end process;
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.trb_net_std.all;\r
+--use work.trb_net_components.all;\r
+-- use work.trb_net16_hub_func.all;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+\r
+-- counts for one register of one chip:\r
+-- sampling errors : those cases in which not all sampled values are equal.\r
+-- matches : sampled value = expected value\r
+-- differences : sampled value /= expected value\r
+--\r
+-- the following equation should hold:\r
+-- matches+differences = register size\r
+-- RAM2: stores for each register \r
+-- MCOUNT = number of bits for which the sampled value \r
+-- matches the expected value\r
+-- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value \r
+-- does not match the expected value\r
+-- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value \r
+-- (not all sampled values equal)\r
+-- this should of course be 0\r
+-- \r
+\r
+\r
+entity jtag_tdo_compare_count_m10 is\r
+ generic (\r
+ MAX_NUMCHIPS_LD : integer;\r
+ MAX_REGISTERS_PLUS_ONE_LD : integer;\r
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;\r
+ MAX_REGLEN_LD : integer\r
+ );\r
+ port (\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)\r
+ -- sample_pulse3 delayed by one clock cycle\r
+ SAMPLE_PULSE3_D1_IN : in std_logic;\r
+ -- inputs from jtag_write_m10/jtag_read_m26devid\r
+ -- chipcount as unsigned\r
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);\r
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10 \r
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);\r
+ \r
+ ENABLE_COUNTERS_IN : in std_logic;\r
+ -- firstbit signal: reset counters before sampling this bit\r
+ IS_FIRSTBIT_IN : in std_logic;\r
+ -- finish signal: dataout => RAM1b, compareout => RAM2\r
+ IS_LASTBIT_IN : in std_logic;\r
+ \r
+ TDO_EXPECTED_IN : in std_logic;\r
+ TDO_SAMPLED_IN : in std_logic;\r
+ TDO_SAMPLING_ERROR_IN : in std_logic;\r
+ \r
+ -- RAM2\r
+ RAM_MATCH_DIFF_COUNT_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);\r
+ --RAM_MATCH_DIFF_COUNT_D_IN : in std_logic_vector(31 downto 0);\r
+ RAM_MATCH_DIFF_COUNT_WE_OUT : out std_logic;\r
+ RAM_MATCH_DIFF_COUNT_D_OUT : out std_logic_vector(31 downto 0)\r
+\r
+ ---- internal error out: signals that read/write sampling has been mixed\r
+ --INTERNAL_ERROR_OUT : out std_logic\r
+ \r
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)\r
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);\r
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); \r
+ );\r
+end entity;\r
+\r
+architecture jtag_tdo_compare_count_m10_arch of jtag_tdo_compare_count_m10 is\r
+\r
+-- state machine for main controlling state machine for TDO sampling:\r
+ type state_type is (WAIT_END_SAMPLING, COUNT_AND_TRIGGER_WRITE_RAM);\r
+ signal state, state_next : state_type;\r
+\r
+ -- counters for SAMPLING_ERROR: value changed in between sampling points\r
+ -- COMPARE_NEQ: sampled value is not equal expected value\r
+ -- COMPARE_EQUAL: sampled value is equal expected value\r
+ -- need at maximum to count to one register length which is 1152 for Mimosa26\r
+ signal sampling_error_count, sampling_error_count_next : unsigned(MAX_REGLEN_LD-1 downto 0);\r
+ signal compare_neq_count, compare_neq_count_next : unsigned(MAX_REGLEN_LD-1 downto 0);\r
+ signal compare_equal_count, compare_equal_count_next : unsigned(MAX_REGLEN_LD-1 downto 0);\r
+ \r
+ -- write reg_counts, pulse to start state machine with state ram2_write_state\r
+ signal write_reg_counts : std_logic; \r
+ \r
+-- state machine for write to RAM2:\r
+ type ram2_write_state_type is (RWC_IDLE, WRITE_MCOUNT, WRITE_DSECOUNT -- first line : writing counter values to RAM2\r
+ -- write_dr_mcount: write compare_equal_count\r
+ -- write_dr_dsecount: write compare_neq_count (low 16 bit of RAM word, DCOUNT) and compare_sampling_error (high 16 bit of RAM word, SECOUNT)\r
+ );\r
+ signal ram2_write_state, ram2_write_state_next : ram2_write_state_type; \r
+ --signal ram2_regnum, ram2_regnum_next: unsigned(MAX_REGISTERS_LD -1 downto 0);\r
+ -- RAM2 driving signals\r
+ signal ram_match_diff_count_a, ram_match_diff_count_a_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);\r
+ signal ram_match_diff_count_data, ram_match_diff_count_data_next : std_logic_vector(31 downto 0);\r
+ signal ram_match_diff_count_we, ram_match_diff_count_we_next : std_logic;\r
+\r
+begin\r
+RAM_MATCH_DIFF_COUNT_A_OUT <= ram_match_diff_count_a;\r
+RAM_MATCH_DIFF_COUNT_D_OUT <= ram_match_diff_count_data;\r
+RAM_MATCH_DIFF_COUNT_WE_OUT <= ram_match_diff_count_we;\r
+\r
+\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ state <= WAIT_END_SAMPLING;\r
+ sampling_error_count <= (others =>'0');\r
+ compare_neq_count <= (others =>'0');\r
+ compare_equal_count <= (others =>'0');\r
+ else\r
+ state <= state_next;\r
+ sampling_error_count <= sampling_error_count_next;\r
+ compare_neq_count <= compare_neq_count_next;\r
+ compare_equal_count <= compare_equal_count_next;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(state, SAMPLE_PULSE3_D1_IN, ENABLE_COUNTERS_IN, TDO_SAMPLED_IN, TDO_SAMPLING_ERROR_IN,\r
+TDO_EXPECTED_IN, IS_FIRSTBIT_IN, IS_LASTBIT_IN, sampling_error_count, compare_neq_count, compare_equal_count)\r
+begin\r
+ write_reg_counts <= '0';\r
+ sampling_error_count_next <= sampling_error_count;\r
+ compare_neq_count_next <= compare_neq_count;\r
+ compare_equal_count_next <= compare_equal_count;\r
+ state_next <= state;\r
+ case state is\r
+ when WAIT_END_SAMPLING =>\r
+ -- this is the idle state, on SAMPLE_PULSE3 check the ENABLE_COUNTERS signal\r
+ -- first sample taken leaving this state\r
+ if (SAMPLE_PULSE3_D1_IN ='1') then\r
+ -- if the bit should be counted\r
+ if(ENABLE_COUNTERS_IN = '1') then\r
+ if(IS_FIRSTBIT_IN = '1') then\r
+ sampling_error_count_next <= (others =>'0');\r
+ compare_neq_count_next <= (others =>'0');\r
+ compare_equal_count_next <= (others =>'0');\r
+ end if;\r
+ state_next <= count_and_trigger_write_ram;\r
+ end if;\r
+ end if;\r
+ -- trigger RAM writes, increment counts \r
+ when COUNT_AND_TRIGGER_WRITE_RAM =>\r
+ if(IS_LASTBIT_IN = '1') then\r
+ write_reg_counts <= '1';\r
+ end if;\r
+ -- increment counts: sampling errors, equal / not equal counts\r
+ if(TDO_SAMPLING_ERROR_IN = '1') then\r
+ sampling_error_count_next <= sampling_error_count + 1;\r
+ end if;\r
+ if(TDO_SAMPLED_IN = TDO_EXPECTED_IN) then\r
+ compare_equal_count_next <= compare_equal_count + 1;\r
+ else\r
+ compare_neq_count_next <= compare_neq_count + 1;\r
+ end if;\r
+ state_next <= wait_end_sampling;\r
+ end case;\r
+end process;\r
+\r
+SYNCHRONOUS_RAM2_WRITE : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ ram2_write_state <= RWC_IDLE;\r
+ ram_match_diff_count_we <= '0';\r
+ ram_match_diff_count_a <= (others => '0');\r
+ ram_match_diff_count_data <= (others => '0');\r
+-- ram2_regnum <= (others => '0'); \r
+ else\r
+ ram2_write_state <= ram2_write_state_next;\r
+ ram_match_diff_count_we <= ram_match_diff_count_we_next;\r
+ ram_match_diff_count_a <= ram_match_diff_count_a_next;\r
+ ram_match_diff_count_data <= ram_match_diff_count_data_next;\r
+-- ram2_regnum <= ram2_regnum_next; \r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_RAM2_WRITE: process(ram2_write_state, ram_match_diff_count_a, ram_match_diff_count_data, write_reg_counts, REGNUM_IN, CHIPNUM_IN, compare_equal_count, compare_neq_count, sampling_error_count)\r
+begin\r
+ ram2_write_state_next <= ram2_write_state;\r
+ ram_match_diff_count_we_next <= '0';\r
+ ram_match_diff_count_a_next <= ram_match_diff_count_a;\r
+ ram_match_diff_count_data_next <= ram_match_diff_count_data;\r
+\r
+ case ram2_write_state is\r
+ when RWC_IDLE =>\r
+ if(write_reg_counts = '1') then\r
+-- ram2_regnum_next <= REGNUM_IN;\r
+ ram2_write_state_next <= write_mcount;\r
+ end if;\r
+ when WRITE_MCOUNT =>\r
+ ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD) <= CHIPNUM_IN; -- chip address\r
+ --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto MAX_REGISTERS_PLUS_ONE_LD+1) <= (others => '0'); -- this could possibly be 0 bits, does this work, then? (gives a warning in modelsim)\r
+ --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD downto 0) <= std_logic_vector(2*unsigned(REGNUM_IN));\r
+ ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1) <= REGNUM_IN;\r
+ ram_match_diff_count_a_next(0) <= '0';\r
+ ram_match_diff_count_data_next(31 downto MAX_REGLEN_LD) <= (others => '0');\r
+ ram_match_diff_count_data_next(MAX_REGLEN_LD-1 downto 0) <= std_logic_vector(compare_equal_count);\r
+ ram_match_diff_count_we_next <= '1';\r
+ ram2_write_state_next <= WRITE_DSECOUNT;\r
+ when WRITE_DSECOUNT =>\r
+ ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD) <= CHIPNUM_IN; -- chip address\r
+ --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*unsigned(REGNUM_IN)+1);\r
+ ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1) <= REGNUM_IN;\r
+ ram_match_diff_count_a_next(0) <= '1';\r
+ ram_match_diff_count_data_next(31 downto MAX_REGLEN_LD+16) <= (others => '0');\r
+ ram_match_diff_count_data_next(MAX_REGLEN_LD-1+16 downto 16) <= std_logic_vector(sampling_error_count);\r
+ ram_match_diff_count_data_next(15 downto MAX_REGLEN_LD) <= (others => '0');\r
+ ram_match_diff_count_data_next(MAX_REGLEN_LD-1 downto 0) <= std_logic_vector(compare_neq_count);\r
+ ram_match_diff_count_we_next <= '1';\r
+ ram2_write_state_next <= rwc_idle;\r
+ end case;\r
+end process;\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.trb_net_std.all;\r
+--use work.trb_net_components.all;\r
+-- use work.trb_net16_hub_func.all;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+\r
+-- counts for one register of one chip:\r
+-- sampling errors : those cases in which not all sampled values are equal.\r
+-- matches : sampled value = expected value\r
+-- differences : sampled value /= expected value\r
+--\r
+-- the following equation should hold:\r
+-- matches+differences = register size\r
+-- RAM2: stores for each register \r
+-- MCOUNT = number of bits for which the sampled value \r
+-- matches the expected value\r
+-- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value \r
+-- does not match the expected value\r
+-- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value \r
+-- (not all sampled values equal)\r
+-- this should of course be 0\r
+-- \r
+\r
+\r
+entity jtag_tdo_compare_counttotal_noram_m10 is\r
+ generic (\r
+ numcounts : integer := 3;\r
+ se_counter_width : integer := 32; -- sampling error counter width\r
+ diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences \r
+ );\r
+ port (\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)\r
+ -- sample_pulse3 delayed by one clock cycle\r
+ SAMPLE_PULSE3_D1_IN : in std_logic;\r
+ -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?)\r
+ ENABLE_COUNTERS_IN : in std_logic;\r
+\r
+ TDO_EXPECTED_IN : in std_logic;\r
+ TDO_SAMPLED_IN : in std_logic;\r
+ TDO_SAMPLING_ERROR_IN : in std_logic;\r
+ BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);\r
+ END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);\r
+ \r
+ -- should be zero if timing is good\r
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0);\r
+ COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0);\r
+ LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0)\r
+\r
+ );\r
+end entity;\r
+\r
+architecture jtag_tdo_compare_counttotal_noram_m10_arch of jtag_tdo_compare_counttotal_noram_m10 is\r
+\r
+-- state machine for main controlling state machine for TDO sampling:\r
+ signal count_i_errors_occured : std_logic_vector(numcounts-1 downto 0);\r
+ --signal count_i_lookingforerrors : std_logic_vector(numcounts-1 downto 0);\r
+\r
+ signal sampling_error_count : unsigned(se_counter_width-1 downto 0);\r
+ \r
+ signal counts : unsigned(numcounts*diff_counter_width-1 downto 0);\r
+ signal SAMPLE_PULSE3_D2 : std_logic;\r
+begin\r
+COUNTS_OUT <= std_logic_vector(counts);\r
+SAMPLING_ERRORS_COUNT_OUT <= std_logic_vector(sampling_error_count);\r
+LAST_VALUES_OUT <= count_i_errors_occured;\r
+\r
+ALL_PROC : process (CLK_IN)\r
+variable i : integer;\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ for i in 0 to numcounts-1 loop\r
+ if(ENABLE_COUNTERS_IN = '1') then\r
+ if(SAMPLE_PULSE3_D2 = '1') then -- when this pulse arrives, the tdo-input from the last chip has been sampled\r
+ if(not(TDO_SAMPLED_IN = TDO_EXPECTED_IN)) then \r
+ --if(count_i_lookingforerrors(i) = '1') then\r
+ -- remember that an error has occured since begin signal\r
+ count_i_errors_occured(i) <= '1';\r
+ --end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ \r
+ if(BEGIN_COUNT_I_IN(i) = '1') then\r
+ -- reset states if begin signal received\r
+ --count_i_lookingforerrors(i) <= '1';\r
+ count_i_errors_occured(i) <= '0'; \r
+ end if;\r
+ if(END_COUNT_I_IN(i) = '1') then\r
+ -- on end signal update counter\r
+ if(count_i_errors_occured(i) = '1') then\r
+ -- increment count\r
+ counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) + 1;\r
+ end if;\r
+ end if;\r
+ end loop;\r
+ if(RESET_IN = '1') then\r
+ count_i_errors_occured <= (others => '0');\r
+ --count_i_lookingforerrors <= (others => '0');\r
+ counts <= (others => '0');\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+SAMPLING_ERRORS : process (CLK_IN)\r
+variable i : integer;\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(SAMPLE_PULSE3_D2 = '1') then\r
+ if(TDO_SAMPLING_ERROR_IN = '1') then\r
+ sampling_error_count <= sampling_error_count + 1;\r
+ end if;\r
+ end if;\r
+ -- delayed pulse\r
+ SAMPLE_PULSE3_D2 <= SAMPLE_PULSE3_D1_IN;\r
+ if(RESET_IN = '1') then\r
+ sampling_error_count <= (others => '0');\r
+ end if;\r
+ end if;\r
+ \r
+end process;\r
+\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.trb_net_std.all;\r
+--use work.trb_net_components.all;\r
+-- use work.trb_net16_hub_func.all;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+\r
+-- RAM1b: stores the data register values\r
+-- read out while writing (so the old values this is) to a RAM with the\r
+-- same layout as the RAM with the remotely configurable register contents.\r
+-- NOTE: the inputs don't need to be buffered again, as they change directly after SAMPLE_PULSE3 and this entity needs the inputs (chipnum_in for example) at maximum ~ 4 clock cycles after SAMPLE_PULSE3_D1 to operate\r
+-- NOTE: this RAM is purely for debugging purposes, and can be removed by\r
+-- by setting the generic enable_ram1b := 0\r
+-- then the compiler should optimize away the constantly idle state machine\r
+-- for writing to the ram, but i'm not sure if this works\r
+\r
+\r
+\r
+entity jtag_tdo_data_to_ram_m10 is\r
+ generic (\r
+ enable_ram1b : std_logic := '1';\r
+ MAX_NUMCHIPS_LD : integer;\r
+ MAX_REGISTERS_PLUS_ONE_LD : integer;\r
+ MAX_REGLEN_LD : integer;\r
+ RAM_JTAG_REGISTERS_DEPTH : integer\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SAMPLE_PULSE3_D1_IN : in std_logic;\r
+ -- active chip as unsigned\r
+ CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);\r
+ -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10 \r
+ REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);\r
+\r
+ -- dataout => RAM1b\r
+ ENABLE_DATAOUT_IN : in std_logic;\r
+ IS_FIRSTBIT_IN : in std_logic;\r
+ IS_LASTBIT_IN : in std_logic; \r
+ TDO_SAMPLED_IN : in std_logic;\r
+ -- RAM1b\r
+ RAM_JTAG_REGISTERS_READOUT_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ RAM_JTAG_REGISTERS_READOUT_D_IN : in std_logic_vector(31 downto 0);\r
+ RAM_JTAG_REGISTERS_READOUT_WE_OUT : out std_logic;\r
+ RAM_JTAG_REGISTERS_READOUT_D_OUT : out std_logic_vector(31 downto 0)\r
+ \r
+ -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)\r
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);\r
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); \r
+ );\r
+end entity;\r
+\r
+architecture jtag_tdo_data_to_ram_m10_arch of jtag_tdo_data_to_ram_m10 is\r
+\r
+-- state machine for main controlling state machine for TDO sampling:\r
+ type state_type is (S_WAIT_BEGIN_SAMPLE, S_TRIGGER_RAM_WRITE);\r
+ signal state, state_next : state_type;\r
+\r
+ -- store one 32bit word to write to RAM1b\r
+ signal data, data_next: std_logic_vector(31 downto 0);\r
+\r
+ -- the bit we are at in the current chip register. used to address memory, and to write to the right bit of the "data" word. \r
+ signal dataout_bitcount, dataout_bitcount_next : unsigned(MAX_REGLEN_LD-1 downto 0);\r
+ \r
+-- write data register or device id to RAM, pulses to start state machine with state ram1b_write_state\r
+ signal write_dr, write_dev_id : std_logic; \r
+-- -- write reg_counts, pulse to start state machine with state ram2_write_state\r
+-- signal write_reg_counts : std_logic; \r
+\r
+ \r
+-- state machine for read/write to RAM1b:\r
+ type ram1b_write_state_type is (RW_IDLE, RW_READ_DR_ADDR, RW_WAIT_READ_DR_ADDR, RW_WRITE_DR_DATA, -- first line : writing to data register in RAM1b\r
+ RW_WRITE_DEV_ID); -- second line: writing dev id to fixed address in memory area of chip in RAM1b\r
+ signal ram1b_write_state, ram1b_write_state_next : ram1b_write_state_type; \r
+\r
+ -- dr pointer, used to address register in RAM1b\r
+ signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);\r
+\r
+ -- RAM1b driving signals\r
+ signal ram_jtag_registers_readout_a, ram_jtag_registers_readout_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);\r
+ signal ram_jtag_registers_readout_data, ram_jtag_registers_readout_data_next : std_logic_vector(31 downto 0);\r
+ signal ram_jtag_registers_readout_wr, ram_jtag_registers_readout_wr_next : std_logic;\r
+ signal ram_jtag_registers_readout_data_in_signal : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+RAM_JTAG_REGISTERS_READOUT_A_OUT <= ram_jtag_registers_readout_a when enable_ram1b = '1' else (others => '0');\r
+RAM_JTAG_REGISTERS_READOUT_D_OUT <= ram_jtag_registers_readout_data when enable_ram1b = '1' else (others => '0');\r
+RAM_JTAG_REGISTERS_READOUT_WE_OUT <= ram_jtag_registers_readout_wr when enable_ram1b = '1' else '0';\r
+ram_jtag_registers_readout_data_in_signal <= RAM_JTAG_REGISTERS_READOUT_D_IN when enable_ram1b = '1' else (others => '0');\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ state <= S_WAIT_BEGIN_SAMPLE;\r
+ data <= (others => '0');\r
+ dataout_bitcount <= (others => '0'); \r
+ else\r
+ state <= state_next;\r
+ data <= data_next;\r
+ dataout_bitcount <= dataout_bitcount_next; \r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(state, SAMPLE_PULSE3_D1_IN, REGNUM_IN, IS_FIRSTBIT_IN, IS_LASTBIT_IN, TDO_SAMPLED_IN, data, dataout_bitcount, ENABLE_DATAOUT_IN)\r
+begin\r
+ write_dr <= '0';\r
+ write_dev_id <= '0';\r
+ data_next <= data;\r
+ dataout_bitcount_next <= dataout_bitcount;\r
+ state_next <= state;\r
+ \r
+ case state is\r
+ when S_WAIT_BEGIN_SAMPLE =>\r
+ -- this is the idle state, on SAMPLE_PULSE3_D1_IN check the ENABLE_DATAOUT signal\r
+ -- first sample taken leaving this state\r
+ if (SAMPLE_PULSE3_D1_IN ='1') then\r
+ -- if the bit should be counted\r
+ if(ENABLE_DATAOUT_IN = '1') then\r
+ if(IS_FIRSTBIT_IN = '1') then\r
+ data_next <= (others =>'0');\r
+ dataout_bitcount_next <= (others =>'0');\r
+ else\r
+ -- if next word starts, clear old data\r
+ if(to_integer(dataout_bitcount(4 downto 0))=31) then\r
+ data_next <= (others => '0');\r
+ end if;\r
+ dataout_bitcount_next <= dataout_bitcount + 1;\r
+ end if;\r
+ state_next <= S_TRIGGER_RAM_WRITE;\r
+ end if;\r
+ end if;\r
+ -- set data, trigger RAM writes \r
+ when S_TRIGGER_RAM_WRITE =>\r
+ data_next(to_integer(dataout_bitcount(4 downto 0))) <= TDO_SAMPLED_IN;\r
+ if((to_integer(dataout_bitcount(4 downto 0)) = 31) or IS_LASTBIT_IN = '1') then \r
+ if(to_integer(unsigned(REGNUM_IN)) = 0) then\r
+ write_dev_id <= '1';\r
+ else\r
+ write_dr <= '1';\r
+ end if;\r
+ end if;\r
+ state_next <= S_WAIT_BEGIN_SAMPLE;\r
+ end case;\r
+end process;\r
+\r
+\r
+SYNCHRONOUS_RAM1B_WRITE : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ ram1b_write_state <= RW_IDLE;\r
+ ram_jtag_registers_readout_a <= (others => '0');\r
+ ram_jtag_registers_readout_data <= (others => '0');\r
+ ram_jtag_registers_readout_wr <= '0';\r
+ dr_pointer <= (others => '0'); \r
+ else\r
+ ram1b_write_state <= ram1b_write_state_next;\r
+ ram_jtag_registers_readout_a <= ram_jtag_registers_readout_a_next;\r
+ ram_jtag_registers_readout_data <= ram_jtag_registers_readout_data_next;\r
+ ram_jtag_registers_readout_wr <= ram_jtag_registers_readout_wr_next;\r
+ dr_pointer <= dr_pointer_next; \r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_RAM1B_WRITE: process(ram1b_write_state, ram_jtag_registers_readout_a, ram_jtag_registers_readout_data, dr_pointer, write_dr, write_dev_id, CHIPNUM_IN, REGNUM_IN, data, ram_jtag_registers_readout_data_in_signal, dataout_bitcount )\r
+begin\r
+ ram1b_write_state_next <= ram1b_write_state;\r
+ ram_jtag_registers_readout_a_next <= ram_jtag_registers_readout_a;\r
+ ram_jtag_registers_readout_data_next <= ram_jtag_registers_readout_data;\r
+ ram_jtag_registers_readout_wr_next <= '0';\r
+ dr_pointer_next <= dr_pointer;\r
+ case ram1b_write_state is\r
+ when RW_IDLE =>\r
+ if(write_dr = '1') then\r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address\r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto MAX_REGISTERS_PLUS_ONE_LD+1) <= (others => '0');\r
+ ram_jtag_registers_readout_a_next(MAX_REGISTERS_PLUS_ONE_LD downto 1) <= REGNUM_IN; -- DR Pointer (REGNUM_IN is write_register+1), multiply that by two\r
+ ram_jtag_registers_readout_a_next(0) <= '0'; -- DR Pointer (REGNUM_IN is write_register+1), multiply that by two\r
+ ram1b_write_state_next <= RW_READ_DR_ADDR;\r
+ elsif(write_dev_id = '1') then\r
+ ram1b_write_state_next <= RW_WRITE_DEV_ID;\r
+ end if;\r
+ when RW_READ_DR_ADDR =>\r
+ ram1b_write_state_next <= RW_WAIT_READ_DR_ADDR;\r
+ when RW_WAIT_READ_DR_ADDR =>\r
+ dr_pointer_next <= unsigned(ram_jtag_registers_readout_data_in_signal(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0));\r
+ ram1b_write_state_next <= RW_WRITE_DR_DATA;\r
+ when RW_WRITE_DR_DATA =>\r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address\r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer+dataout_bitcount(MAX_REGLEN_LD-1 downto 5)); -- DR word address\r
+ ram_jtag_registers_readout_data_next <= data;\r
+ ram_jtag_registers_readout_wr_next <= '1';\r
+ ram1b_write_state_next <= RW_IDLE;\r
+ when RW_WRITE_DEV_ID => \r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address\r
+ ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- reserved: DEV_ID\r
+ ram_jtag_registers_readout_data_next <= data;\r
+ ram_jtag_registers_readout_wr_next <= '1';\r
+ ram1b_write_state_next <= RW_IDLE;\r
+ end case;\r
+end process;\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+--use work.trb_net_std.all;\r
+--use work.trb_net_components.all;\r
+-- use work.trb_net16_hub_func.all;\r
+--use work.version.all;\r
+use work.jtag_constants.all;\r
+\r
+-- this entity samples TDO at three time points\r
+-- given by pulses SAMPLE_PULSE1_IN, SAMPLE_PULSE2_IN, SAMPLE_PULSE3_IN\r
+-- it always takes the value of the middle point (at SAMPLE_PULSE2_IN), \r
+-- but signals a sampling error if not all sampled values are equal\r
+-- output is updated two clock cycles after SAMPLE_PULSE3_IN is 1\r
+\r
+\r
+\r
+\r
+entity jtag_tdo_sample is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)\r
+ -- the first sample is taken directly after this pulse\r
+ SAMPLE_PULSE1_IN : in std_logic;\r
+ SAMPLE_PULSE2_IN : in std_logic;\r
+ SAMPLE_PULSE3_IN : in std_logic;\r
+ \r
+ -- TDO signal, which is to be sampled \r
+ TDO_IN : in std_logic;\r
+ -- sampled value of TDO\r
+ TDO_SAMPLED_OUT : out std_logic;\r
+ -- sampling error\r
+ SAMPLING_ERROR_OUT : out std_logic\r
+ --SAMPLING_FINISHED_PULSE_OUT : out std_logic;\r
+ );\r
+end entity;\r
+\r
+architecture jtag_tdo_sample_arch of jtag_tdo_sample is\r
+\r
+-- state machine for main controlling state machine for TDO sampling:\r
+ type state_type is (WAIT_SAMPLE_PULSES, FINISH_SAMPLING);\r
+ signal state, state_next : state_type;\r
+\r
+ -- the sampled TDO line at times sample_pulse1 + 1, sample_pulse2 + 1, sample_pulse3 + 1\r
+ signal sampled, sampled_next : std_logic_vector(2 downto 0);\r
+ -- updated 2 clocks after sample_pulse3 occurs\r
+ signal sampling_error, sampling_error_next : std_logic; \r
+ signal tdo_sampled, tdo_sampled_next : std_logic;\r
+\r
+begin\r
+--SAMPLING_FINISHED_PULSE_OUT <= sampling_finished_pulse;\r
+SAMPLING_ERROR_OUT <= sampling_error;\r
+TDO_SAMPLED_OUT <= tdo_sampled;\r
+\r
+SYNCHRONOUS_MAIN : process (CLK_IN)\r
+begin\r
+ if (rising_edge(CLK_IN)) then\r
+ if(RESET_IN = '1') then\r
+ state <= WAIT_SAMPLE_PULSES;\r
+ sampled <= (others => '0');\r
+-- sampling_finished_pulse <= '0';\r
+ tdo_sampled <= '0';\r
+ sampling_error <= '0';\r
+ else\r
+ state <= state_next;\r
+ sampled <= sampled_next;\r
+-- sampling_finished_pulse <= sampling_finished_pulse_next;\r
+ tdo_sampled <= tdo_sampled_next;\r
+ sampling_error <= sampling_error_next;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+COMB_MAIN: process(state, SAMPLE_PULSE1_IN, SAMPLE_PULSE2_IN, SAMPLE_PULSE3_IN, TDO_IN, sampled, tdo_sampled, sampling_error)\r
+begin\r
+ state_next <= state;\r
+ sampled_next <= sampled;\r
+ sampling_error_next <= sampling_error;\r
+ tdo_sampled_next <= tdo_sampled;\r
+-- sampling_finished_pulse_next <= '0';\r
+ case state is\r
+ when WAIT_SAMPLE_PULSES =>\r
+ -- this is the idle state, on BEGIN_SAMPLE_IN check the ENABLE_* signals\r
+ -- first sample taken leaving this state\r
+ if (SAMPLE_PULSE1_IN ='1') then\r
+ sampled_next(0) <= TDO_IN;\r
+ end if;\r
+ if (SAMPLE_PULSE2_IN ='1') then\r
+ sampled_next(1) <= TDO_IN;\r
+ end if;\r
+ if (SAMPLE_PULSE3_IN ='1') then\r
+ sampled_next(2) <= TDO_IN;\r
+ state_next <= FINISH_SAMPLING;\r
+ end if;\r
+ -- set sampling_error \r
+ when FINISH_SAMPLING =>\r
+ if(sampled(2) = sampled(1) and sampled(1) = sampled(0) ) then\r
+ sampling_error_next <= '0';\r
+ else\r
+ sampling_error_next <= '1';\r
+ end if;\r
+ tdo_sampled_next <= sampled(1);\r
+-- sampling_finished_pulse_next <= '1';\r
+ state_next <= WAIT_SAMPLE_PULSES;\r
+ end case;\r
+end process;\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.jtag_constants.all;
+use work.jtag_misc.all;
+--use work.monitor_config.all;
+
+-- this entity adds 1 to the error counts in RAM3a, for those registers in which errors occured.
+-- it is a simple implementation, not looking at the number of chips configured,
+-- simply processing the entire memory, thereby going to the maximum number of chips (2**MAX_NUMCHIPS_LD) and the maximum number of registers ( MAX_REGISTERS)
+-- the read_error, data_changed and write_error counting is done separately. always going through the whole memory would take a bit longer, actually this only takes 512 times 7 clock cycles, so 35us.-- we need 7 clock cycles per register because two 32bit integers have to be read from ram3a (4), changed (1) and written back to ram3a (2). the minimum would be some constant + 2 clock cycles/register, because 2 words have to be read from ram (and 2 words have to be written to ram).
+
+entity jtag_update_error_counts_ram3a is
+ generic (
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_PLUS_TWO_LD : integer;
+ RAM_MATCH_DIFF_COUNT_DEPTH : integer;
+ RAM_ERROR_COUNTS_DEPTH : integer;
+ WRITE_ERROR_THRESHOLD : integer;
+ READ_ERROR_THRESHOLD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TRIGGER_UPDATE_DATA_CHANGED_IN : in std_logic;
+ TRIGGER_UPDATE_READ_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_WRITE_ERRORS_IN : in std_logic;
+ TRIGGER_UPDATE_RUN_COUNTER_IN : in std_logic;
+ RUN_COUNTER_IN : in std_logic_vector(31 downto 0);
+ -- RAM2
+ RAM2_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+ RAM2_D_IN : in std_logic_vector(31 downto 0);
+ -- RAM3a
+ RAM3A_A_OUT : out std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+ RAM3A_D_IN : in std_logic_vector(31 downto 0);
+ RAM3A_D_OUT : out std_logic_vector(31 downto 0);
+ RAM3A_WR_OUT :out std_logic;
+
+
+ -- * need this because only for not-removed chips errors should be counted
+ REMOVED_CHIPS_IN : in std_logic_vector(MAX_NUMCHIPS -1 downto 0);
+ -- * only go up to the number of chips configured
+ NUMCHIPS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+ -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ -- if true, there were read errors in last dev_id read
+ READ_ERRORS_OUT : out std_logic;
+ -- if true, there were read errors the last double write to registers (value read the second time didn't equal programmed value)
+ WRITE_ERRORS_OUT : out std_logic;
+ -- if true, the data read from the registers wasn't equal to the data programmed a period before (for example in the last spill break)
+ DATA_CHANGED_OUT : out std_logic;
+ IDLE_OUT : out std_logic
+ );
+end entity;
+
+architecture jtag_update_error_counts_ram3a_arch of jtag_update_error_counts_ram3a is
+type upd_state_type is (UPD_IDLE,
+-- upd1s*: update DATA_CHANGED counts
+UPD1S_START_REG, UPD1S_SETUP_READ_DATA_CH, UPD1S_SETUP_READ_DATA_CH_OV_TH, UPD1S_READ_DATA_CH_OV_TH, UPD1S_WRITE_CALC_NEW_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED_OV_TH, UPD1S_START_FINISH, UPD1S_FINISH_SETUP_READ_DATA_CH, UPD1S_FINISH_SETUP_READ_WAIT, UPD1S_FINISH_READ_DATA_CH_OV_TH, UPD1S_FINISH_CALC_NEW_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH,
+
+UPD3S_START_REG, UPD3S_SETUP_READ_DATA_CH, UPD3S_SETUP_READ_DATA_CH_OV_TH, UPD3S_READ_DATA_CH_OV_TH, UPD3S_WRITE_CALC_NEW_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED_OV_TH, UPD3S_START_FINISH, UPD3S_FINISH_SETUP_READ_DATA_CH, UPD3S_FINISH_SETUP_READ_WAIT, UPD3S_FINISH_READ_DATA_CH_OV_TH, UPD3S_FINISH_CALC_NEW_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH,
+
+
+UPD2S_START_REG, UPD2S_SETUP_READ_DATA_CH, UPD2S_SETUP_READ_DATA_CH_OV_TH, UPD2S_READ_DATA_CH_OV_TH, UPD2S_WRITE_CALC_NEW_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED_OV_TH,
+-- upd2s*: update READ_ERROR counts
+--,UPD2S_SETUP,UPD2S_READ_MCOUNT, UPD2S_READ_DCOUNT,
+-- upd3s*: update WRITE_ERROR counts
+--UPD3S_SETUP, UPD3S_READ_MCOUNT, UPD3S_READ_DCOUNT,UPD3S_WRITE_WRITE_ERRORS, UPD3S_WRITE_WRITE_ERRORS_OV_TH
+
+-- following states unneeded because ram has one clock cycle delay for reading, not two
+--, UPD1S_SETUP_READ_DATA_CH2, UPD3S_SETUP_READ_DATA_CH2, UPD2S_SETUP_READ_DATA_CH2
+-- , UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH, UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH
+UPD4S_WRITE_RUN_COUNTER
+);
+signal state, state_next : upd_state_type;
+
+signal chipnum, chipnum_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
+signal regnum, regnum_next : unsigned(MAX_REGISTERS_LD -1 downto 0);
+signal any_data_changed, any_data_changed_next : std_logic;
+signal any_data_changed_ov_th, any_data_changed_ov_th_next : std_logic;
+signal ram2_a, ram2_a_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
+signal ram3a_a, ram3a_a_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
+signal ram3a_d, ram3a_d_next : std_logic_vector(31 downto 0);
+signal ram3a_wr, ram3a_wr_next : std_logic;
+signal changed_count, changed_count_next : unsigned(31 downto 0);
+signal changed_ov_th_count, changed_ov_th_count_next : unsigned(31 downto 0);
+signal mcount, mcount_next : std_logic_vector(31 downto 0);
+signal dcount, dcount_next : std_logic_vector(31 downto 0);
+signal removed_chips : std_logic_vector(2**MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+-- global data_changed/read_errors/write_errors
+signal gdata_changed, gdata_changed_next : std_logic;
+signal gread_errors, gread_errors_next : std_logic;
+signal gwrite_errors, gwrite_errors_next : std_logic;
+signal numregs : unsigned(MAX_REGISTERS_PLUS_ONE_LD - 1 downto 0);
+signal numregs_vect : std_logic_vector((2**MAX_NUMCHIPS_LD)*MAX_REGISTERS_PLUS_ONE_LD-1 downto 0);
+
+
+begin
+
+IDLE_OUT <= '1' when state = UPD_IDLE else '0';
+RAM2_A_OUT <= ram2_a;
+RAM3A_A_OUT <= ram3a_a;
+RAM3A_D_OUT <= ram3a_d;
+RAM3A_WR_OUT <= ram3a_wr;
+-- only maximum of MAX_NUMCHIPS is allowed, so don't need external signals for these chips,
+-- but internally the integer can go up to 2**MAX_NUMCHIPS_PLUS_ONE_LD-1
+removed_chips(2**MAX_NUMCHIPS_PLUS_ONE_LD-1 downto MAX_NUMCHIPS) <= (others => '1');
+removed_chips(MAX_NUMCHIPS-1 downto 0) <= REMOVED_CHIPS_IN;
+numregs_vect((2**MAX_NUMCHIPS_LD)*MAX_REGISTERS_PLUS_ONE_LD-1 downto MAX_NUMCHIPS*MAX_REGISTERS_PLUS_ONE_LD) <= (others => '0'); -- fill unavailable bits with zeros (to make slices computable)
+numregs_vect(MAX_NUMCHIPS*MAX_REGISTERS_PLUS_ONE_LD-1 downto 0) <= NUMREGS_CONFIGURED_IN;
+numregs <= unsigned(NUMREGS_CONFIGURED_IN((to_integer(chipnum)+1)*MAX_REGISTERS_PLUS_ONE_LD - 1 downto to_integer(chipnum)*MAX_REGISTERS_PLUS_ONE_LD));
+
+READ_ERRORS_OUT <= gread_errors;
+WRITE_ERRORS_OUT <= gwrite_errors;
+DATA_CHANGED_OUT <= gdata_changed;
+
+SEQUENTIAL: process(CLK_IN)
+begin
+ if (rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ state <= UPD_IDLE;
+ ram2_a <= (others => '0');
+ ram3a_a <= (others => '0');
+ ram3a_wr <= '0';
+ ram3a_d <= (others => '0');
+ changed_count <= (others => '0');
+ changed_ov_th_count <= (others => '0');
+ mcount <= (others => '0');
+ dcount <= (others => '0');
+ chipnum <= (others => '0');
+ any_data_changed <= '0';
+ any_data_changed_ov_th <= '0';
+ regnum <= (others => '0');
+ gdata_changed <= '0';
+ gread_errors <= '0';
+ gwrite_errors <= '0';
+ else
+ state <= state_next;
+ ram2_a <= ram2_a_next;
+ ram3a_a <= ram3a_a_next;
+ ram3a_wr <= ram3a_wr_next;
+ ram3a_d <= ram3a_d_next;
+ changed_count <= changed_count_next;
+ changed_ov_th_count <= changed_ov_th_count_next;
+ mcount <= mcount_next;
+ dcount <= dcount_next;
+ chipnum <= chipnum_next;
+ any_data_changed <= any_data_changed_next;
+ any_data_changed_ov_th <= any_data_changed_ov_th_next;
+ regnum <= regnum_next;
+ gdata_changed <= gdata_changed_next;
+ gread_errors <= gread_errors_next;
+ gwrite_errors <= gwrite_errors_next;
+ end if;
+ end if;
+end process;
+
+COMB: process(state, TRIGGER_UPDATE_DATA_CHANGED_IN, TRIGGER_UPDATE_READ_ERRORS_IN, TRIGGER_UPDATE_WRITE_ERRORS_IN, TRIGGER_UPDATE_RUN_COUNTER_IN, RUN_COUNTER_IN, numregs, removed_chips, NUMCHIPS_CONFIGURED_IN, ram3a_d, RAM3A_D_IN, ram3a_a, ram2_a, RAM2_D_IN, chipnum, regnum, any_data_changed, any_data_changed_ov_th, changed_count, changed_ov_th_count, dcount, mcount, gdata_changed, gwrite_errors, gread_errors)
+begin
+ state_next <= state;
+ ram2_a_next <= ram2_a;
+ ram3a_a_next <= ram3a_a;
+ ram3a_d_next <= ram3a_d;
+ ram3a_wr_next <= '0';
+ chipnum_next <= chipnum;
+ regnum_next <= regnum;
+ any_data_changed_next <= any_data_changed;
+ any_data_changed_ov_th_next <= any_data_changed_ov_th;
+ changed_count_next <= changed_count;
+ changed_ov_th_count_next <= changed_ov_th_count;
+ dcount_next <= dcount;
+ mcount_next <= mcount;
+
+ gdata_changed_next <= gdata_changed;
+ gwrite_errors_next <= gwrite_errors;
+ gread_errors_next <= gread_errors;
+
+ case state is
+ when UPD_IDLE =>
+ if(TRIGGER_UPDATE_DATA_CHANGED_IN = '1') then
+ chipnum_next <= (others => '0');
+ regnum_next <= (others => '0');
+ any_data_changed_next <= '0';
+ any_data_changed_ov_th_next <= '0';
+ gdata_changed_next <= '0';
+ state_next <= UPD1S_START_REG;
+ elsif(TRIGGER_UPDATE_READ_ERRORS_IN = '1') then
+ chipnum_next <= (others => '0');
+ regnum_next <= (others => '0');
+ gread_errors_next <= '0';
+ state_next <= UPD2S_START_REG;
+ elsif(TRIGGER_UPDATE_WRITE_ERRORS_IN = '1') then
+ chipnum_next <= (others => '0');
+ regnum_next <= (others => '0');
+ any_data_changed_next <= '0';
+ any_data_changed_ov_th_next <= '0';
+ gwrite_errors_next <= '0';
+ state_next <= UPD3S_START_REG;
+ elsif(TRIGGER_UPDATE_RUN_COUNTER_IN = '1') then
+ chipnum_next <= (others => '0');
+ state_next <= UPD4S_WRITE_RUN_COUNTER;
+ end if;
+ when UPD1S_START_REG =>
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= std_logic_vector(to_unsigned(to_integer(regnum) + 1, MAX_REGISTERS_PLUS_TWO_LD)); -- dr counts start after two read counts, and for each register there are two words.
+ ram2_a_next(0 ) <= '0';
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '1'; -- data changed
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= std_logic_vector(to_unsigned(to_integer(regnum)+2, MAX_REGISTERS_PLUS_TWO_LD)); -- dr1
+ ram3a_a_next(0) <= '0'; --d_ch
+ state_next <= UPD1S_SETUP_READ_DATA_CH;
+ when UPD1S_SETUP_READ_DATA_CH =>
+ -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change
+ ram2_a_next(0) <= '1';
+ ram3a_a_next(0) <= '1';
+ -- state_next <= UPD1S_SETUP_READ_DATA_CH2;
+ --when UPD1S_SETUP_READ_DATA_CH2 =>
+ state_next <= UPD1S_SETUP_READ_DATA_CH_OV_TH;
+ when UPD1S_SETUP_READ_DATA_CH_OV_TH =>
+ changed_count_next <= unsigned(RAM3A_D_IN);
+ mcount_next <= RAM2_D_IN;
+ state_next <= UPD1S_READ_DATA_CH_OV_TH;
+
+ when UPD1S_READ_DATA_CH_OV_TH =>
+ changed_ov_th_count_next <= unsigned(RAM3A_D_IN);
+ dcount_next <= RAM2_D_IN;
+ state_next <= UPD1S_WRITE_CALC_NEW_DATA_CHANGED;
+
+ when UPD1S_WRITE_CALC_NEW_DATA_CHANGED =>
+ -- if 0 bits match, or at least one error, add one to data changed count
+ if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then
+ -- increment error counter
+ changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ any_data_changed_next <= '1';
+ gdata_changed_next <= '1';
+ end if;
+ end if;
+
+ if(unsigned(mcount) = 0 or not unsigned(dcount)< WRITE_ERROR_THRESHOLD) then
+ -- increment error counter
+ changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ any_data_changed_ov_th_next <= '1';
+ gdata_changed_next <= '1';
+ end if;
+ end if;
+ state_next <= UPD1S_WRITE_DR_DATA_CHANGED;
+
+ when UPD1S_WRITE_DR_DATA_CHANGED =>
+ ram3a_a_next(0) <= '0';
+ ram3a_d_next <= std_logic_vector(changed_count);
+ ram3a_wr_next <= '1';
+ state_next <= UPD1S_WRITE_DR_DATA_CHANGED_OV_TH;
+ when UPD1S_WRITE_DR_DATA_CHANGED_OV_TH =>
+ ram3a_a_next(0) <= '1';
+ ram3a_d_next <= std_logic_vector(changed_ov_th_count);
+ ram3a_wr_next <= '1';
+ if((to_integer(regnum) + 1 = numregs) or (numregs = 0) ) then
+ -- finished
+ state_next <= UPD1S_START_FINISH;
+ else
+ regnum_next <= regnum + 1;
+ state_next <= UPD1S_START_REG;
+ end if;
+
+ when UPD1S_START_FINISH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total)
+ state_next <= UPD1S_FINISH_SETUP_READ_DATA_CH;
+ when UPD1S_FINISH_SETUP_READ_DATA_CH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total)
+ -- state_next <= UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH;
+ --when UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH =>
+ state_next <= UPD1S_FINISH_SETUP_READ_WAIT;
+ when UPD1S_FINISH_SETUP_READ_WAIT =>
+ changed_count_next <= unsigned(RAM3A_D_IN);
+ state_next <= UPD1S_FINISH_READ_DATA_CH_OV_TH;
+ when UPD1S_FINISH_READ_DATA_CH_OV_TH =>
+ changed_ov_th_count_next <= unsigned(RAM3A_D_IN);
+ state_next <= UPD1S_FINISH_CALC_NEW_DATA_CHANGED;
+ when UPD1S_FINISH_CALC_NEW_DATA_CHANGED =>
+ if(any_data_changed = '1') then
+ changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ end if;
+ if(any_data_changed_ov_th = '1') then
+ changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ end if;
+ state_next <= UPD1S_FINISH_WRITE_DATA_CHANGED;
+
+ when UPD1S_FINISH_WRITE_DATA_CHANGED =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total)
+ ram3a_d_next <= std_logic_vector(changed_count);
+ ram3a_wr_next <= '1';
+ state_next <= UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH;
+ when UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total)
+ ram3a_d_next <= std_logic_vector(changed_ov_th_count);
+ ram3a_wr_next <= '1';
+ if(to_integer(chipnum) + 1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then
+ -- process next chip
+ chipnum_next <= chipnum + 1;
+ regnum_next <= (others => '0');
+ any_data_changed_next <= '0';
+ any_data_changed_ov_th_next <= '0';
+ state_next <= UPD1S_START_REG;
+ else
+ -- finally really finished
+ state_next <= UPD_IDLE;
+ end if;
+
+ -- UPDATE WRITE ERROR COUNTS
+ when UPD3S_START_REG =>
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= std_logic_vector(to_unsigned(to_integer(regnum) + 1, MAX_REGISTERS_PLUS_TWO_LD)); -- dr counts start after two read counts, and for each register there are two words.
+ ram2_a_next(0 ) <= '0';
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '0'; -- write errors
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= std_logic_vector(to_unsigned(to_integer(regnum)+2, MAX_REGISTERS_PLUS_TWO_LD)); -- dr1
+ ram3a_a_next(0) <= '0'; -- normal count
+ state_next <= UPD3S_SETUP_READ_DATA_CH;
+ when UPD3S_SETUP_READ_DATA_CH =>
+ -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change
+ ram2_a_next(0) <= '1';
+ ram3a_a_next(0) <= '1'; -- count over th
+ -- state_next <= UPD3S_SETUP_READ_DATA_CH2;
+ --when UPD3S_SETUP_READ_DATA_CH2 =>
+ state_next <= UPD3S_SETUP_READ_DATA_CH_OV_TH;
+ when UPD3S_SETUP_READ_DATA_CH_OV_TH =>
+ changed_count_next <= unsigned(RAM3A_D_IN); -- changed_count now is write error count
+ mcount_next <= RAM2_D_IN;
+ state_next <= UPD3S_READ_DATA_CH_OV_TH;
+
+ when UPD3S_READ_DATA_CH_OV_TH =>
+ changed_ov_th_count_next <= unsigned(RAM3A_D_IN); -- changed_ov_th_count now is write errors over threshold count
+ dcount_next <= RAM2_D_IN;
+ state_next <= UPD3S_WRITE_CALC_NEW_DATA_CHANGED;
+
+ when UPD3S_WRITE_CALC_NEW_DATA_CHANGED =>
+ -- if 0 bits match, or at least one error, add one to data changed count
+ if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then
+ -- increment error counter
+ changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ -- onlly add chip errors of not removed chips to global error counter
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ any_data_changed_next <= '1';
+ gwrite_errors_next <= '1';
+ end if;
+ end if;
+
+ if(unsigned(mcount) = 0 or not unsigned(dcount)< WRITE_ERROR_THRESHOLD) then
+ -- increment error counter
+ changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ -- onlly add chip errors of not removed chips to global error counter
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ any_data_changed_ov_th_next <= '1';
+ gwrite_errors_next <= '1';
+
+ end if;
+ end if;
+ state_next <= UPD3S_WRITE_DR_DATA_CHANGED;
+
+ when UPD3S_WRITE_DR_DATA_CHANGED =>
+ ram3a_a_next(0) <= '0';
+ ram3a_d_next <= std_logic_vector(changed_count);
+ ram3a_wr_next <= '1';
+ state_next <= UPD3S_WRITE_DR_DATA_CHANGED_OV_TH;
+ when UPD3S_WRITE_DR_DATA_CHANGED_OV_TH =>
+ ram3a_a_next(0) <= '1';
+ ram3a_d_next <= std_logic_vector(changed_ov_th_count);
+ ram3a_wr_next <= '1';
+ if((to_integer(regnum) + 1 = numregs) or (numregs = 0) ) then
+ -- finished
+ state_next <= UPD3S_START_FINISH;
+ else
+ regnum_next <= regnum + 1;
+ state_next <= UPD3S_START_REG;
+ end if;
+
+ when UPD3S_START_FINISH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total)
+ state_next <= UPD3S_FINISH_SETUP_READ_DATA_CH;
+ when UPD3S_FINISH_SETUP_READ_DATA_CH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total)
+-- state_next <= UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH;
+-- when UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH =>
+ state_next <= UPD3S_FINISH_SETUP_READ_WAIT;
+ when UPD3S_FINISH_SETUP_READ_WAIT =>
+ changed_count_next <= unsigned(RAM3A_D_IN);
+ state_next <= UPD3S_FINISH_READ_DATA_CH_OV_TH;
+ when UPD3S_FINISH_READ_DATA_CH_OV_TH =>
+ changed_ov_th_count_next <= unsigned(RAM3A_D_IN);
+ state_next <= UPD3S_FINISH_CALC_NEW_DATA_CHANGED;
+ when UPD3S_FINISH_CALC_NEW_DATA_CHANGED =>
+ if(any_data_changed = '1') then
+ changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ end if;
+ if(any_data_changed_ov_th = '1') then
+ changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ end if;
+ state_next <= UPD3S_FINISH_WRITE_DATA_CHANGED;
+
+ when UPD3S_FINISH_WRITE_DATA_CHANGED =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total)
+ ram3a_d_next <= std_logic_vector(changed_count);
+ ram3a_wr_next <= '1';
+ state_next <= UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH;
+ when UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total)
+ ram3a_d_next <= std_logic_vector(changed_ov_th_count);
+ ram3a_wr_next <= '1';
+ if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then
+ -- process next chip
+ chipnum_next <= chipnum + 1;
+ regnum_next <= (others => '0');
+ any_data_changed_next <= '0';
+ any_data_changed_ov_th_next <= '0';
+ state_next <= UPD3S_START_REG;
+ else
+ -- finally really finished
+ state_next <= UPD_IDLE;
+ end if;
+
+
+ -- UPDATE READ ERROR COUNTS
+ when UPD2S_START_REG =>
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= (others => '0'); -- the two read counts are the first two words.
+ ram2_a_next(0 ) <= '0';
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '0'; -- read errors
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= (others => '0'); -- read errors
+ ram3a_a_next(0) <= '0'; -- normal count
+ state_next <= UPD2S_SETUP_READ_DATA_CH;
+ when UPD2S_SETUP_READ_DATA_CH =>
+ -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change
+ ram2_a_next(0) <= '1';
+ ram3a_a_next(0) <= '1'; -- count over th
+ -- state_next <= UPD2S_SETUP_READ_DATA_CH2;
+ --when UPD2S_SETUP_READ_DATA_CH2 =>
+ state_next <= UPD2S_SETUP_READ_DATA_CH_OV_TH;
+ when UPD2S_SETUP_READ_DATA_CH_OV_TH =>
+ changed_count_next <= unsigned(RAM3A_D_IN); -- changed_count now is write error count
+ mcount_next <= RAM2_D_IN;
+ state_next <= UPD2S_READ_DATA_CH_OV_TH;
+
+ when UPD2S_READ_DATA_CH_OV_TH =>
+ changed_ov_th_count_next <= unsigned(RAM3A_D_IN); -- changed_ov_th_count now is write errors over threshold count
+ dcount_next <= RAM2_D_IN;
+ state_next <= UPD2S_WRITE_CALC_NEW_DATA_CHANGED;
+
+ when UPD2S_WRITE_CALC_NEW_DATA_CHANGED =>
+ -- if 0 bits match, or at least one error, add one to data changed count
+ if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then
+ -- onlly add chip errors of not removed chips to global error counter
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ -- increment error counter
+ changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ gread_errors_next <= '1';
+ end if;
+ --any_data_changed_next <= '1';
+ end if;
+
+ if(unsigned(mcount) = 0 or not unsigned(dcount)< READ_ERROR_THRESHOLD) then
+ -- onlly add chip errors of not removed chips to global error counter
+ if(removed_chips(to_integer(chipnum)) = '0') then
+ -- increment error counter
+ changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect
+ gread_errors_next <= '1';
+ end if;
+ --any_data_changed_ov_th_next <= '1';
+ end if;
+ state_next <= UPD2S_WRITE_DR_DATA_CHANGED;
+
+ when UPD2S_WRITE_DR_DATA_CHANGED =>
+ ram3a_a_next(0) <= '0';
+ ram3a_d_next <= std_logic_vector(changed_count);
+ ram3a_wr_next <= '1';
+ state_next <= UPD2S_WRITE_DR_DATA_CHANGED_OV_TH;
+ when UPD2S_WRITE_DR_DATA_CHANGED_OV_TH =>
+ ram3a_a_next(0) <= '1';
+ ram3a_d_next <= std_logic_vector(changed_ov_th_count);
+ ram3a_wr_next <= '1';
+ if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then
+ -- process next chip
+ chipnum_next <= chipnum + 1;
+ --any_data_changed_next <= '0';
+ --any_data_changed_ov_th_next <= '0';
+ state_next <= UPD2S_START_REG;
+ else
+ -- finished
+ state_next <= UPD_IDLE;
+ end if;
+
+ -- UPDATE RUN COUNTER part
+ when UPD4S_WRITE_RUN_COUNTER =>
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum);
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '1'; -- data_changed/run_counter
+ ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -2 downto 0) <= (others => '0'); -- data_changed/run_counter
+ ram3a_d_next <= RUN_COUNTER_IN;
+ ram3a_wr_next <= '1';
+ if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then
+ chipnum_next <= chipnum + 1;
+ else
+ state_next <= UPD_IDLE;
+ end if;
+end case;
+end process;
+
+end architecture;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+--use work.version.all;
+use work.jtag_constants.all;
+
+entity jtag_write_m10 is
+ generic (
+ RAM_JTAG_REGISTERS_DEPTH : integer;
+ MAX_NUMCHIPS : integer;
+ MAX_NUMCHIPS_LD : integer;
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer;
+ MAX_REGISTERS_LD : integer;
+ MAX_REGISTERS_PLUS_ONE_LD : integer;
+ MAX_REGLEN_LD : integer;
+ MAX_REGLEN_PLUS_ONE_LD : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ --RAM_JTAG_REGISTERS_READ_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_READ_DEPTH-1 downto 0);
+ --RAM_JTAG_REGISTERS_READ_D_OUT : out std_logic_vector(31 downto 0);
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ -- the zero'th entry points to the first not removed chip
+ -- a value of (others => '1') means that no more non-removed chips follow
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_WRITE_IN : in std_logic;
+ IDLE_OUT : out std_logic;
+
+
+ IS_DR_BIT_OUT : out std_logic;
+ IS_FIRSTBIT_OUT : out std_logic;
+ IS_LASTBIT_OUT : out std_logic;
+ CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+
+ LAST_TCK_CYCLE_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+ EXPECTED_TDO_OUT : out std_logic;
+
+-- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
+ NUMREGS_CONFIGURED_OUT : out std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+ LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0)
+
+
+ );
+end entity;
+
+architecture jtag_write_m10_arch of jtag_write_m10 is
+
+-- this state controls the global behaviour. on reset state idle is entered,
+-- on trigger wait_begin_jtagbitcalc is entered
+-- when begin_jtagbitcalc is set, state becomes either idle or
+-- processing and after finished wait_begin_jtagbitcalc is entered again
+type state_type is (idle, wait_begin_jtagbitcalc, processing);
+signal state, state_next : state_type;
+-- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz.
+type substate_type is (newchip_p1, newchip_IR_wait_p2, newchip_IR_wait_p3, newchip_IR_p4, newchip_DR_p2, newchip_DR_p3, newchip_DR_wait_p4, newchip_DR_p5, samechip_newword_DR_p1, newword_wait_p6, newword_p7, setOutputs_p8);
+signal substate, substate_next : substate_type;
+
+-- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": WRITE_DR, operation = "11": none
+-- the operation is set on entering processing state, in setup operation is set to none
+signal operation, operation_next : unsigned(1 downto 0);
+--
+-- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset
+-- WRITE_IR: operation_phase = 0000 : set TMS=0 => Run-Test/Idle
+-- operation_phase = 0001 : set TMS=1 => Select-DR-Scan
+-- operation_phase = 0010 : set TMS=1 => Select-IR-Scan
+-- operation_phase = 0011 : set TMS=0 => Capture-IR
+-- operation_phase = 0100 : set TMS=0 => Shift-IR
+-- operation_phase = 0101 : set TMS=0 => Shift-IR, HERE SHIFTING OF DATA HAPPENS
+-- operation_phase = 0110 : set TMS=1 => Exit1-IR, HERE LAST BIT OF IR IS SHIFTED
+-- operation_phase = 0111 : set TMS=1 => Update-IR
+-- operation_phase = 1000 : set TMS=0 => Run-Test/Idle
+-- WRITE_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan
+-- operation_phase = 0001 : set TMS=0 => Capture-DR
+-- operation_phase = 0010 : set TMS=0 => Shift-DR
+-- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS
+-- operation_phase = 0100 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED
+-- operation_phase = 0101 : set TMS=1 => Update-DR
+-- operation_phase = 0110 : set TMS=0 => Run-Test/Idle
+-- warning: operation phase may change during processing (because length of register is retrieved from RAM)
+-- but will settle from setOutputs_p8 on
+signal operation_phase, operation_phase_next : unsigned(3 downto 0);
+
+-- In processing state: the register that is currently being written. if regcounter >= numregs of the current chip,
+-- the bypass register is selected (IR=FFFF...F, opcode all ones, see http://en.wikipedia.org/wiki/Joint_Test_Action_Group).
+ -- set to 0 in setup, valid when entering processing, incremented on first JTAG clock cycle belonging to next register
+ -- this means it is incremented on entering processing with JTAG_RESET operation
+signal regcounter, regcounter_next : unsigned(MAX_REGISTERS_LD -1 downto 0);
+
+-- number of registers for current chip,
+-- warning: set while processing
+signal numregs, numregs_next : unsigned(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+-- after the first run through WRITE_IR, maxnumregs equals the maximum value of numregs entry in RAM_JTAG_REGISTERS structure
+signal maxnumregs, maxnumregs_next : unsigned(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+
+-- chipcounter: in processing state: chip-nr. to which the requested bit belongs
+-- set to value for next processing run when leaving state wait_begin_jtagbitcalc
+signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD -1 downto 0);
+
+-- bitcounter: in processing state: bit-nr. inside current chip
+-- set to value for next processing run when leaving state wait_begin_jtagbitcalc,
+-- reset to 0 when chipcounter is changed
+signal bitcounter, bitcounter_next : unsigned(MAX_REGLEN_LD-1 downto 0);
+
+
+-- length: this is the length of the DR/IR respectively of the currently active chip,
+-- warning: this becomes valid only after some processing steps of the first bit for each chip,
+-- but will be valid 10 clock cycles after begin_jtagbitcalc
+-- length = 0 is not allowed
+signal length, length_next : unsigned(MAX_REGLEN_PLUS_ONE_LD-1 downto 0);
+
+-- data_word: value of 32 bit DR/IR word
+signal data_word, data_word_next : std_logic_vector(31 downto 0);
+
+-- dr_pointer: Pointer to DR inside memory area of chip,
+-- so only the lower bits of the address are stored, the rest is stored as chipcounter
+signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
+
+-- JTAG output signal: TDI
+signal tdi, tdi_next : std_logic;
+
+-- JTAG output signal: TMS
+signal tms, tms_next : std_logic;
+
+-- indicates this is the last TCK clock cycle for this write operation
+signal last_tck_cycle, last_tck_cycle_next : std_logic;
+
+-- RAM address
+signal ram_jtag_registers_a, ram_jtag_registers_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+
+-- debugging register
+-- "001": length 0 register found, this is not allowed
+signal last_error_code, last_error_code_next : std_logic_vector(2 downto 0);
+
+-- next_not_removed_chip:
+-- the correct slice from NEXT_NOT_REMOVED_IN, depending on the current value of chipcounter
+signal nxt_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+signal first_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
+
+constant invalid_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) := (others => '1');
+
+-- should a JTAG clock pulse be generated this global_jtag_counter cycle?
+signal enable_jtag_clock, enable_jtag_clock_next : std_logic;
+
+signal numregs_configured, numregs_configured_next : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
+
+-- INSERTLABEL: signals
+begin
+
+NUMREGS_CONFIGURED_OUT <= numregs_configured;
+
+process(CLK_IN)
+begin
+ if(rising_edge(CLK_IN)) then
+ if(RESET_IN='1') then
+ state <= idle;
+ substate <= newchip_p1;
+ operation <= "11";
+ operation_phase <= "0000";
+ regcounter <= (others => '0');
+ numregs <= (others => '0');
+ maxnumregs <= (others => '0');
+ chipcounter <= (others => '0');
+ bitcounter <= (others => '0');
+ length <= (others => '0');
+ data_word <= (others => '0');
+ dr_pointer <= (others => '0');
+ last_error_code <= (others => '0');
+ tdi <= '0';
+ tms <= '0';
+ last_tck_cycle <= '0';
+ ram_jtag_registers_a <= (others => '0');
+ enable_jtag_clock <= '0';
+ numregs_configured <= (others => '0');
+ -- INSERTLABEL: SYNCHRONOUS reset
+ else
+ state <= state_next;
+ substate <= substate_next;
+ operation <= operation_next;
+ operation_phase <= operation_phase_next;
+ regcounter <= regcounter_next;
+ numregs <= numregs_next;
+ maxnumregs <= maxnumregs_next;
+ chipcounter <= chipcounter_next;
+ bitcounter <= bitcounter_next;
+ length <= length_next;
+ data_word <= data_word_next;
+ dr_pointer <= dr_pointer_next;
+ last_error_code <= last_error_code_next;
+ tdi <= tdi_next;
+ tms <= tms_next;
+ last_tck_cycle <= last_tck_cycle_next;
+ ram_jtag_registers_a <= ram_jtag_registers_a_next;
+ enable_jtag_clock <= enable_jtag_clock_next;
+ numregs_configured <= numregs_configured_next;
+
+ -- INSERTLABEL: SYNCHRONOUS update
+ end if;
+ end if;
+end process;
+
+RAM_JTAG_REGISTERS_A_OUT <= ram_jtag_registers_a;
+LAST_TCK_CYCLE_OUT <= last_tck_cycle;
+ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock;
+TDI_OUT <= tdi;
+TMS_OUT <= tms;
+IS_DR_BIT_OUT <= '1' when operation = "10" and (operation_phase = "0011" or operation_phase = "0100") else '0';
+IS_FIRSTBIT_OUT <= '1' when to_integer(bitcounter) = 0 else '0';
+IS_LASTBIT_OUT <= '1' when to_integer(bitcounter)+1 = to_integer(length) else '0';
+CHIPNUM_OUT <= std_logic_vector(chipcounter);
+REGNUM_OUT <= std_logic_vector(regcounter);
+EXPECTED_TDO_OUT <= tdi;
+IDLE_OUT <= '1' when state = idle else '0';
+-- for this assignment to be valid, 0 <= chipcounter< MAX_NUMCHIPS has to be true
+nxt_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN((to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD)); -- first entry points to first not removed chip
+first_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN(MAX_NUMCHIPS_PLUS_ONE_LD - 1 downto 0));
+
+LAST_ERROR_CODE_OUT <= last_error_code;
+
+process(regcounter, maxnumregs, chipcounter, bitcounter, TRIGGER_BEGIN_WRITE_IN, BEGIN_JTAGBITCALC_IN, state, substate, operation, operation_phase, length, data_word, numregs, tdi, tms, dr_pointer, last_error_code, ram_jtag_registers_a, RAM_JTAG_REGISTERS_D_IN,enable_jtag_clock, first_not_removed_chip, nxt_not_removed_chip, last_tck_cycle, numregs_configured) -- INSERTLABEL: sensitivity list
+begin
+ bitcounter_next <= bitcounter;
+ chipcounter_next <= chipcounter;
+ regcounter_next <= regcounter;
+ maxnumregs_next <= maxnumregs;
+ operation_next <= operation;
+ operation_phase_next <= operation_phase;
+ state_next <= state;
+ substate_next <= substate;
+ length_next <= length;
+ data_word_next <= data_word;
+ numregs_next <= numregs;
+ tdi_next <= tdi;
+ tms_next <= tms;
+ dr_pointer_next <= dr_pointer;
+ last_error_code_next <= last_error_code;
+ ram_jtag_registers_a_next <= ram_jtag_registers_a;
+ last_tck_cycle_next <= last_tck_cycle;
+ enable_jtag_clock_next <= enable_jtag_clock;
+ numregs_configured_next <= numregs_configured;
+ -- INSERTLABEL: COMB defaults
+ case state is
+ when idle =>
+ last_tck_cycle_next <= '0';
+ if(TRIGGER_BEGIN_WRITE_IN = '1') then
+ state_next <= wait_begin_jtagbitcalc;
+ operation_next <= "11"; -- none
+ end if;
+ when wait_begin_jtagbitcalc =>
+ if(BEGIN_JTAGBITCALC_IN='1') then
+ state_next <= processing;
+ operation_phase_next <= operation_phase + 1;
+ -- last operation was: none => first JTAG clock cycle, reset
+ if(operation = "11") then
+ regcounter_next <= (others => '0');
+ maxnumregs_next <= (others => '0');
+ operation_next <= "00"; -- JTAG_RESET
+ operation_phase_next <= "0000"; -- Bit Nr. 0
+ enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation
+ substate_next <= setOutputs_p8; -- only output for JTAG_RESET
+
+
+ -- last operation was: JTAG_RESET
+ elsif(operation = "00") then
+ if(operation_phase = "0101") then
+ if(first_not_removed_chip /= invalid_chip) then
+ chipcounter_next <= first_not_removed_chip;
+ operation_next <= "01"; -- WRITE_IR
+ operation_phase_next <= "0000";
+ bitcounter_next <= (others => '0');
+ else
+ -- ERROR: no not removed chips
+ state_next <= idle;
+ end if;
+ end if;
+
+ -- last operation was: WRITE_IR
+ elsif(operation = "01") then
+ substate_next <= setOutputs_p8; -- output has to be done in all cases, only sometimes need to do more
+ if(operation_phase = "0100") then -- Shift-IR entered in last operation
+ substate_next <= newchip_p1;
+ elsif(operation_phase = "0101") then -- Shift-IR
+ -- stay in this phase until the instruction registers (of all chips) have been shifted
+ operation_phase_next <= operation_phase;
+ -- -- we do not need to get a new word, because IR is at most 32 bits.
+ --if(bitcounter(4 downto 0) = "11111" ) then
+ -- substate_next <= getIRword_p3;
+ --end if;
+
+ -- do we need to change to the next not removed chip or finish the register?
+ if(bitcounter >= length -1) then
+ bitcounter_next <= (others => '0');
+ -- set the next not removed chip as the chip the following data is for
+ chipcounter_next <= nxt_not_removed_chip;
+ -- treat as new chip (get numregs, length, IRWord..)
+ substate_next <= newchip_p1;
+ else
+ bitcounter_next <= bitcounter + 1;
+ end if;
+ if (bitcounter = length -2) then
+ -- if next chip is 0, this means the current chip is the last chip and we finish the register with the next bit
+ if(nxt_not_removed_chip = invalid_chip) then
+ -- finish register
+ operation_phase_next <= operation_phase + 1;
+ end if;
+ end if;
+ -- length is set, because first operation already finished, here, so we can test it
+ if(to_integer(length) > 32) then
+ state_next <= idle;
+ last_error_code_next <= "011"; -- IR larger than 32 bit
+ end if;
+ elsif(operation_phase = "1000") then -- Run-Test-Idle
+ operation_next <= "10"; -- WRITE_DR
+ operation_phase_next <= "0000"; -- Select-DR-Scan
+ chipcounter_next <= first_not_removed_chip; -- reset chipcounter -- bug fixed (was set to 0)
+ bitcounter_next <= (others => '0'); -- reset bitcounter
+ end if;
+
+ --last operation was: WRITE_DR
+ elsif(operation = "10") then
+ substate_next <= setOutputs_p8; -- output has to be done in all cases, only sometimes need to do more
+ if(operation_phase = "0010") then -- Shift-DR entered in last operation, but nothing shifted yet
+ substate_next <= newchip_p1;
+ elsif(operation_phase = "0011") then -- Shift-DR
+ -- stay in this phase until the data registers (of all chips) have been shifted
+ operation_phase_next <= operation_phase;
+ -- do we need to get a new word
+ if(bitcounter(4 downto 0) = "11111") then
+ substate_next <= samechip_newword_DR_p1;
+ end if;
+ -- do we need to change to the next not removed chip or finish the register?
+ if(bitcounter >= length -1) then
+ -- last bit of chip chipcounter has been sent as last operation
+ -- and we know, that it's not the last chip, otherwise we would be in the next phase
+ -- (this is changed in the processing state, if the last bit of the last chip is reached!)
+ bitcounter_next <= (others => '0');
+ substate_next <= newchip_p1;
+ -- set this as the chip the following data is for
+ chipcounter_next <= nxt_not_removed_chip;
+ else
+ bitcounter_next <= bitcounter + 1;
+ end if;
+ if (bitcounter = length -2) then
+ -- if next chip is 0, this means the current chip is the last chip and we finish the register with the next bit
+ if(nxt_not_removed_chip = invalid_chip) then
+ -- finish register
+ operation_phase_next <= operation_phase + 1;
+ end if;
+ end if;
+ elsif(operation_phase = "0101") then -- Update DR
+ if(regcounter + 1 >= maxnumregs) then --this is the last JTAG clock cycle needed (going back to Run-Test-Idle)
+ last_tck_cycle_next <= '1';
+ end if;
+ elsif(operation_phase = "0110") then -- Run-Test-Idle
+ if(regcounter + 1 < maxnumregs) then
+ regcounter_next <= regcounter + 1; -- start with next register
+ operation_next <= "00"; -- JTAG_RESET
+ operation_phase_next <= "0000"; -- Bit Nr. 0
+ else
+ --operation_next <= "11"; -- none (finished)
+ --operation_phase_next <= "0000";
+ -- the following will deactivate the jtag clock for one cycle, if another write follows,
+ enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation
+ last_tck_cycle_next <= '0';
+ state_next <= idle;
+ end if;
+ end if;
+ end if;
+
+ end if;
+ when processing =>
+ case substate is
+ when newchip_p1 => -- RAM_ADDR_NEXT: Numregs
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= (others => '0'); -- length&numregs
+ if(operation = "01") then
+ substate_next <= newchip_IR_wait_p2;
+ elsif(operation = "10") then
+ substate_next <= newchip_DR_p2;
+ else
+ state_next <= idle;
+ last_error_code_next <= "010"; -- unallowed operation for newchip_p1
+ end if;
+ when newchip_IR_wait_p2 => -- WAIT - need numregs to get IR word
+ substate_next <= newchip_IR_wait_p3;
+ when newchip_IR_wait_p3 => -- WAIT
+ numregs_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0)); -- numregs
+ numregs_configured_next((to_integer(chipcounter)+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto to_integer(chipcounter)*MAX_REGISTERS_PLUS_ONE_LD) <= RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
+ length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD -1+16 downto 16)); -- IRLen
+ substate_next <= newchip_IR_p4;
+ when newchip_IR_p4 => -- RAM_ADDR_NEXT: IR Word
+ -- Update maxnumregs
+ if(maxnumregs < numregs) then
+ maxnumregs_next <= numregs;
+ end if;
+ -- *** RAM address for next next step *** -- WARNING: copy and pasted this block to samechip_newword_IR_p0
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ -- no more registers for this chip?
+ if(regcounter >= numregs) then
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*(to_integer(numregs)+1)+1 + to_integer(numregs), RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- BYPASS IR word
+ else
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*(to_integer(numregs)+1)+1 + to_integer(regcounter), RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- IR word
+ end if;
+ -- *** RAM address for next next step ***
+ substate_next <= newword_wait_p6;
+
+ when newchip_DR_p2 => -- RAM_ADDR_NEXT: DR Pointer
+ -- WRITE_DR
+ -- *** RAM address for next next step ***
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*regcounter + 2); -- DR Pointer
+ -- *** RAM address for next next step ***
+ substate_next <= newchip_DR_p3;
+ when newchip_DR_p3 => -- RAM_ADDR_NEXT: DRLength
+ numregs_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0));
+ -- *** RAM address for next next step ***
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*regcounter + 3);
+ -- *** RAM address for next next step ***
+ substate_next <= newchip_DR_wait_p4;
+ when newchip_DR_wait_p4 =>
+ -- Check if bypass register is loaded
+ if(to_integer(regcounter) >= to_integer(numregs)) then
+ -- BYPASS register loaded
+ length_next <= to_unsigned(1,MAX_REGLEN_PLUS_ONE_LD);
+ data_word_next <= (others => '0');
+ if(to_integer(nxt_not_removed_chip ) = 0) then
+ operation_phase_next <= operation_phase + 1;
+ end if;
+ substate_next <= setOutputs_p8;
+ else -- normal operation
+ dr_pointer_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0));
+ substate_next <= newchip_DR_p5;
+ end if;
+ when newchip_DR_p5 => -- RAM_ADDR_NEXT: DR data word
+ length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0));
+ -- *** RAM address for next next step *** -- WARNING: copy and pasted this block to samechip_newword_DR_p1
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3);
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word
+ -- *** RAM address for next next step ***
+ substate_next <= newword_wait_p6;
+ when newword_wait_p6 =>
+ if(to_integer(length) = 0) then
+ state_next <= idle;
+ last_error_code_next <= "001";
+ else
+ -- if only one bit in ir/dr, and this is the last chip, then we have to go to Exit1-IR/DR in this operation, this is why the decision can't be taken before processing in all cases
+ if((length = 1) and (nxt_not_removed_chip = invalid_chip)) then
+ operation_phase_next <= operation_phase + 1;
+ end if;
+ substate_next <= newword_p7;
+ end if;
+ when newword_p7 => -- get data word
+ data_word_next <= RAM_JTAG_REGISTERS_D_IN;
+ substate_next <= setOutputs_p8;
+
+-- IR only has maximum of 32 bit, so there is no state samechip_newword_IR_p1
+ when samechip_newword_DR_p1 =>
+ -- *** RAM address for next next step *** -- WARNING: copy and pasted this block from newchip_DR_p5
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+ --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3);
+ ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word
+ -- *** RAM address for next next step ***
+ substate_next <= newword_wait_p6;
+--
+-- when getDRptr_p2 =>
+-- -- *** do stuff with data from last step
+-- if(maxnumregs < numregs) then
+-- maxnumregs_next <= numregs;
+-- end if;
+-- -- *** end stuff with data from last step
+--
+-- dr_pointer_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0));
+-- -- *** RAM address for next step ***
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+-- -- no more registers for this chip?
+-- if(regcounter >= numregs) then
+-- length_next <= to_unsigned(1, length'length); -- Loaded BYPASS register (length=1)
+-- substate_next <= setOutputs_p5;
+-- else
+-- --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3);
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*regcounter + 3);
+-- substate_next <= getDRlength_p3;
+-- end if;
+-- -- *** RAM address for next step ***
+-- when getDRlength_p3 =>
+-- length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0));
+-- -- *** RAM address for next step: getDRword ***
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+-- --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3);
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word
+-- -- *** RAM address for next step ***
+-- substate_next <= getDRword_p4;
+-- when getDRword_p4 =>
+-- if(to_integer(length) = 0) then
+-- state_next <= idle;
+-- last_error_code_next <= "001";
+-- else
+-- -- if only one bit in dr, then we have to go to Exit1-DR in this operation
+-- if(to_integer(length) = 1) then
+-- operation_phase_next <= operation_phase + 1;
+-- end if;
+-- data_word_next <= RAM_JTAG_REGISTERS_D_IN;
+-- substate_next <= setOutputs_p5;
+-- end if;
+-- when getIRlength_p2 =>
+-- length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0));
+-- -- *** RAM address for next step: getIRword ***
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address
+-- -- no more registers for this chip?
+-- if(regcounter >= numregs) then
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*(numregs+1)+1 + numregs); -- BYPASS IR word
+-- else
+-- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*(numregs+1)+1 + regcounter); -- IR word
+-- end if;
+-- -- *** RAM address for next step ***
+-- substate_next <= getIRword_p3;
+-- when getIRword_p3 =>
+-- if(to_integer(length) = 0) then
+-- state_next <= idle;
+-- last_error_code_next <= "001";
+-- else
+-- -- if only one bit in ir, then we have to go to Exit1-IR in this operation
+-- if(to_integer(length) = 1) then
+-- operation_phase_next <= operation_phase + 1;
+-- end if;
+-- data_word_next <= RAM_JTAG_REGISTERS_D_IN;
+-- substate_next <= setOutputs_p5;
+-- end if;
+ when setOutputs_p8 =>
+ tdi_next <= data_word(to_integer(bitcounter(4 downto 0)));
+ if(operation = "00") then -- JTAG_RESET
+ tms_next <= '1';
+ elsif(operation = "01") then -- WRITE_IR
+ if(operation_phase = "0001") then
+ tms_next <= '1';
+ elsif(operation_phase = "0010") then
+ tms_next <= '1';
+ elsif(operation_phase = "0110") then
+ tms_next <= '1';
+ elsif(operation_phase = "0111") then
+ tms_next <= '1';
+ else
+ tms_next <= '0';
+ end if;
+ elsif(operation = "10") then -- WRITE_DR
+ if(operation_phase = "0000") then
+ tms_next <= '1';
+ elsif(operation_phase = "0100") then
+ tms_next <= '1';
+ elsif(operation_phase = "0101") then
+ tms_next <= '1';
+ else
+ tms_next <= '0';
+ end if;
+ end if;
+ -- finished processing
+ state_next <= wait_begin_jtagbitcalc;
+ end case;
+ end case;
+end process;
+
+
+end architecture;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+--use work.trb_net_std.all;
+
+entity ram_dp is
+ generic(
+ depth : integer := 3;
+ width : integer := 16
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(depth-1 downto 0);
+ dout1 : out std_logic_vector(width-1 downto 0);
+ din1 : in std_logic_vector(width-1 downto 0);
+ a2 : in std_logic_vector(depth-1 downto 0);
+ dout2 : out std_logic_vector(width-1 downto 0)
+ );
+end entity;
+
+architecture ram_dp_arch of ram_dp is
+ type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
+ SIGNAL ram : ram_t ; -- := (others => (others => '0'));
+begin
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if wr1 = '1' then
+ ram((conv_integer(a1))) <= din1;
+ dout1 <= din1;
+ else
+ dout1 <= ram(conv_integer(a1));
+ end if;
+ dout2 <= ram(conv_integer(a2));
+ end if;
+ end process;
+
+end architecture;
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+\r
+entity ram_mux2to1_readport is\r
+ generic (\r
+ depth : integer;\r
+ width : integer := 32\r
+ );\r
+ port (\r
+ SELECT_IN : std_logic;\r
+ A0_IN : in std_logic_vector(depth-1 downto 0);\r
+ D0_OUT : out std_logic_vector(width-1 downto 0);\r
+ A1_IN : in std_logic_vector(depth-1 downto 0);\r
+ D1_OUT : out std_logic_vector(width-1 downto 0);\r
+ \r
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);\r
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture ram_mux2to1_readport_arch of ram_mux2to1_readport is\r
+signal addr : std_logic_vector(depth-1 downto 0);\r
+begin\r
+\r
+addr <= A0_IN when SELECT_IN = '0' else A1_IN;\r
+RAM_A_OUT <= addr;\r
+\r
+D0_OUT <= RAM_DOUT_IN;\r
+D1_OUT <= RAM_DOUT_IN;\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+\r
+entity ram_mux2to1_writeport is\r
+ generic (\r
+ depth : integer;\r
+ width : integer := 32\r
+ );\r
+ port (\r
+ SELECT_IN : in std_logic;\r
+ A0_IN : in std_logic_vector(depth-1 downto 0);\r
+ D0_OUT : out std_logic_vector(width-1 downto 0);\r
+ WR0_IN : in std_logic;\r
+ DIN0_IN : in std_logic_vector(width-1 downto 0);\r
+ \r
+ A1_IN : in std_logic_vector(depth-1 downto 0);\r
+ D1_OUT : out std_logic_vector(width-1 downto 0);\r
+ WR1_IN : in std_logic;\r
+ DIN1_IN : in std_logic_vector(width-1 downto 0);\r
+ \r
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);\r
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0);\r
+ RAM_WR_OUT : out std_logic;\r
+ RAM_DIN_OUT : out std_logic_vector(width-1 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture ram_mux2to1_writeport_arch of ram_mux2to1_writeport is\r
+signal addr : std_logic_vector(depth-1 downto 0);\r
+signal wr : std_logic;\r
+signal din : std_logic_vector(width-1 downto 0);\r
+begin\r
+\r
+addr <= A0_IN when SELECT_IN = '0' else A1_IN;\r
+RAM_A_OUT <= addr;\r
+\r
+wr <= WR0_IN when SELECT_IN = '0' else WR1_IN;\r
+RAM_WR_OUT <= wr;\r
+\r
+din <= DIN0_IN when SELECT_IN = '0' else DIN1_IN;\r
+RAM_DIN_OUT <= din;\r
+D0_OUT <= RAM_DOUT_IN;\r
+D1_OUT <= RAM_DOUT_IN;\r
+\r
+end architecture;\r
--- /dev/null
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+\r
+library work;\r
+\r
+entity ram_mux4to1_readport is\r
+ generic (\r
+ depth : integer;\r
+ width : integer := 32\r
+ );\r
+ port (\r
+ SELECT_IN : in std_logic_vector(1 downto 0); -- two bit select input\r
+ A0_IN : in std_logic_vector(depth-1 downto 0);\r
+ D0_OUT : out std_logic_vector(width-1 downto 0);\r
+ A1_IN : in std_logic_vector(depth-1 downto 0);\r
+ D1_OUT : out std_logic_vector(width-1 downto 0);\r
+ A2_IN : in std_logic_vector(depth-1 downto 0);\r
+ D2_OUT : out std_logic_vector(width-1 downto 0);\r
+ A3_IN : in std_logic_vector(depth-1 downto 0);\r
+ D3_OUT : out std_logic_vector(width-1 downto 0);\r
+ \r
+ RAM_A_OUT : out std_logic_vector(depth-1 downto 0);\r
+ RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture ram_mux4to1_readport_arch of ram_mux4to1_readport is\r
+--signal addr : std_logic_vector(depth-1 downto 0);\r
+begin\r
+\r
+--addr <= A0_IN when SELECT_IN = "00" else A1_IN when SELECT_IN = "01" else\r
+-- A2_IN when SELECT_IN = "10" else A3_IN;\r
+ \r
+--process (addr, SELECT_IN, A0_IN, A1_IN, A2_IN, A3_IN)\r
+--begin\r
+-- RAM_A_OUT <= addr;\r
+--end process;\r
+RAM_A_OUT <= A0_IN when SELECT_IN = "00" else A1_IN when SELECT_IN = "01" else\r
+ A2_IN when SELECT_IN = "10" else A3_IN;\r
+\r
+D0_OUT <= RAM_DOUT_IN;\r
+D1_OUT <= RAM_DOUT_IN;\r
+D2_OUT <= RAM_DOUT_IN;\r
+D3_OUT <= RAM_DOUT_IN;\r
+\r
+end architecture;\r
--- /dev/null
+Index: jtag_write_m10.vhd
+===================================================================
+--- jtag_write_m10.vhd (revision 160)
++++ jtag_write_m10.vhd (working copy)
+@@ -333,7 +333,7 @@
+ elsif(operation_phase = "1000") then -- Run-Test-Idle
+ operation_next <= "10"; -- WRITE_DR
+ operation_phase_next <= "0000"; -- Select-DR-Scan
+- chipcounter_next <= (others => '0'); -- reset chipcounter
++ chipcounter_next <= first_not_removed_chip; -- reset chipcounter -- bug fixed (was set to 0)
+ bitcounter_next <= (others => '0'); -- reset bitcounter
+ end if;
+
+Index: jtag_cmd_m26c.vhd
+===================================================================
+--- jtag_cmd_m26c.vhd (revision 166)
++++ jtag_cmd_m26c.vhd (working copy)
+@@ -2357,7 +2357,7 @@
+ if(chip_counter_start = '1') then
+ -- determine number of chips connected in serial to jtag chain
+ cc_chip_i_next <= (others => '0');
+- cc_nextnotremoved_i_next <= (others => '0');
++ cc_nextnotremoved_i_next <= (others => '0'); --position in jtag_next_not_removed,
+ -- with the following initialization no chip will be unremoved, because
+ -- last_not_removed < first_not_removed
+ -- and numchips_active will be set to 0 if really all chips are removed
+@@ -2376,16 +2376,16 @@
+ first_not_removed_next <= cc_chip_i;
+ end if;
+ cc_nextnotremoved_i_next <= cc_chip_i + 1; -- next not removed chip after chip i is stored at location (i+1) in jtag_next_not_removed
+- jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_LD) <=
++ jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD) <=
+ std_logic_vector(cc_chip_i);
+ end if;
+ if(cc_chip_i = numchips_configured - 1) then
+- jtag_next_not_removed_next((to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto (to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_LD) <= (others => '1'); -- set next chip for last chip to invalid
+ cc_state_next <= CC_SETNUMCHIPS; -- finished counting active chips
+ else
+ cc_chip_i_next <= cc_chip_i + 1;
+ end if;
+ when CC_SETNUMCHIPS =>
++ jtag_next_not_removed_next((to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '1'); -- set next chip for last chip to invalid
+ numchips_active_next <= numchips_active_acc;
+ cc_state_next <= CC_IDLE;
+ end case;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+--USE IEEE.std_logic_ARITH.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+--use work.version.all;
+use work.jtag_constants.all;
+
+
+
+entity jtag_cmd_m26c_test is
+end entity;
+
+
+architecture arch of jtag_cmd_m26c_test is
+component CRC_32 is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ CRC_OUT : out std_logic_vector(31 downto 0);
+ CRC_match : out std_logic
+ );
+end component;
+--
+component jtag_cmd_m26c is
+ generic(
+ MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
+ MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
+ MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
+ MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
+ MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
+ MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
+ MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
+ MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
+
+ WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
+
+ READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
+
+ JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
+ JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
+ JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
+ JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
+
+ RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit.
+-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
+ JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
+ JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
+ JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2 -- ceil of ld( value plus one)
+);
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_TMS_OUT : out std_logic;
+ JTAG_TCK_OUT : out std_logic;
+ JTAG_TDI_OUT : out std_logic;
+ JTAG_TDO_IN : in std_logic;
+
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+
+ OFF_SPILL_IN : in std_logic;
+ MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ IDLE_OUT : out std_logic;
+ PROG_JTAG_FINISHED_OUT:out std_logic;
+ READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ RUN_COUNTER_OUT : out std_logic_vector(31 downto 0);
+
+ STARTED_OUT : out std_logic;
+ LAST_RUN_SUCCESSFUL_OUT : out std_logic;
+ LAST_DATA_CHANGED_OUT : out std_logic;
+ LAST_WRITE_ERRORS_OUT : out std_logic;
+ LAST_READ_ERRORS_OUT : out std_logic;
+ CRC_ERROR_OUT : out std_logic
+
+ --BUS_TIMEOUT_IN : in std_logic;
+ );
+end component;
+--component jtag_cmd_m26c is
+-- port(
+-- CLK_IN : in std_logic;
+-- RESET_IN : in std_logic;
+--
+-- JTAG_TMS_OUT : out std_logic;
+-- JTAG_TCK_OUT : out std_logic;
+-- JTAG_TDI_OUT : out std_logic;
+-- JTAG_TDO_IN : in std_logic;
+--
+-- BUS_DATA_IN : in std_logic_vector(31 downto 0);
+-- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+-- BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+-- BUS_READ_IN : in std_logic;
+-- BUS_WRITE_IN : in std_logic;
+-- BUS_DATAREADY_OUT : out std_logic;
+-- BUS_NO_MORE_DATA_OUT : out std_logic;
+-- BUS_WRITE_ACK_OUT : out std_logic;
+-- BUS_UNKNOWN_ADDR_OUT : out std_logic;
+-- OFF_SPILL_IN : in std_logic;
+-- MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+-- --MON_FIFO_DATA_OUT : out std_logic_vector(511 downto 0);
+-- --MON_FIFO_WRITE_OUT : out std_logic_vector(15 downto 0);
+--
+-- IDLE_OUT : out std_logic;
+-- PROG_JTAG_FINISHED_OUT:out std_logic
+-- );
+--end component;
+component top is
+port(
+ TCK_EMU: in std_logic;
+ TMS_EMU: in std_logic;
+ TDI_EMU: in std_logic;
+ TDO_EMU: out std_logic;
+ TRSTB_EMU: in std_logic
+ );
+
+end component;
+signal clk_in, reset_in : std_logic;
+signal jtag_tms_out, jtag_tck_out, jtag_tdi_out, jtag_tdo_in, trstb : std_logic;
+signal bus_data_in : std_logic_vector(31 downto 0);
+signal bus_data_out : std_logic_vector(31 downto 0);
+signal bus_addr_in : std_logic_vector(15 downto 0);
+signal bus_read_in : std_logic;
+signal bus_write_in : std_logic;
+signal bus_dataready_out : std_logic;
+signal bus_no_more_data_out : std_logic;
+signal bus_write_ack_out : std_logic;
+signal bus_unknown_addr_out : std_logic;
+signal trigger_jtag_write : std_logic;
+signal prog_jtag_finished_out : std_logic;
+signal idle_out : std_logic;
+constant RAM_JTAG_REGISTERS_DEPTH : integer := 11;
+
+signal ramcounter : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal statuscounter : std_logic_vector(4 downto 0);
+signal crc32_1_clk_en : std_logic;
+signal crc32_reset_in : std_logic;
+signal crc32_1_data_in : std_logic_vector(31 downto 0);
+signal crc32_1_crc_out : std_logic_vector(31 downto 0);
+signal a,b : std_logic_vector(3 downto 0);
+signal ergebnis : std_logic_vector(7 downto 0);
+signal jtag1_out : std_logic;
+signal jtag2_out : std_logic;
+signal jtag3_in : std_logic;
+signal broken : std_logic;
+
+--signal data_in, ready_for_cmd_out, data_out, data_arrived_out : std_logic;
+begin
+crc32_1: CRC_32 port map(
+ CLK => clk_in,
+ RESET => crc32_reset_in,
+ CLK_EN => crc32_1_clk_en,
+ DATA_IN => crc32_1_data_in,
+ CRC_OUT => crc32_1_crc_out,
+ CRC_match => open
+ );
+jtag_test1 : jtag_cmd_m26c port map( CLK_IN => clk_in,
+ RESET_IN => reset_in,
+ JTAG_TMS_OUT => jtag_tms_out,
+ JTAG_TCK_OUT => jtag_tck_out,
+ JTAG_TDI_OUT => jtag_tdi_out,
+ JTAG_TDO_IN => jtag_tdo_in,
+ BUS_DATA_IN => bus_data_in,
+ BUS_DATA_OUT => bus_data_out,
+ BUS_ADDR_IN => bus_addr_in(8 downto 0),
+ BUS_READ_IN => bus_read_in,
+ BUS_WRITE_IN => bus_write_in,
+ BUS_DATAREADY_OUT => bus_dataready_out,
+ BUS_NO_MORE_DATA_OUT => bus_no_more_data_out,
+ BUS_WRITE_ACK_OUT => bus_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => bus_unknown_addr_out,
+ OFF_SPILL_IN => trigger_jtag_write,
+ IDLE_OUT => idle_out,
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished_out
+);
+--top1 : top port map( TCK_EMU => jtag_tck_out,
+-- TMS_EMU => jtag_tms_out,
+-- TDI_EMU => jtag_tdi_out,
+-- TDO_EMU => jtag1_out,
+-- TRSTB_EMU => trstb
+--);
+--top2 : top port map( TCK_EMU => jtag_tck_out,
+-- TMS_EMU => jtag_tms_out,
+-- TDI_EMU => jtag1_out,
+-- TDO_EMU => jtag2_out,
+-- TRSTB_EMU => trstb
+--);
+--top3 : top port map( TCK_EMU => jtag_tck_out,
+-- TMS_EMU => jtag_tms_out,
+-- TDI_EMU => jtag3_in,
+-- TDO_EMU => jtag_tdo_in,
+-- TRSTB_EMU => trstb
+--);
+
+jtag3_in <= jtag2_out when broken = '0' else '0';
+testtest_commands : process
+begin
+ --jtag_tdo_in <= '0';
+ broken <= '0';
+ bus_addr_in(15 downto 0) <= x"0000";
+ bus_data_in(31 downto 8) <= x"000000";
+ bus_data_in(7 downto 0) <= M26C_CMD_NONE;
+ bus_write_in <= '0';
+ bus_read_in <= '0';
+ trigger_jtag_write <= '0';
+ ramcounter <= (others => '0');
+ statuscounter <= (others => '0');
+ crc32_1_data_in <= x"00000000";
+ crc32_1_clk_en <= '0';
+ trstb <= '1';
+ reset_in <= '1';
+ crc32_reset_in <= '1';
+ wait for 200 ns;
+ trstb <= '0';
+ reset_in <= '0';
+ crc32_reset_in <= '0';
+ wait for 200 ns;
+ trstb <= '1';
+ wait for 100 ns;
+
+
+
+ CHIPLOOP: for i in 2 downto 0 loop
+ crc32_reset_in <= '1';
+ wait for 200 ns;
+ crc32_reset_in <= '0';
+ wait for 200 ns;
+ ramcounter <= (others => '0');
+
+ bus_data_in(31 downto 0) <= std_logic_vector(to_unsigned(i,32));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_RAM_BASEADDR;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ wait until rising_edge(bus_write_ack_out);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0005000B"; -- line 1
+ crc32_1_data_in <= x"0005000B";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"4D323601"; -- line 2
+ crc32_1_data_in <= x"4D323601";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000025"; -- line 3
+ crc32_1_data_in <= x"00000025";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000098"; -- line 4
+ crc32_1_data_in <= x"00000098";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000002A"; -- line 5
+ crc32_1_data_in <= x"0000002A";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000008"; -- line 6
+ crc32_1_data_in <= x"00000008";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000002B"; -- line 7
+ crc32_1_data_in <= x"0000002B";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000008"; -- line 8
+ crc32_1_data_in <= x"00000008";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000002C"; -- line 9
+ crc32_1_data_in <= x"0000002C";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000028"; -- line 10
+ crc32_1_data_in <= x"00000028";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000002E"; -- line 11
+ crc32_1_data_in <= x"0000002E";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000080"; -- line 12
+ crc32_1_data_in <= x"00000080";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000032"; -- line 13
+ crc32_1_data_in <= x"00000032";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000040"; -- line 14
+ crc32_1_data_in <= x"00000040";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000034"; -- line 15
+ crc32_1_data_in <= x"00000034";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000030"; -- line 16
+ crc32_1_data_in <= x"00000030";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000036"; -- line 17
+ crc32_1_data_in <= x"00000036";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"000000A0"; -- line 18
+ crc32_1_data_in <= x"000000A0";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000003B"; -- line 19
+ crc32_1_data_in <= x"0000003B";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000480"; -- line 20
+ crc32_1_data_in <= x"00000480";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000005F"; -- line 21
+ crc32_1_data_in <= x"0000005F";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000480"; -- line 22
+ crc32_1_data_in <= x"00000480";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000083"; -- line 23
+ crc32_1_data_in <= x"00000083";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000480"; -- line 24
+ crc32_1_data_in <= x"00000480";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"51ED658E"; -- line 25
+ crc32_1_data_in <= x"51ED658E";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000000F"; -- line 26
+ crc32_1_data_in <= x"0000000F";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000001E"; -- line 27
+ crc32_1_data_in <= x"0000001E";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000001D"; -- line 28
+ crc32_1_data_in <= x"0000001D";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000013"; -- line 29
+ crc32_1_data_in <= x"00000013";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000012"; -- line 30
+ crc32_1_data_in <= x"00000012";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000016"; -- line 31
+ crc32_1_data_in <= x"00000016";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000017"; -- line 32
+ crc32_1_data_in <= x"00000017";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000015"; -- line 33
+ crc32_1_data_in <= x"00000015";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000011"; -- line 34
+ crc32_1_data_in <= x"00000011";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000010"; -- line 35
+ crc32_1_data_in <= x"00000010";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000014"; -- line 36
+ crc32_1_data_in <= x"00000014";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0000001F"; -- line 37
+ crc32_1_data_in <= x"0000001F";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"0A0A0A64"; -- line 38
+ crc32_1_data_in <= x"0A0A0A64";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"8020280A"; -- line 39
+ crc32_1_data_in <= x"8020280A";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"FFFF3276"; -- line 40
+ crc32_1_data_in <= x"FFFF3276";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"2076FFAA"; -- line 41
+ crc32_1_data_in <= x"2076FFAA";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00643220"; -- line 42
+ crc32_1_data_in <= x"00643220";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000002"; -- line 43
+ crc32_1_data_in <= x"00000002";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 44
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"23F00000"; -- line 45
+ crc32_1_data_in <= x"23F00000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 46
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"7FFFFFFF"; -- line 47
+ crc32_1_data_in <= x"7FFFFFFF";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"001C6000"; -- line 48
+ crc32_1_data_in <= x"001C6000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"01C03C00"; -- line 49
+ crc32_1_data_in <= x"01C03C00";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"7FFF0040"; -- line 50
+ crc32_1_data_in <= x"7FFF0040";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"FFFFFFFF"; -- line 51
+ crc32_1_data_in <= x"FFFFFFFF";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"AAAAAAAA"; -- line 52
+ crc32_1_data_in <= x"AAAAAAAA";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"FC00E000"; -- line 53
+ crc32_1_data_in <= x"FC00E000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000008"; -- line 54
+ crc32_1_data_in <= x"00000008";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"05552000"; -- line 55
+ crc32_1_data_in <= x"05552000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"E0016000"; -- line 56
+ crc32_1_data_in <= x"E0016000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"82AA0555"; -- line 57
+ crc32_1_data_in <= x"82AA0555";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"10000555"; -- line 58
+ crc32_1_data_in <= x"10000555";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"05553000"; -- line 59
+ crc32_1_data_in <= x"05553000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 60
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 61
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 62
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 63
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 64
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 65
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 66
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 67
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 68
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 69
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 70
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 71
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 72
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 73
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 74
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 75
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 76
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 77
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 78
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 79
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 80
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 81
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 82
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 83
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 84
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 85
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 86
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 87
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 88
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 89
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 90
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 91
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 92
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 93
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"50000000"; -- line 94
+ crc32_1_data_in <= x"50000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"05555555"; -- line 95
+ crc32_1_data_in <= x"05555555";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"33310000"; -- line 96
+ crc32_1_data_in <= x"33310000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 97
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 98
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 99
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 100
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 101
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 102
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 103
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 104
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 105
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 106
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 107
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 108
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 109
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 110
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 111
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 112
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 113
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 114
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 115
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 116
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 117
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 118
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 119
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 120
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 121
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 122
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 123
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 124
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 125
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 126
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 127
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 128
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000000"; -- line 129
+ crc32_1_data_in <= x"00000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"30000000"; -- line 130
+ crc32_1_data_in <= x"30000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00000333"; -- line 131
+ crc32_1_data_in <= x"00000333";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"F6F6FFF1"; -- line 132
+ crc32_1_data_in <= x"F6F6FFF1";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111116"; -- line 133
+ crc32_1_data_in <= x"11111116";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 134
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 135
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 136
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 137
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 138
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 139
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 140
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 141
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 142
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 143
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 144
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 145
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 146
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 147
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 148
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 149
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 150
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 151
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 152
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 153
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 154
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 155
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 156
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 157
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 158
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 159
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 160
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 161
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 162
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 163
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"11111111"; -- line 164
+ crc32_1_data_in <= x"11111111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"00011111"; -- line 165
+ crc32_1_data_in <= x"00011111";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"40000000"; -- line 166
+ crc32_1_data_in <= x"40000000";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"16464646"; -- line 167
+ crc32_1_data_in <= x"16464646";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 0) <= x"1CC3851D"; -- line 168
+ crc32_1_data_in <= x"1CC3851D";
+ bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8);
+ bus_addr_in(7 downto 0) <= ramcounter(7 downto 0);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ crc32_1_clk_en <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ crc32_1_clk_en <= '0';
+ wait until rising_edge(bus_write_ack_out);
+ ramcounter <= std_logic_vector(unsigned(ramcounter) + 1);
+
+ end loop;
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(3,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_NUMCHIPS_CONFIGURED;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(10,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME1;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(0,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME2;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME1;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(6,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME2;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(7,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME3;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(9,8));
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SET_DATA_TIME;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+
+ wait for 500*8 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_START;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- --jtag_tdo_in <= '1';
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- --jtag_tdo_in <= '0';
+
+
+
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= x"07"; -- trigger copy ram1b to ram1c on next read-/write-error/datachanged
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 100 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+ broken <= '1';
+
+wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+
+wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+broken <= '0';
+
+ wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+ wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+ wait until idle_out <= '1';
+trigger_jtag_write <= '1';
+wait until idle_out = '0';
+ trigger_jtag_write <= '0';
+
+wait until idle_out = '1';
+
+
+ wait for 500*8 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= M26C_CMD_COPY_TO_STATUS2;
+ bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 500*8 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= (others => '0');
+ bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_STATUS2_UPDATING;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+ wait for 500*8 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= (others => '0'); -- set baseaddr to 0
+ bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5);
+ bus_addr_in(4 downto 0) <= ADDR_STATUS2_RAM3B_BASEADDR;
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_write_in <= '1';
+ wait for 30 ns;
+ bus_write_in <= '0';
+
+-- read status2 ram (error counters etc...)
+ STATUS2LOOP: for i in 0 to 15 loop
+ wait for 500*8 ns;
+ bus_data_in(31 downto 8) <= (others => '0');
+ bus_data_in(7 downto 0) <= (others => '0');
+ bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5);
+ bus_addr_in(4 downto 0) <= std_logic_vector(unsigned(ADDR_STATUS2_RAM3B_BEGIN) + to_unsigned(i,4));
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_read_in <= '1';
+ wait for 30 ns;
+ bus_read_in <= '0';
+ end loop;
+
+wait for 500*8 ns;
+ bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5);
+ bus_addr_in(4 downto 0) <= statuscounter;
+ statuscounter <= std_logic_vector(unsigned(statuscounter)+1);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_read_in <= '1';
+ wait for 30 ns;
+ bus_read_in <= '0';
+wait for 500*8 ns;
+ bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5);
+ bus_addr_in(4 downto 0) <= statuscounter;
+ statuscounter <= std_logic_vector(unsigned(statuscounter)+1);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_read_in <= '1';
+ wait for 30 ns;
+ bus_read_in <= '0';
+wait for 500*8 ns;
+ bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5);
+ bus_addr_in(4 downto 0) <= statuscounter;
+ statuscounter <= std_logic_vector(unsigned(statuscounter)+1);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_read_in <= '1';
+ wait for 30 ns;
+ bus_read_in <= '0';
+wait for 500*8 ns;
+ bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5);
+ bus_addr_in(4 downto 0) <= statuscounter;
+ statuscounter <= std_logic_vector(unsigned(statuscounter)+1);
+ wait for 20 ns;
+ wait until CLK_IN = '1';
+ bus_read_in <= '1';
+ wait for 30 ns;
+ bus_read_in <= '0';
+--
+-- wait for 500*8 ns;
+-- bus_data_in(31 downto 0) <= x"80FFFF01";
+-- bus_addr_in(3 downto 0) <= ADDR_DATA;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+--
+-- wait for 500*8 ns;
+-- bus_data_in(31 downto 0) <= x"00000020";
+-- bus_addr_in(3 downto 0) <= ADDR_LENGTH;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+--
+-- wait for 500*8 ns;
+-- bus_data_in(3 downto 0) <= CMD_SHIFT_DR;
+-- bus_addr_in(3 downto 0) <= ADDR_CMD;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- --jtag_tdo_in <= '1';
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- --jtag_tdo_in <= '0';
+--
+-- wait for 60*8 us;
+-- wait for 500*8 ns;
+-- bus_data_in(3 downto 0) <= "0000";
+-- bus_addr_in(3 downto 0) <= ADDR_DATA;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+--
+-- wait for 500*8 ns;
+-- bus_data_in(3 downto 0) <= CMD_UPDATE_DR;
+-- bus_addr_in(3 downto 0) <= ADDR_CMD;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+--
+-- wait for 30*8 us;
+-- bus_data_in(3 downto 0) <= "0000";
+-- bus_addr_in(3 downto 0) <= ADDR_DATA;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_read_in <= '1';
+-- wait for 20 ns;
+-- bus_read_in <= '0';
+--
+-- wait for 30*8 us;
+-- jtag_tdo_in <= '1';
+-- bus_data_in(3 downto 0) <= CMD_RESET_JTAG;
+-- bus_addr_in(3 downto 0) <= ADDR_CMD;
+-- wait for 20 ns;
+-- wait until CLK_IN = '1';
+-- bus_write_in <= '1';
+-- wait for 20 ns;
+-- bus_write_in <= '0';
+
+
+-- cmd_in <= CMD_NONE;
+-- wait until READY_FOR_CMD_OUT = '1';
+-- data_in <= '1';
+-- cmd_in <= CMD_SHIFT_DR;
+-- wait for 30 ns;
+-- cmd_in <= CMD_NONE;
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- jtag_tdo_in <= '1';
+-- wait until READY_FOR_CMD_OUT = '1';
+-- data_in <= '1';
+-- cmd_in <= CMD_SHIFT_DR;
+-- wait for 30 ns;
+-- cmd_in <= CMD_NONE;
+-- wait until jtag_tck_out = '1';
+-- wait until jtag_tck_out = '0';
+-- jtag_tdo_in <= '0';
+-- wait until READY_FOR_CMD_OUT = '1';
+-- cmd_in <= CMD_UPDATE_DR;
+-- wait for 30 ns;
+-- cmd_in <= CMD_NONE;
+-- wait until READY_FOR_CMD_OUT = '1';
+-- wait for 30 ns;
+-- cmd_in <= CMD_NONE;
+ wait;
+end process;
+testdriver_clk : process
+begin
+ clk_in <= '0';
+ wait for 5 ns;
+ clk_in <= '1';
+ wait for 5 ns;
+end process;
+
+
+end architecture;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+--USE IEEE.numeric_std.ALL;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+--use work.version.all;
+use work.jtag_constants.all;
+
+entity jtag_write_m10_test is
+end entity;
+
+architecture jtag_write_m10_test_arch of jtag_write_m10_test is
+component jtag_write_m10 is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+ RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
+
+ --RAM_JTAG_REGISTERS_READ_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_READ_DEPTH-1 downto 0);
+ --RAM_JTAG_REGISTERS_READ_D_OUT : out std_logic_vector(31 downto 0);
+ -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
+ -- encoded by the bits NEXT_NOT_REMOVED(i*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto i*MAX_NUMCHIPS_LD)
+ -- which should be interpreted as unsigned
+ NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_LD*MAX_NUMCHIPS-1 downto 0);
+
+ BEGIN_JTAGBITCALC_IN : in std_logic;
+ TRIGGER_BEGIN_WRITE_IN : in std_logic;
+
+ ENABLE_COMPARE_OUT : out std_logic;
+ FINISH_COMPARE_OUT : out std_logic;
+ CHIP_COUNTER_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
+ REG_COUNTER_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
+ ENABLE_JTAG_CLOCK_OUT : out std_logic;
+ TMS_OUT : out std_logic;
+ TDI_OUT : out std_logic;
+
+ LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0)
+
+
+ );
+end component;
+
+
+component CRC_32 is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ CRC_OUT : out std_logic_vector(31 downto 0);
+ CRC_match : out std_logic
+ );
+end component;
+component ram_dp is
+ generic(
+ depth : integer := RAM_JTAG_REGISTERS_DEPTH;
+ width : integer := 32
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(depth-1 downto 0);
+ dout1 : out std_logic_vector(width-1 downto 0);
+ din1 : in std_logic_vector(width-1 downto 0);
+ a2 : in std_logic_vector(depth-1 downto 0);
+ dout2 : out std_logic_vector(width-1 downto 0)
+ );
+end component;
+
+signal chip : std_logic_vector(3 downto 0);
+signal CLK, RESET : std_logic;
+signal ram_read_addr, ram_write_addr : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
+signal ram_read_data, ram_write_datain, ram_write_dataout : std_logic_vector(31 downto 0);
+signal ram_write_wr : std_logic;
+signal ramcounter : std_logic_vector(7 downto 0);
+signal next_not_removed : std_logic_vector(MAX_NUMCHIPS_LD*MAX_NUMCHIPS-1 downto 0);
+signal begin_jtagbitcalc, trigger_begin_write: std_logic;
+begin
+
+the_jtag_write_m10 : jtag_write_m10 port map (CLK_IN => CLK, RESET_IN => RESET,RAM_JTAG_REGISTERS_A_OUT=> ram_read_addr, RAM_JTAG_REGISTERS_D_IN => ram_read_data, NEXT_NOT_REMOVED_IN => next_not_removed, BEGIN_JTAGBITCALC_IN => begin_jtagbitcalc, TRIGGER_BEGIN_WRITE_IN => trigger_begin_write, ENABLE_COMPARE_OUT => open, FINISH_COMPARE_OUT => open, CHIP_COUNTER_OUT => open, REG_COUNTER_OUT => open, ENABLE_JTAG_CLOCK_OUT => open, TMS_OUT => open, TDI_OUT => open, LAST_ERROR_CODE_OUT => open);
+
+the_ram : ram_dp generic map(
+ depth => RAM_JTAG_REGISTERS_DEPTH,
+ width => 32
+ )
+ port map ( CLK=> CLK, wr1=>ram_write_wr, a1 =>ram_write_addr, dout1=>ram_write_dataout, din1=>ram_write_datain, a2=>ram_read_addr, dout2=>ram_read_data);
+
+test_process : process
+begin
+ trigger_begin_write <= '0';
+ begin_jtagbitcalc <= '0';
+ ram_write_wr <= '0';
+ chip <= (others =>'0');
+ ramcounter <= (others =>'0');
+ next_not_removed <= (others =>'0');
+
+
+ RESET <= '1';
+ wait for 40 ns;
+ RESET <= '0';
+ wait for 20 ns;
+
+ ramcounter <= ramcounter + 1;
+
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00050002"; -- numregs, IRLen
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000000"; -- reserved
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000a"; -- Ptr1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000029"; -- Length1 = 41 bit
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000c"; -- Ptr2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000040"; -- Length1 = 64 bit
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000029"; -- CRC-32
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000001E"; -- IR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000E"; -- IR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000001F"; -- IR3 (BYPASS)
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0F0F0F0F"; -- DR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0F0F0F0F"; -- DR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"11111111"; -- DR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"11111111"; -- DR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000E"; -- CRC-32
+ ram_write_wr <= '1';
+ wait for 20 ns;
+
+
+
+
+
+
+
+
+
+ ramcounter <= (others => '0');
+ ram_write_wr <= '0';
+ chip <= "0001";
+
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00050001"; -- numregs, IRLen
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000000"; -- reserved
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000a"; -- Ptr1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000029"; -- Length1 = 41 bit
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000c"; -- Ptr2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000040"; -- Length1 = 64 bit
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00000029"; -- CRC-32
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000001E"; -- IR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000E"; -- IR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000001F"; -- IR3 (BYPASS)
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"AAAAAAAA"; -- DR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"AAAAAAAA"; -- DR1
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00FF00FF"; -- DR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"00FF00FF"; -- DR2
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ramcounter <= ramcounter + 1;
+
+ ram_write_addr(11 downto 8) <= chip;
+ ram_write_addr(7 downto 0) <= ramcounter;
+ ram_write_datain <= x"0000000E"; -- CRC-32
+ ram_write_wr <= '1';
+ wait for 20 ns;
+ ram_write_wr <= '0';
+
+
+ next_not_removed(MAX_NUMCHIPS_LD-1 downto 0) <= "0001";
+ next_not_removed(MAX_NUMCHIPS_LD+MAX_NUMCHIPS_LD-1 downto MAX_NUMCHIPS_LD) <= "0000";
+
+
+ trigger_begin_write <= '1';
+ wait for 20 ns;
+ while(true) loop
+ begin_jtagbitcalc <= '1';
+ wait for 20 ns;
+ begin_jtagbitcalc <= '0';
+ wait for 200 ns;
+ end loop;
+
+
+
+end process;
+
+testdriver_clk : process
+begin
+ CLK <= '0';
+ wait for 10 ns;
+ CLK <= '1';
+ wait for 10 ns;
+end process;
+end architecture;
\ No newline at end of file
--- /dev/null
+
+ NET RESET_VIRT LOC = AF16;
+ NET TLK_CLK LOC = AG16;
+ NET TLK_ENABLE LOC = R24 | IOSTANDARD = "LVTTL";
+ NET TLK_LCKREFN LOC = L28 | IOSTANDARD = "LVTTL";
+ NET TLK_LOOPEN LOC = R19 | IOSTANDARD = "LVTTL";
+ NET TLK_PRBSEN LOC = H32 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<0> LOC = G30 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<1> LOC = G31 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<2> LOC = J29 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<3> LOC = J30 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<4> LOC = E32 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<5> LOC = E33 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<6> LOC = N25 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<7> LOC = P26 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<8> LOC = P22 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<9> LOC = R21 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<10> LOC = F33 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<11> LOC = F34 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<12> LOC = K28 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<13> LOC = K29 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<14> LOC = G32 | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<15> LOC = G33 | IOSTANDARD = "LVTTL";
+ NET TLK_RX_CLK LOC = AF18;
+ NET TLK_RX_DV LOC = M30 | IOSTANDARD = "LVTTL";
+ NET TLK_RX_ER LOC = P20 | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<0> LOC = H27 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<1> LOC = H28 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<2> LOC = C32 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<3> LOC = D32 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<4> LOC = J27 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<5> LOC = K27 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<6> LOC = M25 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<7> LOC = M26 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<8> LOC = N22 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<9> LOC = N23 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<10> LOC = H29 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<11> LOC = H30 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<12> LOC = C33 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<13> LOC = C34 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<14> LOC = D34 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TXD<15> LOC = E34 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TX_EN LOC = L29 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET TLK_TX_ER LOC = P24 | IOSTANDARD = "LVTTL" | SLEW=FAST | DRIVE = 12;
+ NET VIRT_CLK LOC = H19 | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
+ NET VIRT_CLKb LOC = H18 | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
+ NET SFP_TX_DIS LOC = N27 | IOSTANDARD = "LVTTL";
+ NET SFP_LOS LOC = M27 | IOSTANDARD = "LVTTL";
+#
+ NET ETRAX_IRQ LOC ="AK12"| IOSTANDARD = "LVTTL";
+ NET FS_PB<0> LOC ="AL5"| IOSTANDARD = "LVTTL";
+ NET FS_PB<1> LOC ="AL4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<2> LOC ="AK4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<3> LOC ="AJ4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<4> LOC ="AP4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<5> LOC ="AN4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<6> LOC ="AD10"| IOSTANDARD = "LVTTL";
+ NET FS_PB<7> LOC ="AD9"| IOSTANDARD = "LVTTL";
+ NET FS_PB<8> LOC ="AN14"| IOSTANDARD = "LVTTL";
+ NET FS_PB<9> LOC ="AP14"| IOSTANDARD = "LVTTL";
+ NET FS_PB<10> LOC ="AJ6"| IOSTANDARD = "LVTTL";
+ NET FS_PB<11> LOC ="AJ5"| IOSTANDARD = "LVTTL";
+ NET FS_PB<12> LOC ="AK7"| IOSTANDARD = "LVTTL";
+ NET FS_PB<13> LOC ="AJ7"| IOSTANDARD = "LVTTL";
+ NET FS_PB<14> LOC ="AN3"| IOSTANDARD = "LVTTL";
+ NET FS_PB<15> LOC ="AN2"| IOSTANDARD = "LVTTL";
+ NET FS_PB<16> LOC ="AK13"| IOSTANDARD = "LVTTL";
+ NET FS_PB<17> LOC ="AL13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<0> LOC ="AL6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<1> LOC ="AK6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<2> LOC ="AL8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<3> LOC ="AK8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<4> LOC ="AH8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<5> LOC ="AH7"| IOSTANDARD = "LVTTL";
+ NET FS_PC<6> LOC ="AM13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<7> LOC ="AN13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<8> LOC ="AM6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<9> LOC ="AM5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<10> LOC ="AJ10"| IOSTANDARD = "LVTTL";
+ NET FS_PC<11> LOC ="AJ9"| IOSTANDARD = "LVTTL";
+ NET FS_PC<12> LOC ="AP5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<13> LOC ="AN5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<14> LOC ="AP6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<15> LOC ="AP7"| IOSTANDARD = "LVTTL";
+ NET FS_PC<16> LOC ="AM8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<17> LOC ="AN8"| IOSTANDARD = "LVTTL";
+
+ NET ONEWIRE LOC ="AK17"| IOSTANDARD = "LVCMOS25";
+ NET ADO_TTL<0> LOC ="AL11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<1> LOC ="AL10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<2> LOC ="AE11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<3> LOC ="AF11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<4> LOC ="AM12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<5> LOC ="AM11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<6> LOC ="AL9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<7> LOC ="AK9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<8> LOC ="AP11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<9> LOC ="AP10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<10> LOC ="AH10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<11> LOC ="AG10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<12> LOC ="AN12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<13> LOC ="AP12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<14> LOC ="AP9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<15> LOC ="AN9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<16> LOC ="AH12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<17> LOC ="AG11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<18> LOC ="AN7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<19> LOC ="AM7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<20> LOC ="AN10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<21> LOC ="AM10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<22> LOC ="AF10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<23> LOC ="AE9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<24> LOC ="AJ12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<25> LOC ="L33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<26> LOC ="L34"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<27> LOC ="M32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<28> LOC ="M33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<29> LOC ="D5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<30> LOC ="G7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<31> LOC ="G6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<32> LOC ="E14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<33> LOC ="D14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<34> LOC ="AL20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<35> LOC ="AJ15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<36> LOC ="AJ14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<37> LOC ="AG20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<38> LOC ="AH20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<39> LOC ="AG15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<40> LOC ="AH14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<41> LOC ="AL16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<42> LOC ="AK16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
+ NET DBAD LOC ="M28"| IOSTANDARD = "LVTTL";
+ NET DGOOD LOC ="H34"| IOSTANDARD = "LVTTL";
+ NET DINT LOC ="L31"| IOSTANDARD = "LVTTL";
+ NET DWAIT LOC ="H33"| IOSTANDARD = "LVTTL";
+ NET ADO_LV<0> LOC ="AC9" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<1> LOC ="AC8" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<2> LOC ="AG3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<3> LOC ="AF3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<4> LOC ="AF6" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<5> LOC ="AE6" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<6> LOC ="AF5" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<7> LOC ="AF4" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<8> LOC ="AL1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<9> LOC ="AK1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<10> LOC ="AJ2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<11> LOC ="AJ1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<12> LOC ="AB6" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<13> LOC ="AB5" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<14> LOC ="AC3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<15> LOC ="AC2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<16> LOC ="Y11" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<17> LOC ="AA11" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<18> LOC ="AD2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<19> LOC ="AD1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<20> LOC ="Y14" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<21> LOC ="AA13" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<22> LOC ="AC5" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<23> LOC ="AC4" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<24> LOC ="AF1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<25> LOC ="AE1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<26> LOC ="AE3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<27> LOC ="AE2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<28> LOC ="AD6" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<29> LOC ="AD5" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<30> LOC ="AC7" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<31> LOC ="AB8" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<32> LOC ="Y16" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<33> LOC ="AA15" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<34> LOC ="AE4" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<35> LOC ="AD4" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<36> LOC ="AH3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<37> LOC ="AH2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<38> LOC ="AG2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<39> LOC ="AG1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<40> LOC ="AK3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<41> LOC ="AK2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<42> LOC ="AF8" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<43> LOC ="AE8" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<44> LOC ="AH5" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<45> LOC ="AH4" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<46> LOC ="AB13" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<47> LOC ="AB12" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<48> LOC ="AM2" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<49> LOC ="AM1" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<50> LOC ="AG8" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<51> LOC ="AG7" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<52> LOC ="AM3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<53> LOC ="AL3" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<54> LOC ="AK22" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<55> LOC ="AK23" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<56> LOC ="AL28" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+ NET ADO_LV<57> LOC ="AL29" | IOSTANDARD = "LVDS_25" | SLEW = "FAST";
+# NET ADO_LV<58> LOC ="AP25";
+# NET ADO_LV<59> LOC ="AP26";
+# NET ADO_LV<60> LOC ="AJ27";
+# NET ADO_LV<61> LOC ="AH27";
+
+#
+
+
+NET "VIRT_CLK" TNM_NET = "VIRT_CLK";
+TIMESPEC "TS_CLK" = PERIOD "VIRT_CLK" 10 ns HIGH 50 %;
+ NET "TLK_CLK" TNM_NET = "TLK_CLK";
+ TIMESPEC "TS_TLK_CLK" = PERIOD "TLK_CLK" 10 ns HIGH 50 %;
+ NET "TLK_RX_CLK" TNM_NET = "TLK_RX_CLK";
+ TIMESPEC "TS_TLK_RX_CLK" = PERIOD "TLK_RX_CLK" 10 ns HIGH 50 %;
+
+
+ INST "TLK_TXD<*>" TNM = "TLK_TX";
+ INST "TLK_TX_EN" TNM = "TLK_TX";
+ INST "TLK_RXD<*>" TNM = "TLK_RX";
+ INST "TLK_RX_DV" TNM = "TLK_RX";
+ INST "TLK_RX_ER" TNM = "TLK_RX";
+
+ TIMEGRP "TLK_TX" OFFSET = OUT 7 ns AFTER "TLK_CLK" HIGH;
+ TIMEGRP "TLK_RX" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "TLK_RX_CLK";
+
+
+#INST "ADO_LV<*>" TNM = "VIRT_CLK_IN";
+#INST "ADO_LV<*>" TNM = "VIRT_CLK_OUT";
+#TIMEGRP "VIRT_CLK_OUT" OFFSET = OUT 9 ns AFTER "VIRT_CLK" HIGH;
+#TIMEGRP "VIRT_CLK_IN" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "VIRT_CLK";
--- /dev/null
+ -- ***************************************************************************
+ -- *
+ -- MAPS Addon to TRB communication *
+ -----------------------------------------------------------------------------*
+ -- Version 5.0 *
+ -----------------------------------------------------------------------------*
+ -- *
+ -- The addon should communicate over the LVDS lines with the TRB2 FPGA *
+ -- The lines are not LVDS, but TTL - LVCMOS25 *
+ -- *
+ -- *
+ -- R1 - R4 32 bit internal registers *
+ -- reg1 - reg4 16 bit internal registers *
+ -- ra - rd 1 bit internal registers *
+ -- ------------------------------------------------------------------ *
+ -- *
+ -- *
+ -- *
+ -- IN/OUT ports use 19 bits each (med_IC) *
+ -- *
+ -- 0 .. 15 16 17 18 *
+ -- DATA RDY CTRL CLK *
+ -- *
+ -- *
+ -- *
+ -- xxxxxxxxxxxxxxxxxxxxxx specific xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx*
+ -- *
+ -- use a reset handler *
+ -- *
+ -- ***************************************************************************
+
+
+
+ LIBRARY ieee;
+ use ieee.std_logic_1164.all;
+ USE IEEE.numeric_std.ALL;
+
+ --USE IEEE.std_logic_UNSIGNED.ALL;
+
+ Library UNISIM;
+ use UNISIM.vcomponents.all;
+
+ library work;
+ use work.trb_net_std.all;
+ use work.mvd_net.all;
+ use work.trb_net_components.all;
+ use work.monitor_config.all;
+
+
+ entity jcb_trb is
+ generic(
+ external_trigger : std_logic := '0'
+ );
+ port(
+
+ VIRT_CLK : in std_logic;
+ VIRT_CLKb : in std_logic;
+
+ RESET_VIRT : in std_logic;
+
+ ADO_LV : out std_logic_vector(57 downto 0);
+
+ ONEWIRE : inout std_logic;
+
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector(15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector(15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DBAD : out std_logic;
+ DWAIT : out std_logic;
+
+ --unused
+ FS_PB : out std_logic_vector(17 downto 0);
+ FS_PC : inout std_logic_vector(17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ ADO_TTL : in std_logic_vector(46 downto 0)
+
+ -- JTAG1_TMS_OUT : out std_logic;
+ -- JTAG1_TCK_OUT : out std_logic;
+ -- JTAG1_TDI_OUT : out std_logic;
+ -- JTAG1_TDO_IN : in std_logic;
+ -- JTAG2_TMS_OUT : out std_logic;
+ -- JTAG2_TCK_OUT : out std_logic;
+ -- JTAG2_TDI_OUT : out std_logic;
+ -- JTAG2_TDO_IN : in std_logic;
+ --
+ --
+ -- JTAG3_TMS_OUT : out std_logic;
+ -- JTAG3_TCK_OUT : out std_logic;
+ -- JTAG3_TDI_OUT : out std_logic;
+ -- JTAG3_TDO_IN : in std_logic;
+
+ -- event_trigger : in std_logic;
+
+ -- MAPS
+ -- MAPS_CLK_out : out std_logic;
+ -- MAPS_start_out : out std_logic;
+ -- MAPS_reset_out : out std_logic
+ );
+ end entity;
+
+
+
+
+
+
+
+
+
+ architecture basic of jcb_trb is
+
+ -- JTAG inputs/outputs
+ signal JTAG1_TMS_OUT : std_logic;
+ signal JTAG1_TCK_OUT : std_logic;
+ signal JTAG1_TDI_OUT : std_logic;
+ signal JTAG1_TDO_IN : std_logic;
+ signal JTAG2_TMS_OUT : std_logic;
+ signal JTAG2_TCK_OUT : std_logic;
+ signal JTAG2_TDI_OUT : std_logic;
+ signal JTAG2_TDO_IN : std_logic;
+
+ signal JTAG3_TMS_OUT : std_logic;
+ signal JTAG3_TCK_OUT : std_logic;
+ signal JTAG3_TDI_OUT : std_logic;
+ signal JTAG3_TDO_IN : std_logic;
+
+ signal event_trigger : std_logic;
+ -- MAPS outputs
+signal MAPS_CLK1_out : std_logic;
+signal MAPS_CLK2_out : std_logic;
+signal MAPS_CLK3_out : std_logic;
+signal MAPS_CLK1_out_int : std_logic; -- internal signal for ODDR
+signal MAPS_CLK1_out_int2 : std_logic; -- internal signal for ODDR
+signal MAPS_CLK2_out_int : std_logic; -- internal signal for ODDR
+signal MAPS_CLK2_out_int2 : std_logic; -- internal signal for ODDR
+signal MAPS_CLK3_out_int : std_logic; -- internal signal for ODDR
+signal MAPS_CLK3_out_int2 : std_logic; -- internal signal for ODDR
+signal MAPS_start1_out : std_logic;
+signal MAPS_start2_out : std_logic;
+signal MAPS_start3_out : std_logic;
+signal MAPS_reset1_out : std_logic;
+signal MAPS_reset2_out : std_logic;
+signal MAPS_reset3_out : std_logic;
+
+
+
+
+ -- the ENDPOINT signals
+ signal ep_MED_DATAREADY_OUT : std_logic;
+ signal ep_MED_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ signal ep_MED_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ signal ep_MED_READ_IN : std_logic;
+ signal ep_MED_DATAREADY_IN : std_logic;
+ signal ep_MED_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ signal ep_MED_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ signal ep_MED_READ_OUT : std_logic;
+ signal ep_MED_STAT_OP_IN : std_logic_vector(15 downto 0);
+ signal ep_MED_CTRL_OP_OUT : std_logic_vector(15 downto 0);
+ signal ep_TRG_TIMING_TRG_RECEIVED_IN : std_logic;
+ signal ep_LVL1_TRG_DATA_VALID_OUT : std_logic; --trigger type, number, code, information are valid
+ signal ep_LVL1_VALID_TIMING_TRG_OUT : std_logic; --valid timing trigger has been received
+ signal ep_LVL1_VALID_NOTIMING_TRG_OUT : std_logic; --valid trigger without timing trigger has been received
+ signal ep_LVL1_INVALID_TRG_OUT : std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ signal ep_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal ep_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal ep_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
+ signal ep_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
+ signal ep_LVL1_INT_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
+ signal ep_FEE_TRG_RELEASE_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
+ signal ep_FEE_TRG_STATUSBITS_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER*32-1 downto 0);
+ signal ep_FEE_DATA_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER*32-1 downto 0);
+ signal ep_FEE_DATA_WRITE_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
+ signal ep_FEE_DATA_FINISHED_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
+ signal ep_FEE_DATA_ALMOST_FULL_OUT : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
+ signal ep_REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal ep_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal ep_REGIO_COMMON_STAT_STROBE_OUT : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal ep_REGIO_COMMON_CTRL_STROBE_OUT : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal ep_REGIO_STAT_REG_IN : std_logic_vector(2**(c_REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
+ signal ep_REGIO_CTRL_REG_OUT : std_logic_vector(2**(c_REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+ signal ep_REGIO_STAT_STROBE_OUT : std_logic_vector(2**(c_REGIO_NUM_STAT_REGS)-1 downto 0);
+ signal ep_REGIO_CTRL_STROBE_OUT : std_logic_vector(2**(c_REGIO_NUM_CTRL_REGS)-1 downto 0);
+ signal ep_BUS_ADDR_OUT : std_logic_vector(16-1 downto 0);
+ signal ep_BUS_DATA_OUT : std_logic_vector(32-1 downto 0);
+ signal ep_BUS_READ_ENABLE_OUT : std_logic;
+ signal ep_BUS_WRITE_ENABLE_OUT : std_logic;
+ signal ep_BUS_TIMEOUT_OUT : std_logic;
+ signal ep_BUS_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
+ signal ep_BUS_DATAREADY_IN : std_logic := '0';
+ signal ep_BUS_WRITE_ACK_IN : std_logic := '0';
+ signal ep_BUS_NO_MORE_DATA_IN : std_logic := '0';
+ signal ep_BUS_UNKNOWN_ADDR_IN : std_logic := '0';
+ signal ep_ONEWIRE_INOUT : std_logic; --temperature sensor
+ signal ep_ONEWIRE_MONITOR_IN : std_logic := '0';
+ signal ep_ONEWIRE_MONITOR_OUT : std_logic;
+ signal ep_REGIO_VAR_ENDPOINT_ID : std_logic_vector (15 downto 0) := (others => '0');
+ signal ep_TIME_GLOBAL_OUT : std_logic_vector (31 downto 0); --global time, microseconds
+ signal ep_TIME_LOCAL_OUT : std_logic_vector ( 7 downto 0); --local time running with chip frequency
+ signal ep_TIME_SINCE_LAST_TRG_OUT : std_logic_vector (31 downto 0); --local time, resetted with each trigger
+ signal ep_TIME_TICKS_OUT : std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
+ signal ep_STAT_DEBUG_IPU : std_logic_vector (31 downto 0);
+ signal ep_STAT_DEBUG_1 : std_logic_vector (31 downto 0);
+ signal ep_STAT_DEBUG_2 : std_logic_vector (31 downto 0);
+ signal ep_STAT_DEBUG_DATA_HANDLER_OUT : std_logic_vector (31 downto 0);
+ signal ep_STAT_DEBUG_IPU_HANDLER_OUT : std_logic_vector (31 downto 0);
+ signal ep_CTRL_MPLEX : std_logic_vector (31 downto 0) := (others => '0');
+ signal ep_IOBUF_CTRL_GEN : std_logic_vector (4*32-1 downto 0) := (others => '0');
+ signal ep_STAT_ONEWIRE : std_logic_vector (31 downto 0);
+ signal ep_STAT_ADDR_DEBUG : std_logic_vector (15 downto 0);
+ signal ep_DEBUG_LVL1_HANDLER_OUT : std_logic_vector (15 downto 0);
+
+
+ -- the med IC communicator signals
+ signal ic_MED_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal ic_MED_PACKET_NUM_IN : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal ic_MED_DATAREADY_IN : std_logic := '0';
+ signal ic_MED_READ_OUT : std_logic := '0';
+ signal ic_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal ic_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal ic_MED_DATAREADY_OUT : std_logic := '0';
+ signal ic_MED_READ_IN : std_logic := '0';
+ signal ic_DATA_OUT : std_logic_vector(15 downto 0) := (others => '0');
+ signal ic_DATA_VALID_OUT : std_logic := '0';
+ signal ic_DATA_CTRL_OUT : std_logic := '0';
+ signal ic_DATA_CLK_OUT : std_logic := '0';
+ signal ic_DATA_IN : std_logic_vector(15 downto 0) := (others => '0');
+ signal ic_DATA_VALID_IN : std_logic := '0';
+ signal ic_DATA_CTRL_IN : std_logic := '0';
+ signal ic_DATA_CLK_IN : std_logic := '0';
+ signal ic_STAT_OP : std_logic_vector(15 downto 0) := (others => '0');
+ signal ic_CTRL_OP : std_logic_vector(15 downto 0) := (others => '0');
+ signal ic_STAT_DEBUG : std_logic_vector(63 downto 0) := (others => '0');
+
+
+ --MU
+ signal mu_REGIO_READ_ENABLE_IN, next_mu_REGIO_READ_ENABLE_IN : std_logic := '0';
+ signal mu_REGIO_WRITE_ENABLE_IN : std_logic := '0';
+ signal mu_REGIO_ADDR_IN, next_mu_REGIO_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0');
+ signal mu_REGIO_DATA_IN : std_logic_vector(31 downto 0);
+ signal mu_REGIO_DATA_OUT : std_logic_vector(31 downto 0) := x"0000_0000";
+ signal mu_REGIO_DATAREADY_OUT : std_logic := '0';
+ signal mu_REGIO_NO_MORE_DATA_OUT : std_logic := '0';
+ signal mu_REGIO_WRITE_ACK_OUT : std_logic := '0';
+ signal mu_REGIO_UNKNOWN_ADDR_OUT : std_logic := '0';
+ signal mu_REGIO_TIMEOUT_IN : std_logic := '0';
+ signal mu_FIFO_DATA_IN, next_mu_FIFO_DATA_IN : std_logic_vector( (FIFO_BUS*FIFO_NUM)-1 downto 0 ) := (others => '0');
+ signal mu_REG_DATA_IN, next_mu_REG_DATA_IN : std_logic_vector( (REG_BUS*REG_NUM)-1 downto 0 ) := (others => '0');
+ signal mu_HW_TRIGGER_IN, next_mu_HW_TRIGGER_IN : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+ signal mu_GLOBAL_TIME_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal mu_LOCAL_TIME_IN : std_logic_vector(7 downto 0) := (others => '0');
+ signal mu_TRIGGER_TIME_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal mu_EVENT_NUMBER_IN : std_logic_vector(7 downto 0) := (others => '0');
+
+
+
+
+ -- Main signals
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '1';
+-- signal soft_reset, next_soft_reset : std_logic := '0';
+
+
+
+
+ --attribute syn_keep : boolean;
+ --attribute syn_keep of next_testsignal : signal is true;
+
+-- COM_SETTINGS signals: for settings in this entity
+signal com_settings_addr_in : std_logic_vector(7 downto 0);
+signal com_settings_data_in : std_logic_vector(31 downto 0);
+signal com_settings_read_enable_in : std_logic;
+signal com_settings_write_enable_in : std_logic;
+signal com_settings_data_out : std_logic_vector(31 downto 0);
+signal com_settings_dataready_out : std_logic;
+signal com_settings_write_ack_out : std_logic;
+signal com_settings_no_more_data_out : std_logic;
+signal com_settings_unknown_addr_out : std_logic;
+signal signals_invert : std_logic_vector(13 downto 0);
+signal signals_invert2 : std_logic_vector(13 downto 0);
+signal signals_invert3 : std_logic_vector(13 downto 0);
+signal waitbeforestart : std_logic_vector(31 downto 0);
+signal beforestartcounter, beforestartcounter_next : std_logic_vector(31 downto 0);
+constant beforestartcounter_zero : std_logic_vector(31 downto 0) := (others => '0');
+signal beforestartcounter_finished, beforestartcounter_finished_next : std_logic;
+signal beforestartcounter_finished_last, beforestartcounter_finished_last_next : std_logic;
+
+signal fet_counter_limit : std_logic_vector(31 downto 0);
+signal jcounter_initvalue : std_logic_vector(28 downto 0); --29 bit
+signal trbnet_fet : std_logic;
+-- JTAG_CMD_M26C connection signals
+signal jtag_cmd_m26c_addr_in : std_logic_vector(8 downto 0);
+signal jtag_cmd_m26c_data_in : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_read_enable_in : std_logic;
+signal jtag_cmd_m26c_write_enable_in : std_logic;
+signal jtag_cmd_m26c_data_out : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_dataready_out : std_logic;
+signal jtag_cmd_m26c_write_ack_out : std_logic;
+signal jtag_cmd_m26c_no_more_data_out : std_logic;
+signal jtag_cmd_m26c_unknown_addr_out : std_logic;
+signal jtag_tck : std_logic;
+signal jtag_tms : std_logic;
+signal jtag_tdi : std_logic;
+signal jtag_tdo_evtlinv : std_logic;
+-- second JTAG entity
+signal jtag_cmd_m26c_addr_in2 : std_logic_vector(8 downto 0);
+signal jtag_cmd_m26c_data_in2 : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_read_enable_in2 : std_logic;
+signal jtag_cmd_m26c_write_enable_in2 : std_logic;
+signal jtag_cmd_m26c_data_out2 : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_dataready_out2 : std_logic;
+signal jtag_cmd_m26c_write_ack_out2 : std_logic;
+signal jtag_cmd_m26c_no_more_data_out2 : std_logic;
+signal jtag_cmd_m26c_unknown_addr_out2 : std_logic;
+signal jtag_tck2 : std_logic;
+signal jtag_tms2 : std_logic;
+signal jtag_tdi2 : std_logic;
+signal jtag_tdo_evtlinv2 : std_logic;
+-- third JTAG entity
+signal jtag_cmd_m26c_addr_in3 : std_logic_vector(8 downto 0);
+signal jtag_cmd_m26c_data_in3 : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_read_enable_in3 : std_logic;
+signal jtag_cmd_m26c_write_enable_in3 : std_logic;
+signal jtag_cmd_m26c_data_out3 : std_logic_vector(31 downto 0);
+signal jtag_cmd_m26c_dataready_out3 : std_logic;
+signal jtag_cmd_m26c_write_ack_out3 : std_logic;
+signal jtag_cmd_m26c_no_more_data_out3 : std_logic;
+signal jtag_cmd_m26c_unknown_addr_out3 : std_logic;
+signal jtag_tck3 : std_logic;
+signal jtag_tms3 : std_logic;
+signal jtag_tdi3 : std_logic;
+signal jtag_tdo_evtlinv3 : std_logic;
+
+
+-- JTAG stuff
+signal jcounter, jcounter_next : std_logic_vector(28 downto 0); --29 bit
+signal off_spill, off_spill_next : std_logic;
+signal fake_event_trigger, fake_event_trigger_next : std_logic;
+signal fet_counter, fet_counter_next : std_logic_vector (31 downto 0); -- 32 bit
+signal my_status : std_logic_vector(8 downto 0);
+signal idle_out : std_logic;
+signal idle_out2 : std_logic;
+signal idle_out3 : std_logic;
+
+signal prog_jtag_finished : std_logic;
+
+signal prog_jtag_finished2 : std_logic;
+
+signal prog_jtag_finished3 : std_logic;
+
+-- spill trigger rising edge detection
+signal event_trigger_ff, event_trigger_ff_next : std_logic;
+signal event_trigger_ff_last, event_trigger_ff_last_next : std_logic;
+signal spillbreak_trigger : std_logic;
+-- spill trigger rising edge detection (MAPS_CLK)
+signal event_trigger_ff_MAPS_CLK, event_trigger_ff_MAPS_CLK_next : std_logic;
+signal event_trigger_ff_last_MAPS_CLK, event_trigger_ff_last_MAPS_CLK_next : std_logic;
+signal spillbreak_trigger_MAPS_CLK : std_logic;
+-- JTAG finished edge detection
+signal prog_jtag_finished_ff_MAPS_CLK, prog_jtag_finished_ff_MAPS_CLK_next : std_logic;
+signal prog_jtag_finished_ff_last_MAPS_CLK, prog_jtag_finished_ff_last_MAPS_CLK_next : std_logic;
+signal prog_jtag_finished_pulse_MAPS_CLK, prog_jtag_finished_pulse_MAPS_CLK_next : std_logic;
+-- MAPS outputs (reset, start)
+signal MAPS_CLK : std_logic;
+signal MAPS_reset, MAPS_reset_next : std_logic;
+signal MAPS_reset_count, MAPS_reset_count_next : std_logic_vector(6 downto 0);
+signal MAPS_start, MAPS_start_next : std_logic;
+signal MAPS_start_count, MAPS_start_count_next : std_logic_vector(6 downto 0);
+
+ -- TrbNet Reset Handler
+ signal reset_CLEAR_IN : std_logic := '0'; -- reset input (high active, async)
+ signal reset_CLEAR_N_IN : std_logic := '0'; -- reset input (low active, async)
+ signal reset_CLK_IN : std_logic := '0'; -- raw master clock, NOT from PLL/DLL!
+ signal reset_SYSCLK_IN : std_logic := '0'; -- PLL/DLL remastered clock
+ signal reset_PLL_LOCKED_IN : std_logic := '0'; -- master PLL lock signal (async)
+ signal reset_RESET_IN : std_logic := '0'; -- general reset signal (SYSCLK)
+ signal reset_TRB_RESET_IN : std_logic := '0'; -- TRBnet reset signal (SYSCLK)
+ signal reset_CLEAR_OUT : std_logic := '0'; -- async reset out, USE WITH CARE!
+ signal reset_RESET_OUT : std_logic := '0'; -- synchronous reset out (SYSCLK)
+ signal reset_DEBUG_OUT : std_logic_vector(15 downto 0) := x"0000";
+
+
+component jtag_cmd_m26c is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_TMS_OUT : out std_logic;
+ JTAG_TCK_OUT : out std_logic;
+ JTAG_TDI_OUT : out std_logic;
+ JTAG_TDO_IN : in std_logic;
+
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+
+ OFF_SPILL_IN : in std_logic;
+ MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ IDLE_OUT : out std_logic;
+ PROG_JTAG_FINISHED_OUT:out std_logic
+ --BUS_TIMEOUT_IN : in std_logic;
+ );
+end component;
+
+ COMPONENT dcm3
+ PORT(
+ CLKIN_IN : IN std_logic;
+ RST_IN : IN std_logic;
+ CLKFX_OUT : OUT std_logic;
+ CLK0_OUT : OUT std_logic;
+ LOCKED_OUT : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+begin
+ETRAX_IRQ <= '1';
+
+--inputs/outputs
+MAPS_reset_OBUFDS1 : OBUFDS
+port map (
+ I => MAPS_reset1_out,
+ O => ADO_LV(2),
+ OB=> ADO_LV(3)
+);
+MAPS_start_OBUFDS1 : OBUFDS
+port map (
+ I => MAPS_start1_out,
+ O => ADO_LV(4),
+ OB=> ADO_LV(5)
+);
+MAPS_CLK_OBUFDS1 : OBUFDS
+port map (
+ I => MAPS_CLK1_out,
+ O => ADO_LV(6),
+ OB=> ADO_LV(7)
+);
+
+jtag1_tck_OBUFDS : OBUFDS
+port map (
+ I => JTAG1_TCK_OUT,
+ O => ADO_LV(8),
+ OB=> ADO_LV(9)
+);
+jtag1_tdi_OBUFDS : OBUFDS
+port map (
+ I => JTAG1_TDI_OUT,
+ O => ADO_LV(10),
+ OB=> ADO_LV(11)
+);
+jtag1_tms_OBUFDS : OBUFDS
+port map (
+ I => JTAG1_TMS_OUT,
+ O => ADO_LV(12),
+ OB=> ADO_LV(13)
+);
+
+
+MAPS_reset_OBUFDS2 : OBUFDS
+port map (
+ I => MAPS_reset2_out,
+ O => ADO_LV(18),
+ OB=> ADO_LV(19)
+);
+MAPS_start_OBUFDS2 : OBUFDS
+port map (
+ I => MAPS_start2_out,
+ O => ADO_LV(20),
+ OB=> ADO_LV(21)
+);
+MAPS_CLK_OBUFDS2 : OBUFDS
+port map (
+ I => MAPS_CLK2_out,
+ O => ADO_LV(22),
+ OB=> ADO_LV(23)
+);
+
+jtag2_tms_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TMS_OUT,
+ O => ADO_LV(24),
+ OB=> ADO_LV(25)
+);
+jtag2_tck_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TCK_OUT,
+ O => ADO_LV(26),
+ OB=> ADO_LV(27)
+);
+jtag2_tdi_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TDI_OUT,
+ O => ADO_LV(28),
+ OB=> ADO_LV(29)
+);
+
+MAPS_reset_OBUFDS3 : OBUFDS
+port map (
+ I => MAPS_reset3_out,
+ O => ADO_LV(34),
+ OB=> ADO_LV(35)
+);
+MAPS_start_OBUFDS3 : OBUFDS
+port map (
+ I => MAPS_start3_out,
+ O => ADO_LV(36),
+ OB=> ADO_LV(37)
+);
+MAPS_CLK_OBUFDS3 : OBUFDS
+port map (
+ I => MAPS_CLK3_out,
+ O => ADO_LV(38),
+ OB=> ADO_LV(39)
+);
+
+jtag3_tms_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TMS_OUT,
+ O => ADO_LV(40),
+ OB=> ADO_LV(41)
+);
+jtag3_tck_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TCK_OUT,
+ O => ADO_LV(42),
+ OB=> ADO_LV(43)
+);
+jtag3_tdi_OBUFDS : OBUFDS
+port map (
+ I => JTAG2_TDI_OUT,
+ O => ADO_LV(44),
+ OB=> ADO_LV(45)
+);
+
+--ADO_LV(1 downto 0) <= (others => '0');
+--ADO_LV(17 downto 14) <= (others => '0');
+--ADO_LV(33 downto 30) <= (others => '0');
+--ADO_LV(57 downto 46) <= (others => '0');
+
+unused1 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(0),
+ OB=> ADO_LV(1)
+);
+
+unused2 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(14),
+ OB=> ADO_LV(15)
+);
+unused3 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(16),
+ OB=> ADO_LV(17)
+);
+unused4 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(30),
+ OB=> ADO_LV(31)
+);
+unused5 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(32),
+ OB=> ADO_LV(33)
+);
+unused6 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(46),
+ OB=> ADO_LV(47)
+);
+unused7 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(48),
+ OB=> ADO_LV(49)
+);
+unused8 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(50),
+ OB=> ADO_LV(51)
+);
+unused9 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(52),
+ OB=> ADO_LV(53)
+);
+unused10 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(54),
+ OB=> ADO_LV(55)
+);
+unused11 : OBUFDS
+port map (
+ I => '0',
+ O => ADO_LV(56),
+ OB=> ADO_LV(57)
+);
+
+
+
+JTAG1_TDO_IN <= ADO_TTL(16);
+JTAG2_TDO_IN <= ADO_TTL(17);
+JTAG3_TDO_IN <= ADO_TTL(18);
+
+event_trigger <= ADO_TTL(19);
+
+
+
+ ---------------------------------------------------------------------
+ -- CLK generator
+ ---------------------------------------------------------------------
+ the_IBUFGDS : IBUFGDS
+ generic map (
+ DIFF_TERM => TRUE,
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => CLK,
+ I => VIRT_CLK,
+ IB => VIRT_CLKb
+ );
+
+
+
+
+
+
+-- ---------------------------------------------------------------------
+-- -- FIFO
+-- ---------------------------------------------------------------------
+-- the_xilinx_BRAM_FIFO_16x1024_1: xilinx_BRAM_FIFO_16x1024
+-- port map(
+-- clk => CLK,
+-- din => fifo_din1,
+-- rd_en => fifo_rd_en1,
+-- rst => RESET,
+-- wr_en => fifo_wr_en1,
+-- data_count => fifo_data_count1,
+-- dout => fifo_dout1,
+-- empty => fifo_empty1,
+-- full => fifo_full1,
+-- valid => fifo_valid1
+-- );
+--
+--
+-- ---------------------------------------------------------------------
+-- -- FIFO
+-- ---------------------------------------------------------------------
+-- the_xilinx_BRAM_FIFO_16x1024_2: xilinx_BRAM_FIFO_16x1024
+-- port map(
+-- clk => CLK,
+-- din => fifo_din2,
+-- rd_en => fifo_rd_en2,
+-- rst => RESET,
+-- wr_en => fifo_wr_en2,
+-- data_count => fifo_data_count2,
+-- dout => fifo_dout2,
+-- empty => fifo_empty2,
+-- full => fifo_full2,
+-- valid => fifo_valid2
+-- );
+--
+
+-- ---------------------------------------------------------------------
+-- -- RESET Handler
+-- ---------------------------------------------------------------------
+-- the_reset_handler: reset_handler_b
+-- generic map(
+-- RESET_DELAY => x"000f"
+-- )
+-- port map(
+-- CLK => CLK,
+-- RESET_IN => soft_reset,
+-- TRB_RESET_IN => not RESET_VIRT,
+-- EXTERNAL_RESET_IN => '0',
+-- RESET_COUNTER_IN => x"00000000",
+-- RESET_OUT => RESET
+-- );
+-- -- next_soft_reset <= ic_STAT_OP(13);
+-- -- next_ttl_obuf(16) <= soft_reset;
+ ----------------------------------------------------------------------------------------------------------------------------------------
+ -- Reset Handler
+ ----------------------------------------------------------------------------------------------------------------------------------------
+ the_trb_net_reset_handler: trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"000f"
+ )
+ port map(
+ CLEAR_IN => reset_CLEAR_IN, -- reset input (high active, async)
+ CLEAR_N_IN => reset_CLEAR_N_IN, -- reset input (low active, async)
+ CLK_IN => reset_CLK_IN, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => reset_SYSCLK_IN, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => reset_PLL_LOCKED_IN,-- master PLL lock signal (async)
+ RESET_IN => reset_RESET_IN, -- general reset signal (SYSCLK)
+ TRB_RESET_IN => reset_TRB_RESET_IN, -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => reset_CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => RESET, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => reset_DEBUG_OUT
+ );
+ reset_CLK_IN <= CLK;
+ reset_SYSCLK_IN <= CLK;
+ reset_CLEAR_IN <= '0';
+ reset_CLEAR_N_IN <= '1';
+ reset_PLL_LOCKED_IN <= '1';
+ reset_RESET_IN <= ep_MED_STAT_OP_IN(13);
+
+
+ the_med_tlk: trb_net16_med_tlk
+ port map(
+ RESET => RESET, -- which reset should be used?
+ CLK => CLK,
+ TLK_CLK => TLK_CLK,
+ TLK_ENABLE => TLK_ENABLE,
+ TLK_LCKREFN => TLK_LCKREFN,
+ TLK_LOOPEN => TLK_LOOPEN,
+ TLK_PRBSEN => TLK_PRBSEN,
+ TLK_RXD => TLK_RXD,
+ TLK_RX_CLK => TLK_RX_CLK,
+ TLK_RX_DV =>TLK_RX_DV,
+ TLK_RX_ER => TLK_RX_ER,
+ TLK_TXD => TLK_TXD,
+ TLK_TX_EN => TLK_TX_EN,
+ TLK_TX_ER => TLK_TX_ER,
+ SFP_LOS => SFP_LOS,
+ SFP_TX_DIS => SFP_TX_DIS,
+ MED_DATAREADY_IN => ep_MED_DATAREADY_OUT,
+ MED_READ_IN => ep_MED_READ_OUT,
+ MED_DATA_IN => ep_MED_DATA_OUT,
+ MED_PACKET_NUM_IN => ep_MED_PACKET_NUM_OUT,
+ MED_DATAREADY_OUT => ep_MED_DATAREADY_IN,
+ MED_READ_OUT => ep_MED_READ_IN,
+ MED_DATA_OUT => ep_MED_DATA_IN,
+ MED_PACKET_NUM_OUT=> ep_MED_PACKET_NUM_IN,
+ STAT => open,
+ STAT_MONITOR => open,
+ STAT_OP => ep_MED_STAT_OP_IN,
+ CTRL_OP => ep_MED_CTRL_OP_OUT
+ --connect STAT(0) to LED
+ );
+
+
+
+-- the_reg_sync : reg_sync
+-- port map(
+--
+-- CLK => CLK,
+-- RESET => '0',
+--
+-- CLK_SLOW => sync_clk_in,
+-- CLK_OUT => sync_ddr_out,
+--
+-- DATA_IN_SLOW => sync_data_in2,
+-- VALID_IN_SLOW => sync_valid_in2,
+-- PACKET_NUM_IN_SLOW => sync_packet_num_in2,
+-- READ_IN_SLOW => sync_read_in2,
+--
+-- DATA_IN_FAST => sync_data_in1,
+-- VALID_IN_FAST => sync_valid_in1,
+-- PACKET_NUM_IN_FAST => sync_packet_num_in1,
+-- READ_IN_FAST => sync_read_in1,
+--
+-- DATA_OUT_SLOW => sync_data_out2,
+-- VALID_OUT_SLOW => sync_valid_out2,
+-- PACKET_NUM_OUT_SLOW => sync_packet_num_out2,
+-- READ_OUT_SLOW => sync_read_out2,
+--
+-- DATA_OUT_FAST => sync_data_out1,
+-- VALID_OUT_FAST => sync_valid_out1,
+-- PACKET_NUM_OUT_FAST => sync_packet_num_out1,
+-- READ_OUT_FAST => sync_read_out1
+--
+-- );
+-- ep_MED_READ_IN <= sync_read_out2;
+-- ep_MED_DATA_IN <= sync_data_out2;
+-- ep_MED_DATAREADY_IN <= sync_valid_out2;
+-- ep_MED_PACKET_NUM_IN <= sync_packet_num_out2;
+--
+-- sync_data_in1 <= ep_MED_DATA_OUT;
+-- sync_valid_in1 <= ep_MED_DATAREADY_OUT;
+-- sync_packet_num_in1 <= ep_MED_PACKET_NUM_OUT;
+-- sync_read_in1 <= ep_MED_READ_OUT;
+---- sync_data_in1 <= ep_testdata;
+---- sync_valid_in1 <= ep_testvalid;
+---- sync_packet_num_in1 <= ep_testpacket;
+---- sync_read_in1 <= ep_testread;
+---- sync_data_in1 <= testsignal(15 downto 0);
+---- sync_valid_in1 <= testsignal(16);
+---- sync_packet_num_in1 <= testsignal(19 downto 17);
+---- sync_read_in1 <= testsignal(20);
+
+
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Endpoint
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_ENDPOINT: trb_net16_endpoint_hades_full_handler
+ generic map(
+ IBUF_DEPTH => (6,6,6,6),
+ FIFO_TO_INT_DEPTH => (6,6,6,6),
+ FIFO_TO_APL_DEPTH => (6,6,6,6),
+ APL_WRITE_ALL_WORDS => (c_NO,c_NO,c_NO,c_NO),
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"FF",
+ REGIO_NUM_STAT_REGS => c_REGIO_NUM_STAT_REGS,
+ REGIO_NUM_CTRL_REGS => c_REGIO_NUM_CTRL_REGS,
+ REGIO_INIT_CTRL_REGS => (others => '0'),
+ REGIO_INIT_ADDRESS => x"F013",
+ REGIO_INIT_BOARD_INFO => x"1234_5678",
+ REGIO_INIT_ENDPOINT_ID => x"1234",
+ REGIO_COMPILE_TIME => x"00000000",
+ REGIO_COMPILE_VERSION => x"0005",
+ REGIO_HARDWARE_VERSION => x"12345678",
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => c_DATA_INTERFACE_NUMBER,
+ DATA_BUFFER_DEPTH => 9,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**8,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**8
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MED_DATAREADY_OUT => ep_MED_DATAREADY_OUT,
+ MED_DATA_OUT => ep_MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => ep_MED_PACKET_NUM_OUT,
+ MED_READ_IN => ep_MED_READ_IN,
+ MED_DATAREADY_IN => ep_MED_DATAREADY_IN,
+ MED_DATA_IN => ep_MED_DATA_IN,
+ MED_PACKET_NUM_IN => ep_MED_PACKET_NUM_IN,
+ MED_READ_OUT => ep_MED_READ_OUT,
+ MED_STAT_OP_IN => ep_MED_STAT_OP_IN,
+ MED_CTRL_OP_OUT => ep_MED_CTRL_OP_OUT,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => ep_TRG_TIMING_TRG_RECEIVED_IN,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => ep_LVL1_TRG_DATA_VALID_OUT, --trigger type, number, code, information are valid
+ LVL1_VALID_TIMING_TRG_OUT => ep_LVL1_VALID_TIMING_TRG_OUT, --valid timing trigger has been received
+ LVL1_VALID_NOTIMING_TRG_OUT => ep_LVL1_VALID_NOTIMING_TRG_OUT, --valid trigger without timing trigger has been received
+ LVL1_INVALID_TRG_OUT => ep_LVL1_INVALID_TRG_OUT, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+ LVL1_TRG_TYPE_OUT => ep_LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_NUMBER_OUT => ep_LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => ep_LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => ep_LVL1_TRG_INFORMATION_OUT,
+ LVL1_INT_TRG_NUMBER_OUT => ep_LVL1_INT_TRG_NUMBER_OUT, --internally generated trigger number, for informational uses only
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN => ep_FEE_TRG_RELEASE_IN,
+ FEE_TRG_STATUSBITS_IN => ep_FEE_TRG_STATUSBITS_IN,
+ FEE_DATA_IN => ep_FEE_DATA_IN,
+ FEE_DATA_WRITE_IN => ep_FEE_DATA_WRITE_IN,
+ FEE_DATA_FINISHED_IN => ep_FEE_DATA_FINISHED_IN,
+ FEE_DATA_ALMOST_FULL_OUT => ep_FEE_DATA_ALMOST_FULL_OUT,
+
+ --Slow Control Port
+ --common registers
+ REGIO_COMMON_STAT_REG_IN => ep_REGIO_COMMON_STAT_REG_IN,
+ REGIO_COMMON_CTRL_REG_OUT => ep_REGIO_COMMON_CTRL_REG_OUT,
+ REGIO_COMMON_STAT_STROBE_OUT => ep_REGIO_COMMON_STAT_STROBE_OUT,
+ REGIO_COMMON_CTRL_STROBE_OUT => ep_REGIO_COMMON_CTRL_STROBE_OUT,
+ --user defined registers
+ REGIO_STAT_REG_IN => ep_REGIO_STAT_REG_IN,
+ REGIO_CTRL_REG_OUT => ep_REGIO_CTRL_REG_OUT,
+ REGIO_STAT_STROBE_OUT => ep_REGIO_STAT_STROBE_OUT,
+ REGIO_CTRL_STROBE_OUT => ep_REGIO_CTRL_STROBE_OUT,
+ --internal data port
+ BUS_ADDR_OUT => ep_BUS_ADDR_OUT,
+ BUS_DATA_OUT => ep_BUS_DATA_OUT,
+ BUS_READ_ENABLE_OUT => ep_BUS_READ_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT => ep_BUS_WRITE_ENABLE_OUT,
+ BUS_TIMEOUT_OUT => ep_BUS_TIMEOUT_OUT,
+ BUS_DATA_IN => ep_BUS_DATA_IN,
+ BUS_DATAREADY_IN => ep_BUS_DATAREADY_IN,
+ BUS_WRITE_ACK_IN => ep_BUS_WRITE_ACK_IN,
+ BUS_NO_MORE_DATA_IN => ep_BUS_NO_MORE_DATA_IN,
+ BUS_UNKNOWN_ADDR_IN => ep_BUS_UNKNOWN_ADDR_IN,
+ --Onewire
+ ONEWIRE_INOUT => ONEWIRE, --temperature sensor
+ ONEWIRE_MONITOR_IN => ep_ONEWIRE_MONITOR_IN,
+ ONEWIRE_MONITOR_OUT => ep_ONEWIRE_MONITOR_OUT,
+ --Config endpoint id, if not statically assigned
+ REGIO_VAR_ENDPOINT_ID => ep_REGIO_VAR_ENDPOINT_ID,
+
+ --Timing registers
+ TIME_GLOBAL_OUT => ep_TIME_GLOBAL_OUT, --global time, microseconds
+ TIME_LOCAL_OUT => ep_TIME_LOCAL_OUT, --local time running with chip frequency
+ TIME_SINCE_LAST_TRG_OUT => ep_TIME_SINCE_LAST_TRG_OUT, --local time, resetted with each trigger
+ TIME_TICKS_OUT => ep_TIME_TICKS_OUT, --bit 1 ms-tick, 0 us-tick
+
+ --Debugging & Status information
+ STAT_DEBUG_IPU => ep_STAT_DEBUG_IPU,
+ STAT_DEBUG_1 => ep_STAT_DEBUG_1,
+ STAT_DEBUG_2 => ep_STAT_DEBUG_2,
+ STAT_DEBUG_DATA_HANDLER_OUT => ep_STAT_DEBUG_DATA_HANDLER_OUT,
+ STAT_DEBUG_IPU_HANDLER_OUT => ep_STAT_DEBUG_IPU_HANDLER_OUT,
+ CTRL_MPLEX => ep_CTRL_MPLEX,
+ IOBUF_CTRL_GEN => ep_IOBUF_CTRL_GEN,
+ STAT_ONEWIRE => ep_STAT_ONEWIRE,
+ STAT_ADDR_DEBUG => ep_STAT_ADDR_DEBUG,
+ DEBUG_LVL1_HANDLER_OUT => ep_DEBUG_LVL1_HANDLER_OUT
+ );
+
+
+
+the_bus_handler : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"b000", 1 => x"8000", 2 => x"c000", 3 => x"d000", 4 => x"e000", others => (others => '0')),
+ PORT_ADDR_MASK => (0 => 9, 1 => 10, 2 => 8, 3 => 9, 4 => 9, others => 0)
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ DAT_ADDR_IN => ep_BUS_ADDR_OUT,
+ DAT_DATA_IN => ep_BUS_DATA_OUT, -- data from TRB endpoint
+ DAT_DATA_OUT => ep_BUS_DATA_IN, -- data to TRB endpoint
+ DAT_READ_ENABLE_IN => ep_BUS_READ_ENABLE_OUT, -- read pulse
+ DAT_WRITE_ENABLE_IN => ep_BUS_WRITE_ENABLE_OUT, -- write pulse
+ DAT_TIMEOUT_IN => ep_BUS_TIMEOUT_OUT, -- access timed out
+ DAT_DATAREADY_OUT => ep_BUS_DATAREADY_IN, -- your data, master, as requested
+ DAT_WRITE_ACK_OUT => ep_BUS_WRITE_ACK_IN, -- data accepted
+ DAT_NO_MORE_DATA_OUT => ep_BUS_NO_MORE_DATA_IN, -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT => ep_BUS_UNKNOWN_ADDR_IN, -- noone here to answer your request
+
+ --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => jtag_cmd_m26c_addr_in,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+9 downto 1*16) => open,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+10) => open,
+ BUS_ADDR_OUT(2*16+7 downto 2*16) => com_settings_addr_in,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+8) => open,
+ BUS_ADDR_OUT(3*16+8 downto 3*16) => jtag_cmd_m26c_addr_in2,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
+ BUS_ADDR_OUT(4*16+8 downto 4*16) => jtag_cmd_m26c_addr_in3,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
+ --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => jtag_cmd_m26c_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => open,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => com_settings_data_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => jtag_cmd_m26c_data_in2,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => jtag_cmd_m26c_data_in3,
+ BUS_READ_ENABLE_OUT(0) => jtag_cmd_m26c_read_enable_in,
+ BUS_READ_ENABLE_OUT(1) => open,
+ BUS_READ_ENABLE_OUT(2) => com_settings_read_enable_in,
+ BUS_READ_ENABLE_OUT(3) => jtag_cmd_m26c_read_enable_in2,
+ BUS_READ_ENABLE_OUT(4) => jtag_cmd_m26c_read_enable_in3,
+ BUS_WRITE_ENABLE_OUT(0) => jtag_cmd_m26c_write_enable_in,
+ BUS_WRITE_ENABLE_OUT(1) => open,
+ BUS_WRITE_ENABLE_OUT(2) => com_settings_write_enable_in,
+ BUS_WRITE_ENABLE_OUT(3) => jtag_cmd_m26c_write_enable_in2,
+ BUS_WRITE_ENABLE_OUT(4) => jtag_cmd_m26c_write_enable_in3,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => jtag_cmd_m26c_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32) => (others => '0'),
+ BUS_DATA_IN(2*32+31 downto 2*32) => com_settings_data_out,
+ BUS_DATA_IN(3*32+31 downto 3*32) => jtag_cmd_m26c_data_out2,
+ BUS_DATA_IN(4*32+31 downto 4*32) => jtag_cmd_m26c_data_out3,
+ BUS_DATAREADY_IN(0) => jtag_cmd_m26c_dataready_out,
+ BUS_DATAREADY_IN(1) => '0',
+ BUS_DATAREADY_IN(2) => com_settings_dataready_out,
+ BUS_DATAREADY_IN(3) => jtag_cmd_m26c_dataready_out2,
+ BUS_DATAREADY_IN(4) => jtag_cmd_m26c_dataready_out3,
+ BUS_WRITE_ACK_IN(0) => jtag_cmd_m26c_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => '0',
+ BUS_WRITE_ACK_IN(2) => com_settings_write_ack_out,
+ BUS_WRITE_ACK_IN(3) => jtag_cmd_m26c_write_ack_out2,
+ BUS_WRITE_ACK_IN(4) => jtag_cmd_m26c_write_ack_out3,
+ BUS_NO_MORE_DATA_IN(0) => jtag_cmd_m26c_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => com_settings_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(3) => jtag_cmd_m26c_no_more_data_out2,
+ BUS_NO_MORE_DATA_IN(4) => jtag_cmd_m26c_no_more_data_out3,
+ BUS_UNKNOWN_ADDR_IN(0) => jtag_cmd_m26c_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => com_settings_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(3) => jtag_cmd_m26c_unknown_addr_out2,
+ BUS_UNKNOWN_ADDR_IN(4) => jtag_cmd_m26c_unknown_addr_out3,
+
+
+
+
+
+ STAT_DEBUG => open
+ );
+
+
+the_jtag3_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms3,
+ JTAG_TCK_OUT => jtag_tck3,
+ JTAG_TDI_OUT => jtag_tdi3,
+ JTAG_TDO_IN => jtag_tdo_evtlinv3,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in3,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out3,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in3(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in3,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in3,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out3,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out3,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out3,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out3,
+
+ OFF_SPILL_IN => off_spill,
+ MY_STATUS_OUT => open,
+ IDLE_OUT => idle_out3,
+ --BUS_TIMEOUT_IN : in std_logic;
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished3
+ );
+the_jtag2_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms2,
+ JTAG_TCK_OUT => jtag_tck2,
+ JTAG_TDI_OUT => jtag_tdi2,
+ JTAG_TDO_IN => jtag_tdo_evtlinv2,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in2,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out2,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in2(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in2,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in2,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out2,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out2,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out2,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out2,
+
+ OFF_SPILL_IN => off_spill,
+ MY_STATUS_OUT => open,
+ IDLE_OUT => idle_out2,
+ --BUS_TIMEOUT_IN : in std_logic;
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished2
+ );
+
+the_jtag_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms,
+ JTAG_TCK_OUT => jtag_tck,
+ JTAG_TDI_OUT => jtag_tdi,
+ JTAG_TDO_IN => jtag_tdo_evtlinv,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out,
+
+ OFF_SPILL_IN => off_spill,
+ MY_STATUS_OUT => my_status,
+ IDLE_OUT => idle_out,
+ --BUS_TIMEOUT_IN : in std_logic;
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished
+ );
+
+--JTAG_TDO_TEST_OUT <= JTAG_TDO_IN;
+
+SEQ_COUNTER : process(CLK, RESET)
+begin
+ if(rising_edge(CLK)) then
+ if(RESET='1') then
+ jcounter <= (others => '0');
+ off_spill <= '0';
+ else
+ jcounter <= jcounter_next;
+ off_spill <= off_spill_next;
+ end if;
+ end if;
+end process;
+
+COMB_COUNTER : process(jcounter, off_spill, spillbreak_trigger, jcounter_initvalue)
+begin
+ jcounter_next <= std_logic_vector(unsigned(jcounter) - 1);
+ off_spill_next <= off_spill;
+ if(spillbreak_trigger = '1') then
+ off_spill_next <= '1';
+ jcounter_next <= jcounter_initvalue;
+ elsif(to_integer(unsigned(jcounter)) = 0) then
+ off_spill_next <= '0';
+ end if;
+end process;
+
+
+
+-- the_IODELAY : IODELAY
+-- generic map (
+-- DELAY_SRC => "I", -- Specify which input port to be used
+-- -- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
+-- HIGH_PERFORMANCE_MODE => TRUE, -- TRUE specifies lower jitter
+-- -- at expense of more power
+-- IDELAY_TYPE => "DEFAULT", -- "DEFAULT", "FIXED" or "VARIABLE"
+-- IDELAY_VALUE => 0, -- 0 to 63 tap values
+-- ODELAY_VALUE => 0, -- 0 to 63 tap values
+-- REFCLK_FREQUENCY => 200.0, -- Frequency used for IDELAYCTRL
+-- -- 175.0 to 225.0
+-- SIGNAL_PATTERN => "DATA") -- Input signal type, "CLOCK" or "DATA"
+-- port map (
+-- DATAOUT => DATAOUT, -- 1-bit delayed data output
+-- C => C, -- 1-bit clock input
+-- CE => CE, -- 1-bit clock enable input
+-- DATAIN => DATAIN, -- 1-bit internal data input
+-- IDATAIN => IDATAIN, -- 1-bit input data input (connect to port)
+-- INC => INC, -- 1-bit increment/decrement input
+-- ODATAIN => ODATAIN, -- 1-bit output data input
+-- RST => RST, -- 1-bit active high, synch reset input
+-- T => T -- 1-bit 3-state control input
+-- );
+
+
+
+--*************************************************************************************************************************
+-- The LOGIC **************************************************************************************************************
+--*************************************************************************************************************************
+
+
+
+ -- LEDs
+ DGOOD <= not ep_MED_STAT_OP_IN(9);
+ DINT <= not (ep_MED_STAT_OP_IN(10) or ep_MED_STAT_OP_IN(11));
+ DBAD <= not '0';
+ DWAIT <= not '0';
+--
+
+
+
+
+-- MAPS CLK output
+ Inst_dcm3: dcm3 PORT MAP(
+ CLKIN_IN => CLK,
+ RST_IN => '0',
+ CLKFX_OUT => MAPS_CLK,
+ CLK0_OUT => open,
+ LOCKED_OUT => open
+ );
+
+--TEST_out <= jtag_tck;
+--TEST_out <= prog_jtag_finished;
+--TEST_out <= '0';
+JTAG1_TCK_OUT <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
+JTAG1_TMS_OUT <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
+JTAG1_TDI_OUT <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
+JTAG2_TCK_OUT <= (jtag_tck2 xor signals_invert2(6)) when signals_invert2(7) = '1' else signals_invert2(6);
+JTAG2_TMS_OUT <= (jtag_tms2 xor signals_invert2(4)) when signals_invert2(5) = '1' else signals_invert2(4);
+JTAG2_TDI_OUT <= (jtag_tdi2 xor signals_invert2(2)) when signals_invert2(3) = '1' else signals_invert2(2);
+JTAG3_TCK_OUT <= (jtag_tck3 xor signals_invert3(6)) when signals_invert3(7) = '1' else signals_invert3(6);
+JTAG3_TMS_OUT <= (jtag_tms3 xor signals_invert3(4)) when signals_invert3(5) = '1' else signals_invert3(4);
+JTAG3_TDI_OUT <= (jtag_tdi3 xor signals_invert3(2)) when signals_invert3(3) = '1' else signals_invert3(2);
+-- x1_saddr(3) <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
+-- x1_saddr(2) <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
+-- x1_saddr(1) <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
+-- x1_saddr(0) <= JTAG_TDO_IN;
+
+jtag_tdo_evtlinv <= (JTAG1_TDO_IN xor signals_invert(0)) when signals_invert(1) = '1' else signals_invert(0);
+jtag_tdo_evtlinv2 <= (JTAG2_TDO_IN xor signals_invert2(0)) when signals_invert2(1) = '1' else signals_invert2(0);
+jtag_tdo_evtlinv3 <= (JTAG3_TDO_IN xor signals_invert3(0)) when signals_invert3(1) = '1' else signals_invert3(0);
+
+MAPS_CLK1_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
+MAPS_CLK1_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
+MAPS_CLK2_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
+MAPS_CLK2_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
+MAPS_CLK3_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
+MAPS_CLK3_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
+
+ ODDR_MAPS_CLK1_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK1_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK1_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK1_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ ODDR_MAPS_CLK2_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK2_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK2_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK2_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ ODDR_MAPS_CLK3_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK3_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK3_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK3_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+
+-- MAPS_start_out
+-- ODDR_MAPS_start_out : ODDR
+-- generic map(
+-- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+-- INIT => '0', -- Initial value for Q port ('1' or '0')
+-- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+-- port map (
+-- Q => MAPS_start_out, -- 1-bit DDR output
+-- C => MAPS_CLK, -- 1-bit clock input
+-- CE => '1', -- 1-bit clock enable input
+-- D1 => not MAPS_start, -- 1-bit data input (positive edge) -- inverted output
+-- D2 => not MAPS_start, -- 1-bit data input (negative edge) -- inverted output
+-- R => '0', -- 1-bit reset input
+-- S => '0' -- 1-bit set input
+-- );
+MAPS_start1_out <= (MAPS_start xor signals_invert(8)) when signals_invert(9) = '1' else signals_invert(8); -- activated/deactivated and inverted/non-inverted
+MAPS_start2_out <= (MAPS_start xor signals_invert2(8)) when signals_invert2(9) = '1' else signals_invert2(8); -- activated/deactivated and inverted/non-inverted
+MAPS_start3_out <= (MAPS_start xor signals_invert3(8)) when signals_invert3(9) = '1' else signals_invert3(8); -- activated/deactivated and inverted/non-inverted
+
+
+ -- MAPS_reset_out
+-- ODDR_MAPS_reset_out : ODDR
+-- generic map(
+-- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+-- INIT => '0', -- Initial value for Q port ('1' or '0')
+-- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+-- port map (
+-- Q => MAPS_reset_out, -- 1-bit DDR output
+-- C => MAPS_CLK, -- 1-bit clock input
+-- CE => '1', -- 1-bit clock enable input
+-- D1 => not MAPS_reset, -- 1-bit data input (positive edge) -- inverted output
+-- D2 => not MAPS_reset, -- 1-bit data input (negative edge) -- inverted output
+-- R => '0', -- 1-bit reset input
+-- S => '0' -- 1-bit set input
+-- );
+--MAPS_reset_out <= not MAPS_reset;
+MAPS_reset1_out <= (MAPS_reset xor signals_invert(10)) when signals_invert(11) = '1' else signals_invert(10);
+MAPS_reset2_out <= (MAPS_reset xor signals_invert2(10)) when signals_invert2(11) = '1' else signals_invert2(10);
+MAPS_reset3_out <= (MAPS_reset xor signals_invert3(10)) when signals_invert3(11) = '1' else signals_invert3(10);
+
+COMB_MAPS_START : process(prog_jtag_finished_pulse_MAPS_CLK, MAPS_start, MAPS_start_count, beforestartcounter, beforestartcounter_finished, beforestartcounter_finished_last, waitbeforestart)
+begin
+ MAPS_start_count_next <= std_logic_vector(unsigned(MAPS_start_count) - 1);
+ if(beforestartcounter /= beforestartcounter_zero) then
+ beforestartcounter_next <= std_logic_vector(unsigned(beforestartcounter) - 1);
+ end if;
+ MAPS_start_next <= MAPS_start;
+ if(MAPS_start = '1') then
+ if(to_integer(unsigned(MAPS_start_count)) = 0) then
+ MAPS_start_next <= '0';
+ end if;
+ end if;
+ if(prog_jtag_finished_pulse_MAPS_CLK = '1') then
+ beforestartcounter_next <= waitbeforestart;
+ end if;
+ if(beforestartcounter_finished = '1' and beforestartcounter_finished_last='0') then
+ MAPS_start_next <= '1';
+ MAPS_start_count_next <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0)
+ end if;
+end process;
+
+beforestartcounter_finished_next <= '1' when beforestartcounter = beforestartcounter_zero else '0';
+beforestartcounter_finished_last_next <= beforestartcounter_finished;
+
+SEQ_MAPS_START : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ if(RESET='1') then
+ MAPS_start <= '0';
+ MAPS_start_count <= (others => '0');
+ beforestartcounter <= (others => '0');
+ beforestartcounter_finished <= '1';
+ beforestartcounter_finished_last <= '1';
+ else
+ MAPS_start <= MAPS_start_next;
+ MAPS_start_count <= MAPS_start_count_next;
+ beforestartcounter <= beforestartcounter_next;
+ beforestartcounter_finished <= beforestartcounter_finished_next;
+ beforestartcounter_finished_last <= beforestartcounter_finished_last_next;
+ end if;
+ end if;
+end process;
+
+
+
+COMB_MAPS_RESET : process(spillbreak_trigger_MAPS_CLK, MAPS_reset, MAPS_reset_count)
+begin
+ MAPS_reset_count_next <= std_logic_vector(unsigned(MAPS_reset_count) - 1);
+ MAPS_reset_next <= MAPS_reset;
+ if(MAPS_reset = '1') then
+ if(to_integer(unsigned(MAPS_reset_count)) = 0) then
+ MAPS_reset_next <= '0';
+ end if;
+ end if;
+ if(spillbreak_trigger_MAPS_CLK = '1') then
+ MAPS_reset_next <= '1';
+ MAPS_reset_count_next <= "1100100"; -- 3 clock cycles reset (on for 2,1,0)
+ end if;
+end process;
+
+-- reset signal
+SEQ_MAPS_RESET : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ if(RESET='1') then
+ MAPS_reset <= '0';
+ MAPS_reset_count <= (others => '0');
+ else
+ MAPS_reset <= MAPS_reset_next;
+ MAPS_reset_count <= MAPS_reset_count_next;
+ end if;
+ end if;
+end process;
+
+
+-- spill trigger (MAPS_CLK)
+spillbreak_trigger_MAPS_CLK <= '1' when (event_trigger_ff_MAPS_CLK = '1' and event_trigger_ff_last_MAPS_CLK = '0') else '0';
+event_trigger_ff_MAPS_CLK_next <= event_trigger when external_trigger = '1' else
+ fake_event_trigger;
+event_trigger_ff_last_MAPS_CLK_next <= event_trigger_ff_MAPS_CLK;
+SEQ_SPILLTRIGGER_MAPS_CLK : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ if(RESET='1') then
+ event_trigger_ff_last_MAPS_CLK <= '0';
+ event_trigger_ff_MAPS_CLK <= '0';
+ else
+ event_trigger_ff_MAPS_CLK <= event_trigger_ff_MAPS_CLK_next;
+ event_trigger_ff_last_MAPS_CLK <= event_trigger_ff_last_MAPS_CLK_next;
+ end if;
+ end if;
+end process;
+
+
+-- spill trigger
+spillbreak_trigger <= '1' when (event_trigger_ff = '1' and event_trigger_ff_last = '0') else '0';
+event_trigger_ff_next <= event_trigger when external_trigger = '1' else
+ fake_event_trigger;
+event_trigger_ff_last_next <= event_trigger_ff;
+SEQ_SPILLTRIGGER : process(CLK, RESET)
+begin
+ if(rising_edge(CLK)) then
+ if(RESET='1') then
+ event_trigger_ff_last <= '0';
+ event_trigger_ff <= '0';
+ else
+ event_trigger_ff <= event_trigger_ff_next;
+ event_trigger_ff_last <= event_trigger_ff_last_next;
+ end if;
+ end if;
+end process;
+
+
+-- spill trigger (MAPS_CLK)
+prog_jtag_finished_pulse_MAPS_CLK <= '1' when (prog_jtag_finished_ff_MAPS_CLK = '1' and prog_jtag_finished_ff_last_MAPS_CLK = '0') else '0';
+prog_jtag_finished_ff_MAPS_CLK_next <= prog_jtag_finished and prog_jtag_finished2 and prog_jtag_finished3;
+prog_jtag_finished_ff_last_MAPS_CLK_next <= prog_jtag_finished_ff_MAPS_CLK;
+SEQ_PROG_JTAG_FINISHED_MAPS_CLK : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ if(RESET='1') then
+ prog_jtag_finished_ff_MAPS_CLK <= '0';
+ prog_jtag_finished_ff_last_MAPS_CLK <= '0';
+ else
+ prog_jtag_finished_ff_MAPS_CLK <= prog_jtag_finished_ff_MAPS_CLK_next;
+ prog_jtag_finished_ff_last_MAPS_CLK <= prog_jtag_finished_ff_last_MAPS_CLK_next;
+ end if;
+ end if;
+end process;
+
+fet_counter_next <= (others => '0') when trbnet_fet = '1' else std_logic_vector(unsigned(fet_counter) +1) and fet_counter_limit;
+fake_event_trigger_next <= '1' when (fet_counter = x"00000000" or fet_counter = x"00000001") else
+ '0';
+
+fet_c_sync: process(CLK, RESET)
+begin
+ if(rising_edge(CLK)) then
+ if(RESET='1') then
+ fet_counter <= (others => '0');
+ fake_event_trigger <= '0';
+ else
+ fet_counter <= fet_counter_next;
+ fake_event_trigger <= fake_event_trigger_next;
+ end if;
+ end if;
+end process;
+
+com_settings_all : process
+begin
+ wait until (CLK'event and CLK='1');
+ com_settings_write_ack_out <= '0';
+ com_settings_dataready_out <= '0';
+ trbnet_fet <= '0';
+ if(com_settings_write_enable_in = '1') then
+ if(com_settings_addr_in = x"01") then
+ fet_counter_limit <= com_settings_data_in;
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"02") then
+ jcounter_initvalue <= com_settings_data_in(28 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"03") then
+ trbnet_fet <= '1';
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"06") then
+ signals_invert <= com_settings_data_in(13 downto 0); -- 13-12: MAPS_CLK, 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"07") then
+ waitbeforestart <= com_settings_data_in(31 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"08") then
+ signals_invert2 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"09") then
+ signals_invert3 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ end if;
+ elsif(com_settings_read_enable_in = '1') then
+ if(com_settings_addr_in = x"01") then
+ com_settings_data_out <= fet_counter_limit;
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"02") then
+ com_settings_data_out(28 downto 0) <= jcounter_initvalue;
+ com_settings_data_out(31 downto 29) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"04") then
+ com_settings_data_out <= fet_counter;
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"05") then
+ com_settings_data_out(28 downto 0) <= jcounter;
+ com_settings_data_out(31 downto 29) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"06") then
+ com_settings_data_out(13 downto 0) <= signals_invert;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"07") then
+ com_settings_data_out <= waitbeforestart;
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"08") then
+ com_settings_data_out(13 downto 0) <= signals_invert2;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"09") then
+ com_settings_data_out(13 downto 0) <= signals_invert3;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ end if;
+ end if;
+ if(RESET = '1') then
+ fet_counter_limit <= x"7FFFFFFF";
+ jcounter_initvalue <= (others => '1');
+ trbnet_fet <= '0';
+ end if;
+end process;
+
+
+
+
+
+end architecture basic;
--- /dev/null
+; Copyright 1991-2011 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+vital2000 = $MODEL_TECH/../vital2000
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+verilog = $MODEL_TECH/../verilog
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.2
+mtiUvm = $MODEL_TECH/../uvm-1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, effects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance
+; SeparateConfigLibrary = 1;
+
+; Change how subprogram out parameter of type array and record are treated.
+; If 1, always initial the out parameter to its default value.
+; If 2, do not initialize the out parameter.
+; The value 0 indicates use the default for the langauge version being compiled.
+; Prior to 10.1 all langauge version did not initialize out composite parameters.
+; 10.1 and later files compile with -2008 initialize by default
+; InitOutCompositeParam = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 10 ms
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 20000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 20000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations. The default value is 1000. A
+; value of 0 indicates no limit.
+; SolveACTMaxOps = 1000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 29
+Project_File_0 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_dp.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 21 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_1 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_data_to_ram_m10.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356029 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_2 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_bypassreg_testchain_m10.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349358604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_3 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_delay_expected_values.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355704 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_write_m10.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux2to1_writeport.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 23 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_6 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_read_m26devid_m10.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355852 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_7 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355799 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_8 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux2to1_readport.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 22 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_9 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_update_error_counts_ram3a.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349358039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_10 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/blank_ram.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_11 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_cmd_m26c_test.vhd
+Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350916161 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_12 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net16_regio_bus_handler.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_13 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_cmd_m26c.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907441 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_14 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux4to1_readport.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 24 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_15 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_misc.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907477 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_16 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/copy_ram.vhd
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_17 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net_components.vhd
+Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_18 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_check_crc_ram1a.vhd
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356551 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_19 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_init_ram1b.vhd
+Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355717 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_20 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/crc_32.vhd
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_21 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_sample.vhd
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_22 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/version.vhd
+Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_23 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_compare_counttotal_noram_m10.vhd
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350915625 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_24 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_compare_count_m10.vhd
+Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356574 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_25 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net_std.vhd
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_26 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tck_out_component.vhd
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_27 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_pulses.vhd
+Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_28 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_constants.vhd
+Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907278 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick =
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+Project_Major_Version = 10
+Project_Minor_Version = 0
jspc29 / jtag_mvd.git / commitdiff