]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
ADC: convert explicitly to std_logic_vector
authorAndreas Neiser <neiser@kph.uni-mainz.de>
Wed, 14 Jan 2015 10:26:34 +0000 (11:26 +0100)
committerAndreas Neiser <neiser@kph.uni-mainz.de>
Wed, 14 Jan 2015 10:26:34 +0000 (11:26 +0100)
ADC/source/adc_ad9219.vhd

index 9fb36780f097a5a4747645e4adbafa60048cd664..3a1d16b4f3f75585b4585609cfcce9fe2fe2d12f 100644 (file)
@@ -248,7 +248,7 @@ gen_chips : for i in 0 to NUM_DEVICES-1 generate
 
   proc_debug : process begin
     wait until rising_edge(CLK);
-    DEBUG(i*32+31 downto i*32+4) <= counter(i);
+    DEBUG(i*32+31 downto i*32+4) <= std_logic_vector(counter(i));
     case state_q(i) is
       when S1 =>     DEBUG(i*32+3 downto  i*32+0) <= x"1";
       when S2 =>     DEBUG(i*32+3 downto  i*32+0) <= x"2";