add 80 MHz output in pll for mimosis readout

diff --git a/mimosis/cores/pll_200_160/pll_200_160.lpc b/mimosis/cores/pll_200_160/pll_200_160.lpc
index defee1c5ce877391f02490408daea27e1d4e5f59..fe3553ead61a7f48ee0283991dee25104813a6c0 100644 (file)
--- a/mimosis/cores/pll_200_160/pll_200_160.lpc
+++ b/mimosis/cores/pll_200_160/pll_200_160.lpc
@@ -1,9 +1,9 @@
 [Device]
 Family=ecp5um
-PartType=LFE5UM-85F
-PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-45F
+PartName=LFE5UM-45F-8BG381C
 SpeedGrade=8
-Package=CABGA756
+Package=CABGA381
 OperatingCondition=COM
 Status=P
 
@@ -16,8 +16,8 @@ CoreRevision=5.8
 ModuleName=pll_200_160
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=11/12/2021
-Time=15:18:43
+Date=01/08/2024
+Time=15:30:09
 
 [Parameters]
 Verilog=0
@@ -49,11 +49,11 @@ CLKOS2_TOL=0.0
 CLKOS2_DIV=16
 CLKOS2_ACTUAL_FREQ=40.000000
 CLKOS2_MUXC=DISABLED
-CLKOS3_Enable=DISABLED
-CLKOS3_FREQ=100.00
+CLKOS3_Enable=ENABLED
+CLKOS3_FREQ=80
 CLKOS3_TOL=0.0
-CLKOS3_DIV=1
-CLKOS3_ACTUAL_FREQ=
+CLKOS3_DIV=8
+CLKOS3_ACTUAL_FREQ=80.000000
 CLKOS3_MUXD=DISABLED
 FEEDBK_PATH=CLKOP
 CLKFB_DIV=4
@@ -90,4 +90,4 @@ PLL_LOCK_STK=DISABLED
 PLL_USE_SMI=DISABLED
 
 [Command]
-cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1
+cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -fclkos3 80 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -fb_mode 1

diff --git a/mimosis/cores/pll_200_160/pll_200_160.sbx b/mimosis/cores/pll_200_160/pll_200_160.sbx
index 2c7f06c9ac9b48911a280fe5853f2cd51e83f509..bfe6c948ed0ac7d23d166f2afd5d80cc1c1dfb76 100644 (file)
--- a/mimosis/cores/pll_200_160/pll_200_160.sbx
+++ b/mimosis/cores/pll_200_160/pll_200_160.sbx
@@ -45,8 +45,8 @@
             <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
             <lattice:synthesis>synplify</lattice:synthesis>
             <lattice:date>2019-06-04.11:21:55</lattice:date>
-            <lattice:modified>2021-07-02.12:08:04</lattice:modified>
-            <lattice:diamond>3.11.2.446</lattice:diamond>
+            <lattice:modified>2024-01-08.15:30:17</lattice:modified>
+            <lattice:diamond>3.12.1.454</lattice:diamond>
             <lattice:language>VHDL</lattice:language>
             <lattice:attributes>
                 <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
@@ -78,15 +78,15 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Package</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>PartName</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F-8BG381C</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>PartType</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>SpeedGrade</lattice:lpckey>
@@ -115,7 +115,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Date</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">07/02/2021</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">01/08/2024</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>ModuleName</lattice:lpckey>
@@ -127,11 +127,11 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>SourceFormat</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Time</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">12:07:59</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">15:30:09</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>VendorName</lattice:lpckey>
@@ -188,7 +188,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">40.000000</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
@@ -196,7 +196,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
@@ -204,11 +204,11 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">40.00</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
@@ -228,7 +228,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">80.000000</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
@@ -236,7 +236,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
@@ -244,11 +244,11 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">80</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
@@ -413,7 +413,7 @@
                 <lattice:lpcsection lattice:name="Command"/>
                 <lattice:lpcentry>
                     <lattice:lpckey>cmd_line</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -fclkos3 80 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
                 </lattice:lpcentry>
             </lattice:lpc>
             <lattice:groups/>

diff --git a/mimosis/cores/pll_200_160/pll_200_160.vhd b/mimosis/cores/pll_200_160/pll_200_160.vhd
index 6759858e063c9b2060ec1af89b3cf5a45fd2b884..46cc0911a257a7a73e7be0bae67150d403d135b3 100644 (file)
--- a/mimosis/cores/pll_200_160/pll_200_160.vhd
+++ b/mimosis/cores/pll_200_160/pll_200_160.vhd
@@ -1,8 +1,8 @@
 -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
 -- Module  Version: 5.7
---/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 
+--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -fclkos3 80 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/trb5sc/mimosis/cores/pll_200_160/pll_200_160.fdc 
 
--- Fri Nov 12 15:18:43 2021
+-- Mon Jan  8 15:30:17 2024
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -14,7 +14,8 @@ entity pll_200_160 is
         CLKI: in  std_logic; 
         CLKOP: out  std_logic; 
         CLKOS: out  std_logic; 
-        CLKOS2: out  std_logic);
+        CLKOS2: out  std_logic; 
+        CLKOS3: out  std_logic);
 end pll_200_160;
 
 architecture Structure of pll_200_160 is
@@ -22,18 +23,21 @@ architecture Structure of pll_200_160 is
     -- internal signal declarations
     signal REFCLK: std_logic;
     signal LOCK: std_logic;
+    signal CLKOS3_t: std_logic;
     signal CLKOS2_t: std_logic;
     signal CLKOS_t: std_logic;
     signal CLKOP_t: std_logic;
     signal scuba_vhi: std_logic;
     signal scuba_vlo: std_logic;
 
+    attribute FREQUENCY_PIN_CLKOS3 : string; 
     attribute FREQUENCY_PIN_CLKOS2 : string; 
     attribute FREQUENCY_PIN_CLKOS : string; 
     attribute FREQUENCY_PIN_CLKOP : string; 
     attribute FREQUENCY_PIN_CLKI : string; 
     attribute ICP_CURRENT : string; 
     attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "80.000000";
     attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000";
     attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000";
     attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
@@ -55,15 +59,15 @@ begin
     PLLInst_0: EHXPLLL
         generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
         STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
-        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  7, CLKOS2_FPHASE=>  0, 
         CLKOS2_CPHASE=>  15, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  1, 
         CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  3, PLL_LOCK_MODE=>  0, 
         CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
         CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
-        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED", 
         OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", 
         OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 
-        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  8, 
         CLKOS2_DIV=>  16, CLKOS_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  4, 
         CLKI_DIV=>  5, FEEDBK_PATH=> "CLKOP")
         port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 
@@ -72,9 +76,10 @@ begin
             STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
             ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
             ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 
-            CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
-            REFCLK=>REFCLK, CLKINTFB=>open);
+            CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK, 
+            INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
 
+    CLKOS3 <= CLKOS3_t;
     CLKOS2 <= CLKOS2_t;
     CLKOS <= CLKOS_t;
     CLKOP <= CLKOP_t;