ADC_CMD_2 : std_logic_vector(19 downto 0) := x"1d3cb";
ADC_CMD_3 : std_logic_vector(19 downto 0) := x"1e5cb";
ADC_CMD_4 : std_logic_vector(19 downto 0) := x"2f3cb";
- ADC_CMD_T : std_logic_vector(19 downto 0) := x"1F393"
+ ADC_CMD_T : std_logic_vector(19 downto 0) := x"1F393";
+ NUM_COINCIDENCES : integer range 1 to 24 := 24;
+ NUM_MULTIPLICITIES : integer range 1 to 3 := 3
);
port(
CLK : in std_logic;
THE_SED : entity work.sedcheck
port map(
CLK => CLK,
+ DISABLE_IN => PREPARE_FOR_RELOAD,
ERROR_OUT => SED_ERROR_OUT,
RELOAD_OUT => sed_reload_i,
BUS_RX => bussed_rx,
THE_TRIG_LOGIC : entity work.input_to_trigger_logic_record
generic map(
INPUTS => TRIG_GEN_INPUT_NUM,
- OUTPUTS => TRIG_GEN_OUTPUT_NUM
+ OUTPUTS => TRIG_GEN_OUTPUT_NUM,
+ NUM_COINCIDENCES => NUM_COINCIDENCES,
+ NUM_MULTIPLICITIES => NUM_MULTIPLICITIES
)
port map(
CLK => CLK,