updated trb3_gbe to new gbe

diff --git a/trb3_gbe/compile_central_frankfurt.pl b/trb3_gbe/compile_central_frankfurt.pl
index 9b1dab80a5daf96f8913c8dc87f0ecdc3fd78097..c5e582fd5485105738c00cf8e98ed0a4295d31ac 100755 (executable)
--- a/trb3_gbe/compile_central_frankfurt.pl
+++ b/trb3_gbe/compile_central_frankfurt.pl
@@ -10,7 +10,7 @@ use strict;
 #Settings for this project
 my $TOPNAME                      = "trb3_central";  #Name of top-level entity
 #my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
-my $lattice_path                 = '/d/jspc29/lattice/diamond/2.2_x64';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
 # my $synplify_path                = '/d/jspc29/lattice/synplify/fpga_e201103/';
 my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";

diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj
index 202a0afd0f621e1c97df4e8785a28802cba1bc25..d06e52e64c8b4cfc9c50220b37c852daf7c18845 100644 (file)
--- a/trb3_gbe/trb3_central.prj
+++ b/trb3_gbe/trb3_central.prj
@@ -26,6 +26,10 @@ set_option -fixgatedclocks 3
 set_option -fixgeneratedclocks 3
 set_option -compiler_compatible true
 
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
 
 # simulation options
 set_option -write_verilog 0
@@ -135,6 +139,15 @@ add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_c
 add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v"
 add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v"
 
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd"
+
+
 
 #trbnet and base files
 
@@ -203,6 +216,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"

diff --git a/trb3_gbe/trb3_central_constraints.lpf b/trb3_gbe/trb3_central_constraints.lpf
index 06450c8db4e35cc0e9541be231045ea63d8f60b0..c0bd043c7800ca0e13450226204b3df1c5ec3f43 100644 (file)
--- a/trb3_gbe/trb3_central_constraints.lpf
+++ b/trb3_gbe/trb3_central_constraints.lpf
@@ -150,8 +150,8 @@ UGROUP "gbe_rx_tx"
 #Normal design\r
 REGION "GBE_REGION" "R30C20D" 35 40 DEVSIZE;\r
 REGION "GBE_MAIN_REGION" "R74C40C" 38 36 DEVSIZE;\r
-LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
-LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
+#LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
+#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
 \r
 #Reduced design\r
 # REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
@@ -164,7 +164,7 @@ LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
 REGION "MED0" "R69C4D" 35 40 DEVSIZE;\r
 FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
 FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ;\r
-LOCATE UGROUP "tsmac" REGION "MED0" ;\r
+#LOCATE UGROUP "tsmac" REGION "MED0" ;\r
 BLOCK JTAGPATHS ;\r
 UGROUP "sd_tx_to_pcs" \r
        BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q\r

diff --git a/wasa/.gitignore b/wasa/.gitignore
new file mode 100644 (file)
index 0000000..5191b60
--- /dev/null
+++ b/wasa/.gitignore
@@ -0,0 +1 @@
+project