#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
#my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
-my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
set_option -fixgeneratedclocks 3
set_option -compiler_compatible true
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
# simulation options
set_option -write_verilog 0
add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v"
add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd"
+
+
#trbnet and base files
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
#Normal design\r
REGION "GBE_REGION" "R30C20D" 35 40 DEVSIZE;\r
REGION "GBE_MAIN_REGION" "R74C40C" 38 36 DEVSIZE;\r
-LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
-LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
+#LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
+#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
\r
#Reduced design\r
# REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
REGION "MED0" "R69C4D" 35 40 DEVSIZE;\r
FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ;\r
-LOCATE UGROUP "tsmac" REGION "MED0" ;\r
+#LOCATE UGROUP "tsmac" REGION "MED0" ;\r
BLOCK JTAGPATHS ;\r
UGROUP "sd_tx_to_pcs" \r
BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q\r