finish CTS / backplane master design

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 6fe8d5220bd4c0690b47d3b9617159215b581b44..319220cd1969e19641977d35085810a143bfd5ff 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -26,7 +26,7 @@ entity trb3sc_cts is
     BACK_GPIO            : inout std_logic_vector( 3 downto 0);
     
     SPARE_IN             : in    std_logic_vector( 1 downto  0);
-    INP                  : in    std_logic_vector(31-12*USE_RJADAPT downto  0); 
+    INP                  : in    std_logic_vector(31-12*USE_RJADAPT+64*USE_BACKPLANE downto  64*USE_BACKPLANE); 
     RJ_IO                : out   std_logic_vector( 3 downto  0); --0, inner RJ trigger output
     RJ_IO_IN             : in    std_logic_vector( 1 downto  0);
     REFOUT               : out   std_logic_vector( 8*USE_RJADAPT-1 downto  0);
@@ -49,20 +49,20 @@ entity trb3sc_cts is
     SFP_MOD2             : inout std_logic_vector( 1 downto 0) := (others => 'Z');
     SFP_TX_DIS           : out   std_logic_vector( 1 downto 0) := (others => '0');  
 
-    LED_HUB_LINKOK       : out   std_logic_vector(8 downto 1);
-    LED_HUB_RX           : out   std_logic_vector(8 downto 1);
-    LED_HUB_TX           : out   std_logic_vector(8 downto 1);
-    HUB_MOD0             : in    std_logic_vector(8 downto 1);
-    HUB_MOD1             : inout std_logic_vector(8 downto 1);
-    HUB_MOD2             : inout std_logic_vector(8 downto 1);
-    HUB_TXDIS            : out   std_logic_vector(8 downto 1);
-    HUB_LOS              : in    std_logic_vector(8 downto 1);
+    LED_HUB_LINKOK       : out   std_logic_vector(8*USE_ADDON-1 downto 1);
+    LED_HUB_RX           : out   std_logic_vector(8*USE_ADDON-1 downto 1);
+    LED_HUB_TX           : out   std_logic_vector(8*USE_ADDON-1 downto 1);
+    HUB_MOD0             : in    std_logic_vector(8*USE_ADDON-1 downto 1);
+    HUB_MOD1             : inout std_logic_vector(8*USE_ADDON-1 downto 1);
+    HUB_MOD2             : inout std_logic_vector(8*USE_ADDON-1 downto 1);
+    HUB_TXDIS            : out   std_logic_vector(8*USE_ADDON-1 downto 1);
+    HUB_LOS              : in    std_logic_vector(8*USE_ADDON-1 downto 1);
 
     --Lines to slaves
-    BACK_MASTER_READY    : out   std_logic_vector(8 downto 0);
-    BACK_SLAVE_READY     : in    std_logic_vector(8 downto 0);
-    BACK_TRIG1           : in    std_logic_vector(8 downto 0);
-    BACK_TRIG2           : in    std_logic_vector(8 downto 0);    
+    BACK_MASTER_READY    : out   std_logic_vector(9*USE_BACKPLANE-1 downto 0);
+    BACK_SLAVE_READY     : in    std_logic_vector(9*USE_BACKPLANE-1 downto 0);
+    BACK_TRIG1           : in    std_logic_vector(9*USE_BACKPLANE-1 downto 0);
+    BACK_TRIG2           : in    std_logic_vector(9*USE_BACKPLANE-1 downto 0);    
     
     --Serdes switch
     PCSSW_ENSMB          : out   std_logic;
@@ -77,10 +77,10 @@ entity trb3sc_cts is
     ADC_DOUT             : in    std_logic;
 
     --SPI
-    DAC_OUT_SDO      : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
-    DAC_OUT_SCK      : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
-    DAC_OUT_CS       : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
-    DAC_IN_SDI       : in  std_logic_vector(6 downto 5+2*USE_RJADAPT); --
+    DAC_OUT_SDO      : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); --
+    DAC_OUT_SCK      : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); --
+    DAC_OUT_CS       : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); --
+    DAC_IN_SDI       : in  std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); --
 
     
     --Flash, 1-wire, Reload
@@ -939,7 +939,7 @@ gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate
 end generate;
 gen_inputs_bkpl : if USE_BACKPLANE = 1 generate        
   cts_addon_triggers_in(1 downto 0)  <= SPARE_IN(1 downto 0);
-  cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
+  cts_addon_triggers_in(33 downto 2) <= INP(95 downto 64);
   cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);  
   gen_trg_inputs : for i in 0 to 8 generate
     cts_addon_triggers_in(i*2+37 downto i*2+36) <= BACK_TRIG2(i) & BACK_TRIG1(i);
@@ -1185,7 +1185,7 @@ end generate;
 ---------------------------------------------------------------------------
 -- I/O
 ---------------------------------------------------------------------------
-gen_SPI : if USE_RJADAPT = 0 generate
+gen_SPI : if USE_RJADAPT = 0 and USE_BACKPLANE = 0 generate
   spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
   DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
   DAC_OUT_CS(6 downto 5)  <= spi_cs(5 downto 4);

diff --git a/pinout/trb3sc_hub_ctsrj.lpf b/pinout/trb3sc_hub_ctsrj.lpf
index 282b4a4175cd5d11a3abfb2076c2ba15e18c6afa..bb731465d789eea34143f0476fa45a164b49db92 100644 (file)
--- a/pinout/trb3sc_hub_ctsrj.lpf
+++ b/pinout/trb3sc_hub_ctsrj.lpf
@@ -295,6 +295,11 @@ IOBUF  PORT "RJ_IO_1" IO_TYPE=LVDS25 ;
 IOBUF  PORT "RJ_IO_2" IO_TYPE=LVDS25E ;\r
 IOBUF  PORT "RJ_IO_3" IO_TYPE=LVDS25E ;\r
 \r
+LOCATE COMP "RJ_IO_IN_0"                      SITE "R28";\r
+LOCATE COMP "RJ_IO_IN_1"                      SITE "R31";\r
+IOBUF  PORT "RJ_IO_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+IOBUF  PORT "RJ_IO_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+\r
 \r
 LOCATE COMP "SPARE_IN_0"                    SITE "K31";\r
 LOCATE COMP "SPARE_IN_1"                    SITE "R4";\r

diff --git a/pinout/trb3sc_master.lpf b/pinout/trb3sc_master.lpf
index 6276efe82ffa5d831593f6f71a999fe447e45f74..cfc72c401cf5def128304332b5e22d9871e1279e 100644 (file)
--- a/pinout/trb3sc_master.lpf
+++ b/pinout/trb3sc_master.lpf
@@ -261,6 +261,11 @@ IOBUF  PORT "RJ_IO_1" IO_TYPE=LVDS25 ;
 IOBUF  PORT "RJ_IO_2" IO_TYPE=LVDS25E ;\r
 IOBUF  PORT "RJ_IO_3" IO_TYPE=LVDS25E ;\r
 \r
+LOCATE COMP "RJ_IO_IN_0"                      SITE "R28";\r
+LOCATE COMP "RJ_IO_IN_1"                      SITE "R31";\r
+IOBUF  PORT "RJ_IO_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+IOBUF  PORT "RJ_IO_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+\r
 \r
 LOCATE COMP "SPARE_IN_0"                    SITE "K31";\r
 LOCATE COMP "SPARE_IN_1"                    SITE "R4";\r