+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
--- /dev/null
+#-w
+#-i 15
+#-l 5
+#-y
+#-s 12
+#-t 6
+#-c 1
+#-e 2
+##-g guidefile.ncd
+##-m nodelist.txt
+#-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+
+-w
+-l 5
+-i 6
+-n 1
+-t 5
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=ON:parHoldLimit=10000
+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
# Basic Settings
#################################################################
-SYSCONFIG MCCLK_FREQ = 20;
-
-FREQUENCY PORT CLK_CORE_PCLK 240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz;
-
-FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz;
-FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz;
-FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz;
-
-FREQUENCY PORT CLK_EXT_PCLK 200 MHz;
-FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz;
-FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz;
-
-
-MULTICYCLE TO CELL "THE_MEDIA_INT*/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_INT*/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_MEDIA_INT*/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "THE_MEDIA_INT*/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_write_i";
-BLOCK PATH TO CLKNET "THE_MEDIA_INT*/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_read_i";
-
-FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
-FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
-
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "SFP*";
BLOCK PATH FROM PORT "SFP*";
BLOCK PATH TO PORT "PROGRAMN";
BLOCK PATH TO PORT "TEMPSENS";
BLOCK PATH FROM PORT "TEMPSENS";
-BLOCK PATH TO PORT "TESTLINE";
+BLOCK PATH TO PORT "TEST_LINE";
PROHIBIT PRIMARY NET "ENPIRION_CLOCK_c" ;
PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ;
+
+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_osc TO CLKNET clk_100_osc 5x;
-# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_EXT_c 2x;
+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
system("cat tdc_release/dirich_tdc_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
system("ln -s $cwd/../../tdc/base/cores/ecp5/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
} else {
- system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+# system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
system("cat tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf");
system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
system("ln -s $cwd/../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
}
- system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+# system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
#edit the lpf file according to tdc settings
system("unlink $WORKDIR/compile_tdc.pl");
+++ /dev/null
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
-
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x;