GbE hub recompiled with new FIFO interfacing

diff --git a/gbe_hub/clock_reset_handler.vhd b/gbe_hub/clock_reset_handler.vhd
index 8a3dc29e7b5947104dbdd18443b5c90278e33cd6..ff888f2bb5dd1629f4c056c50b74c14c52f035a9 100644 (file)
--- a/gbe_hub/clock_reset_handler.vhd
+++ b/gbe_hub/clock_reset_handler.vhd
@@ -20,6 +20,9 @@ entity clock_reset_handler is
     CLEAR_OUT         : out std_logic;
     CLEAR_N_OUT       : out std_logic;
     --
+    TICK_MS_OUT       : out std_logic;
+    TICK_US_OUT       : out std_logic;
+    --
     ENPIRION_CLOCK    : out std_logic;
     LED_RED_OUT       : out std_logic;
     LED_GREEN_OUT     : out std_logic
@@ -35,6 +38,14 @@ signal clk_enpirion                 : std_logic;
 signal pll_enpirion_locked          : std_logic;
 signal enpirion_clock_i             : std_logic;
 
+signal ms_counter                   : unsigned(16 downto 0);
+signal ms_counter_done_x            : std_logic;
+signal ms_counter_done              : std_logic;
+
+signal us_counter                   : unsigned(6 downto 0);
+signal us_counter_done_x            : std_logic;
+signal us_counter_done              : std_logic;
+
 attribute syn_keep                  : boolean;
 attribute syn_preserve              : boolean;
 attribute syn_keep of clear_n_i     : signal is true;
@@ -44,6 +55,44 @@ begin
 
   CLK_OUT <= CLK_IN;
 
+---------------------------------------------------------------------------
+-- 1ms tick counter
+---------------------------------------------------------------------------
+  THE_MS_COUNTER_PROC: process( CLK_IN )
+  begin
+    if( rising_edge(CLK_IN) ) then
+      ms_counter_done <= ms_counter_done_x;
+      if( ms_counter_done = '1' ) then
+        ms_counter <= b"1_1110_1000_0100_0110";
+      else
+        ms_counter <= ms_counter - 1;
+      end if;
+    end if;
+  end process THE_MS_COUNTER_PROC; 
+ 
+  ms_counter_done_x <= '1' when (ms_counter = b"0_0000_0000_0000_0000") else '0'; 
+
+  TICK_MS_OUT <= ms_counter_done;
+
+---------------------------------------------------------------------------
+-- 1us tick counter
+---------------------------------------------------------------------------
+  THE_US_COUNTER_PROC: process( CLK_IN )
+  begin
+    if( rising_edge(CLK_IN) ) then
+      us_counter_done <= us_counter_done_x;
+      if( us_counter_done = '1' ) then
+        us_counter <= b"111_1011";
+      else
+        us_counter <= us_counter - 1;
+      end if;
+    end if;
+  end process THE_US_COUNTER_PROC; 
+ 
+  us_counter_done_x <= '1' when (us_counter = b"000_0000") else '0'; 
+
+  TICK_US_OUT <= us_counter_done;
+
 ---------------------------------------------------------------------------
 -- Startup timer, generates inital reset
 ---------------------------------------------------------------------------          

diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj
index 535628d0f300b182305c99fa0391701e144f3507..39b5f668363e7beaec9e137801e96dc35111b686 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.prj
+++ b/gbe_hub/trb3sc_gbe_hub.prj
@@ -181,12 +181,8 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
 
 
 #GbE
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_single.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"

diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd
index 014ec04c0c858374cc2f121992c8482dada1275c..c4fd23e9cf6194ff63d29c946eac9640a1e6eff2 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.vhd
+++ b/gbe_hub/trb3sc_gbe_hub.vhd
@@ -117,7 +117,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
   signal gsc_reply_packet_num       : std_logic_vector(2 downto 0);
   signal gsc_busy                   : std_logic;
 
-  signal status                     : std_logic_vector(15 downto 0);
+  signal status                     : std_logic_vector(7 downto 0);
 
   -- SerDes low level stuff
   signal tx_pll_lol_i               : std_logic;
@@ -163,6 +163,14 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
   signal link_active                : std_logic;
   
   signal debug                      : std_logic_vector(31 downto 0);
+
+  signal sniffer_data               : std_logic_vector(7 downto 0);
+  signal sniffer_wr                 : std_logic;
+  signal sniffer_eof                : std_logic;
+  signal sniffer_error              : std_logic;
+  
+  signal tick_ms_int                : std_logic;
+  signal tick_us_int                : std_logic;
   
 begin
 
@@ -201,112 +209,23 @@ begin
     CLEAR_OUT         => clear_i,
     CLEAR_N_OUT       => clear_n_i,
     --
+    TICK_MS_OUT       => tick_ms_int,
+    TICK_US_OUT       => tick_us_int,
     ENPIRION_CLOCK    => ENPIRION_CLOCK,
     LED_RED_OUT       => LED_RJ_RED(1),
     LED_GREEN_OUT     => LED_RJ_GREEN(1)
   );
   
+  
 ---------------------------------------------------------------------------
--- PCSC is four ports downlink
+-- scattering: data from uplink is distributed to downlinks
 ---------------------------------------------------------------------------
-  THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo
-  generic map(
-    LINKS_ACTIVE                => "1111"
-  )
-  port map(
-    RESET                       => reset_i,
-    RESET_N                     => reset_n_i,
-    CLEAR                       => clear_i,
-    CLEAR_N                     => clear_n_i,
-    CLK_125                     => clk_sys,
-    -- SerDes 0 -- DOWNLINK
-    -- FIFO interface RX           
-    FIFO_FULL_IN(0)             => ul_tx_fifofull,
-    FIFO_WR_OUT(0)              => dl_rx_data(6)(9),
-    FIFO_DATA_OUT(8 downto 0)   => dl_rx_data(6)(8 downto 0),
-    FRAME_START_OUT(0)          => dl_rx_data(6)(10),
-    FRAME_REQ_IN(0)             => dl_rx_frame_req(6),
-    FRAME_ACK_OUT(0)            => dl_rx_frame_ack(6),
-    FRAME_AVAIL_OUT(0)          => dl_rx_frame_avail(6),
-    -- FIFO interface TX           
-    FIFO_WR_IN(0)               => ul_rx_data(9),
-    FIFO_DATA_IN(8 downto 0)    => ul_rx_data(8 downto 0),
-    FRAME_START_IN(0)           => ul_rx_data(10),
-    FIFO_FULL_OUT(0)            => dl_tx_fifofull(6),
-    -- SerDes 1 - DOWNLINK         
-    -- FIFO interface RX           
-    FIFO_FULL_IN(1)             => ul_tx_fifofull,
-    FIFO_WR_OUT(1)              => dl_rx_data(7)(9),
-    FIFO_DATA_OUT(17 downto 9)  => dl_rx_data(7)(8 downto 0),
-    FRAME_START_OUT(1)          => dl_rx_data(7)(10),
-    FRAME_REQ_IN(1)             => dl_rx_frame_req(7),
-    FRAME_ACK_OUT(1)            => dl_rx_frame_ack(7),
-    FRAME_AVAIL_OUT(1)          => dl_rx_frame_avail(7),
-    -- FIFO interface TX           
-    FIFO_WR_IN(1)               => ul_rx_data(9),
-    FIFO_DATA_IN(17 downto 9)   => ul_rx_data(8 downto 0),
-    FRAME_START_IN(1)           => ul_rx_data(10),
-    FIFO_FULL_OUT(1)            => dl_tx_fifofull(7),
-    -- SerDes 2 -- DOWNLINK        
-    -- FIFO interface RX           
-    FIFO_FULL_IN(2)             => ul_tx_fifofull,
-    FIFO_WR_OUT(2)              => dl_rx_data(4)(9),
-    FIFO_DATA_OUT(26 downto 18) => dl_rx_data(4)(8 downto 0),
-    FRAME_START_OUT(2)          => dl_rx_data(4)(10),
-    FRAME_REQ_IN(2)             => dl_rx_frame_req(4),
-    FRAME_ACK_OUT(2)            => dl_rx_frame_ack(4),
-    FRAME_AVAIL_OUT(2)          => dl_rx_frame_avail(4),
-    -- FIFO interface TX           
-    FIFO_WR_IN(2)               => ul_rx_data(9),
-    FIFO_DATA_IN(26 downto 18)  => ul_rx_data(8 downto 0),
-    FRAME_START_IN(2)           => ul_rx_data(10),
-    FIFO_FULL_OUT(2)            => dl_tx_fifofull(4),
-    -- SerDes 3 -- DOWNLINK        
-    -- FIFO interface RX           
-    FIFO_FULL_IN(3)             => ul_tx_fifofull,
-    FIFO_WR_OUT(3)              => dl_rx_data(5)(9),
-    FIFO_DATA_OUT(35 downto 27) => dl_rx_data(5)(8 downto 0),
-    FRAME_START_OUT(3)          => dl_rx_data(5)(10),
-    FRAME_REQ_IN(3)             => dl_rx_frame_req(5),
-    FRAME_ACK_OUT(3)            => dl_rx_frame_ack(5),
-    FRAME_AVAIL_OUT(3)          => dl_rx_frame_avail(5),
-    -- FIFO interface TX           
-    FIFO_WR_IN(3)               => ul_rx_data(9),
-    FIFO_DATA_IN(35 downto 27)  => ul_rx_data(8 downto 0),
-    FRAME_START_IN(3)           => ul_rx_data(10),
-    FIFO_FULL_OUT(3)            => dl_tx_fifofull(5),
-    -- SFP Connection
-    SD_PRSNT_N_IN(0)            => HUB_MOD0(3),
-    SD_PRSNT_N_IN(1)            => HUB_MOD0(4),
-    SD_PRSNT_N_IN(2)            => HUB_MOD0(1),
-    SD_PRSNT_N_IN(3)            => HUB_MOD0(2),
-    SD_LOS_IN(0)                => HUB_LOS(3),
-    SD_LOS_IN(1)                => HUB_LOS(4),
-    SD_LOS_IN(2)                => HUB_LOS(1),
-    SD_LOS_IN(3)                => HUB_LOS(2),
-    SD_TXDIS_OUT(0)             => HUB_TXDIS(3),
-    SD_TXDIS_OUT(1)             => HUB_TXDIS(4),
-    SD_TXDIS_OUT(2)             => HUB_TXDIS(1),
-    SD_TXDIS_OUT(3)             => HUB_TXDIS(2),
-    -- SerDes control          
-    TX_PLOL_LOL_OUT             => tx_pll_lol_c_i,
-    TX_PCS_RST_IN               => tx_pcs_rst_i,
-    RX_LINK_READY_OUT           => open,
-    TX_LINK_READY_IN            => link_tx_ready_i,
-    PCS_AN_READY_OUT(0)         => pcs_an_ready, --open, -- for internal SCTRL
-    LINK_ACTIVE_OUT(0)          => link_active, --open, -- for internal SCTRL
-    -- Debug                   
-    STATUS_OUT                  => status_raw(3 * 32 - 1 downto 2 * 32),
-    DEBUG_OUT                   => open
-  );
-  
-  -- scattering: data from uplink is distributed to downlinks
   THE_SCATTER: entity scatter_ports
   port map(
     CLK                       => clk_sys,
     RESET                     => reset_i,
     --
-    FIFO_FULL_IN(3 downto 0)  => dl_tx_fifofull(3 downto 0),
+    FIFO_FULL_IN(10 downto 1) => dl_tx_fifofull(10 downto 1),
     FIFO_FULL_OUT             => ul_rx_fifofull,
     FRAME_AVAIL_IN            => ul_rx_frame_avail,
     FRAME_REQ_OUT             => ul_rx_frame_req,
@@ -316,15 +235,19 @@ begin
     DEBUG                     => open
   );
 
+---------------------------------------------------------------------------
+-- gathering: data from downlink ports is forwarded
+---------------------------------------------------------------------------
   THE_GATHER: entity gather_ports
   port map(
     CLK                          => clk_sys,
     RESET                        => reset_i,
     --
-    FRAME_AVAIL_IN(10 downto 0)   => dl_rx_frame_avail,
-    FRAME_REQ_OUT(10 downto 0)    => dl_rx_frame_req,
-    FRAME_ACK_IN(10 downto 0)     => dl_rx_frame_ack,
-    PORT_SELECT_OUT(10 downto 0)  => port_sel,
+    FRAME_AVAIL_IN(10 downto 0)  => dl_rx_frame_avail(10 downto 0),
+    FRAME_REQ_OUT(10 downto 0)   => dl_rx_frame_req(10 downto 0),
+    FRAME_ACK_IN(10 downto 0)    => dl_rx_frame_ack(10 downto 0),
+    PORT_SELECT_OUT(10 downto 0) => port_sel(10 downto 0),
+    PORT_MUX_OUT                 => open,
     CYCLE_DONE_OUT               => open,
     --
     DEBUG                        => open
@@ -389,7 +312,7 @@ begin
       -- Trigger
       TRIGGER_IN               => '0',
       -- we connect to FIFO interface directly
-      -- FIFO interface RX
+      -- FIFO interface TX (send frames)
       FIFO_DATA_OUT            => dl_rx_data(0)(8 downto 0),
       FIFO_FULL_IN             => ul_tx_fifofull,
       FIFO_WR_OUT              => dl_rx_data(0)(9),
@@ -397,13 +320,13 @@ begin
       FRAME_ACK_OUT            => dl_rx_frame_ack(0),
       FRAME_AVAIL_OUT          => dl_rx_frame_avail(0),
       FRAME_START_OUT          => dl_rx_data(0)(10),
-      -- FIFO interface TX
-      FIFO_FULL_OUT            => dl_tx_fifofull(0),
-      FIFO_WR_IN               => ul_rx_data(9),
-      FIFO_DATA_IN             => ul_rx_data(8 downto 0),
-      FRAME_START_IN           => ul_rx_data(10),
+      -- FIFO interface RX (receive frames)
+      MAC_RX_DATA_IN           => sniffer_data,
+      MAC_RX_WRITE_IN          => sniffer_wr,
+      MAC_RX_EOF_IN            => sniffer_eof,
+      MAC_RX_ERROR_IN          => sniffer_error,
       --
-      PCS_AN_READY_IN          => pcs_an_ready,
+      PCS_AN_READY_IN          => link_active,
       LINK_ACTIVE_IN           => link_active,
       --                        
       -- unique adresses
@@ -549,66 +472,62 @@ begin
   flash_miso_i <= FLASH_OUT;
 
   do_reboot_i  <= common_ctrl_reg(15) or reboot_from_gbe;
-
+  
 ---------------------------------------------------------------------------
--- LED
+-- PCSA is one port downlink (backplane)
 ---------------------------------------------------------------------------
-  -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
-  LED_GREEN            <= not status(6); --'0';
-  LED_ORANGE           <= not status(5); --'0';
-  LED_RED              <= not '0';
-  LED_YELLOW           <= not '0';
-
---GEN_HUB_LEDS : for i in 0 to 6 generate
---  LED_HUB_LINKOK(i+1) <= not '0';
---  LED_HUB_TX(i+1)     <= not '0';
---  LED_HUB_RX(i+1)     <= not '0';
---end generate;
-
-  LED_HUB_LINKOK(1)  <= not status_raw(10 * 8 + 6); --'0'; -- C2
-  LED_HUB_TX(1)      <= not status_raw(10 * 8 + 5); --'0';
-  LED_HUB_RX(1)      <= not '0';
-
-  LED_HUB_LINKOK(2)  <= not status_raw(11 * 8 + 6); --'0'; -- C3
-  LED_HUB_TX(2)      <= not status_raw(11 * 8 + 5); --'0';
-  LED_HUB_RX(2)      <= not '0';
-
-  LED_HUB_LINKOK(3)  <= not status_raw(8 * 8 + 6); --'0'; -- C0
-  LED_HUB_TX(3)      <= not status_raw(8 * 8 + 5); --'0';
-  LED_HUB_RX(3)      <= not '0';
-
-  LED_HUB_LINKOK(4)  <= not status_raw(9 * 8 + 6); --'0'; -- C1
-  LED_HUB_TX(4)      <= not status_raw(9 * 8 + 5); --'0';
-  LED_HUB_RX(4)      <= not '0';
-
-  LED_HUB_LINKOK(5)  <= not status_raw(4 * 8 + 6); --'0'; -- B0
-  LED_HUB_TX(5)      <= not status_raw(4 * 8 + 5); --'0';
-  LED_HUB_RX(5)      <= not '0';
-
-  LED_HUB_LINKOK(6)  <= not status_raw(5 * 8 + 6); --'0'; -- B1
-  LED_HUB_TX(6)      <= not status_raw(5 * 8 + 5); --'0';
-  LED_HUB_RX(6)      <= not '0';
-  
-  LED_HUB_LINKOK(7)  <= not status_raw(5 * 8 + 6); --'0'; -- B2
-  LED_HUB_TX(7)      <= not status_raw(6 * 8 + 5); --'0';
-  LED_HUB_RX(7)      <= not '0';
-
-  LED_HUB_LINKOK(8)  <= not status_raw(5 * 8 + 6); --'0'; -- B3
-  LED_HUB_TX(8)      <= not status_raw(7 * 8 + 5); --'0';
-  LED_HUB_RX(8)      <= not '0';
-
-  LED_SFP_GREEN(0)   <= not status_raw(12 * 8 + 6); --'0'; -- D0
-  LED_SFP_RED(0)     <= not status_raw(12 * 8 + 5); --'0';
-
-  LED_SFP_GREEN(1)   <= not status_raw(13 * 8 + 6); --'0'; -- D1
-  LED_SFP_RED(1)     <= not status_raw(13 * 8 + 5); --'0';
-  
-  LED_WHITE(1)       <= not additional_reg(31); --'0';
-  LED_WHITE(0)       <= not status(8); --'0';
-
-  LED_RJ_GREEN(0)    <= not status_raw(0 * 8 + 6); -- A0
-  LED_RJ_RED(0)      <= not status_raw(0 * 8 + 5);
-  
+  THE_GBE_MED_RAW_PCSA: entity gbe_med_fifo
+  generic map(
+    LINKS_ACTIVE                => "0001"
+  )
+  port map(
+    RESET                       => reset_i,
+    RESET_N                     => reset_n_i,
+    CLEAR                       => clear_i,
+    CLEAR_N                     => clear_n_i,
+    CLK_125                     => clk_sys,
+    -- SerDes 0 -- DOWNLINK
+    -- FIFO interface RX           
+    FIFO_FULL_IN(0)             => ul_tx_fifofull,
+    FIFO_WR_OUT(0)              => dl_rx_data(10)(9),
+    FIFO_DATA_OUT(8 downto 0)   => dl_rx_data(10)(8 downto 0),
+    FRAME_START_OUT(0)          => dl_rx_data(10)(10),
+    FRAME_REQ_IN(0)             => dl_rx_frame_req(10),
+    FRAME_ACK_OUT(0)            => dl_rx_frame_ack(10),
+    FRAME_AVAIL_OUT(0)          => dl_rx_frame_avail(10),
+    -- FIFO interface TX           
+    FIFO_WR_IN(0)               => ul_rx_data(9),
+    FIFO_DATA_IN(8 downto 0)    => ul_rx_data(8 downto 0),
+    FRAME_START_IN(0)           => ul_rx_data(10),
+    FIFO_FULL_OUT(0)            => dl_tx_fifofull(10),
+    -- SerDes 1 -- UNUSED
+    -- SerDes 2 -- UNUSED
+    -- SerDes 3 -- UNUSED
+    -- SFP Connection
+    SD_PRSNT_N_IN(0)            => HUB_MOD0(5),
+    SD_PRSNT_N_IN(1)            => '1',
+    SD_PRSNT_N_IN(2)            => '1',
+    SD_PRSNT_N_IN(3)            => '1',
+    SD_LOS_IN(0)                => HUB_LOS(5),
+    SD_LOS_IN(1)                => '1',
+    SD_LOS_IN(2)                => '1',
+    SD_LOS_IN(3)                => '1',
+    SD_TXDIS_OUT(0)             => HUB_TXDIS(5),
+    SD_TXDIS_OUT(1)             => open,
+    SD_TXDIS_OUT(2)             => open,
+    SD_TXDIS_OUT(3)             => open,
+    -- SerDes control          
+    TX_PLOL_LOL_OUT             => tx_pll_lol_a_i,
+    TX_PCS_RST_IN               => tx_pcs_rst_i,
+    RX_LINK_READY_OUT           => open,
+    TX_LINK_READY_IN            => link_tx_ready_i,
+    PCS_AN_READY_OUT(0)         => open, -- for internal SCTRL
+    LINK_ACTIVE_OUT(0)          => open, -- for internal SCTRL
+    TICK_MS_IN                  => tick_ms_int,
+    -- Debug                   
+    STATUS_OUT                  => status_raw(1 * 32 - 1 downto 0 * 32),
+    DEBUG_OUT                   => open
+  );
   
 ---------------------------------------------------------------------------
 -- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon)
@@ -697,19 +616,112 @@ begin
     TX_PCS_RST_IN               => tx_pcs_rst_i,
     RX_LINK_READY_OUT           => open,
     TX_LINK_READY_IN            => link_tx_ready_i,
-    PCS_AN_READY_OUT(0)         => open, -- for internal SCTRL
-    LINK_ACTIVE_OUT(0)          => open, -- for internal SCTRL
+    TICK_MS_IN                  => tick_ms_int,
     -- Debug                   
     STATUS_OUT                  => status_raw(2 * 32 - 1 downto 1 * 32),
     DEBUG_OUT                   => open
   );
 
+---------------------------------------------------------------------------
+-- PCSC is four ports downlink
+---------------------------------------------------------------------------
+  THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo
+  generic map(
+    LINKS_ACTIVE                => "1111"
+  )
+  port map(
+    RESET                       => reset_i,
+    RESET_N                     => reset_n_i,
+    CLEAR                       => clear_i,
+    CLEAR_N                     => clear_n_i,
+    CLK_125                     => clk_sys,
+    -- SerDes 0 -- DOWNLINK
+    -- FIFO interface RX           
+    FIFO_FULL_IN(0)             => ul_tx_fifofull,
+    FIFO_WR_OUT(0)              => dl_rx_data(6)(9),
+    FIFO_DATA_OUT(8 downto 0)   => dl_rx_data(6)(8 downto 0),
+    FRAME_START_OUT(0)          => dl_rx_data(6)(10),
+    FRAME_REQ_IN(0)             => dl_rx_frame_req(6),
+    FRAME_ACK_OUT(0)            => dl_rx_frame_ack(6),
+    FRAME_AVAIL_OUT(0)          => dl_rx_frame_avail(6),
+    -- FIFO interface TX           
+    FIFO_WR_IN(0)               => ul_rx_data(9),
+    FIFO_DATA_IN(8 downto 0)    => ul_rx_data(8 downto 0),
+    FRAME_START_IN(0)           => ul_rx_data(10),
+    FIFO_FULL_OUT(0)            => dl_tx_fifofull(6),
+    -- SerDes 1 - DOWNLINK         
+    -- FIFO interface RX           
+    FIFO_FULL_IN(1)             => ul_tx_fifofull,
+    FIFO_WR_OUT(1)              => dl_rx_data(7)(9),
+    FIFO_DATA_OUT(17 downto 9)  => dl_rx_data(7)(8 downto 0),
+    FRAME_START_OUT(1)          => dl_rx_data(7)(10),
+    FRAME_REQ_IN(1)             => dl_rx_frame_req(7),
+    FRAME_ACK_OUT(1)            => dl_rx_frame_ack(7),
+    FRAME_AVAIL_OUT(1)          => dl_rx_frame_avail(7),
+    -- FIFO interface TX           
+    FIFO_WR_IN(1)               => ul_rx_data(9),
+    FIFO_DATA_IN(17 downto 9)   => ul_rx_data(8 downto 0),
+    FRAME_START_IN(1)           => ul_rx_data(10),
+    FIFO_FULL_OUT(1)            => dl_tx_fifofull(7),
+    -- SerDes 2 -- DOWNLINK        
+    -- FIFO interface RX           
+    FIFO_FULL_IN(2)             => ul_tx_fifofull,
+    FIFO_WR_OUT(2)              => dl_rx_data(4)(9),
+    FIFO_DATA_OUT(26 downto 18) => dl_rx_data(4)(8 downto 0),
+    FRAME_START_OUT(2)          => dl_rx_data(4)(10),
+    FRAME_REQ_IN(2)             => dl_rx_frame_req(4),
+    FRAME_ACK_OUT(2)            => dl_rx_frame_ack(4),
+    FRAME_AVAIL_OUT(2)          => dl_rx_frame_avail(4),
+    -- FIFO interface TX           
+    FIFO_WR_IN(2)               => ul_rx_data(9),
+    FIFO_DATA_IN(26 downto 18)  => ul_rx_data(8 downto 0),
+    FRAME_START_IN(2)           => ul_rx_data(10),
+    FIFO_FULL_OUT(2)            => dl_tx_fifofull(4),
+    -- SerDes 3 -- DOWNLINK        
+    -- FIFO interface RX           
+    FIFO_FULL_IN(3)             => ul_tx_fifofull,
+    FIFO_WR_OUT(3)              => dl_rx_data(5)(9),
+    FIFO_DATA_OUT(35 downto 27) => dl_rx_data(5)(8 downto 0),
+    FRAME_START_OUT(3)          => dl_rx_data(5)(10),
+    FRAME_REQ_IN(3)             => dl_rx_frame_req(5),
+    FRAME_ACK_OUT(3)            => dl_rx_frame_ack(5),
+    FRAME_AVAIL_OUT(3)          => dl_rx_frame_avail(5),
+    -- FIFO interface TX           
+    FIFO_WR_IN(3)               => ul_rx_data(9),
+    FIFO_DATA_IN(35 downto 27)  => ul_rx_data(8 downto 0),
+    FRAME_START_IN(3)           => ul_rx_data(10),
+    FIFO_FULL_OUT(3)            => dl_tx_fifofull(5),
+    -- SFP Connection
+    SD_PRSNT_N_IN(0)            => HUB_MOD0(3),
+    SD_PRSNT_N_IN(1)            => HUB_MOD0(4),
+    SD_PRSNT_N_IN(2)            => HUB_MOD0(1),
+    SD_PRSNT_N_IN(3)            => HUB_MOD0(2),
+    SD_LOS_IN(0)                => HUB_LOS(3),
+    SD_LOS_IN(1)                => HUB_LOS(4),
+    SD_LOS_IN(2)                => HUB_LOS(1),
+    SD_LOS_IN(3)                => HUB_LOS(2),
+    SD_TXDIS_OUT(0)             => HUB_TXDIS(3),
+    SD_TXDIS_OUT(1)             => HUB_TXDIS(4),
+    SD_TXDIS_OUT(2)             => HUB_TXDIS(1),
+    SD_TXDIS_OUT(3)             => HUB_TXDIS(2),
+    -- SerDes control          
+    TX_PLOL_LOL_OUT             => tx_pll_lol_c_i,
+    TX_PCS_RST_IN               => tx_pcs_rst_i,
+    RX_LINK_READY_OUT           => open,
+    TX_LINK_READY_IN            => link_tx_ready_i,
+    TICK_MS_IN                  => tick_ms_int,
+    -- Debug                   
+    STATUS_OUT                  => status_raw(3 * 32 - 1 downto 2 * 32),
+    DEBUG_OUT                   => open
+  );
+
 ---------------------------------------------------------------------------
 -- PCSD is one uplink / one downlink
 ---------------------------------------------------------------------------
   THE_GBE_MED_RAW_PCSD: entity gbe_med_fifo
   generic map(
-    LINKS_ACTIVE                => "0011"
+    LINKS_ACTIVE                => "0011",
+    SNIFFER_PORT                => 0
   )
   port map(
     RESET                       => reset_i,
@@ -731,7 +743,7 @@ begin
     FIFO_DATA_IN(8 downto 0)    => ul_tx_data_q(8 downto 0),
     FRAME_START_IN(0)           => ul_tx_data_q(10),
     FIFO_FULL_OUT(0)            => ul_tx_fifofull,
-    -- SerDes 1 - DOWNLINK         
+    -- SerDes 1 - DOWNLINK
     -- FIFO interface RX           
     FIFO_FULL_IN(1)             => ul_tx_fifofull,
     FIFO_WR_OUT(1)              => dl_rx_data(1)(9),
@@ -754,73 +766,24 @@ begin
     SD_LOS_IN(1)                => SFP_LOS(1),
     SD_TXDIS_OUT(0)             => SFP_TX_DIS(0),
     SD_TXDIS_OUT(1)             => SFP_TX_DIS(1),
+    -- internal sniffer port
+    MAC_RX_DATA_OUT             => sniffer_data,
+    MAC_RX_WRITE_OUT            => sniffer_wr,
+    MAC_RX_EOF_OUT              => sniffer_eof,
+    MAC_RX_ERROR_OUT            => sniffer_error,
     -- SerDes control          
     TX_PLOL_LOL_OUT             => tx_pll_lol_d_i,
     TX_PCS_RST_IN               => tx_pcs_rst_i,
     RX_LINK_READY_OUT           => open,
     TX_LINK_READY_IN            => link_tx_ready_i,
     PCS_AN_READY_OUT(0)         => open, -- for internal SCTRL
-    LINK_ACTIVE_OUT(0)          => open, -- for internal SCTRL
+    LINK_ACTIVE_OUT(0)          => link_active, -- for internal SCTRL
+    TICK_MS_IN                  => tick_ms_int,
     -- Debug                   
     STATUS_OUT                  => status_raw(4 * 32 - 1 downto 3 * 32),
     DEBUG_OUT                   => open
   );
 
----------------------------------------------------------------------------
--- PCSA is one port downlink (backplane)
----------------------------------------------------------------------------
-  THE_GBE_MED_RAW_PCSA: entity gbe_med_fifo
-  generic map(
-    LINKS_ACTIVE                => "0001"
-  )
-  port map(
-    RESET                       => reset_i,
-    RESET_N                     => reset_n_i,
-    CLEAR                       => clear_i,
-    CLEAR_N                     => clear_n_i,
-    CLK_125                     => clk_sys,
-    -- SerDes 0 -- DOWNLINK
-    -- FIFO interface RX           
-    FIFO_FULL_IN(0)             => ul_tx_fifofull,
-    FIFO_WR_OUT(0)              => dl_rx_data(10)(9),
-    FIFO_DATA_OUT(8 downto 0)   => dl_rx_data(10)(8 downto 0),
-    FRAME_START_OUT(0)          => dl_rx_data(10)(10),
-    FRAME_REQ_IN(0)             => dl_rx_frame_req(10),
-    FRAME_ACK_OUT(0)            => dl_rx_frame_ack(10),
-    FRAME_AVAIL_OUT(0)          => dl_rx_frame_avail(10),
-    -- FIFO interface TX           
-    FIFO_WR_IN(0)               => ul_rx_data(9),
-    FIFO_DATA_IN(8 downto 0)    => ul_rx_data(8 downto 0),
-    FRAME_START_IN(0)           => ul_rx_data(10),
-    FIFO_FULL_OUT(0)            => dl_tx_fifofull(10),
-    -- SerDes 1 -- UNUSED
-    -- SerDes 2 -- UNUSED
-    -- SerDes 3 -- UNUSED
-    -- SFP Connection
-    SD_PRSNT_N_IN(0)            => HUB_MOD0(5),
-    SD_PRSNT_N_IN(1)            => '1',
-    SD_PRSNT_N_IN(2)            => '1',
-    SD_PRSNT_N_IN(3)            => '1',
-    SD_LOS_IN(0)                => HUB_LOS(5),
-    SD_LOS_IN(1)                => '1',
-    SD_LOS_IN(2)                => '1',
-    SD_LOS_IN(3)                => '1',
-    SD_TXDIS_OUT(0)             => HUB_TXDIS(5),
-    SD_TXDIS_OUT(1)             => open,
-    SD_TXDIS_OUT(2)             => open,
-    SD_TXDIS_OUT(3)             => open,
-    -- SerDes control          
-    TX_PLOL_LOL_OUT             => tx_pll_lol_a_i,
-    TX_PCS_RST_IN               => tx_pcs_rst_i,
-    RX_LINK_READY_OUT           => open,
-    TX_LINK_READY_IN            => link_tx_ready_i,
-    PCS_AN_READY_OUT(0)         => open, -- for internal SCTRL
-    LINK_ACTIVE_OUT(0)          => open, -- for internal SCTRL
-    -- Debug                   
-    STATUS_OUT                  => status_raw(1 * 32 - 1 downto 0 * 32),
-    DEBUG_OUT                   => open
-  );
-
 ---------------------------------------------------------------------------
 -- RSL for TX of SerDes, based on extRSL logic
 ---------------------------------------------------------------------------
@@ -838,4 +801,57 @@ begin
  
   tx_pll_lol_i <= tx_pll_lol_a_i or tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i;
 
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+  LED_GREEN            <= not status(0); --'0';
+  LED_ORANGE           <= not '0';
+  LED_RED              <= not '0';
+  LED_YELLOW           <= not '0';
+
+  LED_HUB_LINKOK(1)  <= not status_raw(10 * 8 + 6); --'0'; -- C2
+  LED_HUB_TX(1)      <= not status_raw(10 * 8 + 5); --'0';
+  LED_HUB_RX(1)      <= not '0';
+
+  LED_HUB_LINKOK(2)  <= not status_raw(11 * 8 + 6); --'0'; -- C3
+  LED_HUB_TX(2)      <= not status_raw(11 * 8 + 5); --'0';
+  LED_HUB_RX(2)      <= not '0';
+
+  LED_HUB_LINKOK(3)  <= not status_raw(8 * 8 + 6); --'0'; -- C0
+  LED_HUB_TX(3)      <= not status_raw(8 * 8 + 5); --'0';
+  LED_HUB_RX(3)      <= not '0';
+
+  LED_HUB_LINKOK(4)  <= not status_raw(9 * 8 + 6); --'0'; -- C1
+  LED_HUB_TX(4)      <= not status_raw(9 * 8 + 5); --'0';
+  LED_HUB_RX(4)      <= not '0';
+
+  LED_HUB_LINKOK(5)  <= not status_raw(4 * 8 + 6); --'0'; -- B0
+  LED_HUB_TX(5)      <= not status_raw(4 * 8 + 5); --'0';
+  LED_HUB_RX(5)      <= not '0';
+
+  LED_HUB_LINKOK(6)  <= not status_raw(5 * 8 + 6); --'0'; -- B1
+  LED_HUB_TX(6)      <= not status_raw(5 * 8 + 5); --'0';
+  LED_HUB_RX(6)      <= not '0';
+  
+  LED_HUB_LINKOK(7)  <= not status_raw(6 * 8 + 6); --'0'; -- B2
+  LED_HUB_TX(7)      <= not status_raw(6 * 8 + 5); --'0';
+  LED_HUB_RX(7)      <= not '0';
+
+  LED_HUB_LINKOK(8)  <= not status_raw(7 * 8 + 6); --'0'; -- B3
+  LED_HUB_TX(8)      <= not status_raw(7 * 8 + 5); --'0';
+  LED_HUB_RX(8)      <= not '0';
+
+  LED_SFP_GREEN(0)   <= not status_raw(12 * 8 + 6); --'0'; -- D0
+  LED_SFP_RED(0)     <= not status_raw(12 * 8 + 5); --'0';
+
+  LED_SFP_GREEN(1)   <= not status_raw(13 * 8 + 6); --'0'; -- D1
+  LED_SFP_RED(1)     <= not status_raw(13 * 8 + 5); --'0';
+  
+  LED_WHITE(1)       <= not additional_reg(31); --'0';
+  LED_WHITE(0)       <= not status(0); --'0';
+
+  LED_RJ_GREEN(0)    <= not status_raw(0 * 8 + 6); -- A0
+  LED_RJ_RED(0)      <= not status_raw(0 * 8 + 5);
+
 end architecture;