adding IncludedFeatures tables to projects

diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
index 6d5f5f344def125416691ee97cf94ad635ed4513..38ea0fe3e08b05fee2e35c556604dad5c023dd48 100644 (file)
--- a/backplanemaster/config.vhd
+++ b/backplanemaster/config.vhd
@@ -19,7 +19,7 @@ package config is
     constant USE_RXCLOCK            : integer := c_NO;
    
 --Address settings   
-    constant INIT_ADDRESS           : std_logic_vector := x"F3CD";
+    constant INIT_ADDRESS           : std_logic_vector := x"F3CE";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60";
    
 
@@ -27,6 +27,9 @@ package config is
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
 
+    constant INCLUDE_GBE            : integer  := c_YES;
+    
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -51,16 +54,16 @@ package config is
 
 
 --With GbE:
--- for MII_NUMBER=5 (4 downlinks, 1 uplink):
--- port 0,1,2,3: downlinks to other FPGA
--- port 4: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL
--- port 5: SCTRL channel on uplink to CTS
--- port 6: SCTRL channel from GbE interface
+-- for MII_NUMBER=10
+-- port 0-8: downlinks to other FPGA
+-- port 9: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL
+-- port 10: SCTRL channel on uplink to CTS
+-- port 11: SCTRL channel from GbE interface
 
- constant INTERFACE_NUM       : integer := 5;
- constant MII_IS_UPLINK       : hub_mii_config_t := (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0);
- constant MII_IS_DOWNLINK     : hub_mii_config_t := (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0);
- constant MII_IS_UPLINK_ONLY  : hub_mii_config_t := (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0);
+ constant INTERFACE_NUM       : integer := 10;
+ constant MII_IS_UPLINK       : hub_mii_config_t := (0,0,0,0,0,0,0,0,0, 1,1,1,0,0,0,0,0);--0,0,0,0,0,
+ constant MII_IS_DOWNLINK     : hub_mii_config_t := (1,1,1,1,1,1,1,1,1, 1,0,0,0,0,0,0,0);--1,1,1,1,1,
+ constant MII_IS_UPLINK_ONLY  : hub_mii_config_t := (0,0,0,0,0,0,0,0,0, 0,1,1,0,0,0,0,0);--0,0,0,0,0,
 
 ------------------------------------------------------------------------------
 --Select settings by configuration 
@@ -89,27 +92,25 @@ package body config is
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
 
-  
-  
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+    t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+    t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+    t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+    t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+    t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;  
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
 

diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd
index e72fe379930503e099a4932235ed3c7ee17eea77..5819d13d9b18dca846bcac214178d11c4eae5968 100644 (file)
--- a/hubaddon/config.vhd
+++ b/hubaddon/config.vhd
@@ -87,26 +87,25 @@ package body config is
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
 
   
-  
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+--     t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+--     t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+--     t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+--     t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+--     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+--     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;  
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
 

diff --git a/padiwa/config.vhd b/padiwa/config.vhd
index f6c9a18c5ff8ff3a2de56fa425087057b16dd5a7..36735cef93c7fb143f3f0cc6e583ab1af77a6c70 100644 (file)
--- a/padiwa/config.vhd
+++ b/padiwa/config.vhd
@@ -40,7 +40,8 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
-   
+    constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;   
+    constant INCLUDE_STATISTICS     : integer  := c_YES;      
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -91,23 +92,26 @@ package body config is
   
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+    t(7 downto 0)   := std_logic_vector(to_unsigned(1,8));
+    t(11 downto 8)  := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+    t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+    t(15)           := '1'; --TDC
+    t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+    
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+    t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;   
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
 

diff --git a/pulser/config.vhd b/pulser/config.vhd
index 5719dad584072503bd878dfd041add3c0fa5837f..6881b7149d129b66675845b5b51945c4fe877869 100644 (file)
--- a/pulser/config.vhd
+++ b/pulser/config.vhd
@@ -76,23 +76,23 @@ package body config is
   
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+--     t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+--     t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+--     t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+--     t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+--     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+--     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;  
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
 

diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd
index 6679bdf4e8fe6ac80aaf2496993060984650e4ec..224296b3ac3e97520775abcbdb841ca3b7e441ce 100644 (file)
--- a/tdctemplate/config.vhd
+++ b/tdctemplate/config.vhd
@@ -41,6 +41,9 @@ package config is
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
    
+    constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;   
+    constant INCLUDE_STATISTICS     : integer  := c_YES;   
+   
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -91,23 +94,26 @@ package body config is
   
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+    t(7 downto 0)   := std_logic_vector(to_unsigned(1,8));
+    t(11 downto 8)  := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+    t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+    t(15)           := '1'; --TDC
+    t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+    
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+    t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;   
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
 

diff --git a/template/config.vhd b/template/config.vhd
index abe29a010ad33fa16b083a93261e0c060c8aee49..b3d9f928870745431851ad212d88108c4ab56794 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -73,28 +73,21 @@ package body config is
                                       HW_INFO_BASE );
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
-
-  
   
 function generateIncludedFeatures return std_logic_vector is
   variable t : std_logic_vector(63 downto 0);
-begin
-  t               := (others => '0');
-  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
-  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
-  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
-  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
-  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
-  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
-  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
-  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
-  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
-  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
-  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
-  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
-  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
-  return t;
-end function;  
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+
+    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+    t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+    t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;  
 
   constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;