Revert "started to work on padiwa configuration Flash"

This reverts commit 4e1038284dfb58e8fae40ec53cb215c16d601e3e.

diff --git a/wasa/cores/UFM_WB.v b/wasa/cores/UFM_WB.v
index 28fa5481dd7dc25cfb6f614b3665cb917421b775..a85c386a6406ddbf779b8ed1f4aedd8f6ec6e252 100644 (file)
--- a/wasa/cores/UFM_WB.v
+++ b/wasa/cores/UFM_WB.v
@@ -44,8 +44,8 @@
 
 `timescale 1ns / 100ps
 `include "efb_define_def.v"
-//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v"
-//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v"
+`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v"
+`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v"
 
 module UFM_WB(
                                  input clk_i

diff --git a/wasa/panda_dirc_wasa.p2t b/wasa/panda_dirc_wasa.p2t
index a6bbb27682ad2648b76031d0729fc9d385970d26..0e70172113854799fb6e2bf40de993a0f5cbd80e 100644 (file)
--- a/wasa/panda_dirc_wasa.p2t
+++ b/wasa/panda_dirc_wasa.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 12
+-t 11
 -c 1
 -e 2
 -m nodelist.txt

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index 40cf547d75b46269a0623a047610ecb44bef5e36..a1a94f0cd3c7387a768f4c77e19629ca8e6c254a 100644 (file)
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -14,7 +14,7 @@ use machxo2.all;
 \r
 entity panda_dirc_wasa is\r
   generic(\r
-    PADIWA_FLAVOUR : integer := 1\r
+    PADIWA_FLAVOUR : integer := 2\r
     );\r
   port(\r
     CON        : out std_logic_vector(16 downto 1);\r
@@ -163,7 +163,7 @@ signal idram : idram_t;
 type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);\r
 signal ram   : ram_t;\r
 \r
-signal pwm_i : std_logic_vector(32 downto 1);\r
+signal pwm_i : std_logic_vector(31 downto 0);\r
 signal INP_i     : std_logic_vector(15 downto 0);\r
 signal spi_reg00_i : std_logic_vector(15 downto 0);\r
 signal spi_reg10_i : std_logic_vector(15 downto 0);\r
@@ -261,29 +261,22 @@ clk_source: OSCH
 ---------------------------------------------------------------------------\r
 -- Input re-ordering\r
 ---------------------------------------------------------------------------\r
-\r
-gen_outputs_1 : if PADIWA_FLAVOUR = 1 generate\r
-  INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & \r
-           INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9)  & INP(1);\r
-  PWM   <= pwm_i(16) & pwm_i(8) & pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & \r
-           pwm_i(12) & pwm_i(4) & pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9)  & pwm_i(1);\r
-end generate;\r
-\r
-\r
-gen_outputs_2 : if PADIWA_FLAVOUR = 2 generate\r
+gen_outputs_1 : if PADIWA_FLAVOUR = 2 generate\r
   INP_i <= INP;\r
-  PWM <= pwm_i(16 downto 1);\r
+  PWM <= pwm_i(15 downto 0);\r
 end generate;\r
 \r
 \r
-gen_outputs_3 : if PADIWA_FLAVOUR = 3 generate\r
-  INP_i <= INP(9)  & INP(1) & INP(10) & INP(2) & INP(11) & INP(3) & INP(12) & INP(4) & \r
-           INP(13) & INP(5) & INP(14) & INP(6) & INP(15) & INP(7) & INP(16) & INP(8);\r
-  PWM   <= pwm_i(16) & pwm_i(8) & pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & \r
-           pwm_i(12) & pwm_i(4) & pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9)  & pwm_i(1);\r
+gen_outputs_2 : if PADIWA_FLAVOUR = 1 generate\r
+  INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & \r
+           INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9)  & INP(1);\r
+  PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & \r
+         pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9)  & pwm_i(1) & pwm_i(8)  & pwm_i(0);\r
 end generate;\r
 \r
-   \r
+  \r
+  \r
+  \r
 ---------------------------------------------------------------------------\r
 -- SPI Interface\r
 ---------------------------------------------------------------------------  \r