*** empty log message ***

diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t
index 3838d811216aae4a52b87bd1e14709b294e4a965..15b316a853d63beaa0c3f350b9e030b5c59941e2 100644 (file)
--- a/cts/trb3_central.p2t
+++ b/cts/trb3_central.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 10
+-t 2
 -c 1
 -e 2
 #-g guidefile.ncd

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 522ec7784259813710db35225b64d7124eb3d42e..6c751cfb509503eb06bed91cf0de7c82b78a49d9 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -89,8 +89,8 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vh
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
@@ -223,13 +223,13 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
 
-add_file -vhdl -lib work "../cts2/cts_pkg.vhd"
-add_file -vhdl -lib work "../cts2/cts_fifo.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_input.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_coin.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_pseudorand_pulser.vhd"
-add_file -vhdl -lib work "../cts2/cts_trigger.vhd"
-add_file -vhdl -lib work "../cts2/cts.vhd"
+add_file -vhdl -lib work "source/cts_pkg.vhd"
+add_file -vhdl -lib work "source/cts_fifo.vhd"
+add_file -vhdl -lib work "source/cts_trg_input.vhd"
+add_file -vhdl -lib work "source/cts_trg_coin.vhd"
+add_file -vhdl -lib work "source/cts_trg_pseudorand_pulser.vhd"
+add_file -vhdl -lib work "source/cts_trigger.vhd"
+add_file -vhdl -lib work "source/cts.vhd"
 
 add_file -vhdl -lib work "./trb3_central.vhd"
 

diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf
index ddf8486f5076ff44ae6ba22066a09089e6ce475c..7276d94e69182c692aa20cebfcf6186bc7bfcd4e 100644 (file)
--- a/cts/trb3_central_constraints.lpf
+++ b/cts/trb3_central_constraints.lpf
@@ -143,11 +143,11 @@ UGROUP "gbe_rx_tx"
 \r
        \r
 REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
-REGION "MED0" "R75C2D" 30 35 DEVSIZE;\r
+REGION "MED0" "R75C2D" 30 45 DEVSIZE;\r
 LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
 FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
 FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ;\r
-REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;\r
+REGION "GBE_MAIN_REGION" "R74C50C" 38 36 DEVSIZE;\r
 LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
 LOCATE UGROUP "tsmac" REGION "MED0" ;\r
 BLOCK JTAGPATHS ;\r