update included features

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index 4ee63b3cfebc4f1203a92712a8d2c8acb12cc2cf..570b011588a8cc5c38c0f958f18e1b508fea19c2 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -6,12 +6,8 @@
 \hline\hline
 1 & \multicolumn{3}{X|}{``Central'' - For a normal central FPGA design with Cts and/or GbE}\\
  & 3 -- 0   & ExtModule   & Type of external trigger module (0: none, 1: CBM MBS, 2: Mainz M2)\\ 
- & 4        & CtsTdc      & TDC channels included. Usually connected to the first trigger inputs of the CTS. 
-If a trigger module is present, the first channel will connect to its async output signal \\
- & 5        & CtsTdcX     & The connection of TDC channels is non-standard. Refer to documentation. \\
  & 11 -- 8  & DoubleEdge  & See table 2.\\
- & 15       & CTS         & The design contains a CTS module. A complete list of components can be obtained from the 
-CTS registers. \\
+ & 15       & TDC         & The design contains a TDC module. \\
  & 16       & GbeData     & Event data is sent via GbE \\
  & 17       & GbeCtrl     & FPGA accepts slow-control messages via GbE \\
  & 19 -- 18 & GbeDataBuf  & Size of the buffer for event data. 1: 64 kB \\
@@ -23,12 +19,11 @@ CTS registers. \\
  & 41       & ReferenceTime & Reference Time Path 0: RJ-45 (default) 1: 
 Through Clock Manager (cbmtof only)\\
  & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
- & 43       & Uart        & Uart on RJ45\_CLOCK(4) (TTL)\\
- & 47 -- 44 & InpMonitor  & Monitoring of input signals. See register 0xcf8f for number of channels and number of fifos 
-\\
+ & 43       & Uart        & Uart on RJ45\_CLOCK(4) (TTL) o HDR\_IO\\
+ & 44       & InpMonitor  & Monitoring of input signals.\\
  & 51 -- 48 & TrgModule   & Type of trigger module 0: none, 1: simple or, 2: edge detect \\
- & 55 -- 52 & Clock       & Main clock source: 0: onboard 200 MHz, 1: onboard 125 MHz, 2: 200 MHz RX clock on SFP1, 3: 
-125 MHz RX clock on SFP1, 4: external clock input 200 MHz, 5: external clock input 125 MHz\\
+ & 55 -- 52 & Clock       & TRB3 - Main clock source: 0: onboard 200 MHz, 1: onboard 125 MHz, 2: 200 MHz RX clock on SFP1, 3: 125 MHz RX clock on SFP1, 4: external clock input 200 MHz, 5: external clock input 125 MHz\newline
+ TRB3sc - 52: 120 MHz instead of 100 MHz, 53: use RX clock, 54: external clock, 55: has 200 Mhz oscillator\\
 \hline\hline
 2 & \multicolumn{3}{X|}{``TDC'' - For TDC designs. Detailed information about the TDC setup can be found in register 
 0xc8xx}\\

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 0fc76de1d524e93dafc387e31b70e0d48e795073..c22723f5df21d278c812f5f5daf2743e4df51eb9 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -201,6 +201,7 @@ All boards of a given type are accessible by a broadcast address at the same tim
  \item 0x52 DiRich Combiner
  \item 0x60 Trb3sc
  \item 0x61 Trb3sc Hub
+ \item 0x70 ECal TDC
 \end{itemize*}
 
 The initial address set with \signal{Regio\_Init\_Address} can be chosen from the following set: