first three enyties work

diff --git a/trigger_edgedetect.vhd b/trigger_edgedetect.vhd
new file mode 100644 (file)
index 0000000..4bc28c6
--- /dev/null
+++ b/trigger_edgedetect.vhd
@@ -0,0 +1,95 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+
+  entity trg_edgedetect is
+  port(
+  clk_in      : in std_logic;
+  signals     : in std_logic_vector(31 downto 0);
+--   reg_inhalt  : in std_logic_vector(31 downto 0);
+  processed_signals   : out std_logic_vector(31 downto 0) 
+  );
+end trg_edgedetect;
+  
+  
+  
+  
+architecture behave of trg_edgedetect is 
+
+signal temp_save : std_logic_vector(31 downto 0);
+signal testing   : std_logic_vector(31 downto 0):=x"00001111";
+
+
+begin
+
+detect_step1: process is
+begin 
+  wait until rising_edge(clk_in);
+  for i in 0 to 31 loop
+    temp_save(i)<=signals(i);
+  end loop;
+
+end process;
+
+detect_step2: process is
+begin 
+  wait until falling_edge(clk_in);
+  for i in 0 to 31 loop
+    if signals(i)='1' and temp_save(i)='0' then
+      processed_signals(i)<='1';
+    else
+      processed_signals(i)<='0';
+    end if;
+  end loop;
+
+end process;
+
+-- detect_step3: process is
+-- begin
+--   wait until falling_edge(clk_in);
+--   for i in 0 to 31 loop
+--     if signals(i)='1' then
+--       if temp_save(i)='0' then
+--         processed_signals(i)<='1';
+--       else processed_signals(i)<='0';
+--       end if;
+--       else processed_signals(i)<='0';
+--     end if;
+--   end loop;
+-- end process;
+
+-- processed_signals<=testing;
+end behave;
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diff --git a/trigger_enable.vhd b/trigger_enable.vhd
new file mode 100644 (file)
index 0000000..f64603f
--- /dev/null
+++ b/trigger_enable.vhd
@@ -0,0 +1,40 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+
+  
+
+  
+entity trg_enable is
+  port(
+  clk_in      : in std_logic;
+  signals     : in std_logic_vector(31 downto 0);
+  reg_inhalt  : in std_logic_vector(31 downto 0);
+  processed_signals   : out std_logic_vector(31 downto 0)
+  );
+end trg_enable;
+  
+architecture behave of trg_enable is 
+
+
+
+begin
+
+enable: process is
+begin
+  wait until rising_edge(clk_in);
+  for i in 0 to 31 loop
+    if reg_inhalt(i) = '0' then
+      processed_signals(i) <= '0';
+    else 
+      processed_signals(i) <= signals(i);
+    end if;
+  end loop;  
+end process;
+
+
+
+end behave;

diff --git a/trigger_inverter.vhd b/trigger_inverter.vhd
new file mode 100644 (file)
index 0000000..74eabcb
--- /dev/null
+++ b/trigger_inverter.vhd
@@ -0,0 +1,37 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+  
+  
+  
+
+entity trg_inverter is
+  port(
+  clk_in      : in std_logic;
+  signals     : in std_logic_vector(31 downto 0);
+  reg_inhalt  : in std_logic_vector(31 downto 0);
+  processed_signals   : out std_logic_vector(31 downto 0)
+  );
+end trg_inverter;
+
+architecture behave of trg_inverter is 
+  
+  
+begin
+
+invert: process is 
+  begin
+  wait until rising_edge(clk_in);
+  for i in 0 to 31 loop
+    if reg_inhalt(i) = '1' then
+      processed_signals(i) <= not signals(i);
+    else 
+      processed_signals(i) <= signals(i);
+    end if;
+  end loop;  
+  end process;
+
+end behave;