fixed small timing bug, IF

diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj
index d7e790cfbf7448f6c47805fd426104456505f611..745b9d9d5441fba697d50d11dbdaefcf4f4ed8d9 100644 (file)
--- a/amps2/padiwa_amps2.prj
+++ b/amps2/padiwa_amps2.prj
@@ -17,6 +17,10 @@ add_file -vhdl -lib work "../source/pwm.vhd"
 add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
 add_file -vhdl -lib work "padiwa_amps2.vhd"
 
+add_file -vhdl -lib work "../source/timer.vhd"
+add_file -vhdl -lib work "../source/Amps2_Interface.vhd"
+add_file -vhdl -lib work "../source/i2c_master.vhd"
+add_file -vhdl -lib work "../source/Amps2_TempSensor_UID.vhd"
 
 
 #add_file -vhdl -lib work "../cores/flashram.vhd"

diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd
index d0dc11152824cad6b9793d8d75bb413835c5b900..bcfe44f3ddcf6a98a520b3fa80ec927ae0522d5f 100644 (file)
--- a/amps2/padiwa_amps2.vhd
+++ b/amps2/padiwa_amps2.vhd
@@ -80,6 +80,7 @@ architecture arch of padiwa_amps2 is
   signal bus_read    : std_logic := '0';\r
   signal bus_write   : std_logic := '0';\r
   signal bus_ready   : std_logic;\r
+  signal delayed_bus_ready : std_logic_vector(1 downto 0) := "00";\r
   signal bus_busy    : std_logic;\r
 \r
   signal spi_data_out  : std_logic_vector(15 downto 0);\r
@@ -132,7 +133,8 @@ architecture arch of padiwa_amps2 is
   signal delayed_inputs   : std_logic_vector(127 downto 0);\r
   signal selected_delay   : std_logic_vector(8 downto 1);\r
   signal delayselect      : integer range 0 to 15;\r
- \r
+\r
+  \r
   component OSCH\r
     generic (NOM_FREQ: string := "133.00");\r
     port (\r
@@ -157,12 +159,12 @@ clk_source: OSCH
   );\r
   \r
 THE_PLL : entity work.pll_in133_out33_133_266 \r
-    port map (\r
-        CLKI => clk_osc,\r
-        CLKOP => clk_i, --133\r
-        CLKOS => clk_33, --33 \r
-        CLKOS2=> clk_266 --266\r
-        );\r
+  port map (\r
+    CLKI => clk_osc,\r
+    CLKOP => clk_i, --133\r
+    CLKOS => clk_33, --33 \r
+    CLKOS2=> clk_266 --266\r
+  );\r
 \r
 \r
 ---------------------------------------------------------------------------\r
@@ -210,7 +212,7 @@ THE_PLL : entity work.pll_in133_out33_133_266
 \r
 THE_SPI : entity work.spi_slave\r
   port map(\r
-    CLK       => clk_i,\r
+    CLK       => clk_33,\r
     SPI_CLK   => SPI_CLK,\r
     SPI_CS    => SPI_CS,\r
     SPI_IN    => SPI_IN,\r
@@ -232,7 +234,7 @@ THE_SPI : entity work.spi_slave
 \r
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
   port map(\r
-    CLK => clk_i,\r
+    CLK => clk_33,\r
     RESET => '0',\r
 \r
     SPI_DATA_IN   => spi_data_out,\r
@@ -258,6 +260,13 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
 -- Temperature and UID reader\r
 ---------------------------------------------------------------------------  \r
 \r
+TEMP_SENSOR_AND_UID: entity temp_sensor_and_UID\r
+  port map(\r
+    clk => clk_i,\r
+    temperature => temperature_i,\r
+    sda => I2C_SCL,\r
+    scl => I2C_SCL\r
+  );\r
 \r
 \r
 ---------------------------------------------------------------------------\r
@@ -281,31 +290,52 @@ end generate;
 ---------------------------------------------------------------------------  \r
 \r
 THE_IO_REG : process begin\r
-  wait until rising_edge(clk_i);\r
+  wait until rising_edge(clk_33);\r
   bus_ready     <= '0';\r
   pwm_write_i   <= '0';    \r
-\r
+  spi_tx_data   <= x"0000";\r
+  \r
+  if delayed_bus_ready = "01" then\r
+    --bus_ready <= '1';\r
+    spi_tx_data <= pwm_data_o;\r
+    delayed_bus_ready <= "10";\r
+  elsif delayed_bus_ready = "10" then\r
+    bus_ready <= '1';\r
+    spi_tx_data <= pwm_data_o;\r
+    delayed_bus_ready <= "00";\r
+  else\r
+    delayed_bus_ready <= "00";\r
+  end if;\r
+      \r
   if bus_read = '1' then\r
     bus_ready <= '1';\r
-    case spi_addr is\r
-      when x"20" => spi_tx_data <= input_enable;\r
-      when x"21" => spi_tx_data <= inp_status;\r
-      when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ;\r
-      when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
-      when x"24" => spi_tx_data <= inp_invert;\r
-      when x"25" => spi_tx_data <= inp_stretch;\r
-      when x"26" => spi_tx_data <= comp_setting;\r
-      when x"27" => spi_tx_data <= x"00" & discharge_disable;\r
-      when x"28" => spi_tx_data <= x"00" & discharge_override;\r
-      when x"29" => spi_tx_data <= x"00" & discharge_highz;\r
-      when x"2a" => spi_tx_data <= x"00" & delay_invert;\r
-      when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8));\r
-\r
-      when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
-      when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
-      when x"32" => spi_tx_data <= x"0000";\r
-      when others => null;\r
-    end case;\r
+    if (spi_addr >= x"00") and (spi_addr < x"10") and delayed_bus_ready = "00"then\r
+      bus_ready <= '0';\r
+      delayed_bus_ready <= "01";\r
+      spi_tx_data <= pwm_data_o;\r
+      pwm_addr_i  <= spi_addr(3 downto 0);\r
+    else\r
+      case spi_addr is\r
+        when x"14" => spi_tx_data <= "0000" & temperature_i;\r
+        when x"20" => spi_tx_data <= input_enable;\r
+        when x"21" => spi_tx_data <= inp_status;\r
+        when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ;\r
+        when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
+        when x"24" => spi_tx_data <= inp_invert;\r
+        when x"25" => spi_tx_data <= inp_stretch;\r
+        when x"26" => spi_tx_data <= comp_setting;\r
+        when x"27" => spi_tx_data <= x"00" & discharge_disable;\r
+        when x"28" => spi_tx_data <= x"00" & discharge_override;\r
+        when x"29" => spi_tx_data <= x"00" & discharge_highz;\r
+        when x"2a" => spi_tx_data <= x"00" & delay_invert;\r
+        when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8));\r
+\r
+        when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
+        when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+        when x"32" => spi_tx_data <= x"0000";\r
+        when others => null;\r
+      end case;\r
+    end if;\r
   elsif bus_write = '1' then\r
     if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM\r
       pwm_data_i  <= spi_rx_data;\r