-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.math_real.all;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
- component buf_tester is --trb_net16_gbe_buf is\r
- generic( \r
- DO_SIMULATION : integer range 0 to 1 := 1;\r
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
- );\r
- port(\r
- CLK : in std_logic;\r
- TEST_CLK : in std_logic; -- only for simulation!\r
- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
- RESET : IN std_logic;\r
- GSR_N : IN std_logic;\r
- STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);\r
- ------------------------\r
- IP_CFG_START_IN : IN std_logic;\r
- IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);\r
- IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);\r
- MR_RESET_IN : IN std_logic;\r
- MR_MODE_IN : IN std_logic;\r
- MR_RESTART_IN : IN std_logic;\r
- IP_CFG_MEM_CLK_OUT : OUT std_logic;\r
- IP_CFG_DONE_OUT : OUT std_logic;\r
- IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);\r
- -- gk 29.03.10\r
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- gk 26.04.10\r
- -- registers setup interface\r
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
- -- gk 23.04.10\r
- LED_PACKET_SENT_OUT : out std_logic;\r
- LED_AN_DONE_N_OUT : out std_logic;\r
- ------------------------\r
- CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
- CTS_CODE_IN : IN std_logic_vector(7 downto 0);\r
- CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
- CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);\r
- CTS_START_READOUT_IN : IN std_logic;\r
- CTS_READ_IN : IN std_logic;\r
- FEE_DATA_IN : IN std_logic_vector(15 downto 0);\r
- FEE_DATAREADY_IN : IN std_logic;\r
- FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);\r
- FEE_BUSY_IN : IN std_logic;\r
- SFP_RXD_P_IN : IN std_logic;\r
- SFP_RXD_N_IN : IN std_logic;\r
- SFP_REFCLK_P_IN : IN std_logic;\r
- SFP_REFCLK_N_IN : IN std_logic;\r
- SFP_PRSNT_N_IN : IN std_logic;\r
- SFP_LOS_IN : IN std_logic; \r
- STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
- CTS_DATAREADY_OUT : OUT std_logic;\r
- CTS_READOUT_FINISHED_OUT : OUT std_logic;\r
- CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
- CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
- FEE_READ_OUT : OUT std_logic;\r
- SFP_TXD_P_OUT : OUT std_logic;\r
- SFP_TXD_N_OUT : OUT std_logic;\r
- SFP_TXDIS_OUT : OUT std_logic;\r
- IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0);\r
- IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0);\r
- IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);\r
- IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);\r
- IG_DATA_TST : OUT std_logic_vector(15 downto 0);\r
- IG_WCNT_TST : OUT std_logic_vector(15 downto 0);\r
- IG_RCNT_TST : OUT std_logic_vector(16 downto 0);\r
- IG_RD_EN_TST : OUT std_logic;\r
- IG_WR_EN_TST : OUT std_logic;\r
- IG_EMPTY_TST : OUT std_logic;\r
- IG_AEMPTY_TST : OUT std_logic;\r
- IG_FULL_TST : OUT std_logic;\r
- IG_AFULL_TST : OUT std_logic;\r
- PC_WR_EN_TST : OUT std_logic;\r
- PC_DATA_TST : OUT std_logic_vector(7 downto 0);\r
- PC_READY_TST : OUT std_logic;\r
- PC_START_OF_SUB_TST : OUT std_logic;\r
- PC_END_OF_DATA_TST : OUT std_logic;\r
- PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0);\r
- PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0);\r
- PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0);\r
- PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0);\r
- PC_PADDING_TST : OUT std_logic;\r
- PC_DECODING_TST : OUT std_logic_vector(31 downto 0);\r
- PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0);\r
- PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0);\r
- PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0);\r
- PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);\r
- PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);\r
- PC_SHF_EMPTY_TST : OUT std_logic;\r
- PC_SHF_FULL_TST : OUT std_logic;\r
- PC_SHF_WR_EN_TST : OUT std_logic;\r
- PC_SHF_RD_EN_TST : OUT std_logic;\r
- PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0);\r
- PC_DF_EMPTY_TST : OUT std_logic;\r
- PC_DF_FULL_TST : OUT std_logic;\r
- PC_DF_WR_EN_TST : OUT std_logic;\r
- PC_DF_RD_EN_TST : OUT std_logic;\r
- PC_DF_Q_TST : OUT std_logic_vector(7 downto 0);\r
- PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0);\r
- PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0);\r
- PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0);\r
- PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0);\r
- PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0);\r
- PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);\r
- PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);\r
- FC_WR_EN_TST : OUT std_logic;\r
- FC_DATA_TST : OUT std_logic_vector(7 downto 0);\r
- FC_H_READY_TST : OUT std_logic;\r
- FC_READY_TST : OUT std_logic;\r
- FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0);\r
- FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0);\r
- FC_IDENT_TST : OUT std_logic_vector(15 downto 0);\r
- FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0);\r
- FC_SOD_TST : OUT std_logic;\r
- FC_EOD_TST : OUT std_logic;\r
- FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0);\r
- FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);\r
- FT_DATA_TST : OUT std_logic_vector(8 downto 0);\r
- FT_TX_EMPTY_TST : OUT std_logic;\r
- FT_START_OF_PACKET_TST : OUT std_logic;\r
- FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0);\r
- FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0);\r
- FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);\r
- MAC_HADDR_TST : OUT std_logic_vector(7 downto 0);\r
- MAC_HDATA_TST : OUT std_logic_vector(7 downto 0);\r
- MAC_HCS_TST : OUT std_logic;\r
- MAC_HWRITE_TST : OUT std_logic;\r
- MAC_HREAD_TST : OUT std_logic;\r
- MAC_HREADY_TST : OUT std_logic;\r
- MAC_HDATA_EN_TST : OUT std_logic;\r
- MAC_FIFOAVAIL_TST : OUT std_logic;\r
- MAC_FIFOEOF_TST : OUT std_logic;\r
- MAC_FIFOEMPTY_TST : OUT std_logic;\r
- MAC_TX_READ_TST : OUT std_logic;\r
- MAC_TX_DONE_TST : OUT std_logic;\r
- PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0);\r
- PCS_AN_COMPLETE_TST : OUT std_logic;\r
- PCS_AN_PAGE_RX_TST : OUT std_logic;\r
- ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL CLK : std_logic;\r
- SIGNAL TEST_CLK : std_logic;\r
- SIGNAL RESET : std_logic;\r
- SIGNAL GSR_N : std_logic;\r
- SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL IP_CFG_START_IN : std_logic;\r
- SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0);\r
- SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0);\r
- SIGNAL MR_RESET_IN : std_logic;\r
- SIGNAL MR_MODE_IN : std_logic;\r
- SIGNAL MR_RESTART_IN : std_logic;\r
- SIGNAL IP_CFG_MEM_CLK_OUT : std_logic;\r
- SIGNAL IP_CFG_DONE_OUT : std_logic;\r
- SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);\r
- SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);\r
- SIGNAL CTS_START_READOUT_IN : std_logic;\r
- SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL CTS_DATAREADY_OUT : std_logic;\r
- SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;\r
- SIGNAL CTS_READ_IN : std_logic;\r
- SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);\r
- SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);\r
- SIGNAL FEE_DATAREADY_IN : std_logic;\r
- SIGNAL FEE_READ_OUT : std_logic;\r
- SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);\r
- SIGNAL FEE_BUSY_IN : std_logic;\r
- SIGNAL SFP_RXD_P_IN : std_logic;\r
- SIGNAL SFP_RXD_N_IN : std_logic;\r
- SIGNAL SFP_TXD_P_OUT : std_logic;\r
- SIGNAL SFP_TXD_N_OUT : std_logic;\r
- SIGNAL SFP_REFCLK_P_IN : std_logic;\r
- SIGNAL SFP_REFCLK_N_IN : std_logic;\r
- SIGNAL SFP_PRSNT_N_IN : std_logic;\r
- SIGNAL SFP_LOS_IN : std_logic;\r
- SIGNAL SFP_TXDIS_OUT : std_logic;\r
- SIGNAL IG_CTS_CTR_TST : std_logic_vector(2 downto 0);\r
- SIGNAL IG_REM_CTR_TST : std_logic_vector(3 downto 0);\r
- SIGNAL IG_BSM_LOAD_TST : std_logic_vector(3 downto 0);\r
- SIGNAL IG_BSM_SAVE_TST : std_logic_vector(3 downto 0);\r
- SIGNAL IG_DATA_TST : std_logic_vector(15 downto 0);\r
- SIGNAL IG_WCNT_TST : std_logic_vector(15 downto 0);\r
- SIGNAL IG_RCNT_TST : std_logic_vector(16 downto 0);\r
- SIGNAL IG_RD_EN_TST : std_logic;\r
- SIGNAL IG_WR_EN_TST : std_logic;\r
- SIGNAL IG_EMPTY_TST : std_logic;\r
- SIGNAL IG_AEMPTY_TST : std_logic;\r
- SIGNAL IG_FULL_TST : std_logic;\r
- SIGNAL IG_AFULL_TST : std_logic;\r
- SIGNAL PC_WR_EN_TST : std_logic;\r
- SIGNAL PC_DATA_TST : std_logic_vector(7 downto 0);\r
- SIGNAL PC_READY_TST : std_logic;\r
- SIGNAL PC_START_OF_SUB_TST : std_logic;\r
- SIGNAL PC_END_OF_DATA_TST : std_logic;\r
- SIGNAL PC_SUB_SIZE_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_TRIG_NR_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_PADDING_TST : std_logic;\r
- SIGNAL PC_DECODING_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_EVENT_ID_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_QUEUE_DEC_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_BSM_CONSTR_TST : std_logic_vector(3 downto 0);\r
- SIGNAL PC_BSM_LOAD_TST : std_logic_vector(3 downto 0);\r
- SIGNAL PC_BSM_SAVE_TST : std_logic_vector(3 downto 0);\r
- SIGNAL PC_SHF_EMPTY_TST : std_logic;\r
- SIGNAL PC_SHF_FULL_TST : std_logic;\r
- SIGNAL PC_SHF_WR_EN_TST : std_logic;\r
- SIGNAL PC_SHF_RD_EN_TST : std_logic;\r
- SIGNAL PC_SHF_Q_TST : std_logic_vector(7 downto 0);\r
- SIGNAL PC_DF_EMPTY_TST : std_logic;\r
- SIGNAL PC_DF_FULL_TST : std_logic;\r
- SIGNAL PC_DF_WR_EN_TST : std_logic;\r
- SIGNAL PC_DF_RD_EN_TST : std_logic;\r
- SIGNAL PC_DF_Q_TST : std_logic_vector(7 downto 0); \r
- SIGNAL PC_ALL_CTR_TST : std_logic_vector(4 downto 0);\r
- SIGNAL PC_SUB_CTR_TST : std_logic_vector(4 downto 0);\r
- SIGNAL PC_BYTES_LOADED_TST : std_logic_vector(15 downto 0);\r
- SIGNAL PC_SIZE_LEFT_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_SUB_SIZE_TO_SAVE_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_SUB_SIZE_LOADED_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_SUB_BYTES_LOADED_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);\r
- SIGNAL PC_ACT_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);\r
- SIGNAL FC_WR_EN_TST : std_logic;\r
- SIGNAL FC_DATA_TST : std_logic_vector(7 downto 0);\r
- SIGNAL FC_H_READY_TST : std_logic;\r
- SIGNAL FC_READY_TST : std_logic;\r
- SIGNAL FC_IP_SIZE_TST : std_logic_vector(15 downto 0);\r
- SIGNAL FC_UDP_SIZE_TST : std_logic_vector(15 downto 0);\r
- SIGNAL FC_IDENT_TST : std_logic_vector(15 downto 0);\r
- SIGNAL FC_FLAGS_OFFSET_TST : std_logic_vector(15 downto 0);\r
- SIGNAL FC_SOD_TST : std_logic;\r
- SIGNAL FC_EOD_TST : std_logic;\r
- SIGNAL FC_BSM_CONSTR_TST : std_logic_vector(7 downto 0);\r
- SIGNAL FC_BSM_TRANS_TST : std_logic_vector(3 downto 0);\r
- SIGNAL FT_DATA_TST : std_logic_vector(8 downto 0);\r
- SIGNAL FT_TX_EMPTY_TST : std_logic;\r
- SIGNAL FT_START_OF_PACKET_TST : std_logic;\r
- SIGNAL FT_BSM_INIT_TST : std_logic_vector(3 downto 0);\r
- SIGNAL FT_BSM_MAC_TST : std_logic_vector(3 downto 0);\r
- SIGNAL FT_BSM_TRANS_TST : std_logic_vector(3 downto 0);\r
- SIGNAL MAC_HADDR_TST : std_logic_vector(7 downto 0);\r
- SIGNAL MAC_HDATA_TST : std_logic_vector(7 downto 0);\r
- SIGNAL MAC_HCS_TST : std_logic;\r
- SIGNAL MAC_HWRITE_TST : std_logic;\r
- SIGNAL MAC_HREAD_TST : std_logic;\r
- SIGNAL MAC_HREADY_TST : std_logic;\r
- SIGNAL MAC_HDATA_EN_TST : std_logic;\r
- SIGNAL MAC_FIFOAVAIL_TST : std_logic;\r
- SIGNAL MAC_FIFOEOF_TST : std_logic;\r
- SIGNAL MAC_FIFOEMPTY_TST : std_logic;\r
- SIGNAL MAC_TX_READ_TST : std_logic;\r
- SIGNAL MAC_TX_DONE_TST : std_logic;\r
- SIGNAL PCS_AN_LP_ABILITY_TST : std_logic_vector(15 downto 0);\r
- SIGNAL PCS_AN_COMPLETE_TST : std_logic;\r
- SIGNAL PCS_AN_PAGE_RX_TST : std_logic;\r
- SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0);\r
- --gk 29.03.10\r
- signal SLV_ADDR_IN : std_logic_vector(7 downto 0);\r
- signal SLV_READ_IN : std_logic;\r
- signal SLV_WRITE_IN : std_logic;\r
- signal SLV_BUSY_OUT : std_logic;\r
- signal SLV_ACK_OUT : std_logic;\r
- signal SLV_DATA_IN : std_logic_vector(31 downto 0);\r
- signal SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: buf_tester --trb_net16_gbe_buf \r
- GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )\r
- PORT MAP(\r
- CLK => CLK,\r
- CLK_125_TX_IN => '0',\r
- CLK_125_RX_IN => '0',\r
- TEST_CLK => TEST_CLK,\r
- RESET => RESET,\r
- GSR_N => GSR_N,\r
- STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,\r
- STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,\r
- IP_CFG_START_IN => IP_CFG_START_IN,\r
- IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,\r
- IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,\r
- MR_RESET_IN => MR_RESET_IN,\r
- MR_MODE_IN => MR_MODE_IN,\r
- MR_RESTART_IN => MR_RESTART_IN,\r
- IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,\r
- IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,\r
- IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,\r
- -- gk 29.03.10\r
- SLV_ADDR_IN => SLV_ADDR_IN,\r
- SLV_READ_IN => SLV_READ_IN,\r
- SLV_WRITE_IN => SLV_WRITE_IN,\r
- SLV_BUSY_OUT => SLV_BUSY_OUT,\r
- SLV_ACK_OUT => SLV_ACK_OUT,\r
- SLV_DATA_IN => SLV_DATA_IN,\r
- SLV_DATA_OUT => SLV_DATA_OUT,\r
- -- gk 22.04.10\r
- -- registers setup interface\r
- BUS_ADDR_IN => x"00",\r
- BUS_DATA_IN => x"0000_0000",\r
- BUS_DATA_OUT => open,\r
- BUS_WRITE_EN_IN => '0',\r
- BUS_READ_EN_IN => '0',\r
- BUS_ACK_OUT => open,\r
- -- gk 23.04.10\r
- LED_PACKET_SENT_OUT => open,\r
- LED_AN_DONE_N_OUT => open,\r
- --------------------------\r
- CTS_NUMBER_IN => CTS_NUMBER_IN,\r
- CTS_CODE_IN => CTS_CODE_IN,\r
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,\r
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,\r
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,\r
- CTS_DATA_OUT => CTS_DATA_OUT,\r
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,\r
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,\r
- CTS_READ_IN => CTS_READ_IN,\r
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,\r
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,\r
- FEE_READ_OUT => FEE_READ_OUT,\r
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,\r
- FEE_BUSY_IN => FEE_BUSY_IN,\r
- SFP_RXD_P_IN => SFP_RXD_P_IN,\r
- SFP_RXD_N_IN => SFP_RXD_N_IN,\r
- SFP_TXD_P_OUT => SFP_TXD_P_OUT,\r
- SFP_TXD_N_OUT => SFP_TXD_N_OUT,\r
- SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,\r
- SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,\r
- SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,\r
- SFP_LOS_IN => SFP_LOS_IN,\r
- SFP_TXDIS_OUT => SFP_TXDIS_OUT,\r
- IG_CTS_CTR_TST => IG_CTS_CTR_TST,\r
- IG_REM_CTR_TST => IG_REM_CTR_TST,\r
- IG_BSM_LOAD_TST => IG_BSM_LOAD_TST,\r
- IG_BSM_SAVE_TST => IG_BSM_SAVE_TST,\r
- IG_DATA_TST => IG_DATA_TST,\r
- IG_WCNT_TST => IG_WCNT_TST,\r
- IG_RCNT_TST => IG_RCNT_TST,\r
- IG_RD_EN_TST => IG_RD_EN_TST,\r
- IG_WR_EN_TST => IG_WR_EN_TST,\r
- IG_EMPTY_TST => IG_EMPTY_TST,\r
- IG_AEMPTY_TST => IG_AEMPTY_TST,\r
- IG_FULL_TST => IG_FULL_TST,\r
- IG_AFULL_TST => IG_AFULL_TST,\r
- PC_WR_EN_TST => PC_WR_EN_TST,\r
- PC_DATA_TST => PC_DATA_TST,\r
- PC_READY_TST => PC_READY_TST,\r
- PC_START_OF_SUB_TST => PC_START_OF_SUB_TST,\r
- PC_END_OF_DATA_TST => PC_END_OF_DATA_TST,\r
- PC_SUB_SIZE_TST => PC_SUB_SIZE_TST,\r
- PC_TRIG_NR_TST => PC_TRIG_NR_TST,\r
- PC_PADDING_TST => PC_PADDING_TST,\r
- PC_DECODING_TST => PC_DECODING_TST,\r
- PC_EVENT_ID_TST => PC_EVENT_ID_TST,\r
- PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST,\r
- PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST,\r
- PC_BSM_LOAD_TST => PC_BSM_LOAD_TST,\r
- PC_BSM_SAVE_TST => PC_BSM_SAVE_TST,\r
- PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST,\r
- PC_SHF_FULL_TST => PC_SHF_FULL_TST,\r
- PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST,\r
- PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST,\r
- PC_SHF_Q_TST => PC_SHF_Q_TST,\r
- PC_DF_EMPTY_TST => PC_DF_EMPTY_TST,\r
- PC_DF_FULL_TST => PC_DF_FULL_TST,\r
- PC_DF_WR_EN_TST => PC_DF_WR_EN_TST,\r
- PC_DF_RD_EN_TST => PC_DF_RD_EN_TST,\r
- PC_DF_Q_TST => PC_DF_Q_TST,\r
- PC_ALL_CTR_TST => PC_ALL_CTR_TST,\r
- PC_SUB_CTR_TST => PC_SUB_CTR_TST,\r
- PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST,\r
- PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST,\r
- PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST,\r
- PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST,\r
- PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST,\r
- PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST,\r
- PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST, \r
- FC_WR_EN_TST => FC_WR_EN_TST,\r
- FC_DATA_TST => FC_DATA_TST,\r
- FC_H_READY_TST => FC_H_READY_TST,\r
- FC_READY_TST => FC_READY_TST,\r
- FC_IP_SIZE_TST => FC_IP_SIZE_TST,\r
- FC_UDP_SIZE_TST => FC_UDP_SIZE_TST,\r
- FC_IDENT_TST => FC_IDENT_TST,\r
- FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST,\r
- FC_SOD_TST => FC_SOD_TST,\r
- FC_EOD_TST => FC_EOD_TST,\r
- FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST,\r
- FC_BSM_TRANS_TST => FC_BSM_TRANS_TST,\r
- FT_DATA_TST => FT_DATA_TST,\r
- FT_TX_EMPTY_TST => FT_TX_EMPTY_TST,\r
- FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST,\r
- FT_BSM_INIT_TST => FT_BSM_INIT_TST,\r
- FT_BSM_MAC_TST => FT_BSM_MAC_TST,\r
- FT_BSM_TRANS_TST => FT_BSM_TRANS_TST,\r
- MAC_HADDR_TST => MAC_HADDR_TST,\r
- MAC_HDATA_TST => MAC_HDATA_TST,\r
- MAC_HCS_TST => MAC_HCS_TST,\r
- MAC_HWRITE_TST => MAC_HWRITE_TST,\r
- MAC_HREAD_TST => MAC_HREAD_TST,\r
- MAC_HREADY_TST => MAC_HREADY_TST,\r
- MAC_HDATA_EN_TST => MAC_HDATA_EN_TST,\r
- MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST,\r
- MAC_FIFOEOF_TST => MAC_FIFOEOF_TST,\r
- MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST,\r
- MAC_TX_READ_TST => MAC_TX_READ_TST,\r
- MAC_TX_DONE_TST => MAC_TX_DONE_TST,\r
- PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST,\r
- PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST,\r
- PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST,\r
- ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT\r
- );\r
-\r
-\r
-\r
--- 100 MHz system clock\r
-CLOCK_GEN_PROC: process\r
-begin\r
- clk <= '1'; wait for 5.0 ns;\r
- clk <= '0'; wait for 5.0 ns;\r
-end process CLOCK_GEN_PROC;\r
-\r
--- 125 MHz MAC clock\r
-CLOCK2_GEN_PROC: process\r
-begin\r
- test_clk <= '1'; wait for 4.0 ns;\r
- test_clk <= '0'; wait for 3.0 ns;\r
-end process CLOCK2_GEN_PROC;\r
-\r
--- Testbench\r
-TESTBENCH_PROC: process\r
--- test data from TRBnet\r
-variable test_data_len : integer range 0 to 65535 := 1;\r
-variable test_loop_len : integer range 0 to 65535 := 0;\r
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";\r
-variable test_evt_len : unsigned(15 downto 0) := x"0000";\r
-variable test_data : unsigned(15 downto 0) := x"ffff";\r
-\r
-variable trigger_counter : unsigned(15 downto 0) := x"4710";\r
-variable trigger_loop : integer range 0 to 65535 := 15;\r
-\r
--- 1400 bytes MTU => 350 as limit for fragmentation\r
-variable max_event_size : real := 512.0;\r
-\r
-variable seed1 : positive; -- seed for random generator\r
-variable seed2 : positive; -- seed for random generator\r
-variable rand : real; -- random value (0.0 ... 1.0)\r
-variable int_rand : integer; -- random value, scaled to your needs\r
-variable cts_random_number : std_logic_vector(7 downto 0);\r
-\r
-variable stim : std_logic_vector(15 downto 0);\r
-\r
-\r
--- RND test\r
---UNIFORM(seed1, seed2, rand);\r
---int_rand := INTEGER(TRUNC(rand*65536.0));\r
---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));\r
-\r
-begin\r
- -- Setup signals\r
- reset <= '0';\r
- gsr_n <= '1';\r
- \r
- stage_ctrl_regs_in <= x"0000_0000";\r
- \r
- --ip_cfg_start_in <= '0';\r
- --ip_cfg_bank_sel_in <= x"0";\r
- --ip_cfg_mem_data_in <= x"0000_0000";\r
- mr_reset_in <= '0';\r
- mr_mode_in <= '0';\r
- mr_restart_in <= '0';\r
- SLV_ADDR_IN <= x"00";\r
- SLV_READ_IN <= '0';\r
- SLV_WRITE_IN <= '0';\r
- SLV_DATA_IN <= x"0000_0000";\r
- \r
- sfp_los_in <= '0'; -- signal from SFP is present\r
- sfp_prsnt_n_in <= '0'; -- SFP itself is present\r
- sfp_refclk_n_in <= '0';\r
- sfp_refclk_p_in <= '1';\r
- \r
- cts_number_in <= x"0000";\r
- cts_code_in <= x"00";\r
- cts_information_in <= x"00";\r
- cts_readout_type_in <= x"0";\r
- cts_start_readout_in <= '0';\r
- cts_read_in <= '0';\r
- \r
- fee_data_in <= x"0000";\r
- fee_dataready_in <= '0';\r
- fee_status_bits_in <= x"1234_5678";\r
- fee_busy_in <= '0';\r
- \r
- wait for 22 ns;\r
- \r
- -- Reset the whole stuff\r
- wait until rising_edge(clk);\r
- reset <= '1';\r
- gsr_n <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- reset <= '0';\r
- gsr_n <= '1';\r
- wait until rising_edge(clk);\r
- --wait for 100 ns;\r
- \r
- -- Tests may start here\r
- wait until ft_bsm_init_tst = x"7";\r
-\r
- --ip_cfg_start_in <= '1';\r
-\r
- wait for 500 ns;\r
-\r
-\r
--------------------------------------------------------------------------------\r
--- Loop the transmissions\r
--------------------------------------------------------------------------------\r
- trigger_counter := x"4710";\r
- trigger_loop := 10;\r
-\r
- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop\r
- -- generate a real random byte for CTS\r
- UNIFORM(seed1, seed2, rand);\r
- int_rand := INTEGER(TRUNC(rand*256.0));\r
- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));\r
- \r
- -- IPU transmission starts\r
- wait until rising_edge(clk);\r
- cts_number_in <= std_logic_vector( trigger_counter );\r
- cts_code_in <= cts_random_number;\r
- cts_information_in <= x"d1"; -- cts_information_in <= x"de"; -- gk 29.03.10\r
- cts_readout_type_in <= x"1";\r
- cts_start_readout_in <= '1';\r
- wait until rising_edge(clk);\r
- wait for 400 ns;\r
-\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '1';\r
- wait for 300 ns;\r
- wait until rising_edge(clk);\r
-\r
- -- ONE DATA TRANSMISSION\r
- -- dice a length\r
- UNIFORM(seed1, seed2, rand);\r
- test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;\r
- \r
- test_data_len := 9685;\r
- --test_data_len := 400;\r
- \r
- -- calculate the needed variables\r
- test_loop_len := 2*(test_data_len - 1) + 1;\r
- test_hdr_len := to_unsigned( test_data_len + 1, 16 );\r
- test_evt_len := to_unsigned( test_data_len, 16 );\r
-\r
- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)\r
- fee_dataready_in <= '1';\r
- fee_data_in <= x"10" & cts_random_number;\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( trigger_counter );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk); -- BLA\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_hdr_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word\r
- fee_data_in <= x"ff21";\r
- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- fee_data_in <= std_logic_vector( test_evt_len );\r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_data_in <= x"ff22"; \r
- wait until rising_edge(clk) and (fee_read_out = '1');\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
-\r
- test_data := x"ffff";\r
- MY_DATA_LOOP: for J in 0 to test_loop_len loop\r
- test_data := test_data + 1;\r
- wait until rising_edge(clk);\r
- fee_data_in <= std_logic_vector(test_data); \r
- if( (test_data MOD 5) = 0 ) then\r
- fee_dataready_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '1';\r
- else\r
- fee_dataready_in <= '1';\r
- end if;\r
- --fee_dataready_in <= '1';\r
- end loop MY_DATA_LOOP;\r
- -- there must be padding words to get multiple of four LWs\r
- \r
- wait until rising_edge(clk);\r
- fee_dataready_in <= '0';\r
- fee_data_in <= x"0000"; \r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- fee_busy_in <= '0';\r
-\r
-\r
- trigger_loop := trigger_loop + 1;\r
- trigger_counter := trigger_counter + 1;\r
-\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_read_in <= '1';\r
- wait until rising_edge(clk);\r
- cts_read_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- cts_start_readout_in <= '0';\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk);\r
- wait until rising_edge(clk); \r
- \r
- --wait for 8 us;\r
-\r
- end loop MY_TRIGGER_LOOP;\r
-\r
--- wait for 8 us;\r
--------------------------------------------------------------------------------\r
--- end of loop\r
--------------------------------------------------------------------------------\r
- -- Stay a while... stay forever!!!\r
- wait; \r
- \r
-end process TESTBENCH_PROC;\r
-\r
-END;\r
-\r
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.math_real.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY testbench IS
+END testbench;
+
+ARCHITECTURE behavior OF testbench IS
+ component trb_net16_gbe_buf is
+ generic(
+ DO_SIMULATION : integer range 0 to 1 := 1;
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
+ );
+ port(
+ CLK : in std_logic;
+ TEST_CLK : in std_logic; -- only for simulation!
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ RESET : IN std_logic;
+ GSR_N : IN std_logic;
+ STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);
+ ------------------------
+ IP_CFG_START_IN : IN std_logic;
+ IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);
+ IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);
+ MR_RESET_IN : IN std_logic;
+ MR_MODE_IN : IN std_logic;
+ MR_RESTART_IN : IN std_logic;
+ IP_CFG_MEM_CLK_OUT : OUT std_logic;
+ IP_CFG_DONE_OUT : OUT std_logic;
+ IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);
+ -- gk 29.03.10
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- gk 26.04.10
+ -- registers setup interface
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10
+ -- gk 23.04.10
+ LED_PACKET_SENT_OUT : out std_logic;
+ LED_AN_DONE_N_OUT : out std_logic;
+ ------------------------
+ CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);
+ CTS_CODE_IN : IN std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : IN std_logic;
+ CTS_READ_IN : IN std_logic;
+ FEE_DATA_IN : IN std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : IN std_logic;
+ FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : IN std_logic;
+ SFP_RXD_P_IN : IN std_logic;
+ SFP_RXD_N_IN : IN std_logic;
+ SFP_REFCLK_P_IN : IN std_logic;
+ SFP_REFCLK_N_IN : IN std_logic;
+ SFP_PRSNT_N_IN : IN std_logic;
+ SFP_LOS_IN : IN std_logic;
+ STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);
+ CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : OUT std_logic;
+ CTS_READOUT_FINISHED_OUT : OUT std_logic;
+ CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);
+ FEE_READ_OUT : OUT std_logic;
+ SFP_TXD_P_OUT : OUT std_logic;
+ SFP_TXD_N_OUT : OUT std_logic;
+ SFP_TXDIS_OUT : OUT std_logic;
+ IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0);
+ IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0);
+ IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
+ IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
+ IG_DATA_TST : OUT std_logic_vector(15 downto 0);
+ IG_WCNT_TST : OUT std_logic_vector(15 downto 0);
+ IG_RCNT_TST : OUT std_logic_vector(16 downto 0);
+ IG_RD_EN_TST : OUT std_logic;
+ IG_WR_EN_TST : OUT std_logic;
+ IG_EMPTY_TST : OUT std_logic;
+ IG_AEMPTY_TST : OUT std_logic;
+ IG_FULL_TST : OUT std_logic;
+ IG_AFULL_TST : OUT std_logic;
+ PC_WR_EN_TST : OUT std_logic;
+ PC_DATA_TST : OUT std_logic_vector(7 downto 0);
+ PC_READY_TST : OUT std_logic;
+ PC_START_OF_SUB_TST : OUT std_logic;
+ PC_END_OF_DATA_TST : OUT std_logic;
+ PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0);
+ PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0);
+ PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0);
+ PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0);
+ PC_PADDING_TST : OUT std_logic;
+ PC_DECODING_TST : OUT std_logic_vector(31 downto 0);
+ PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0);
+ PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0);
+ PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0);
+ PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
+ PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
+ PC_SHF_EMPTY_TST : OUT std_logic;
+ PC_SHF_FULL_TST : OUT std_logic;
+ PC_SHF_WR_EN_TST : OUT std_logic;
+ PC_SHF_RD_EN_TST : OUT std_logic;
+ PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0);
+ PC_DF_EMPTY_TST : OUT std_logic;
+ PC_DF_FULL_TST : OUT std_logic;
+ PC_DF_WR_EN_TST : OUT std_logic;
+ PC_DF_RD_EN_TST : OUT std_logic;
+ PC_DF_Q_TST : OUT std_logic_vector(7 downto 0);
+ PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0);
+ PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0);
+ PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0);
+ PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
+ PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
+ FC_WR_EN_TST : OUT std_logic;
+ FC_DATA_TST : OUT std_logic_vector(7 downto 0);
+ FC_H_READY_TST : OUT std_logic;
+ FC_READY_TST : OUT std_logic;
+ FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0);
+ FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0);
+ FC_IDENT_TST : OUT std_logic_vector(15 downto 0);
+ FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0);
+ FC_SOD_TST : OUT std_logic;
+ FC_EOD_TST : OUT std_logic;
+ FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0);
+ FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
+ FT_DATA_TST : OUT std_logic_vector(8 downto 0);
+ FT_TX_EMPTY_TST : OUT std_logic;
+ FT_START_OF_PACKET_TST : OUT std_logic;
+ FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0);
+ FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0);
+ FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
+ MAC_HADDR_TST : OUT std_logic_vector(7 downto 0);
+ MAC_HDATA_TST : OUT std_logic_vector(7 downto 0);
+ MAC_HCS_TST : OUT std_logic;
+ MAC_HWRITE_TST : OUT std_logic;
+ MAC_HREAD_TST : OUT std_logic;
+ MAC_HREADY_TST : OUT std_logic;
+ MAC_HDATA_EN_TST : OUT std_logic;
+ MAC_FIFOAVAIL_TST : OUT std_logic;
+ MAC_FIFOEOF_TST : OUT std_logic;
+ MAC_FIFOEMPTY_TST : OUT std_logic;
+ MAC_TX_READ_TST : OUT std_logic;
+ MAC_TX_DONE_TST : OUT std_logic;
+ PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0);
+ PCS_AN_COMPLETE_TST : OUT std_logic;
+ PCS_AN_PAGE_RX_TST : OUT std_logic;
+ ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL CLK : std_logic;
+ SIGNAL TEST_CLK : std_logic;
+ SIGNAL RESET : std_logic;
+ SIGNAL GSR_N : std_logic;
+ SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0);
+ SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0);
+ SIGNAL IP_CFG_START_IN : std_logic;
+ SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0);
+ SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0);
+ SIGNAL MR_RESET_IN : std_logic;
+ SIGNAL MR_MODE_IN : std_logic;
+ SIGNAL MR_RESTART_IN : std_logic;
+ SIGNAL IP_CFG_MEM_CLK_OUT : std_logic;
+ SIGNAL IP_CFG_DONE_OUT : std_logic;
+ SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0);
+ SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0);
+ SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0);
+ SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0);
+ SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0);
+ SIGNAL CTS_START_READOUT_IN : std_logic;
+ SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0);
+ SIGNAL CTS_DATAREADY_OUT : std_logic;
+ SIGNAL CTS_READOUT_FINISHED_OUT : std_logic;
+ SIGNAL CTS_READ_IN : std_logic;
+ SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0);
+ SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
+ SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0);
+ SIGNAL FEE_DATAREADY_IN : std_logic;
+ SIGNAL FEE_READ_OUT : std_logic;
+ SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0);
+ SIGNAL FEE_BUSY_IN : std_logic;
+ SIGNAL SFP_RXD_P_IN : std_logic;
+ SIGNAL SFP_RXD_N_IN : std_logic;
+ SIGNAL SFP_TXD_P_OUT : std_logic;
+ SIGNAL SFP_TXD_N_OUT : std_logic;
+ SIGNAL SFP_REFCLK_P_IN : std_logic;
+ SIGNAL SFP_REFCLK_N_IN : std_logic;
+ SIGNAL SFP_PRSNT_N_IN : std_logic;
+ SIGNAL SFP_LOS_IN : std_logic;
+ SIGNAL SFP_TXDIS_OUT : std_logic;
+ SIGNAL IG_CTS_CTR_TST : std_logic_vector(2 downto 0);
+ SIGNAL IG_REM_CTR_TST : std_logic_vector(3 downto 0);
+ SIGNAL IG_BSM_LOAD_TST : std_logic_vector(3 downto 0);
+ SIGNAL IG_BSM_SAVE_TST : std_logic_vector(3 downto 0);
+ SIGNAL IG_DATA_TST : std_logic_vector(15 downto 0);
+ SIGNAL IG_WCNT_TST : std_logic_vector(15 downto 0);
+ SIGNAL IG_RCNT_TST : std_logic_vector(16 downto 0);
+ SIGNAL IG_RD_EN_TST : std_logic;
+ SIGNAL IG_WR_EN_TST : std_logic;
+ SIGNAL IG_EMPTY_TST : std_logic;
+ SIGNAL IG_AEMPTY_TST : std_logic;
+ SIGNAL IG_FULL_TST : std_logic;
+ SIGNAL IG_AFULL_TST : std_logic;
+ SIGNAL PC_WR_EN_TST : std_logic;
+ SIGNAL PC_DATA_TST : std_logic_vector(7 downto 0);
+ SIGNAL PC_READY_TST : std_logic;
+ SIGNAL PC_START_OF_SUB_TST : std_logic;
+ SIGNAL PC_END_OF_DATA_TST : std_logic;
+ SIGNAL PC_SUB_SIZE_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_TRIG_NR_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_PADDING_TST : std_logic;
+ SIGNAL PC_DECODING_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_EVENT_ID_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_QUEUE_DEC_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_BSM_CONSTR_TST : std_logic_vector(3 downto 0);
+ SIGNAL PC_BSM_LOAD_TST : std_logic_vector(3 downto 0);
+ SIGNAL PC_BSM_SAVE_TST : std_logic_vector(3 downto 0);
+ SIGNAL PC_SHF_EMPTY_TST : std_logic;
+ SIGNAL PC_SHF_FULL_TST : std_logic;
+ SIGNAL PC_SHF_WR_EN_TST : std_logic;
+ SIGNAL PC_SHF_RD_EN_TST : std_logic;
+ SIGNAL PC_SHF_Q_TST : std_logic_vector(7 downto 0);
+ SIGNAL PC_DF_EMPTY_TST : std_logic;
+ SIGNAL PC_DF_FULL_TST : std_logic;
+ SIGNAL PC_DF_WR_EN_TST : std_logic;
+ SIGNAL PC_DF_RD_EN_TST : std_logic;
+ SIGNAL PC_DF_Q_TST : std_logic_vector(7 downto 0);
+ SIGNAL PC_ALL_CTR_TST : std_logic_vector(4 downto 0);
+ SIGNAL PC_SUB_CTR_TST : std_logic_vector(4 downto 0);
+ SIGNAL PC_BYTES_LOADED_TST : std_logic_vector(15 downto 0);
+ SIGNAL PC_SIZE_LEFT_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_SUB_SIZE_TO_SAVE_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_SUB_SIZE_LOADED_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_SUB_BYTES_LOADED_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);
+ SIGNAL PC_ACT_QUEUE_SIZE_TST : std_logic_vector(31 downto 0);
+ SIGNAL FC_WR_EN_TST : std_logic;
+ SIGNAL FC_DATA_TST : std_logic_vector(7 downto 0);
+ SIGNAL FC_H_READY_TST : std_logic;
+ SIGNAL FC_READY_TST : std_logic;
+ SIGNAL FC_IP_SIZE_TST : std_logic_vector(15 downto 0);
+ SIGNAL FC_UDP_SIZE_TST : std_logic_vector(15 downto 0);
+ SIGNAL FC_IDENT_TST : std_logic_vector(15 downto 0);
+ SIGNAL FC_FLAGS_OFFSET_TST : std_logic_vector(15 downto 0);
+ SIGNAL FC_SOD_TST : std_logic;
+ SIGNAL FC_EOD_TST : std_logic;
+ SIGNAL FC_BSM_CONSTR_TST : std_logic_vector(7 downto 0);
+ SIGNAL FC_BSM_TRANS_TST : std_logic_vector(3 downto 0);
+ SIGNAL FT_DATA_TST : std_logic_vector(8 downto 0);
+ SIGNAL FT_TX_EMPTY_TST : std_logic;
+ SIGNAL FT_START_OF_PACKET_TST : std_logic;
+ SIGNAL FT_BSM_INIT_TST : std_logic_vector(3 downto 0);
+ SIGNAL FT_BSM_MAC_TST : std_logic_vector(3 downto 0);
+ SIGNAL FT_BSM_TRANS_TST : std_logic_vector(3 downto 0);
+ SIGNAL MAC_HADDR_TST : std_logic_vector(7 downto 0);
+ SIGNAL MAC_HDATA_TST : std_logic_vector(7 downto 0);
+ SIGNAL MAC_HCS_TST : std_logic;
+ SIGNAL MAC_HWRITE_TST : std_logic;
+ SIGNAL MAC_HREAD_TST : std_logic;
+ SIGNAL MAC_HREADY_TST : std_logic;
+ SIGNAL MAC_HDATA_EN_TST : std_logic;
+ SIGNAL MAC_FIFOAVAIL_TST : std_logic;
+ SIGNAL MAC_FIFOEOF_TST : std_logic;
+ SIGNAL MAC_FIFOEMPTY_TST : std_logic;
+ SIGNAL MAC_TX_READ_TST : std_logic;
+ SIGNAL MAC_TX_DONE_TST : std_logic;
+ SIGNAL PCS_AN_LP_ABILITY_TST : std_logic_vector(15 downto 0);
+ SIGNAL PCS_AN_COMPLETE_TST : std_logic;
+ SIGNAL PCS_AN_PAGE_RX_TST : std_logic;
+ SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0);
+ --gk 29.03.10
+ signal SLV_ADDR_IN : std_logic_vector(7 downto 0);
+ signal SLV_READ_IN : std_logic;
+ signal SLV_WRITE_IN : std_logic;
+ signal SLV_BUSY_OUT : std_logic;
+ signal SLV_ACK_OUT : std_logic;
+ signal SLV_DATA_IN : std_logic_vector(31 downto 0);
+ signal SLV_DATA_OUT : std_logic_vector(31 downto 0);
+
+BEGIN
+
+-- Please check and add your generic clause manually
+ uut: trb_net16_gbe_buf
+ GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
+ PORT MAP(
+ CLK => CLK,
+ CLK_125_TX_IN => '0',
+ CLK_125_RX_IN => '0',
+ TEST_CLK => TEST_CLK,
+ RESET => RESET,
+ GSR_N => GSR_N,
+ STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,
+ STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,
+ IP_CFG_START_IN => IP_CFG_START_IN,
+ IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,
+ IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,
+ MR_RESET_IN => MR_RESET_IN,
+ MR_MODE_IN => MR_MODE_IN,
+ MR_RESTART_IN => MR_RESTART_IN,
+ IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,
+ IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,
+ IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,
+ -- gk 29.03.10
+ SLV_ADDR_IN => SLV_ADDR_IN,
+ SLV_READ_IN => SLV_READ_IN,
+ SLV_WRITE_IN => SLV_WRITE_IN,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT,
+ SLV_DATA_IN => SLV_DATA_IN,
+ SLV_DATA_OUT => SLV_DATA_OUT,
+ -- gk 22.04.10
+ -- registers setup interface
+ BUS_ADDR_IN => x"00",
+ BUS_DATA_IN => x"0000_0000",
+ BUS_DATA_OUT => open,
+ BUS_WRITE_EN_IN => '0',
+ BUS_READ_EN_IN => '0',
+ BUS_ACK_OUT => open,
+ -- gk 23.04.10
+ LED_PACKET_SENT_OUT => open,
+ LED_AN_DONE_N_OUT => open,
+ --------------------------
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ SFP_RXD_P_IN => SFP_RXD_P_IN,
+ SFP_RXD_N_IN => SFP_RXD_N_IN,
+ SFP_TXD_P_OUT => SFP_TXD_P_OUT,
+ SFP_TXD_N_OUT => SFP_TXD_N_OUT,
+ SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,
+ SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,
+ SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
+ SFP_LOS_IN => SFP_LOS_IN,
+ SFP_TXDIS_OUT => SFP_TXDIS_OUT,
+ IG_CTS_CTR_TST => IG_CTS_CTR_TST,
+ IG_REM_CTR_TST => IG_REM_CTR_TST,
+ IG_BSM_LOAD_TST => IG_BSM_LOAD_TST,
+ IG_BSM_SAVE_TST => IG_BSM_SAVE_TST,
+ IG_DATA_TST => IG_DATA_TST,
+ IG_WCNT_TST => IG_WCNT_TST,
+ IG_RCNT_TST => IG_RCNT_TST,
+ IG_RD_EN_TST => IG_RD_EN_TST,
+ IG_WR_EN_TST => IG_WR_EN_TST,
+ IG_EMPTY_TST => IG_EMPTY_TST,
+ IG_AEMPTY_TST => IG_AEMPTY_TST,
+ IG_FULL_TST => IG_FULL_TST,
+ IG_AFULL_TST => IG_AFULL_TST,
+ PC_WR_EN_TST => PC_WR_EN_TST,
+ PC_DATA_TST => PC_DATA_TST,
+ PC_READY_TST => PC_READY_TST,
+ PC_START_OF_SUB_TST => PC_START_OF_SUB_TST,
+ PC_END_OF_DATA_TST => PC_END_OF_DATA_TST,
+ PC_SUB_SIZE_TST => PC_SUB_SIZE_TST,
+ PC_TRIG_NR_TST => PC_TRIG_NR_TST,
+ PC_PADDING_TST => PC_PADDING_TST,
+ PC_DECODING_TST => PC_DECODING_TST,
+ PC_EVENT_ID_TST => PC_EVENT_ID_TST,
+ PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST,
+ PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST,
+ PC_BSM_LOAD_TST => PC_BSM_LOAD_TST,
+ PC_BSM_SAVE_TST => PC_BSM_SAVE_TST,
+ PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST,
+ PC_SHF_FULL_TST => PC_SHF_FULL_TST,
+ PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST,
+ PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST,
+ PC_SHF_Q_TST => PC_SHF_Q_TST,
+ PC_DF_EMPTY_TST => PC_DF_EMPTY_TST,
+ PC_DF_FULL_TST => PC_DF_FULL_TST,
+ PC_DF_WR_EN_TST => PC_DF_WR_EN_TST,
+ PC_DF_RD_EN_TST => PC_DF_RD_EN_TST,
+ PC_DF_Q_TST => PC_DF_Q_TST,
+ PC_ALL_CTR_TST => PC_ALL_CTR_TST,
+ PC_SUB_CTR_TST => PC_SUB_CTR_TST,
+ PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST,
+ PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST,
+ PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST,
+ PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST,
+ PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST,
+ PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST,
+ PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST,
+ FC_WR_EN_TST => FC_WR_EN_TST,
+ FC_DATA_TST => FC_DATA_TST,
+ FC_H_READY_TST => FC_H_READY_TST,
+ FC_READY_TST => FC_READY_TST,
+ FC_IP_SIZE_TST => FC_IP_SIZE_TST,
+ FC_UDP_SIZE_TST => FC_UDP_SIZE_TST,
+ FC_IDENT_TST => FC_IDENT_TST,
+ FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST,
+ FC_SOD_TST => FC_SOD_TST,
+ FC_EOD_TST => FC_EOD_TST,
+ FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST,
+ FC_BSM_TRANS_TST => FC_BSM_TRANS_TST,
+ FT_DATA_TST => FT_DATA_TST,
+ FT_TX_EMPTY_TST => FT_TX_EMPTY_TST,
+ FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST,
+ FT_BSM_INIT_TST => FT_BSM_INIT_TST,
+ FT_BSM_MAC_TST => FT_BSM_MAC_TST,
+ FT_BSM_TRANS_TST => FT_BSM_TRANS_TST,
+ MAC_HADDR_TST => MAC_HADDR_TST,
+ MAC_HDATA_TST => MAC_HDATA_TST,
+ MAC_HCS_TST => MAC_HCS_TST,
+ MAC_HWRITE_TST => MAC_HWRITE_TST,
+ MAC_HREAD_TST => MAC_HREAD_TST,
+ MAC_HREADY_TST => MAC_HREADY_TST,
+ MAC_HDATA_EN_TST => MAC_HDATA_EN_TST,
+ MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST,
+ MAC_FIFOEOF_TST => MAC_FIFOEOF_TST,
+ MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST,
+ MAC_TX_READ_TST => MAC_TX_READ_TST,
+ MAC_TX_DONE_TST => MAC_TX_DONE_TST,
+ PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST,
+ PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST,
+ PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST,
+ ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT
+ );
+
+
+
+-- 100 MHz system clock
+CLOCK_GEN_PROC: process
+begin
+ clk <= '1'; wait for 5.0 ns;
+ clk <= '0'; wait for 5.0 ns;
+end process CLOCK_GEN_PROC;
+
+-- 125 MHz MAC clock
+CLOCK2_GEN_PROC: process
+begin
+ test_clk <= '1'; wait for 4.0 ns;
+ test_clk <= '0'; wait for 3.0 ns;
+end process CLOCK2_GEN_PROC;
+
+-- Testbench
+TESTBENCH_PROC: process
+-- test data from TRBnet
+variable test_data_len : integer range 0 to 65535 := 1;
+variable test_loop_len : integer range 0 to 65535 := 0;
+variable test_hdr_len : unsigned(15 downto 0) := x"0000";
+variable test_evt_len : unsigned(15 downto 0) := x"0000";
+variable test_data : unsigned(15 downto 0) := x"ffff";
+
+variable trigger_counter : unsigned(15 downto 0) := x"4710";
+variable trigger_loop : integer range 0 to 65535 := 15;
+
+-- 1400 bytes MTU => 350 as limit for fragmentation
+variable max_event_size : real := 512.0;
+
+variable seed1 : positive; -- seed for random generator
+variable seed2 : positive; -- seed for random generator
+variable rand : real; -- random value (0.0 ... 1.0)
+variable int_rand : integer; -- random value, scaled to your needs
+variable cts_random_number : std_logic_vector(7 downto 0);
+
+variable stim : std_logic_vector(15 downto 0);
+
+
+-- RND test
+--UNIFORM(seed1, seed2, rand);
+--int_rand := INTEGER(TRUNC(rand*65536.0));
+--stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
+
+begin
+ -- Setup signals
+ reset <= '0';
+ gsr_n <= '1';
+
+ stage_ctrl_regs_in <= x"0000_0000";
+
+ --ip_cfg_start_in <= '0';
+ --ip_cfg_bank_sel_in <= x"0";
+ --ip_cfg_mem_data_in <= x"0000_0000";
+ mr_reset_in <= '0';
+ mr_mode_in <= '0';
+ mr_restart_in <= '0';
+ SLV_ADDR_IN <= x"00";
+ SLV_READ_IN <= '0';
+ SLV_WRITE_IN <= '0';
+ SLV_DATA_IN <= x"0000_0000";
+
+ sfp_los_in <= '0'; -- signal from SFP is present
+ sfp_prsnt_n_in <= '0'; -- SFP itself is present
+ sfp_refclk_n_in <= '0';
+ sfp_refclk_p_in <= '1';
+
+ cts_number_in <= x"0000";
+ cts_code_in <= x"00";
+ cts_information_in <= x"00";
+ cts_readout_type_in <= x"0";
+ cts_start_readout_in <= '0';
+ cts_read_in <= '0';
+
+ fee_data_in <= x"0000";
+ fee_dataready_in <= '0';
+ fee_status_bits_in <= x"1234_5678";
+ fee_busy_in <= '0';
+
+ wait for 22 ns;
+
+ -- Reset the whole stuff
+ wait until rising_edge(clk);
+ reset <= '1';
+ gsr_n <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ reset <= '0';
+ gsr_n <= '1';
+ wait until rising_edge(clk);
+ --wait for 100 ns;
+
+ -- Tests may start here
+ wait until ft_bsm_init_tst = x"7";
+
+ --ip_cfg_start_in <= '1';
+
+ wait for 500 ns;
+
+
+-------------------------------------------------------------------------------
+-- Loop the transmissions
+-------------------------------------------------------------------------------
+ trigger_counter := x"4710";
+ trigger_loop := 10;
+
+ MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
+ -- generate a real random byte for CTS
+ UNIFORM(seed1, seed2, rand);
+ int_rand := INTEGER(TRUNC(rand*256.0));
+ cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
+
+ -- IPU transmission starts
+ wait until rising_edge(clk);
+ cts_number_in <= std_logic_vector( trigger_counter );
+ cts_code_in <= cts_random_number;
+ cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
+ cts_readout_type_in <= x"1";
+ cts_start_readout_in <= '1';
+ wait until rising_edge(clk);
+ wait for 400 ns;
+
+ wait until rising_edge(clk);
+ fee_busy_in <= '1';
+ wait for 300 ns;
+ wait until rising_edge(clk);
+
+ -- ONE DATA TRANSMISSION
+ -- dice a length
+ UNIFORM(seed1, seed2, rand);
+ test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;
+
+ test_data_len := 9685;
+ --test_data_len := 400;
+
+ -- calculate the needed variables
+ test_loop_len := 2*(test_data_len - 1) + 1;
+ test_hdr_len := to_unsigned( test_data_len + 1, 16 );
+ test_evt_len := to_unsigned( test_data_len, 16 );
+
+ -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
+ fee_dataready_in <= '1';
+ fee_data_in <= x"10" & cts_random_number;
+ wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
+ fee_dataready_in <= '0';
+ wait until rising_edge(clk); -- BLA
+ wait until rising_edge(clk); -- BLA
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ fee_dataready_in <= '1';
+ fee_data_in <= std_logic_vector( trigger_counter );
+ wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
+ fee_dataready_in <= '0';
+ wait until rising_edge(clk); -- BLA
+ wait until rising_edge(clk); -- BLA
+ wait until rising_edge(clk); -- BLA
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ fee_dataready_in <= '1';
+ fee_data_in <= std_logic_vector( test_hdr_len );
+ wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
+ fee_data_in <= x"ff21";
+ wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
+ fee_dataready_in <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ fee_dataready_in <= '1';
+ fee_data_in <= std_logic_vector( test_evt_len );
+ wait until rising_edge(clk) and (fee_read_out = '1');
+ fee_data_in <= x"ff22";
+ wait until rising_edge(clk) and (fee_read_out = '1');
+ fee_dataready_in <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+
+ test_data := x"ffff";
+ MY_DATA_LOOP: for J in 0 to test_loop_len loop
+ test_data := test_data + 1;
+ wait until rising_edge(clk);
+ fee_data_in <= std_logic_vector(test_data);
+ if( (test_data MOD 5) = 0 ) then
+ fee_dataready_in <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ fee_dataready_in <= '1';
+ else
+ fee_dataready_in <= '1';
+ end if;
+ --fee_dataready_in <= '1';
+ end loop MY_DATA_LOOP;
+ -- there must be padding words to get multiple of four LWs
+
+ wait until rising_edge(clk);
+ fee_dataready_in <= '0';
+ fee_data_in <= x"0000";
+
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ fee_busy_in <= '0';
+
+
+ trigger_loop := trigger_loop + 1;
+ trigger_counter := trigger_counter + 1;
+
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ cts_read_in <= '1';
+ wait until rising_edge(clk);
+ cts_read_in <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ cts_start_readout_in <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+
+ --wait for 8 us;
+
+ end loop MY_TRIGGER_LOOP;
+
+-- wait for 8 us;
+-------------------------------------------------------------------------------
+-- end of loop
+-------------------------------------------------------------------------------
+ -- Stay a while... stay forever!!!
+ wait;
+
+end process TESTBENCH_PROC;
+
+END;
+
jspc29 / trbnet.git / commitdiff