-- and c_IS_UNUSED for port not being used.
-- Signals for internal port are automatically generated in case of c_IS_SLAVE.
-- INCLUDE_DLM: '1' inserts Trudy and Eve, and activates the control signals.
--- '0' is "normal" operation.
+-- '0' is "normal" Ethernet operation.
-- In case no Slave Port is inside the media interface, local port signals are set to zero.
-- If a Slave Port is inside, the local port is connected there.
SYNC_TX_PLL_IN : in std_logic;
WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST
-- DLM
- DLM_INJECT_IN : in std_logic_vector(3 downto 0) := (others => '0');
- DLM_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0) := (others => '0');
- DLM_FOUND_OUT : out std_logic_vector(3 downto 0);
- DLM_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
- DLM_CLK_OUT : out std_logic_vector(3 downto 0);
+ DLM_RX_OUT : out std_logic; -- pulse from slave port, if any
+ DLM_RX_PL_OUT : out std_logic_vector(7 downto 0); -- payload from slave port, if any
+ DLM_TX_IN : in std_logic := '0';
+ DLM_TX_PL_IN : in std_logic_vector(7 downto 0) := (others => '0');
-- Debug
WAP_OUT : out std_logic_vector(15 downto 0);
STATUS_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
signal lsm_status : std_logic_vector(3 downto 0);
signal rx_clk_en : std_logic_vector(3 downto 0);
signal tx_clk_en : std_logic_vector(3 downto 0);
- signal operational_rate : std_logic_vector(4 * 2 - 1 downto 0);
- signal an_complete : std_logic_vector(3 downto 0);
- signal mr_page_rx : std_logic_vector(3 downto 0);
- signal mr_lp_adv_ability : std_logic_vector(4 * 16 - 1 downto 0);
- signal mr_main_reset : std_logic_vector(3 downto 0);
- signal mr_restart_an : std_logic_vector(3 downto 0);
- signal mr_adv_ability : std_logic_vector(4 * 16 - 1 downto 0);
- signal mr_an_enable : std_logic_vector(3 downto 0);
signal an_link_ok : std_logic_vector(3 downto 0);
signal pcs_rxd : std_logic_vector(4 * 8 - 1 downto 0);
signal pcs_rx_en : std_logic_vector(3 downto 0);
signal tsm_hcs_n : std_logic_vector(3 downto 0);
signal tsm_hdata : std_logic_vector(4 * 8 - 1 downto 0);
signal tsm_haddr : std_logic_vector(4 * 8 - 1 downto 0);
-
- signal synced_rst : std_logic;
-
+
signal powerup_ch : std_logic_vector(3 downto 0);
signal link_rx_ready : std_logic_vector(3 downto 0);
signal rx_los_low : std_logic_vector(3 downto 0);
signal rx_pcs_rst_q : std_logic_vector(3 downto 0);
signal rx_serdes_rst : std_logic_vector(3 downto 0);
signal rx_serdes_rst_q : std_logic_vector(3 downto 0);
- signal tx_plol_lol : std_logic;
+ signal serdes_active : std_logic_vector(3 downto 0);
signal debug : std_logic_vector(63 downto 0);
- -- for replacing register interface
- signal delay_q : std_logic_vector(4 * 8 - 1 downto 0);
- signal pulse : std_logic_vector(3 downto 0);
-
signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic_vector(3 downto 0);
signal mac_tx_data : std_logic_vector(4 * 8 - 1 downto 0);
signal wa_position_i : std_logic_vector(15 downto 0) := x"ffff";
signal wap_requested_i : std_logic_vector(15 downto 0);
signal is_wap_zero : std_logic_vector(3 downto 0);
+ signal dlm_rx_i : std_logic_vector(3 downto 0);
+ signal dlm_data_rx_i : std_logic_vector(31 downto 0);
+
+ signal an_link_ok_i : std_logic_vector(3 downto 0);
signal quad_mode : integer range 0 to 100;
+ signal main_rx_state : std_logic_vector(15 downto 0);
+
+ signal mr_page_rx_i : std_logic_vector(3 downto 0);
+-- signal rst_n_sgmii_i : std_logic_vector(3 downto 0);
+
begin
-- constants used as reminder
link_rx_ready(3) when (LINK_MODE(3) = c_IS_SLAVE) else
'0';
--------------------------------------------------
+-------------------------------------------------
-- WAP request (for testing)
-------------------------------------------------
wap_requested_i(0*4+3 downto 0*4) <= WAP_REQUESTED_IN when (LINK_MODE(0) = c_IS_MASTER) else x"0";
wap_requested_i(2*4+3 downto 2*4) <= WAP_REQUESTED_IN when (LINK_MODE(2) = c_IS_MASTER) else x"0";
wap_requested_i(3*4+3 downto 3*4) <= WAP_REQUESTED_IN when (LINK_MODE(3) = c_IS_MASTER) else x"0";
+-------------------------------------------------
+-------------------------------------------------
+ DLM_RX_OUT <= dlm_rx_i(0) when (LINK_MODE(0) = c_IS_SLAVE) else
+ dlm_rx_i(1) when (LINK_MODE(1) = c_IS_SLAVE) else
+ dlm_rx_i(2) when (LINK_MODE(2) = c_IS_SLAVE) else
+ dlm_rx_i(3) when (LINK_MODE(3) = c_IS_SLAVE) else
+ '0';
+
+ DLM_RX_PL_OUT <= dlm_data_rx_i(7 downto 0) when (LINK_MODE(0) = c_IS_SLAVE) else
+ dlm_data_rx_i(15 downto 8) when (LINK_MODE(1) = c_IS_SLAVE) else
+ dlm_data_rx_i(23 downto 16) when (LINK_MODE(2) = c_IS_SLAVE) else
+ dlm_data_rx_i(31 downto 24) when (LINK_MODE(3) = c_IS_SLAVE) else
+ x"00";
+
-------------------------------------------------
-- SerDes quad
-------------------------------------------------
hdoutp_ch0 => SD_TXD_P_OUT(0),
hdoutn_ch0 => SD_TXD_N_OUT(0),
rxiclk_ch0 => sd_rx_clk(0),
- txiclk_ch0 => MASTER_CLK_IN, -- CLK_125
+ txiclk_ch0 => MASTER_CLK_IN,
rx_full_clk_ch0 => sd_rx_clk(0),
rx_half_clk_ch0 => open,
tx_full_clk_ch0 => open,
hdoutp_ch1 => SD_TXD_P_OUT(1),
hdoutn_ch1 => SD_TXD_N_OUT(1),
rxiclk_ch1 => sd_rx_clk(1),
- txiclk_ch1 => MASTER_CLK_IN, -- CLK_125,
+ txiclk_ch1 => MASTER_CLK_IN,
rx_full_clk_ch1 => sd_rx_clk(1),
rx_half_clk_ch1 => open,
tx_full_clk_ch1 => open,
hdoutp_ch2 => SD_TXD_P_OUT(2),
hdoutn_ch2 => SD_TXD_N_OUT(2),
rxiclk_ch2 => sd_rx_clk(2),
- txiclk_ch2 => MASTER_CLK_IN, -- CLK_125,
+ txiclk_ch2 => MASTER_CLK_IN,
rx_full_clk_ch2 => sd_rx_clk(2),
rx_half_clk_ch2 => open,
tx_full_clk_ch2 => open,
hdoutp_ch3 => SD_TXD_P_OUT(3),
hdoutn_ch3 => SD_TXD_N_OUT(3),
rxiclk_ch3 => sd_rx_clk(3),
- txiclk_ch3 => MASTER_CLK_IN, -- CLK_125,
+ txiclk_ch3 => MASTER_CLK_IN,
rx_full_clk_ch3 => sd_rx_clk(3),
rx_half_clk_ch3 => open,
tx_full_clk_ch3 => open,
lsm_status_ch3_s => lsm_status(3),
rx_cdr_lol_ch3_s => rx_cdr_lol(3),
---- Miscallaneous ports
- fpga_txrefclk => MASTER_CLK_IN, --CLK_125,
+ fpga_txrefclk => MASTER_CLK_IN,
tx_serdes_rst_c => '0',
- tx_pll_lol_qd_s => tx_plol_lol,
+ tx_pll_lol_qd_s => TX_PLOL_LOL_OUT,
rst_qd_c => CLEAR, -- ONLY ONCE
serdes_rst_qd_c => '0',
- tx_sync_qd_c => SYNC_TX_PLL_IN, --'0'
+ tx_sync_qd_c => SYNC_TX_PLL_IN,
-- SCI interface
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
SCI_WRN => sci_write_i
);
- TX_PLOL_LOL_OUT <= tx_plol_lol;
-
-- SCI reader for WAP position
THE_SCI_READER : entity work.gbe_sci_reader
port map(
WAP_OUT <= wa_position_i;
- -- in case we have no uplink port...
+ -- in case we have no uplink port, no local port is generated
NO_LOCAL_GEN: if (quad_mode < 8) generate
MAC_RX_DATA_OUT <= (others => '0');
MAC_RX_WRITE_OUT <= '0';
MAC_RX_EOF_OUT <= '0';
MAC_RX_ERROR_OUT <= '0';
end generate NO_LOCAL_GEN;
-
+
+ -- generate master and slave channel, i.e. active SerDes connections
CHANNEL_GEN : for i in 0 to 3 generate
CHANNEL_ACTIVE_GEN : if ((LINK_MODE(i) = c_IS_SLAVE) or (LINK_MODE(i) = c_IS_MASTER)) generate
THE_TX_PARSER: entity parser
port map(
- CLK => MASTER_CLK_IN, --CLK_125,
+ CLK => MASTER_CLK_IN,
RESET => CLEAR,
--
- PHY_D_IN => sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8),
- PHY_K_IN => sd_tx_kcntl_dst(i),
+ PHY_D_IN => sd_tx_data_src(i * 8 + 7 downto i * 8),
+ PHY_K_IN => sd_tx_kcntl_src(i),
--
UNKNOWN_OUT => unknown_tx_int(i),
IDLE_OUT => idle_tx_int(i),
CLK => sd_rx_clk(i),
RESET => CLEAR,
--
- PHY_D_IN => sd_rx_data_src((i + 1) * 8 - 1 downto i * 8),
- PHY_K_IN => sd_rx_kcntl_src(i),
+ PHY_D_IN => sd_rx_data_dst(i * 8 + 7 downto i * 8),
+ PHY_K_IN => sd_rx_kcntl_dst(i),
--
UNKNOWN_OUT => unknown_rx_int(i),
IDLE_OUT => idle_rx_int(i),
DEBUG_OUT((i + 1) * 32 - 2) <= '0';
DEBUG_OUT((i + 1) * 32 - 3) <= '0';
DEBUG_OUT((i + 1) * 32 - 4) <= '0';
- DEBUG_OUT((i + 1) * 32 - 5) <= is_wap_zero(i);
- DEBUG_OUT((i + 1) * 32 - 6) <= sci_read_i;
- DEBUG_OUT((i + 1) * 32 - 7) <= tx_clk_avail_i;
- DEBUG_OUT((i + 1) * 32 - 8) <= link_active(i);
- DEBUG_OUT((i + 1) * 32 - 9) <= mac_ready_conf(i);
- DEBUG_OUT((i + 1) * 32 - 10) <= mac_reconf(i);
- DEBUG_OUT((i + 1) * 32 - 11) <= an_complete(i);
- DEBUG_OUT((i + 1) * 32 - 12) <= mr_page_rx(i);
- DEBUG_OUT((i + 1) * 32 - 13) <= mr_restart_an(i);
- DEBUG_OUT((i + 1) * 32 - 14) <= cfg_rx_int(i);
- DEBUG_OUT((i + 1) * 32 - 15) <= idle_rx_int(i);
- DEBUG_OUT((i + 1) * 32 - 16) <= unknown_rx_int(i);
- DEBUG_OUT((i + 1) * 32 - 17) <= cfg_tx_int(i);
- DEBUG_OUT((i + 1) * 32 - 18) <= idle_tx_int(i);
- DEBUG_OUT((i + 1) * 32 - 19) <= unknown_tx_int(i);
- DEBUG_OUT((i + 1) * 32 - 20) <= TX_LINK_READY_IN;
- DEBUG_OUT((i + 1) * 32 - 21) <= link_rx_ready(i);
- DEBUG_OUT((i + 1) * 32 - 22) <= rx_serdes_rst(i);
- DEBUG_OUT((i + 1) * 32 - 23) <= rx_pcs_rst(i);
- DEBUG_OUT((i + 1) * 32 - 24) <= sd_rx_disp_error(i);
- DEBUG_OUT((i + 1) * 32 - 25) <= sd_rx_cv_error(i);
- DEBUG_OUT((i + 1) * 32 - 26) <= lsm_status(i);
- DEBUG_OUT((i + 1) * 32 - 27) <= rx_los_low(i);
- DEBUG_OUT((i + 1) * 32 - 28) <= rx_cdr_lol(i);
- DEBUG_OUT((i + 1) * 32 - 29) <= TX_PCS_RST_IN;
- DEBUG_OUT((i + 1) * 32 - 30) <= tx_plol_lol;
- DEBUG_OUT((i + 1) * 32 - 31) <= RESET;
- DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR;
+ DEBUG_OUT((i + 1) * 32 - 5) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 6) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 7) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 8) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 9) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 10) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 11) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 12) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 13) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 14) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 15) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 16) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 17) <= '0'; -- (15)
+ DEBUG_OUT((i + 1) * 32 - 18) <= '0'; -- (14)
+ DEBUG_OUT((i + 1) * 32 - 19) <= '0'; -- (13)
+ DEBUG_OUT((i + 1) * 32 - 20) <= an_link_ok_i(i); -- (12)
+ DEBUG_OUT((i + 1) * 32 - 21) <= mr_page_rx_i(i); -- (11)
+ DEBUG_OUT((i + 1) * 32 - 22) <= cfg_rx_int(i); -- (10)
+ DEBUG_OUT((i + 1) * 32 - 23) <= idle_rx_int(i); -- (9)
+ DEBUG_OUT((i + 1) * 32 - 24) <= unknown_rx_int(i); -- (8)
+ DEBUG_OUT((i + 1) * 32 - 25) <= cfg_tx_int(i); -- (7)
+ DEBUG_OUT((i + 1) * 32 - 26) <= idle_tx_int(i); -- (6)
+ DEBUG_OUT((i + 1) * 32 - 27) <= unknown_tx_int(i); --(5)
+ DEBUG_OUT((i + 1) * 32 - 28) <= link_active(i); -- (4)
+ DEBUG_OUT((i + 1) * 32 - 29) <= link_rx_ready(i); -- (3)
+ DEBUG_OUT((i + 1) * 32 - 30) <= TX_LINK_READY_IN; -- (2)
+ DEBUG_OUT((i + 1) * 32 - 31) <= RESET; -- (1)
+ DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR; -- (0)
powerup_ch(i) <= '1';
SD_TXDIS_OUT(i) <= '0';
CV_IN => sd_rx_cv_error(i),
LSM_IN => lsm_status(i),
LOS_IN => rx_los_low(i),
- WAP_ZERO_IN => is_wap_zero(i), --'1', -- not needed here
+ WAP_ZERO_IN => is_wap_zero(i),
-- outputs
WAP_REQ_OUT => open, -- not needed here
RX_SERDES_RST_OUT => rx_serdes_rst(i), -- CLK_REF based
RX_PCS_RST_OUT => rx_pcs_rst(i), -- CLK_REF based
LINK_RX_READY_OUT => link_rx_ready(i), -- CLK_REF based
- STATE_OUT => open
+ STATE_OUT => main_rx_state(i * 4 + 3 downto i * 4) --open
);
-- BUG, WAP_REQUESTED_IN to be replaced by wap_requested_i()
TRUDY_AND_EVE: if INCLUDE_DLM(i) = 1 generate
THE_TRUDY: entity inserter
port map(
- CLK => MASTER_CLK_IN, --sd_tx_clk(i), --CLK_125,
- RESET => CLEAR,
+ CLK => MASTER_CLK_IN,
+ CLEAR => CLEAR, -- MUST NOT BE RESET!
+ ACTIVE_IN => TX_LINK_READY_IN,
-- PHY output
- PHY_D_IN => sd_tx_data_src((i + 1) * 8 - 1 downto i * 8),
+ PHY_D_IN => sd_tx_data_src(i * 8 + 7 downto i * 8),
PHY_K_IN => sd_tx_kcntl_src(i),
PHY_CD_IN => sd_tx_correct_disp_src(i),
-- SerDes input
- TX_D_OUT => sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8),
+ TX_D_OUT => sd_tx_data_dst(i * 8 + 7 downto i * 8),
TX_K_OUT => sd_tx_kcntl_dst(i),
TX_CD_OUT => sd_tx_correct_disp_dst(i),
-- DLM stuff
- DLM_DATA_IN => DLM_DATA_IN((i + 1) * 8 - 1 downto i * 8),
- DLM_INJECT_IN => DLM_INJECT_IN(i),
+ DLM_DATA_IN => DLM_TX_PL_IN,
+ DLM_INJECT_IN => DLM_TX_IN,
--
DEBUG_OUT => open
);
-
+
THE_EVE: entity remover
port map(
CLK => sd_rx_clk(i),
- RESET => CLEAR,
+ CLEAR => CLEAR, -- MUST NOT BE RESET!
+ ACTIVE_IN => link_rx_ready(i),
-- SerDes output
- RX_D_IN => sd_rx_data_src((i + 1) * 8 - 1 downto i * 8),
+ RX_D_IN => sd_rx_data_src(i * 8 + 7 downto i * 8),
RX_K_IN => sd_rx_kcntl_src(i),
-- PHY input
- PHY_D_OUT => sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8),
+ PHY_D_OUT => sd_rx_data_dst(i * 8 + 7 downto i * 8),
PHY_K_OUT => sd_rx_kcntl_dst(i),
-- DLM stuff
- DLM_DATA_OUT => DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8),
- DLM_FOUND_OUT => DLM_FOUND_OUT(i),
+ DLM_DATA_OUT => dlm_data_rx_i(i * 8 + 7 downto i * 8),
+ DLM_FOUND_OUT => dlm_rx_i(i),
--
DEBUG_OUT => open
);
end generate TRUDY_AND_EVE;
NO_TRUDY_AND_EVE: if INCLUDE_DLM(i) = 0 generate
- sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_tx_data_src((i + 1) * 8 - 1 downto i * 8);
- sd_tx_kcntl_dst(i) <= sd_tx_kcntl_src(i);
- sd_tx_correct_disp_dst(i) <= sd_tx_correct_disp_src(i);
- sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_rx_data_src((i + 1) * 8 - 1 downto i * 8);
- sd_rx_kcntl_dst(i) <= sd_rx_kcntl_src(i);
- DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8) <= (others => '0');
- DLM_FOUND_OUT(i) <= '0';
+ sd_tx_data_dst(i * 8 + 7 downto i * 8) <= sd_tx_data_src(i * 8 + 7 downto i * 8);
+ sd_tx_kcntl_dst(i) <= sd_tx_kcntl_src(i);
+ sd_tx_correct_disp_dst(i) <= sd_tx_correct_disp_src(i);
+ sd_rx_data_dst(i * 8 + 7 downto i * 8) <= sd_rx_data_src(i * 8 + 7 downto i * 8);
+ sd_rx_kcntl_dst(i) <= sd_rx_kcntl_src(i);
end generate NO_TRUDY_AND_EVE;
- ------------------------------------------------------------
- ------------------------------------------------------------
- ------------------------------------------------------------
+ -- Reset signal for SGMII core
+ -- rst_n_sgmii_i
+
+-- rst_n_sgmii_i(i) <= link_rx_ready(i) when (LINK_MODE(i) = c_IS_SLAVE) else
+-- TX_LINK_READY_IN when (LINK_MODE(i) = c_IS_MASTER) else
+-- '0';
+
-- SGMII core
SGMII_GBE_PCS : sgmii_gbe_pcs42
port map(
- rst_n => RESET_N, --CLEAR_N,
- signal_detect => link_rx_ready(i),
+ rst_n => CLEAR_N, --rst_n_sgmii_i(i), --RESET_N,
+ signal_detect => link_rx_ready(i), --serdes_active(i),
gbe_mode => '1',
sgmii_mode => '0',
- operational_rate => operational_rate((i + 1) * 2 - 1 downto i * 2),
+ operational_rate => b"10",
debug_link_timer_short => '0',
force_isolate => '0',
force_loopback => '0',
rx_compensation_err => open,
ctc_drop_flag => open,
ctc_add_flag => open,
- an_link_ok => open,
+ an_link_ok => an_link_ok_i(i),
-- MAC interface
- tx_clk_125 => MASTER_CLK_IN, --CLK_125,
+ tx_clk_125 => MASTER_CLK_IN,
tx_clock_enable_source => tx_clk_en(i),
tx_clock_enable_sink => tx_clk_en(i),
- tx_d => pcs_txd((i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
+ tx_d => pcs_txd(i * 8 + 7 downto i * 8), -- TX data from MAC
tx_en => pcs_tx_en(i), -- TX data enable from MAC
tx_er => pcs_tx_er(i), -- TX error from MAC
- rx_clk_125 => MASTER_CLK_IN, --CLK_125,
+ rx_clk_125 => MASTER_CLK_IN,
rx_clock_enable_source => rx_clk_en(i),
rx_clock_enable_sink => rx_clk_en(i),
- rx_d => pcs_rxd((i + 1 ) * 8 - 1 downto i * 8), -- RX data to MAC
+ rx_d => pcs_rxd(i * 8 + 7 downto i * 8), -- RX data to MAC
rx_dv => pcs_rx_en(i), -- RX data enable to MAC
rx_er => pcs_rx_er(i), -- RX error to MAC
col => open,
crs => open,
-- SerDes interface
- tx_data => sd_tx_data_src((i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
+ tx_data => sd_tx_data_src(i * 8 + 7 downto i * 8), -- TX data to SerDes
tx_kcntl => sd_tx_kcntl_src(i), -- TX komma control to SerDes
tx_disparity_cntl => sd_tx_correct_disp_src(i), -- idle parity state control in IPG (to SerDes)
xmit_autoneg => xmit(i),
serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
- rx_data => sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
+ rx_data => sd_rx_data_dst(i * 8 + 7 downto i * 8), -- RX data from SerDes
rx_kcntl => sd_rx_kcntl_dst(i), -- RX komma control from SerDes
rx_err_decode_mode => '0', -- receive error control mode fixed to normal
rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
rx_disp_err => sd_rx_disp_error(i), -- RX disparity error from SerDes
rx_cv_err => sd_rx_cv_error(i), -- RX code violation error from SerDes
-- Autonegotiation stuff
- mr_an_complete => an_complete(i),
- mr_page_rx => mr_page_rx(i),
- mr_lp_adv_ability => mr_lp_adv_ability((i + 1) * 16 - 1 downto i * 16),
- mr_main_reset => mr_main_reset(i),
- mr_an_enable => mr_an_enable(i),
- mr_restart_an => mr_restart_an(i),
- mr_adv_ability => mr_adv_ability((i + 1) * 16 - 1 downto i * 16)
+ mr_an_complete => open,
+ mr_page_rx => mr_page_rx_i(i), --open,
+ mr_lp_adv_ability => open,
+ mr_main_reset => CLEAR,
+ mr_an_enable => link_rx_ready(i), --'1',
+ mr_restart_an => '0',
+ mr_adv_ability => x"0020"
);
-
- operational_rate((i + 1) * 2 - 1 downto i * 2) <= b"10";
-
- mr_main_reset(i) <= RESET;
- mr_restart_an(i) <= pulse(i);
- mr_an_enable(i) <= link_rx_ready(i);
- mr_adv_ability((i + 1) * 16 - 1 downto i * 16) <= x"0020";
-
--- SYNC_PROC: process( CLK_125 )
- SYNC_PROC: process( MASTER_CLK_IN )
- begin
--- if( rising_edge(CLK_125) ) then
- if( rising_edge(MASTER_CLK_IN) ) then
- delay_q((i + 1) * 8 - 1 downto i * 8) <= delay_q((i + 1) * 8 - 2 downto i * 8) & link_rx_ready(i);
- end if;
- end process SYNC_PROC;
-
- pulse(i) <= not delay_q((i + 1) * 8 - 1) and delay_q((i + 1) * 8 - 2);
-- TSMAC core
MAC: tsmac41
port map(
----------------- clock and reset port declarations ------------------
- hclk => MASTER_CLK_IN, --CLK_125,
- txmac_clk => MASTER_CLK_IN, --CLK_125,
- rxmac_clk => MASTER_CLK_IN, --CLK_125,
+ hclk => MASTER_CLK_IN,
+ txmac_clk => MASTER_CLK_IN,
+ rxmac_clk => MASTER_CLK_IN,
reset_n => RESET_N,
------------------- Input signals to the GMII ----------------
- rxd => pcs_rxd((i + 1) * 8 - 1 downto i * 8),
+ rxd => pcs_rxd(i * 8 + 7 downto i * 8),
rx_dv => pcs_rx_en(i),
rx_er => pcs_rx_er(i),
-------------------- Input signals to the CPU I/F -------------------
- haddr => tsm_haddr((i + 1) * 8 - 1 downto i * 8),
- hdatain => tsm_hdata((i + 1) * 8 - 1 downto i * 8),
+ haddr => tsm_haddr(i * 8 + 7 downto i * 8),
+ hdatain => tsm_hdata(i * 8 + 7 downto i * 8),
hcs_n => tsm_hcs_n(i),
hwrite_n => tsm_hwrite_n(i),
hread_n => tsm_hread_n(i),
---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => mac_tx_data((i + 1) * 8 - 1 downto i * 8),
+ tx_fifodata => mac_tx_data(i * 8 + 7 downto i * 8),
tx_fifoavail => mac_fifoavail(i),
tx_fifoeof => mac_fifoeof(i),
tx_fifoempty => mac_fifoempty(i),
rx_fifo_full => mac_rx_fifofull(i),
ignore_pkt => '0',
---------------- Output signals from the GMII -----------------------
- txd => pcs_txd((i + 1) * 8 - 1 downto i * 8),
+ txd => pcs_txd(i * 8 + 7 downto i * 8),
tx_en => pcs_tx_en(i),
tx_er => pcs_tx_er(i),
----------------- Output signals from the CPU I/F -------------------
------------- Output signals from the Rx MAC FIFO I/F ---------------
rx_fifo_error => open,
rx_stat_vector => open,
- rx_dbout => mac_rx_data((i + 1) * 8 - 1 downto i * 8),
+ rx_dbout => mac_rx_data(i * 8 + 7 downto i * 8),
rx_write => mac_rx_wr(i),
rx_stat_en => open,
rx_eof => mac_rx_eof(i),
-- CAN BE OPTIMIZED
TSMAC_CONTROLLER : trb_net16_gbe_mac_control
port map(
- CLK => MASTER_CLK_IN, --CLK_125,
+ CLK => MASTER_CLK_IN,
RESET => RESET,
-- signals to/from main controller
MC_TSMAC_READY_OUT => mac_ready_conf(i),
MC_PROMISC_IN => '1',
MC_MAC_ADDR_IN => (others => '0'),
-- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => tsm_haddr((i + 1) * 8 - 1 downto i * 8),
- TSM_HDATA_OUT => tsm_hdata((i + 1) * 8 - 1 downto i * 8),
+ TSM_HADDR_OUT => tsm_haddr(i * 8 + 7 downto i * 8),
+ TSM_HDATA_OUT => tsm_hdata(i * 8 + 7 downto i * 8),
TSM_HCS_N_OUT => tsm_hcs_n(i),
TSM_HWRITE_N_OUT => tsm_hwrite_n(i),
TSM_HREAD_N_OUT => tsm_hread_n(i),
-- initializes MAC after AN is complete
THE_FW_GBE_LSM: entity gbe_lsm
port map(
- CLK => MASTER_CLK_IN, --CLK_125,
+ CLK => MASTER_CLK_IN,
RESET => RESET,
--
- MAC_AN_COMPLETE_IN => an_complete(i),
+ MAC_AN_COMPLETE_IN => an_link_ok_i(i),
MAC_READY_CONF_IN => mac_ready_conf(i),
MAC_RECONF_OUT => mac_reconf(i),
--
-- RX ringbuffer
THE_FW_RB: entity rx_rb
port map(
- CLK => MASTER_CLK_IN, --CLK_125,
+ CLK => MASTER_CLK_IN,
RESET => RESET,
-- MAC interface (RX)
- MAC_RX_DATA_IN => mac_rx_data((i + 1) * 8 - 1 downto i * 8),
+ MAC_RX_DATA_IN => mac_rx_data(i * 8 + 7 downto i * 8),
MAC_RX_WR_IN => mac_rx_wr(i),
MAC_RX_EOF_IN => mac_rx_eof(i),
MAC_RX_ERROR_IN => mac_rx_err(i),
-- FIFO interface (TX)
FIFO_FULL_IN => FIFO_FULL_IN(i),
FIFO_WR_OUT => FIFO_WR_OUT(i),
- FIFO_Q_OUT => FIFO_DATA_OUT((i + 1) * 9 - 1 downto i * 9),
+ FIFO_Q_OUT => FIFO_DATA_OUT(i * 9 + 8 downto i * 9),
FRAME_REQ_IN => FRAME_REQ_IN(i),
FRAME_ACK_OUT => FRAME_ACK_OUT(i),
FRAME_AVAIL_OUT => FRAME_AVAIL_OUT(i),
-- TX FIFO
THE_FW_FIFO: entity tx_fifo
port map(
- CLK => MASTER_CLK_IN, --CLK_125,
+ CLK => MASTER_CLK_IN,
RESET => RESET,
-- MAC interface
- MAC_TX_DATA_OUT => mac_tx_data((i + 1) * 8 - 1 downto i * 8),
+ MAC_TX_DATA_OUT => mac_tx_data(i * 8 + 7 downto i * 8),
MAC_TX_READ_IN => mac_tx_read(i),
MAC_FIFOEOF_OUT => mac_fifoeof(i),
MAC_FIFOEMPTY_OUT => mac_fifoempty(i),
-- FIFO interface
FIFO_FULL_OUT => FIFO_FULL_OUT(i),
FIFO_WR_IN => FIFO_WR_IN(i),
- FIFO_D_IN => FIFO_DATA_IN((i + 1) * 9 - 1 downto i * 9),
+ FIFO_D_IN => FIFO_DATA_IN(i * 9 + 8 downto i * 9),
-- Link stuff
FRAME_START_IN => FRAME_START_IN(i),
LINK_ACTIVE_IN => link_active(i)
);
- PCS_AN_READY_OUT(i) <= an_complete(i); -- needed for internal SCTRL
+ PCS_AN_READY_OUT(i) <= an_link_ok_i(i); -- needed for internal SCTRL
LINK_ACTIVE_OUT(i) <= link_active(i);
-- LED connections, can be simplified by CE signal, to get rid of local counter instances
led_activity_x(i) <= pcs_rx_en(i) or pcs_tx_en(i);
--- THE_LED_ACT_PROC: process( CLK_125 )
THE_LED_ACT_PROC: process( MASTER_CLK_IN )
begin
--- if( rising_edge(CLK_125) ) then
if( rising_edge(MASTER_CLK_IN) ) then
if( led_activity_x(i) = '1' ) then
led_activity((i + 1) * 2 - 2) <= '1';
end if;
end process THE_LED_ACT_PROC;
+ serdes_active(i) <= TX_LINK_READY_IN and link_rx_ready(i);
+
-- Status signals
- STATUS_OUT(i * 8 + 7) <= '0'; -- unused
+ STATUS_OUT(i * 8 + 7) <= serdes_active(i); -- SerDes is operational
STATUS_OUT(i * 8 + 6) <= link_active(i); -- link is active
STATUS_OUT(i * 8 + 5) <= led_activity((i + 1) * 2 - 1); -- long LED signal for activity
STATUS_OUT(i * 8 + 4) <= pcs_rx_en(i); -- SerDes RX activity
STATUS_OUT(i * 8 + 3) <= pcs_tx_en(i); -- SerDes TX activity
- STATUS_OUT(i * 8 + 2) <= an_complete(i); -- GbE Autonegotiation completed
+ STATUS_OUT(i * 8 + 2) <= an_link_ok_i(i); -- GbE Autonegotiation completed
STATUS_OUT(i * 8 + 1) <= link_rx_ready(i); -- SerDes Rx channel operational
STATUS_OUT(i * 8 + 0) <= TX_LINK_READY_IN; -- SerDes Tx channel operational
INT_PORT_GEN: if (LINK_MODE(i) = c_IS_SLAVE) generate
- MAC_RX_DATA_OUT <= mac_rx_data((i + 1) * 8 - 1 downto i * 8);
+ MAC_RX_DATA_OUT <= mac_rx_data(i * 8 + 7 downto i * 8);
MAC_RX_WRITE_OUT <= mac_rx_wr(i);
MAC_RX_EOF_OUT <= mac_rx_eof(i);
MAC_RX_ERROR_OUT <= mac_rx_err(i);
CHANNEL_INACTIVE_GEN : if (LINK_MODE(i) = c_IS_UNUSED) generate
- DEBUG_OUT((i + 1) * 32 - 1 downto i * 32) <= (others => '0');
+ DEBUG_OUT(i * 32 + 31 downto i * 32) <= (others => '0');
powerup_ch(i) <= '0';
SD_TXDIS_OUT(i) <= '1';
LINK_ACTIVE_OUT(i) <= '0';
-- Status signals
- STATUS_OUT(i * 8 + 7) <= '0'; -- unused
- STATUS_OUT(i * 8 + 6) <= '0'; -- link is active
- STATUS_OUT(i * 8 + 5) <= '0'; -- long LED signal for activity
- STATUS_OUT(i * 8 + 4) <= '0'; -- SerDes RX activity
- STATUS_OUT(i * 8 + 3) <= '0'; -- SerDes TX activity
- STATUS_OUT(i * 8 + 2) <= '0'; -- GbE Autonegotiation completed
- STATUS_OUT(i * 8 + 1) <= '0'; -- SerDes Rx channel operational
- STATUS_OUT(i * 8 + 0) <= '0'; -- SerDes Tx channel operational
+ STATUS_OUT(i * 8 + 7) <= '0'; -- SerDes is operational
+ STATUS_OUT(i * 8 + 6) <= '0'; -- link is active
+ STATUS_OUT(i * 8 + 5) <= '0'; -- long LED signal for activity
+ STATUS_OUT(i * 8 + 4) <= '0'; -- SerDes RX activity
+ STATUS_OUT(i * 8 + 3) <= '0'; -- SerDes TX activity
+ STATUS_OUT(i * 8 + 2) <= '0'; -- GbE Autonegotiation completed
+ STATUS_OUT(i * 8 + 1) <= '0'; -- SerDes Rx channel operational
+ STATUS_OUT(i * 8 + 0) <= '0'; -- SerDes Tx channel operational
end generate CHANNEL_INACTIVE_GEN;
end generate CHANNEL_GEN;
--- THE_LED_TIMER_PROC: process( CLK_125 )
THE_LED_TIMER_PROC: process( MASTER_CLK_IN )
begin
--- if( rising_edge(CLK_125) ) then
if( rising_edge(MASTER_CLK_IN) ) then
led_timer_done <= led_timer_done_x;
led_timer <= led_timer + 1;
led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
end architecture gbe_med_fifo_arch;
+
+-- -- Debug signals, MSB to LSB
+-- DEBUG_OUT((i + 1) * 32 - 1) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 2) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 3) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 4) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 5) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 6) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 7) <= '0';
+-- DEBUG_OUT((i + 1) * 32 - 8) <= an_link_ok_i(i);
+-- DEBUG_OUT((i + 1) * 32 - 9) <= is_wap_zero(i);
+-- DEBUG_OUT((i + 1) * 32 - 10) <= sci_read_i;
+-- DEBUG_OUT((i + 1) * 32 - 11) <= tx_clk_avail_i;
+-- DEBUG_OUT((i + 1) * 32 - 12) <= link_active(i);
+-- DEBUG_OUT((i + 1) * 32 - 13) <= an_complete(i);
+-- DEBUG_OUT((i + 1) * 32 - 14) <= cfg_rx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 15) <= idle_rx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 16) <= unknown_rx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 17) <= cfg_tx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 18) <= idle_tx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 19) <= unknown_tx_int(i);
+-- DEBUG_OUT((i + 1) * 32 - 20) <= TX_LINK_READY_IN;
+-- DEBUG_OUT((i + 1) * 32 - 21) <= link_rx_ready(i);
+-- DEBUG_OUT((i + 1) * 32 - 22) <= rx_serdes_rst(i);
+-- DEBUG_OUT((i + 1) * 32 - 23) <= rx_pcs_rst(i);
+-- DEBUG_OUT((i + 1) * 32 - 24) <= sd_rx_disp_error(i);
+-- DEBUG_OUT((i + 1) * 32 - 25) <= sd_rx_cv_error(i);
+-- DEBUG_OUT((i + 1) * 32 - 26) <= lsm_status(i);
+-- DEBUG_OUT((i + 1) * 32 - 27) <= rx_los_low(i);
+-- DEBUG_OUT((i + 1) * 32 - 28) <= rx_cdr_lol(i);
+-- DEBUG_OUT((i + 1) * 32 - 29) <= TX_PCS_RST_IN;
+-- DEBUG_OUT((i + 1) * 32 - 30) <= tx_plol_lol;
+-- DEBUG_OUT((i + 1) * 32 - 31) <= RESET;
+-- DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR;
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