--- /dev/null
+../../trb3/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+-- use GBE
+ constant INCLUDE_GBE : integer := c_YES;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 1; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 1; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - fine time + (if 0x3ff full chain)
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F350";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"80";
+
+ constant INCLUDE_UART : integer := c_YES; --300 slices
+ constant INCLUDE_SPI : integer := c_YES; --300 slices
+ constant INCLUDE_LCD : integer := c_NO; --800 slices
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2
+ constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 32;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+ --t(16 downto 16) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --data via GbE
+ --t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+ t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-85F',
+Package => 'CABGA756',
+Speedgrade => '8',
+
+
+TOPNAME => "trb5sc_gbe",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
+synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
+
+nodelist_file => '../nodelist_frankfurt.txt',
+pinout_file => 'trb5sc_gbe',
+par_options => '../par.p2t',
+
+
+#Include only necessary lpf files
+include_TDC => 1,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-85F',
+Package => 'CABGA756',
+Speedgrade => '8',
+
+
+TOPNAME => "trb5sc_gbe",
+lm_license_file_for_synplify => "27000\@lxcad03.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.10_x64/',
+synplify_path => '/opt/synplicity/O-2018.09-SP1/',#K-2015.09',
+#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
+
+nodelist_file => 'nodes_gsi_template.txt',
+pinout_file => 'trb5sc_gbe',
+par_options => '../par.p2t',
+
+
+#pinout_file => 'trb3sc_richSensor',
+
+#Include only necessary lpf files
+include_TDC => 0,
+include_GBE => 1,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+#!/usr/bin/env perl
+
+# small straight-forward program to create a diamond project based on the standard trb3 project structure
+# execute the script with the current project as working directory. if existing the current project may be altered.
+# take care !
+
+
+use strict;
+use warnings;
+use Data::Dumper;
+use File::Copy;
+use Term::ANSIColor;
+use Cwd 'abs_path';
+
+sub parsePRJ {
+ my $input = shift;
+ my $options = {};
+ my @files = ();
+
+ open FH, "<" , $input;
+ while (my $line = <FH>) {
+ chomp $line;
+ if ($line =~ m/^\s*set_option -([^\s]+)\s+"?([^"]+)"?\s*$/) {
+ $options->{$1} = $2;
+ }
+
+ if ($line =~ m/^\s*add_file -(vhdl|verilog|fpga_constraint)( -lib "?([^"\s]+)"?|)? "?([^"]+)"?\s*$/g) {
+ push @files, [$3, $4];
+ }
+
+
+ }
+
+ close FH;
+
+ return ($options, \@files);
+}
+
+sub generateLDF {
+ my $prj_file = shift;
+ my $options = shift;
+ my $files = shift;
+
+ my $path = '../';
+
+ open FH, ">", $prj_file;
+
+ my $device = $options->{'part'} . $options->{'speed_grade'} . $options->{'package'};
+ $device =~ s/_/\-/g;
+
+ my $prj_title = $options->{'top_module'};
+ $prj_title =~ s/trb3_(central|periph)_(.+)/$2/;
+
+ my $def_impl = $options->{'top_module'};
+
+ my $inclPath = $options->{'include_path'};
+ $inclPath = '' if (!$inclPath);
+ $inclPath =~ s/\{(.*)\}$/$1/;
+ #$inclPath = abs_path($inclPath) if ($inclPath);
+
+ print FH "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n";
+ print FH "<BaliProject version=\"3.2\" title=\"$prj_title\" device=\"$device\" default_implementation=\"$def_impl\">\n";
+ print FH " <Options/>\n";
+ print FH " <Implementation title=\"$def_impl\" dir=\"$def_impl\" description=\"Automatically generated implemenatation\" default_strategy=\"Strategy1\">\n";
+ print FH " <Options def_top=\"$def_impl\">\n";
+ print FH " <Option name=\"include path\" value=\"$path$inclPath\" />\n" if ($inclPath);
+ print FH " <Option name=\"top\" value=\"$def_impl\" />\n";
+ print FH " </Options>\n";
+
+
+ my $lpf_included = 0;
+
+ for my $filer (@{$files}) {
+ my $file = $filer->[1];
+ my $lib = $filer->[0];
+ my $suffix = $file;
+ my $fpath = $path . $file;
+ $suffix =~ s/^.*\.([^.]+)$/$1/g;
+ if ("vhd" eq $suffix) {
+ print FH " <Source name=\"$fpath\" type=\"VHDL\" type_short=\"VHDL\"><Options " . ($lib? " lib=\"$lib\"":'') . " /></Source>\n";
+ } elsif ("v" eq $suffix) {
+ print FH " <Source name=\"$fpath\" type=\"Verilog\" type_short=\"Verilog\"><Options " . ($lib? " lib=\"$lib\"":'') . " /></Source>\n";
+ } elsif ("lpf" eq $suffix) {
+ print FH " <Source name=\"$fpath\" type=\"Logic Preference\" type_short=\"LPF\"><Options/></Source>\n";
+ $lpf_included = 1;
+ } elsif ("fdc" eq $suffix) {
+ print FH " <Source name=\"$fpath\" type=\"Synplify Design Constraints File\" type_short=\"SDC\"><Options/></Source>\n";
+ } else {
+ print "WARNING: Could not determine type of input file $file. Not included!\n";
+ }
+ }
+
+ print FH " </Implementation>\n";
+ print FH " <Strategy name=\"Strategy1\" file=\"auto_strat.sty\"/>\n";
+ print FH "</BaliProject>\n";
+
+ close FH;
+
+ if (!$lpf_included) {
+ print color "red bold";
+ print "WARNING: No lpf included. You won't be able to load this project with diamond. Check your compile_constraints.pl script!\n";
+ print color "reset";
+ }
+}
+
+sub generateSTY {
+ my $file = shift;
+ open FH, ">", $file;
+ print FH <<STY
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+ <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+ <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+ <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+ <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+ <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+ <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+ <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+ <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+ <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+ <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+ <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+ <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+ <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+ <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+ <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+ <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+ <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+ <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+ <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+ <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+ <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+ <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+ <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+ <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+ <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+ <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+ <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+ <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+ <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+ <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+ <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+ <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+ <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+ <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+ <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+ <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+ <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+ <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+ <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+ <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+ <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+ <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+ <Property name="PROP_LST_PrfOutput" value="False" time="0"/>
+ <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+ <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+ <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+ <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+ <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+ <Property name="PROP_LST_UseIOReg" value="True" time="0"/>
+ <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+ <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+ <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+ <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+ <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+ <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+ <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+ <Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/>
+ <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+ <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+ <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+ <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+ <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+ <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
+ <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+ <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+ <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+ <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+ <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+ <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+ <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+ <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+ <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+ <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+ <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+ <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+ <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+ <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+ <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+ <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+ <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+ <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+ <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+ <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+ <Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/>
+ <Property name="PROP_PAR_ParMatchFact" value="" time="0"/>
+ <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+ <Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/>
+ <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+ <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+ <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+ <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+ <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+ <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+ <Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
+ <Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
+ <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+ <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+ <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+ <Property name="PROP_PAR_parHold" value="Off" time="0"/>
+ <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+ <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+ <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+ <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+ <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+ <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+ <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+ <Property name="PROP_PRE_VSynOutPref" value="False" time="0"/>
+ <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+ <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+ <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+ <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+ <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+ <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+ <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+ <Property name="PROP_SYN_EdfFanout" value="100" time="0"/>
+ <Property name="PROP_SYN_EdfFixGateClocks" value="3" time="0"/>
+ <Property name="PROP_SYN_EdfFixGeneratedClocks" value="3" time="0"/>
+ <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
+ <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfInPrfWrite" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+ <Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
+ <Property name="PROP_SYN_EdfNumStartEnd" value="0" time="0"/>
+ <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+ <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfRunRetiming" value="None" time="0"/>
+ <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfUnconsClk" value="True" time="0"/>
+ <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+ <Property name="PROP_SYN_ResolvedMixedDrivers" value="True" time="0"/>
+ <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+ <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+ <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+ <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+ <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+ <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+ <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+ <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+ <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+ <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+</Strategy>
+STY
+;
+ close FH;
+}
+
+# Search project file
+ my @prj_files = glob('*.prj');
+ die "No .prj found? Is the current working dir the project root?" if 0 == scalar @prj_files;
+ die "Multiple prj-files found. This is not supported by this tool." if 1 < scalar @prj_files;
+ my $input = shift @prj_files;
+
+ print "NOTE: Use $input as input file\n";
+
+# parse PRJ file
+ my ($options, $files) = parsePRJ $input;
+
+# create dir if necessary
+ mkdir 'project' unless (-e 'project');
+
+# create workdir
+ if (-e './compile_constraints.pl') {
+ my $workdir = 'project/' . $options->{'top_module'};
+ my $lpffile = $workdir . '/' . $options->{'top_module'} . ".lpf";
+
+ print "NOTE: execute ./compile_constraints.pl $workdir\n";
+ system "./compile_constraints.pl $workdir";
+
+ if(-e $lpffile) {
+ rename $lpffile, 'project/' . $options->{'top_module'} . '.lpf';
+ push @$files, ['work', 'project/' . $options->{'top_module'} . '.lpf'];
+ } else {
+ print "WARNING: compile_constraints did not generate $lpffile. Please include the necessary contraint files manually\n";
+ }
+ } else {
+ print "No ./compile_constraints.pl script found. Please make sure, the workdir contains all links and constraint-files\n";
+ }
+
+# generate ldf
+ my $project_file = 'project/' . $options->{'top_module'} . '.ldf';
+ if (-e $project_file) {move $project_file, $project_file . '.backup'};
+ generateLDF $project_file, $options, $files;
+ print "NOTE: LDF generated\n";
+
+# generate strategy file
+ unless (-e 'project/auto_strat.sty') {
+ generateSTY 'project/auto_strat.sty';
+ print "NOTE: STY generated\n";
+ }
+
+
+
+print "\nNOTE: The version.vhd file is neither generated nor updated when building in diamond.\n";
+print "\nUse command-line compilation to create a version file.\n";
+print "\nDone. Execute \n> diamond $project_file\nto open the project\n";
--- /dev/null
+-w
+#-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 10
+-t 11
+-c 2
+-e 2
+-i 10
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
--- /dev/null
+../../tdc/releases/tdc_v2.3/
\ No newline at end of file
--- /dev/null
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+FREQUENCY PORT CLK_200 200 MHz;
+FREQUENCY PORT CLK_125 125 MHz;
+FREQUENCY PORT CLK_EXT 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
+
+FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
+
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
+BLOCK PATH TO PORT "TEST_LINE*";
+
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+GSR_NET NET "clear_i";
+
+# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+
+
+REGION "MEDIA" "R81C44D" 13 25;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_gbe"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_gbe.edf"
+set_option log_file "workdir/trb5sc_project.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+#add_file -vhdl -lib work "./project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+
+#channel 1, SFP
+add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
+add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+add_file -vhdl -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
+add_file -verilog -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+##########################################
+
+add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd"
+#add_file -vhdl -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" #200MHz
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/pcs_sync_reset.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd"
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_pcs.v"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_gbe_pcs35.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v"
+#add_file -verilog -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"#200MHz
+#add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/tsmac35.v"
+#add_file -vhdl -lib work "/opt/lattice/diamond/3.10_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#GbE ExtRefClk
+#add_file -vhdl -lib work "./project/GbePcsExtrefclk/GbePcsExtrefclk.vhd"
+#add_file -vhdl -lib work "./project/GbePcsExtrefclk/extref/extref.vhd"
+#add_file -vhdl -lib work "./project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
+#END GbE ExtRefClk
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+##end GbE
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
+
+add_file -vhdl -lib work "./project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+
+add_file -vhdl -lib work "./trb5sc_gbe.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+--use work.ecp5um.all;
+
+entity trb5sc_gbe is
+ port(
+ CLK_200 : in std_logic;
+ CLK_125 : in std_logic;
+ CLK_EXT : in std_logic;
+
+ TRIG_IN_BACKPL : in std_logic; --Reference Time
+ TRIG_IN_RJ45 : in std_logic; --Reference Time
+ IN_SELECT_EXT_CLOCK : in std_logic;
+
+ SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3
+ BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1
+
+ SFP_TX_DIS : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_MOD_0 : in std_logic;
+
+ SFP_ADD_TX_DIS : out std_logic;
+ SFP_ADD_LOS : in std_logic;
+ SFP_ADD_MOD0 : in std_logic;
+
+ --FE_GPIO : inout std_logic_vector(11 downto 0);
+ --FE_CLK : out std_logic_vector( 2 downto 1);
+ --FE_DIFF : inout std_logic_vector(63 downto 0);
+ INP : inout std_logic_vector(63 downto 0);
+
+ --ADC
+ ADC_SCLK : out std_logic;
+ ADC_NCS : out std_logic;
+ ADC_MOSI : out std_logic;
+ ADC_MISO : in std_logic;
+ --Flash, Reload
+ FLASH_SCLK : out std_logic;
+ FLASH_NCS : out std_logic;
+ FLASH_MOSI : out std_logic;
+ FLASH_MISO : in std_logic;
+ FLASH_HOLD : out std_logic;
+ FLASH_WP : out std_logic;
+ PROGRAMN : out std_logic;
+ --I2C
+ I2C_SDA : inout std_logic;
+ I2C_SCL : inout std_logic;
+ TMP_ALERT : in std_logic;
+
+ --LED
+ LED : out std_logic_vector(8 downto 1);
+ LED_SFP_YELLOW : out std_logic;
+ LED_SFP_GREEN : out std_logic;
+ LED_SFP_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);
+ LED_RJ_RED : out std_logic_vector(1 downto 0);
+ LED_EXT_CLOCK : out std_logic;
+
+ --Other Connectors
+ TEST : inout std_logic_vector(14 downto 1);
+ HDR_IO : inout std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_NCS : signal is true;
+ attribute syn_useioff of FLASH_SCLK : signal is true;
+ attribute syn_useioff of FLASH_MOSI : signal is true;
+ attribute syn_useioff of FLASH_MISO : signal is true;
+
+
+end entity;
+
+architecture arch of trb5sc_gbe is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+ signal trigger_in_i : std_logic;
+
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+ signal debug_tools : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;
+
+
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 0);
+
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , busgbeip_tx, busgbereg_tx, busscigbe_tx, busmeddbg_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busgbeip_rx, busgbereg_rx, busscigbe_rx, busmeddbg_rx : CTRLBUS_RX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal clock_select : std_logic;
+ signal bus_master_active : std_logic;
+ signal flash_clk_i : std_logic;
+
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+ signal header_io_i : std_logic_vector(10 downto 1);
+ signal timer : TIMERS;
+ signal led_off : std_logic;
+ --TDC
+ signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1);
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
+
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ signal link_stat_in_reg : std_logic;
+
+ signal gbe_cts_number : std_logic_vector(15 downto 0);
+ signal gbe_cts_code : std_logic_vector( 7 downto 0);
+ signal gbe_cts_information : std_logic_vector( 7 downto 0);
+ signal gbe_cts_readout_type : std_logic_vector( 3 downto 0);
+ signal gbe_cts_start_readout : std_logic;
+ signal gbe_cts_readout_finished : std_logic;
+ signal gbe_cts_status_bits : std_logic_vector(31 downto 0);
+
+ signal gbe_fee_data : std_logic_vector(15 downto 0);
+ signal gbe_fee_dataready : std_logic;
+ signal gbe_fee_read : std_logic;
+ signal gbe_fee_status_bits : std_logic_vector(31 downto 0);
+ signal gbe_fee_busy : std_logic;
+
+ signal reboot_from_gbe : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_init_packet_num : std_logic_vector( 2 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector( 2 downto 0);
+ signal gsc_reply_read : std_logic;
+ signal gsc_busy : std_logic;
+ signal reset_via_gbe : std_logic;
+
+ signal debug_media : std_logic_vector(255 downto 0);
+
+ signal pll125_lock, clk_125_pll : std_logic;
+begin
+
+trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);
+
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ CLOCK_IN => CLK_200,
+ RESET_FROM_NET => med2int(0).stat_op(13),
+ SEND_RESET_IN => med2int(0).stat_op(15),
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ REF_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ RAW_CLK_OUT => clk_full_osc,
+
+ DEBUG_OUT => debug_clock_reset
+ );
+
+
+
+-- THE_CAL_PLL : entity work.pll_in125_out125_out33
+-- port map(
+-- CLKI => CLK_125,
+-- --CLKOP => clk_cal
+-- CLKOP => clk_125_pll,
+-- CLKOS => clk_cal,
+-- LOCK => pll125_lock
+-- );
+
+
+---------------------------------------------------------------------------
+-- GbE
+---------------------------------------------------------------------------
+ GBE : entity work.gbe_wrapper
+ generic map(
+ DO_SIMULATION => 0,
+ INCLUDE_DEBUG => 0,
+ USE_INTERNAL_TRBNET_DUMMY => 0,
+ USE_EXTERNAL_TRBNET_DUMMY => 0,
+ RX_PATH_ENABLE => 1,
+ FIXED_SIZE_MODE => 1,
+ INCREMENTAL_MODE => 1,
+ FIXED_SIZE => 100,
+ FIXED_DELAY_MODE => 1,
+ UP_DOWN_MODE => 0,
+ UP_DOWN_LIMIT => 100,
+ FIXED_DELAY => 100,
+
+ NUMBER_OF_GBE_LINKS => 4,
+ LINKS_ACTIVE => "0001",
+
+ LINK_HAS_READOUT => "0001",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001",
+ LINK_HAS_FWD => "0000"
+ )
+
+ port map(
+ CLK_SYS_IN => clk_sys,
+ CLK_125_IN => CLK_EXT,--CLK_125,--CLK_125,
+ -- CLK_200_IN => CLK_EXT,
+ RESET => reset_i,
+ GSR_N => GSR_N,
+
+ TRIGGER_IN => '0',
+
+ SD_PRSNT_N_IN(0) => SFP_ADD_MOD0,
+ --SD_PRSNT_N_IN(3 downto 1)=> "111",
+ SD_LOS_IN(0) => SFP_ADD_LOS,
+ --SD_LOS_IN(3 downto 1) => "111",
+ SD_TXDIS_OUT(0) => SFP_ADD_TX_DIS,
+ --SD_TXDIS_OUT(3 downto 1) => open,
+ CTS_NUMBER_IN => gbe_cts_number,
+ CTS_CODE_IN => gbe_cts_code,
+ CTS_INFORMATION_IN => gbe_cts_information,
+ CTS_READOUT_TYPE_IN => gbe_cts_readout_type,
+ CTS_START_READOUT_IN => gbe_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
+
+ FEE_DATA_IN => gbe_fee_data,
+ FEE_DATAREADY_IN => gbe_fee_dataready,
+ FEE_READ_OUT => gbe_fee_read,
+ FEE_STATUS_BITS_IN => gbe_fee_status_bits,
+ FEE_BUSY_IN => gbe_fee_busy,
+
+ MC_UNIQUE_ID_IN => timer.uid,
+ MY_TRBNET_ADDRESS_IN => timer.network_address,
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+ BUS_SCI_RX => busscigbe_rx,
+ BUS_SCI_TX => busscigbe_tx,
+
+ MAKE_RESET_OUT => reset_via_gbe,
+
+ DEBUG_OUT => open,
+
+ DEBUG_media => debug_media
+ );
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
+ generic map(
+ SERDES_NUM => 0,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => sfp_prsnt_i,
+ SD_LOS_IN => sfp_los_i,
+ SD_TXDIS_OUT => sfp_txdis_i,
+ --Control Interface
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+ gen_sfp_con : if SERDES_NUM = 1 generate
+ sfp_los_i <= SFP_LOS;
+ sfp_prsnt_i <= SFP_MOD_0;
+ SFP_TX_DIS <= sfp_txdis_i;
+ end generate;
+ gen_bpl_con : if SERDES_NUM = 0 generate
+ sfp_los_i <= BACK_GPIO(1);
+ sfp_prsnt_i <= BACK_GPIO(1);
+ BACK_GPIO(0) <= sfp_txdis_i;
+ end generate;
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
+ generic map (
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
+
+ --Slow Control Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+
+ ONEWIRE_INOUT => open,
+ I2C_SCL => I2C_SCL,
+ I2C_SDA => I2C_SDA,
+ --Timing registers
+ TIMERS_OUT => timer
+ );
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 8,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"8100", 5 => x"8300", 6 => x"e000", 7 => x"b200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 12, 7 => 9, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => bustdc_rx,
+ BUS_RX(4) => busgbeip_rx,
+ BUS_RX(5) => busgbereg_rx,
+ BUS_RX(6) => busmeddbg_rx,
+ BUS_RX(7) => busscigbe_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => bustdc_tx,
+ BUS_TX(4) => busgbeip_tx,
+ BUS_TX(5) => busgbereg_tx,
+ BUS_TX(6) => busmeddbg_tx,
+ BUS_TX(7) => busscigbe_tx,
+
+ STAT_DEBUG => open
+ );
+
+
+--BUS Handler
+ proc_reg : process
+ begin
+ wait until rising_edge(clk_sys);
+ busmeddbg_tx.ack <= '0';
+ busmeddbg_tx.nack <= '0';
+ busmeddbg_tx.unknown <= '0';
+
+ if busmeddbg_rx.write = '1' then
+ busmeddbg_tx.ack <= '0';
+ busmeddbg_tx.unknown <= '1';
+ elsif busmeddbg_rx.read = '1' then
+ busmeddbg_tx.ack <= '1';
+ if busmeddbg_rx.addr(11 downto 0) = x"000" then
+ busmeddbg_tx.data <= debug_media(31 downto 0);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"001" then
+ busmeddbg_tx.data <= debug_media(63 downto 32);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"002" then
+ busmeddbg_tx.data <= debug_media(95 downto 64);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"003" then
+ busmeddbg_tx.data <= debug_media(127 downto 96);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"004" then
+ busmeddbg_tx.data <= debug_media(159 downto 128);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"005" then
+ busmeddbg_tx.data <= debug_media(191 downto 160);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"006" then
+ busmeddbg_tx.data <= debug_media(223 downto 192);
+ elsif busmeddbg_rx.addr(11 downto 0) = x"007" then
+ busmeddbg_tx.data(0) <= pll125_lock;--debug_media(255 downto 224);
+ busmeddbg_tx.data(31 downto 1) <= (others => '0');
+ else
+ busmeddbg_tx.ack <= '0';
+ busmeddbg_tx.unknown <= '1';
+ end if;
+
+ end if;
+ end process;
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_NCS,
+ FLASH_CLK => FLASH_SCLK,
+ FLASH_IN => FLASH_MISO,
+ FLASH_OUT => FLASH_MOSI,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ --Header
+ HEADER_IO => HDR_IO(9 downto 0),
+ ADDITIONAL_REG(0) => led_off,
+ --LCD
+ LCD_DATA_IN => (others => '0'),
+ --ADC
+ ADC_CS => ADC_NCS,
+ ADC_MOSI => ADC_MOSI,
+ ADC_MISO => ADC_MISO,
+ ADC_CLK => ADC_SCLK,
+ --Trigger & Monitor
+ MONITOR_INPUTS => monitor_inputs_i,
+ TRIG_GEN_INPUTS => trigger_inputs_i,
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => debug_tools
+ );
+
+
+
+ FLASH_HOLD <= '1';
+ FLASH_WP <= '1';
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+
+ monitor_inputs_i <= INP(MONITOR_INPUT_NUM-1 downto 0);
+ trigger_inputs_i <= INP(TRIG_GEN_INPUT_NUM-1 downto 0);
+ hit_in_i <= INP(NUM_TDC_CHANNELS-2 downto 0);
+
+ assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
+
+ HDR_IO(15 downto 10) <= (others => '0');
+ TEST(13 downto 1) <= (others => '0');
+ TEST(14) <= FLASH_NCS;
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+
+ LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
+ -- DEBUG GbE 0 = on; 1=off
+ LED(1) <= not debug_media( 3); -- tx_pll_lol
+ LED(2) <= not debug_media( 4); -- rx_cdr_lol
+ LED(3) <= not debug_media(10); -- an_link_ok
+ LED (8 downto 4) <= b"11111";
+ --
+ LED_RJ_GREEN <= FLASH_NCS & FLASH_NCS;
+ LED_RJ_RED <= "11";
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off;
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+--
+-- THE_TDC : entity work.TDC_record
+-- generic map (
+-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+-- STATUS_REG_NR => 21, -- Number of status regs
+-- DEBUG => c_NO,
+-- SIMULATION => c_NO)
+-- port map (
+-- RESET => reset_i,
+-- CLK_TDC => clk_full,
+-- CLK_READOUT => clk_sys, -- Clock for the readout
+-- REFERENCE_TIME => trigger_in_i, -- Reference time input
+-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+-- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+-- -- Trigger signals from handler
+-- BUSRDO_RX => readout_rx,
+-- BUSRDO_TX => readout_tx(0),
+-- -- Slow control bus
+-- BUS_RX => bustdc_rx,
+-- BUS_TX => bustdc_tx,
+-- -- Dubug signals
+-- INFO_IN => timer,
+-- LOGIC_ANALYSER_OUT => open
+-- );
+
+
+-------------------------------------------------------------------------------
+-- No trigger/data endpoint included
+-------------------------------------------------------------------------------
+readout_tx(0).data_finished <= '1';
+readout_tx(0).data_write <= '0';
+readout_tx(0).busy_release <= '1';
+
+end architecture;
+
+
+
--- /dev/null
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+
+SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
+BANK 0 VCCIO 2.5 V;
+BANK 1 VCCIO 2.5 V;
+BANK 2 VCCIO 2.5 V;
+BANK 3 VCCIO 2.5 V;
+BANK 4 VCCIO 3.3 V;
+BANK 6 VCCIO 2.5 V;
+BANK 7 VCCIO 2.5 V;
+BANK 8 VCCIO 3.3 V;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_125" SITE "AD1"; #was "OSC_CORE_125"
+LOCATE COMP "CLK_200" SITE "AD32"; #was "OSC_CORE_200"
+LOCATE COMP "CLK_EXT" SITE "C28"; #was "EXT_CLOCK"
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100;
+
+#####
+#LOCATE COMP "CLK_GbE_extRef_P" SITE "AM23";
+#IOBUF PORT "CLK_GbE_extRef_P" IO_TYPE=LVTTL33;
+#LOCATE COMP "CLK_GbE_extRef_N" SITE "AM24";
+#IOBUF PORT "CLK_GbE_extRef_N" IO_TYPE=LVTTL33;
+# LOCATE COMP "ENPIRION_CLOCK" SITE "AM31";
+# IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33;
+
+#################################################################
+# Trigger I/O
+#################################################################
+LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3";
+LOCATE COMP "TRIG_IN_RJ45" SITE "AC2";
+DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ;
+IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100;
+
+
+LOCATE COMP "SPARE_0" SITE "AC3";
+LOCATE COMP "SPARE_1" SITE "AB1";
+DEFINE PORT GROUP "SPARE_group" "SPARE*" ;
+IOBUF GROUP "SPARE_group" IO_TYPE=LVDS ;
+
+#################################################################
+# SFP
+#################################################################
+LOCATE COMP "SFP_TX_DIS" SITE "AH28";
+LOCATE COMP "SFP_LOS" SITE "AK29";
+LOCATE COMP "SFP_MOD_0" SITE "AG28";
+IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+
+# LOCATE COMP "SFP_RATE_SEL" SITE "AG30";
+# LOCATE COMP "SFP_TX_FAULT" SITE "AH30";
+# LOCATE COMP "SFP_MOD_1" SITE "AG29";
+# LOCATE COMP "SFP_MOD_2" SITE "AJ28";
+
+
+#################################################################
+# Frontend
+#################################################################
+LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0"
+LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1"
+LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2"
+LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3"
+LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4"
+LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5"
+LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6"
+LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7"
+DEFINE PORT GROUP "MISO_group" "MISO*" ;
+IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33;
+DEFINE PORT GROUP "CS_group" "CS*" ;
+IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25;
+
+
+LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8"
+LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9"
+LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10"
+LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11"
+IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ;
+
+# DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ;
+# IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1"
+LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2"
+IOBUF PORT "SCK" IO_TYPE=LVDS ;
+IOBUF PORT "MOSI" IO_TYPE=LVDS ;
+
+# DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ;
+# IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100;
+
+LOCATE COMP "INP_48" SITE "R29"; #"FE_DIFF[0]"
+LOCATE COMP "INP_49" SITE "T29"; #"FE_DIFF[1]"
+LOCATE COMP "INP_50" SITE "P31"; #"FE_DIFF[2]"
+LOCATE COMP "INP_51" SITE "R30"; #"FE_DIFF[3]"
+LOCATE COMP "INP_52" SITE "N32"; #"FE_DIFF[4]"
+LOCATE COMP "INP_53" SITE "U31"; #"FE_DIFF[5]"
+LOCATE COMP "INP_54" SITE "R32"; #"FE_DIFF[6]"
+LOCATE COMP "INP_55" SITE "W30"; #"FE_DIFF[7]"
+LOCATE COMP "INP_56" SITE "T32"; #"FE_DIFF[8]"
+LOCATE COMP "INP_57" SITE "V32"; #"FE_DIFF[9]"
+LOCATE COMP "INP_58" SITE "Y26"; #"FE_DIFF[10]"
+LOCATE COMP "INP_59" SITE "Y28"; #"FE_DIFF[11]"
+LOCATE COMP "INP_60" SITE "Y29"; #"FE_DIFF[12]"
+LOCATE COMP "INP_61" SITE "AB26"; #"FE_DIFF[13]"
+LOCATE COMP "INP_62" SITE "AB28"; #"FE_DIFF[14]"
+LOCATE COMP "INP_63" SITE "AC26"; #"FE_DIFF[15]"
+LOCATE COMP "INP_16" SITE "D29"; #"FE_DIFF[16]"
+LOCATE COMP "INP_17" SITE "F29"; #"FE_DIFF[17]"
+LOCATE COMP "INP_18" SITE "B32"; #"FE_DIFF[18]"
+LOCATE COMP "INP_19" SITE "D30"; #"FE_DIFF[19]"
+LOCATE COMP "INP_20" SITE "F30"; #"FE_DIFF[20]"
+LOCATE COMP "INP_21" SITE "C32"; #"FE_DIFF[21]"
+LOCATE COMP "INP_22" SITE "F31"; #"FE_DIFF[22]"
+LOCATE COMP "INP_23" SITE "F32"; #"FE_DIFF[23]"
+LOCATE COMP "INP_24" SITE "H31"; #"FE_DIFF[24]"
+LOCATE COMP "INP_25" SITE "J30"; #"FE_DIFF[25]"
+LOCATE COMP "INP_26" SITE "K31"; #"FE_DIFF[26]"
+LOCATE COMP "INP_27" SITE "K32"; #"FE_DIFF[27]"
+LOCATE COMP "INP_28" SITE "L31"; #"FE_DIFF[28]"
+LOCATE COMP "INP_29" SITE "J29"; #"FE_DIFF[29]"
+LOCATE COMP "INP_30" SITE "H27"; #"FE_DIFF[30]"
+LOCATE COMP "INP_31" SITE "K27"; #"FE_DIFF[31]"
+LOCATE COMP "INP_0" SITE "D4"; #"FE_DIFF[32]"
+LOCATE COMP "INP_1" SITE "F4"; #"FE_DIFF[33]"
+LOCATE COMP "INP_2" SITE "B1"; #"FE_DIFF[34]"
+LOCATE COMP "INP_3" SITE "D3"; #"FE_DIFF[35]"
+LOCATE COMP "INP_4" SITE "F3"; #"FE_DIFF[36]"
+LOCATE COMP "INP_5" SITE "C1"; #"FE_DIFF[37]"
+LOCATE COMP "INP_6" SITE "F2"; #"FE_DIFF[38]"
+LOCATE COMP "INP_7" SITE "F1"; #"FE_DIFF[39]"
+LOCATE COMP "INP_8" SITE "H2"; #"FE_DIFF[40]"
+LOCATE COMP "INP_9" SITE "J3"; #"FE_DIFF[41]"
+LOCATE COMP "INP_10" SITE "K2"; #"FE_DIFF[42]"
+LOCATE COMP "INP_11" SITE "K1"; #"FE_DIFF[43]"
+LOCATE COMP "INP_12" SITE "L2"; #"FE_DIFF[44]"
+LOCATE COMP "INP_13" SITE "J4"; #"FE_DIFF[45]"
+LOCATE COMP "INP_14" SITE "H6"; #"FE_DIFF[46]"
+LOCATE COMP "INP_15" SITE "K6"; #"FE_DIFF[47]"
+LOCATE COMP "INP_32" SITE "R4"; #"FE_DIFF[48]"
+LOCATE COMP "INP_33" SITE "T4"; #"FE_DIFF[49]"
+LOCATE COMP "INP_34" SITE "P2"; #"FE_DIFF[50]"
+LOCATE COMP "INP_35" SITE "R3"; #"FE_DIFF[51]"
+LOCATE COMP "INP_36" SITE "N1"; #"FE_DIFF[52]"
+LOCATE COMP "INP_37" SITE "U2"; #"FE_DIFF[53]"
+LOCATE COMP "INP_38" SITE "R1"; #"FE_DIFF[54]"
+LOCATE COMP "INP_39" SITE "W3"; #"FE_DIFF[55]"
+LOCATE COMP "INP_40" SITE "T1"; #"FE_DIFF[56]"
+LOCATE COMP "INP_41" SITE "V1"; #"FE_DIFF[57]"
+LOCATE COMP "INP_42" SITE "Y7"; #"FE_DIFF[58]"
+LOCATE COMP "INP_43" SITE "Y5"; #"FE_DIFF[59]"
+LOCATE COMP "INP_44" SITE "Y4"; #"FE_DIFF[60]"
+LOCATE COMP "INP_45" SITE "AB7"; #"FE_DIFF[61]"
+LOCATE COMP "INP_46" SITE "AB5"; #"FE_DIFF[62]"
+LOCATE COMP "INP_47" SITE "AC7"; #"FE_DIFF[63]"
+
+DEFINE PORT GROUP "INP_group" "INP*" ;
+IOBUF GROUP "INP_group" IO_TYPE=LVDS DIFFRESISTOR=100;
+
+
+
+#################################################################
+# Temperature, Flash & ID
+#################################################################
+LOCATE COMP "I2C_SDA" SITE "A11";
+LOCATE COMP "I2C_SCL" SITE "B11";
+LOCATE COMP "TMP_ALERT" SITE "C11";
+IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ;
+
+
+LOCATE COMP "PROGRAMN" SITE "AH1";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+
+
+LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16";
+IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ;
+
+
+LOCATE COMP "FLASH_HOLD" SITE "AL1";
+LOCATE COMP "FLASH_MISO" SITE "AJ2";
+LOCATE COMP "FLASH_MOSI" SITE "AK2";
+LOCATE COMP "FLASH_NCS" SITE "AJ3";
+LOCATE COMP "FLASH_SCLK" SITE "AJ1";
+LOCATE COMP "FLASH_WP" SITE "AM2";
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE;
+
+
+LOCATE COMP "ADC_MISO" SITE "AK3";
+LOCATE COMP "ADC_MOSI" SITE "AL3";
+LOCATE COMP "ADC_NCS" SITE "AH3";
+LOCATE COMP "ADC_SCLK" SITE "AG3";
+IOBUF PORT "ADC_SCLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;
+IOBUF PORT "ADC_NCS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;
+IOBUF PORT "ADC_MOSI" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;
+IOBUF PORT "ADC_MISO" IO_TYPE=LVTTL33 PULLMODE=UP ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_SFP_YELLOW" SITE "AG32";
+LOCATE COMP "LED_SFP_GREEN" SITE "AK30";
+LOCATE COMP "LED_SFP_RED" SITE "AH32";
+DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ;
+IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ;
+
+LOCATE COMP "LED_1" SITE "A26";
+LOCATE COMP "LED_2" SITE "B26";
+LOCATE COMP "LED_3" SITE "A28";
+LOCATE COMP "LED_4" SITE "A29";
+LOCATE COMP "LED_5" SITE "A30";
+LOCATE COMP "LED_6" SITE "A31";
+LOCATE COMP "LED_7" SITE "B29";
+LOCATE COMP "LED_8" SITE "B30";
+IOBUF PORT "LED_1" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_2" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_3" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_4" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_5" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_6" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_7" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED_8" IO_TYPE=LVCMOS25 ;
+
+
+LOCATE COMP "LED_RJ_GREEN_0" SITE "AK32";
+LOCATE COMP "LED_RJ_RED_0" SITE "AJ32";
+LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30";
+LOCATE COMP "LED_RJ_GREEN_1" SITE "AM30";
+LOCATE COMP "LED_RJ_RED_1" SITE "AL30";
+IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVTTL33 ;
+
+#################################################################
+# Test & Other IO
+#################################################################
+LOCATE COMP "TEST_1" SITE "A7";
+LOCATE COMP "TEST_2" SITE "A5";
+LOCATE COMP "TEST_3" SITE "A4";
+LOCATE COMP "TEST_4" SITE "A3";
+LOCATE COMP "TEST_5" SITE "A2";
+LOCATE COMP "TEST_6" SITE "B3";
+LOCATE COMP "TEST_7" SITE "B4";
+LOCATE COMP "TEST_8" SITE "B7";
+LOCATE COMP "TEST_9" SITE "C7";
+LOCATE COMP "TEST_10" SITE "C8";
+LOCATE COMP "TEST_11" SITE "D7";
+LOCATE COMP "TEST_12" SITE "D8";
+LOCATE COMP "TEST_13" SITE "E8";
+LOCATE COMP "TEST_14" SITE "F8";
+DEFINE PORT GROUP "TEST_group" "TEST*" ;
+IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8;
+
+
+LOCATE COMP "HDR_IO_0" SITE "A23";
+LOCATE COMP "HDR_IO_1" SITE "A22";
+LOCATE COMP "HDR_IO_2" SITE "B22";
+LOCATE COMP "HDR_IO_3" SITE "A24";
+LOCATE COMP "HDR_IO_4" SITE "C23";
+LOCATE COMP "HDR_IO_5" SITE "B23";
+LOCATE COMP "HDR_IO_6" SITE "C22";
+LOCATE COMP "HDR_IO_7" SITE "C24";
+LOCATE COMP "HDR_IO_8" SITE "D23";
+LOCATE COMP "HDR_IO_9" SITE "D24";
+LOCATE COMP "HDR_IO_10" SITE "E23";
+LOCATE COMP "HDR_IO_11" SITE "D22";
+LOCATE COMP "HDR_IO_12" SITE "F23";
+LOCATE COMP "HDR_IO_13" SITE "E22";
+LOCATE COMP "HDR_IO_14" SITE "F20";
+LOCATE COMP "HDR_IO_15" SITE "F22";
+DEFINE PORT GROUP "HDR_group" "HDR*" ;
+IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
+
+
+LOCATE COMP "BACK_GPIO_0" SITE "P28";
+LOCATE COMP "BACK_GPIO_1" SITE "P29";
+LOCATE COMP "BACK_GPIO_2" SITE "R27";
+LOCATE COMP "BACK_GPIO_3" SITE "T27";
+DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ;
+IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
jspc29 / trb5sc.git / commitdiff