signal stat_errorbits_ready : std_logic;
signal stat_errorbits_unknown : std_logic;
+ signal stat_busycntincl_addr : std_logic_vector(3 downto 0);
+ signal stat_busycntincl_read : std_logic;
+ signal stat_busycntincl_write : std_logic;
+ signal stat_busycntincl_data : std_logic_vector(31 downto 0);
+ signal stat_busycntincl_ready : std_logic;
+ signal stat_busycntincl_ack : std_logic;
+ signal stat_busycntincl_unknown : std_logic;
+
+ signal stat_busycntexcl_addr : std_logic_vector(3 downto 0);
+ signal stat_busycntexcl_read : std_logic;
+ signal stat_busycntexcl_write : std_logic;
+ signal stat_busycntexcl_data : std_logic_vector(31 downto 0);
+ signal stat_busycntexcl_ready : std_logic;
+ signal stat_busycntexcl_ack : std_logic;
+ signal stat_busycntexcl_unknown : std_logic;
+
+ signal stat_globaltime_read : std_logic;
+ signal stat_globaltime_write : std_logic;
+ signal last_stat_globaltime_read : std_logic;
+ signal last_stat_globaltime_write: std_logic;
+
signal iobuf_ctrl_stat : std_logic_vector(63 downto 0);
signal iobuf_reset_ipu_counter : std_logic;
signal iobuf_reset_sctrl_counter : std_logic;
+ type cnt_t is array (MII_NUMBER-1 downto 0) of unsigned(31 downto 0);
+ signal busy_counter_excl : cnt_t;
+ signal busy_counter_incl : cnt_t;
+ signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER-1 downto 0);
+ signal reg_excl_enable : std_logic_vector(MII_NUMBER-1 downto 0);
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_preserve of m_DATA_IN : signal is true;
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", others => x"0000"),
- PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, others => 0)
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, others => 0)
)
port map(
- CLK => CLK,
- RESET => reset_i,
-
- DAT_ADDR_IN => DAT_ADDR_OUT,
- DAT_DATA_IN => DAT_DATA_OUT,
- DAT_DATA_OUT => DAT_DATA_IN,
- DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
- DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
- DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
- DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
- DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
- DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
-
- BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
- BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
- BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
- BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
- BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
- BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
- BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
- BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
- BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
- BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
-
- BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
- BUS_ADDR_OUT(31 downto 21) => open,
- BUS_DATA_OUT(63 downto 32) => open,
- BUS_READ_ENABLE_OUT(1) => stat_packets_read,
- BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(63 downto 32) => stat_packets_data,
- BUS_DATAREADY_IN(1) => stat_packets_ready,
- BUS_WRITE_ACK_IN(1) => stat_packets_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
-
- BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
- BUS_ADDR_OUT(47 downto 36) => open,
- BUS_DATA_OUT(95 downto 64) => open,
- BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
- BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
- BUS_DATAREADY_IN(2) => stat_errorbits_ready,
- BUS_WRITE_ACK_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
+ CLK => CLK,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => DAT_ADDR_OUT,
+ DAT_DATA_IN => DAT_DATA_OUT,
+ DAT_DATA_OUT => DAT_DATA_IN,
+ DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
+ DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
+ DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
+ DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
+ DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
+ DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
+ DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
+
+ BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
+ BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
+ BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
+ BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
+ BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
+ BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
+ BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
+ BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
+ BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
+
+ BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
+ BUS_ADDR_OUT(31 downto 21) => open,
+ BUS_DATA_OUT(63 downto 32) => open,
+ BUS_READ_ENABLE_OUT(1) => stat_packets_read,
+ BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(63 downto 32) => stat_packets_data,
+ BUS_DATAREADY_IN(1) => stat_packets_ready,
+ BUS_WRITE_ACK_IN(1) => stat_packets_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
+
+ BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
+ BUS_ADDR_OUT(47 downto 36) => open,
+ BUS_DATA_OUT(95 downto 64) => open,
+ BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
+ BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
+ BUS_DATAREADY_IN(2) => stat_errorbits_ready,
+ BUS_WRITE_ACK_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
+
+ BUS_ADDR_OUT(51 downto 48) => stat_busycntincl_addr,
+ BUS_ADDR_OUT(63 downto 52) => open,
+ BUS_DATA_OUT(127 downto 96) => open,
+ BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
+ BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
+ BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
+ BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
+
+ BUS_ADDR_OUT(67 downto 64) => stat_busycntexcl_addr,
+ BUS_ADDR_OUT(79 downto 68) => open,
+ BUS_DATA_OUT(159 downto 128) => open,
+ BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
+ BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data,
+ BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
+ BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
+
+ BUS_ADDR_OUT(95 downto 80) => open,
+ BUS_DATA_OUT(191 downto 160) => open,
+ BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
+ BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATA_IN(191 downto 160) => global_time,
+ BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
+ BUS_WRITE_ACK_IN(5) => '0',
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
STAT_DEBUG => open
);
end if;
end process;
+------------------------------------
+--STAT busy counters
+------------------------------------
+ gen_busy_counters : for i in 0 to MII_NUMBER-1 generate
+ proc_busy_counters : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reg_STAT_POINTS_locked(i) <= buf_STAT_POINTS_locked(i);
+ if reg_STAT_POINTS_locked(i) = '1' and
+ or_all(reg_STAT_POINTS_locked(MII_NUMBER-1 downto 0) and not (std_logic_vector(to_unsigned(2**i,MII_NUMBER)))) = '0' then
+ reg_excl_enable(i) <= '1';
+ else
+ reg_excl_enable(i) <= '0';
+ end if;
+
+ if stat_busycntincl_ack = '1' then
+ busy_counter_incl(i) <= (others => '0');
+ elsif reg_STAT_POINTS_locked(i) = '1' then
+ busy_counter_incl(i) <= busy_counter_incl(i) + to_unsigned(1,1);
+ end if;
+
+ if stat_busycntexcl_ack = '1' then
+ busy_counter_excl(i) <= (others => '0');
+ elsif reg_excl_enable(i) = '1' then
+ busy_counter_excl(i) <= busy_counter_excl(i) + to_unsigned(1,1);
+ end if;
+
+ end if;
+ end process;
+ end generate;
+
+ proc_busy_counter_incl_register : process(CLK)
+ variable tmp : integer range 0 to 15;
+ begin
+ if rising_edge(CLK) then
+ last_stat_globaltime_read <= stat_globaltime_read;
+ last_stat_globaltime_write <= stat_globaltime_write;
+
+ stat_busycntincl_unknown <= '0';
+ stat_busycntincl_ready <= '0';
+ if stat_busycntincl_read = '1' then
+ tmp := to_integer(unsigned(stat_busycntincl_addr));
+ if tmp < MII_NUMBER then
+ stat_busycntincl_data <= busy_counter_incl(tmp);
+ stat_busycntincl_ready <= '1';
+ else
+ stat_busycntincl_data <= (others => '0');
+ stat_busycntincl_ready <= '1';
+ end if;
+ end if;
+ if stat_busycntincl_write = '1' then
+ stat_busycntincl_ack <= '1';
+ else
+ stat_busycntincl_ack <= '0';
+ end if;
+ end if;
+ end process;
+
+ proc_busy_counter_excl_register : process(CLK)
+ variable tmp : integer range 0 to 15;
+ begin
+ if rising_edge(CLK) then
+ stat_busycntexcl_unknown <= '0';
+ stat_busycntexcl_ready <= '0';
+ if stat_busycntexcl_read = '1' then
+ tmp := to_integer(unsigned(stat_busycntexcl_addr));
+ if tmp < MII_NUMBER then
+ stat_busycntexcl_data <= busy_counter_excl(tmp);
+ stat_busycntexcl_ready <= '1';
+ else
+ stat_busycntexcl_data <= (others => '0');
+ stat_busycntexcl_ready <= '1';
+ end if;
+ end if;
+ if stat_busycntexcl_write = '1' then
+ stat_busycntexcl_ack <= '1';
+ else
+ stat_busycntexcl_ack <= '0';
+ end if;
+ end if;
+ end process;
+
------------------------------------
--Control Registers
------------------------------------
--Debugging Signals
---------------------------------------------------------------------
- --debug Status and Control ports
--- buf_STAT_DEBUG(4 downto 0) <= HUB_INIT_DATAREADY_IN(15 downto 11);
--- buf_STAT_DEBUG(9 downto 5) <= HUB_INIT_READ_OUT(15 downto 11);
--- buf_STAT_DEBUG(14 downto 10) <= HUB_REPLY_READ_OUT(15 downto 11);
--- buf_STAT_DEBUG(19 downto 15) <= HUB_INIT_DATAREADY_OUT(15 downto 11);
--- buf_STAT_DEBUG(24 downto 20) <= HUB_INIT_READ_IN(15 downto 11);
--- buf_STAT_DEBUG(27 downto 25) <= CTRL_DEBUG(2 downto 0);
--- buf_STAT_DEBUG(28) <= stream_port_connected;
--- buf_STAT_DEBUG(30 downto 29) <= "00";
--- buf_STAT_DEBUG(31) <= CLK;
buf_STAT_DEBUG(31 downto 0) <= (others => '0');
--- buf_STAT_DEBUG(18 downto 16) <= IOBUF_IBUF_BUFFER(20+32*6 downto 18+32*6);
--- buf_STAT_DEBUG(21 downto 19) <= IOBUF_IBUF_BUFFER(20+32*7 downto 18+32*7);
--- buf_STAT_DEBUG(25 downto 22) <= buf_to_hub_REPLY_DATA(6*c_DATA_WIDTH+3 downto 6*c_DATA_WIDTH);
--- buf_STAT_DEBUG(26) <= buf_to_hub_REPLY_DATAREADY(6);
--- buf_STAT_DEBUG(30 downto 27) <= buf_to_hub_REPLY_DATA(7*c_DATA_WIDTH+3 downto 7*c_DATA_WIDTH);
--- buf_STAT_DEBUG(31) <= buf_to_hub_REPLY_DATAREADY(7);
-
IOBUF_CTRL_GEN <= (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E";
CLOCK_FREQUENCY : integer range 1 to 200 := 100;
USE_ONEWIRE : integer range 0 to 2 := c_YES;
--media interfaces
);
port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
--Media Interface
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
--Event information coming from CTS
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
--Information sent to CTS
--status data, equipped with DHDR
- CTS_DATA_IN : in std_logic_vector (31 downto 0);
- CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
- CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic;
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_IN : in std_logic;
- ONEWIRE_MONITOR_OUT : out std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ ONEWIRE_MONITOR_OUT : out std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
--REGIO INTERFACE
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
--status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
--Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
);
end entity;
THE_HUB : trb_net16_hub_base
generic map (
--hub control
- HUB_CTRL_CHANNELNUM => HUB_CTRL_CHANNELNUM,
- HUB_CTRL_DEPTH => HUB_CTRL_DEPTH,
- HUB_USED_CHANNELS => HUB_USED_CHANNELS,
- USE_CHECKSUM => USE_CHECKSUM,
- USE_VENDOR_CORES => USE_VENDOR_CORES,
- IBUF_SECURE_MODE => IBUF_SECURE_MODE,
- INIT_ADDRESS => INIT_ADDRESS,
- INIT_UNIQUE_ID => INIT_UNIQUE_ID,
- COMPILE_TIME => COMPILE_TIME,
- COMPILE_VERSION => COMPILE_VERSION,
- HARDWARE_VERSION => HARDWARE_VERSION,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- USE_ONEWIRE => USE_ONEWIRE,
- MII_NUMBER => mii,
- MII_IBUF_DEPTH => MII_IBUF_DEPTH,
- MII_IS_UPLINK => MII_IS_UPLINK,
- MII_IS_DOWNLINK => MII_IS_DOWNLINK,
- INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
- INT_NUMBER => 3,
- INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0)
+ HUB_CTRL_CHANNELNUM => HUB_CTRL_CHANNELNUM,
+ HUB_CTRL_DEPTH => HUB_CTRL_DEPTH,
+ HUB_USED_CHANNELS => HUB_USED_CHANNELS,
+ USE_CHECKSUM => USE_CHECKSUM,
+ USE_VENDOR_CORES => USE_VENDOR_CORES,
+ IBUF_SECURE_MODE => IBUF_SECURE_MODE,
+ INIT_ADDRESS => INIT_ADDRESS,
+ INIT_UNIQUE_ID => INIT_UNIQUE_ID,
+ COMPILE_TIME => COMPILE_TIME,
+ COMPILE_VERSION => COMPILE_VERSION,
+ HARDWARE_VERSION => HARDWARE_VERSION,
+ HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ USE_ONEWIRE => USE_ONEWIRE,
+ MII_NUMBER => mii,
+ MII_IBUF_DEPTH => MII_IBUF_DEPTH,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
+ INT_NUMBER => 3,
+ INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0)
)
port map (
CLK => CLK,
jspc29 / trbnet.git / commitdiff