# Command line for ngdbuild
#
#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd";
-$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf $TOPNAME.edf $TOPNAME.ngd";
+$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd /home/marek/trbv2 $TOPNAME.edf $TOPNAME.ngd";
execute($c);
#
# Command line for fpgafit
# Command line for genarate programming file (.bit)
#
+
+foreach (<$TOPNAME"."_pad.txt>) {
+ @a=split (/\s*\|\s*/,$_);
+ if( ($a[2] ne "" &&
+ $a[2] ne "Signal Name") &&
+ $a[13] ne "LOCATED"
+ )
+ {
+ print "error, pins were assigned automatically:\n$_\n";
+ exit;
+ }
+}
+
#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME";
$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd";
when READ_DSP_MEMORY_NEXT =>
debug_register <= "010";
ADDRESS_DSP <= reg_address_dsp;
- DSP_DATA_OUT <= (others => x"a5a5a5a5");
+-- DSP_DATA_OUT <= (others => x"a5a5a5a5");
+ DSP_DATA_OUT <= (others => 'Z');
RD_OUT <= '0';
WRL <= '1';
WRH <= '1';
ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
DATA_VALID : in std_logic;
ETRAX_BUS_BUSY : out std_logic;
- ETRAX_READ_ONE_kW : in std_logic;
- ETRAX_HAS_TO_READ_EVENT : in std_logic;
- ETRAX_IS_READY_TO_READ : in std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
TDC_TCK : out std_logic;
TDC_TDI : out std_logic;
TDC_TMS : out std_logic;
signal etrax_data_pulse_2 : std_logic;
signal etrax_data_pulse_3: std_logic;
signal debug_reg_04 : std_logic_vector(15 downto 0);
+
begin
-
--- ACK_PULSER : edge_to_pulse
--- port map (
--- clock => CLK,
--- en_clk => '1',
--- signal_in => ETRAX_DATA_BUS_C(16),
--- pulse => etrax_ack_pulse);
-
ETRAX_TRIGG_PULSER : edge_to_pulse
port map (
clock => CLK,
en_clk => '1',
signal_in => ETRAX_DATA_BUS_C(16),
pulse => etrax_trigger_pulse);
+ ETRAX_TRIGG_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_C(17),
+ pulse => ETRAX_IS_READY_TO_READ);
RW_FINISHED_PULSER : edge_to_pulse
port map (
clock => CLK,
QOUT => counter_for_test
);
TDC_TRST <= not fpga_register_18_i(0);--etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
- TDC_RESET <= not fpga_register_17_i(0);
- EXTERNAL_RESET <= etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
+ TDC_RESET <= fpga_register_17_i(0);
+ EXTERNAL_RESET <= ETRAX_DATA_BUS_C(16) and ETRAX_DATA_BUS_C(17);
+ ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1';
REGISTERS: process (CLK)
begin
if rising_edge(CLK) then
FPGA_REGISTER_18 <= fpga_register_18_i; --this is used for jatgTDC
--reset
FPGA_REGISTER_19 <= fpga_register_19_i;
- FPGA_REGISTER_20 <= fpga_register_20_i;
+ FPGA_REGISTER_20 <= fpga_register_20_i; --enable TDC clock
FPGA_REGISTER_21 <= fpga_register_21_i;
FPGA_REGISTER_22 <= fpga_register_22_i;
FPGA_REGISTER_23 <= fpga_register_23_i;
-- end if;
end if;
end process REGISTERS;
- ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, RESET)
+ ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17))
begin
if rising_edge(CLK) then
if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
when IDLE =>
fpga_register_00_i <= x"00000001";
if etrax_trigger_pulse = '1' then
- -- saved_rw_mode(17 downto 0) <= ETRAX_DATA_BUS_C;
ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
else
ETRAX_RW_STATE_nextstate <= IDLE;
when SAVE_ADDRESS_1 =>
fpga_register_00_i <= x"00000002";
if etrax_trigger_pulse = '1' then
--- saved_address(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2;
else
ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
when SAVE_ADDRESS_2 =>
fpga_register_00_i <= x"00000003";
if etrax_trigger_pulse = '1' then
- -- saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
if saved_rw_mode(15) = '1' then
ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
else
when SAVE_DATA_1 =>
fpga_register_00_i <= x"00000004";
if etrax_trigger_pulse = '1' then
- -- saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
else
ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
when SAVE_DATA_2 =>
fpga_register_00_i <= x"00000005";
if etrax_trigger_pulse = '1' then
- -- saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
else
ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
end case;
end process ETRAX_FPGA_COMUNICATION;
- REGISTER_ETRAX_BUS: process (CLK, RESET)
+ REGISTER_ETRAX_BUS: process (CLK, RESET,ETRAX_RW_STATE_currentstate)
begin
if rising_edge(CLK) then
if RESET = '1' then
begin
if rising_edge(CLK) then
if RESET = '1' then
--- EXTERNAL_DATA <= (others => 'Z');
elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '1' then
--- EXTERNAL_DATA <= (others => 'Z');
EXTERNAL_ACK <= '1';
elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '0' then
--- EXTERNAL_DATA <= saved_data;
EXTERNAL_ACK <= '1';
- -- elsif ETRAX_RW_STATE_currentstate = SAVING_EXTERNAL_DATA then --or
--- (ETRAX_RW_STATE_currentstate = SEND_VALID and etrax_trigger_pulse ='1')then
--- EXTERNAL_ACK <= '1';
--- EXTERNAL_DATA <= (others => 'Z');
else
EXTERNAL_ACK <= '0';
--- EXTERNAL_DATA <= (others => 'Z');
end if;
end if;
end process EXTERNAL_DATA_LOGIC;
- ETRAX_DATA_BUS_CHOOSE : process (CLK, RESET,ETRAX_RW_STATE_currentstate)
+ ETRAX_DATA_BUS_CHOOSE : process (CLK, RESET,ETRAX_RW_STATE_currentstate, DATA_VALID)
begin
if rising_edge(CLK) then
if RESET = '1' then
- ETRAX_DATA_BUS_B <= "00"& x"FF00";--(others => 'Z');
+ ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";--(others => 'Z');
elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);--
ETRAX_DATA_BUS_B(16) <= '1';
- ETRAX_DATA_BUS_B(17) <= '0';
+ -- ETRAX_DATA_BUS_B(17) <= '0';
elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);--
ETRAX_DATA_BUS_B(16) <= '1';
- ETRAX_DATA_BUS_B(17) <= '0';
+ -- ETRAX_DATA_BUS_B(17) <= '0';
+ elsif DATA_VALID = '1' then
+ ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
+ -- ETRAX_DATA_BUS_B(17) <= CLK;
+ ETRAX_DATA_BUS_B(16) <= '1';
else
ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_07_i(15 downto 0);
- ETRAX_DATA_BUS_B(17 downto 16) <= "00";
+ ETRAX_DATA_BUS_B(16) <= '0';
end if;
end if;
end process ETRAX_DATA_BUS_CHOOSE;
- TDC_JAM_SIGNALS : process (CLK, RESET)
+
+ ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0';
+
+ TDC_JAM_SIGNALS : process (CLK, RESET, DATA_VALID, fpga_register_16_i(0))
begin
if rising_edge(CLK) then
if RESET = '1' then
- TDC_TMS <= '0';
- TDC_TCK <= '0';
- TDC_TDI <= '0';
+ TDC_TMS <= '1';
+ TDC_TCK <= '1';
+ TDC_TDI <= '1';
ETRAX_DATA_BUS_C <= (others => 'Z');
elsif fpga_register_16_i(0) = '1' then
- ETRAX_DATA_BUS_C <= (others => 'Z');
+-- ETRAX_DATA_BUS_C <= (others => 'Z');
TDC_TMS <= ETRAX_DATA_BUS_C(1);
TDC_TCK <= ETRAX_DATA_BUS_C(2);
TDC_TDI <= ETRAX_DATA_BUS_C(3);
ETRAX_DATA_BUS_C(0) <= TDC_TDO;
ETRAX_DATA_BUS_C(17 downto 1) <= (others => 'Z');
-- ETRAX_DATA_BUS_C(13 downto 0) <= (others => 'Z');
+ elsif DATA_VALID = '1' then
+ ETRAX_DATA_BUS_C(15 downto 0) <= DATA_BUS(31 downto 16);
+ ETRAX_DATA_BUS_C(16) <= 'Z';
+ ETRAX_DATA_BUS_C(17) <= 'Z';
+ TDC_TMS <= '1';
+ TDC_TCK <= '1';
+ TDC_TDI <= '1';
else
TDC_TMS <= '1';
TDC_TCK <= '1';
end if;
end if;
end process TDC_JAM_SIGNALS;
-
--- TDC_TMS <= '0';
--- TDC_TCK <= '0';
--- TDC_TDI <= '0';
--- ETRAX_DATA_BUS_B <= "11" & x"abba";
--- ETRAX_DATA_BUS_B <= RESET & RESET & x"abb" & '0' & '0' & RESET & '0';
--- ETRAX_DATA_BUS_C <= "11" & x"baca";
- DATA_SOURCE_SELECT : process (CLK)
+ DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address)
begin
if rising_edge(CLK) then
if RESET ='1' or (ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
end if;
end if;
end process DATA_SOURCE_SELECT;
- -----------------------------------------------------------------------------
- -- test counetrs
- -----------------------------------------------------------------------------
--- ETRAX_DATA_BUS_PULSER_00 : edge_to_pulse
--- port map (
--- clock => CLK,
--- en_clk => '1',
--- signal_in => ETRAX_DATA_BUS_C(17),
--- pulse => etrax_data_pulse_0 );
--- ETRAX_DATA_BUS_PULSER_01 : edge_to_pulse
--- port map (
--- clock => CLK,
--- en_clk => '1',
--- signal_in => ETRAX_DATA_BUS_C(16),
--- pulse => etrax_data_pulse_1 );
--- ETRAX_DATA_BUS_PULSER_02 : edge_to_pulse
--- port map (
--- clock => CLK,
--- en_clk => '1',
--- signal_in => ETRAX_DATA_BUS_C(12),
--- pulse => etrax_data_pulse_2 );
--- ETRAX_DATA_BUS_PULSER_03 : edge_to_pulse
--- port map (
--- clock => CLK,
--- en_clk => '1',
--- signal_in => ETRAX_DATA_BUS_C(5),
--- pulse => etrax_data_pulse_3 );
-
--- DEBUG_COUNTERS: process (CLK, RESET)
--- begin
--- if rising_edge(CLK) then
--- if RESET = '1' then
--- debug_reg_00 <= (others => '0');
--- debug_reg_01 <= (others => '0');
--- debug_reg_02 <= (others => '0');
--- debug_reg_03 <= (others => '0');
--- elsif etrax_data_pulse_0 = '1' then
--- debug_reg_00 <= debug_reg_00 + 1;
--- elsif etrax_data_pulse_1 = '1' then
--- debug_reg_01 <= debug_reg_01 + 1;
--- elsif etrax_data_pulse_2 = '1' then
--- debug_reg_02 <= debug_reg_02 + 1;
--- elsif etrax_data_pulse_3 = '1' then
--- debug_reg_03 <= debug_reg_03 + 1;
--- else
--- debug_reg_00 <= debug_reg_00;
--- debug_reg_01 <= debug_reg_01;
--- debug_reg_02 <= debug_reg_02;
--- debug_reg_03 <= debug_reg_03;
--- end if;
--- end if;
--- end process DEBUG_COUNTERS;
--- -- ETRAX_DATA_BUS_B(15 downto 0) <= debug_reg_03 & debug_reg_02 & debug_reg_01 & debug_reg_00;
--- -- ETRAX_DATA_BUS_B(16) <= '1' when debug_reg_00 /= debug_reg_01 or
--- -- debug_reg_00 /= debug_reg_02 or
--- -- debug_reg_00 /= debug_reg_03 or
--- -- debug_reg_01 /= debug_reg_02 or
--- -- debug_reg_01 /= debug_reg_03 or
--- -- debug_reg_02 /= debug_reg_03 else '0';
--- DEBUG_COUNT_OUT: process (CLK, RESET)
--- begin -- process DEBUG_COUNT_OUT
--- if rising_edge(CLK) then -- rising clock edge
--- if RESET = '1' then -- asynchronous reset (active low)
--- debug_reg_04 <= (others => '0');
--- else
-
--- debug_reg_04 <= debug_reg_04 + 1;
--- end if;
--- end if;
--- end process DEBUG_COUNT_OUT;
--- EXTERNAL_DEBUG <= '1' when debug_reg_04 < x"00ff" else '0';
- end etrax_interface;
+end etrax_interface;
fsm : process (clock)
begin -- process fsm
- if clock'event and clock = '1' then -- rising clock edge
+ if rising_edge(clock) then -- rising clock edge
if en_clk = '1' then
current_state <= next_state;
signal_sync <= signal_in;
LVL2_BUSY : out std_logic;
TDC_LVL1_BUSY : in std_logic;
TDC_LVL2_BUSY : in std_logic;
+ ETRAX_BUSY : in std_logic;
+ ETRAX_BUS_BUSY : in std_logic;
LVL1_TRIGG : in std_logic;
LVL2_TRIGG : in std_logic;
TRIGGER_CODE : in std_logic_vector(3 downto 0);
- TDC_READOUT_COMPLETED : in std_logic
+ TDC_READOUT_COMPLETED : in std_logic;
+ TRIGGER_WITHOUT_HADES : in std_logic
);
end lvl1_and_lvl2_busy;
architecture lvl1_and_lvl2_busy of lvl1_and_lvl2_busy is
signal write_busy_lvl1 : std_logic;
signal count_busy_lvl2 : std_logic;
signal write_busy_lvl1_pulse : std_logic;
+ signal tdc_lvl2_busy_pulse : std_logic;
begin
-------------------------------------------------------------------------------
-- LVL1 start pulse for count (up)
signal_in => LVL2_TRIGG,
pulse => lvl2_count_pulse);
-----------------------------------------------------------------------------
--- UP PULSE
+--LVL1 UP PULSE
-----------------------------------------------------------------------------
LVL1_UP_PULSER : edge_to_pulse
port map (
en_clk => '1',
signal_in => write_busy_lvl1,
pulse => write_busy_lvl1_pulse);
+-----------------------------------------------------------------------------
+--LVL2 UP PULSE
+-----------------------------------------------------------------------------
+ LVL2_UP_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => TDC_LVL2_BUSY,
+ pulse => tdc_lvl2_busy_pulse);
-------------------------------------------------------------------------------
-- up down counter(difference)
-------------------------------------------------------------------------------
port map (
QOUT => count_lvl1_lvl2_diff,
UP => write_busy_lvl1_pulse,
- DOWN => lvl2_count_pulse,
+ DOWN => tdc_lvl2_busy_pulse,--lvl2_count_pulse,
CLK => CLK,
CLR => RESET);
-----------------------------------------------------------------------------
-- LEVEL 1 BUSY LOGIC
-----------------------------------------------------------------------------
- BUSY_LVL1 : process (CLK)
+ BUSY_LVL1 : process (CLK,TDC_READOUT_COMPLETED, RESET,lvl1_count_pulse, TRIGGER_CODE)
begin
if rising_edge(CLK) then
if TDC_READOUT_COMPLETED = '1' or RESET = '1' then
write_busy_lvl1 <= '0';
- elsif lvl1_count_pulse = '1' and TRIGGER_CODE /= x"d" then
+ elsif (lvl1_count_pulse = '1' and TRIGGER_CODE /= x"d") or TRIGGER_WITHOUT_HADES = '1' then
write_busy_lvl1 <= '1';
end if;
end if;
----------------------------------------------------------------------------
-- LEVEL 2 BUSY LOGIC
----------------------------------------------------------------------------
- LVL1_BUSY <= write_busy_lvl1 or TDC_LVL1_BUSY;
count_busy_lvl2 <= write_busy_lvl1 when count_lvl1_lvl2_diff = x"01" else '0';
- LVL2_BUSY <= TDC_LVL2_BUSY or count_busy_lvl2;
+ LVL2_BUSY <= TDC_LVL2_BUSY or count_busy_lvl2 or ETRAX_BUSY or ETRAX_BUS_BUSY;
+ -- TDC_LVL2_BUSY - write busy
+ -- ETRAX_BUSY - etrax is not ready
+ -- ETRAX_BUS_BUSY - comunication between etrax and FPGA
+ -- count_busy_lvl2 - there is no event inside memory
-------------------------------------------------------------------------------
-- End of LVL2 TRIGGER LOGIC
-------------------------------------------------------------------------------
B_TDC_READY : in std_logic;
C_TDC_READY : in std_logic;
D_TDC_READY : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
SEND_TDC_TOKEN : out std_logic;
RECEIVED_TDC_TOKEN : in std_logic;
GET_TDC_DATA : out std_logic; --Signal to TDC chip
COUNTER_l : in std_logic_vector(31 downto 0);
COUNTER_m : in std_logic_vector(31 downto 0);
LVL2_TRIGGER : in std_logic_vector(1 downto 0);
- TDC_DATA_OUT : out std_logic_vector (31 downto 0); --data to RAM (LVL2)
+ TDC_DATA_OUT : out std_logic_vector (31 downto 0); --data to ETRAX (LVL2)
TDC_DATA_VALID : out std_logic; -- The TDC_DATA_OUT can be written
- -- to RAM
- ETRAX_READ_ONE_kW : in std_logic;
- ETRAX_HAS_TO_READ_EVENT : out std_logic; --this signal has to be used in
- --LVL2 busy !!!!
ETRAX_IS_READY_TO_READ : in std_logic;
TDC_LVL1_BUSY : out std_logic;
- TDC_LVL2_BUSY : out std_logic
+ TDC_LVL2_BUSY : out std_logic;
+ TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
+ BUNCH_RESET : out std_logic;
+ EVENT_RESET : out std_logic
);
end tdc_interface;
architecture tdc_interface of tdc_interface is
signal_in : in std_logic;
pulse : out std_logic);
end component;
- component lvl1_fifo
- port (
- RESET : in std_logic;
- WRITE_ADDRESS : in std_logic_vector (19 downto 0);
- READ_ADDRESS : in std_logic_vector (19 downto 0);
- DATA_IN : in std_logic_vector (31 downto 0);
- DATA_OUT : out std_logic_vector (31 downto 0);
- CLK_IN : in std_logic;
- CLK_OUT : in std_logic;
- TDC_DATA_VALID : in std_logic;
- END_EVENT_MARKER_IN : in std_logic;
- END_EVENT_MARKER_OUT : out std_logic);
+ component lvl1_memory
+ port (
+ addra : IN std_logic_VECTOR(14 downto 0);
+ addrb : IN std_logic_VECTOR(14 downto 0);
+ clka : IN std_logic;
+ clkb : IN std_logic;
+ dina : IN std_logic_VECTOR(31 downto 0);
+ doutb : OUT std_logic_VECTOR(31 downto 0);
+ wea : IN std_logic);
end component;
component up_down_counter_16_bit
port (
CLK : in std_logic;
CLR : in std_logic
);
- end component;
- signal tdc_ready : std_logic;
- signal write_eneble_and_tdc_ready : std_logic_vector(23 downto 0);
- signal write_address : std_logic_vector(19 downto 0);
- signal write_address_tdc_data : std_logic_vector(19 downto 0);
- signal read_address : std_logic_vector(19 downto 0);
- signal data_to_lvl1_fifo : std_logic_vector (31 downto 0);
- signal tdc_ready_or_add_word : std_logic;
+ end component;
+ component BUFG
+ port(
+ O: out std_ulogic;
+ I: in std_ulogic
+ );
+ end component;
+component DCM_ADV
+ generic( CLK_FEEDBACK : string := "1X";
+ CLKDV_DIVIDE : real := 2.0;
+ CLKFX_DIVIDE : integer := 1;
+ CLKFX_MULTIPLY : integer := 4;
+ CLKIN_DIVIDE_BY_2 : boolean := FALSE;
+ CLKIN_PERIOD : real := 10.0;
+ CLKOUT_PHASE_SHIFT : string := "NONE";
+ DCM_AUTOCALIBRATION : boolean := TRUE;
+ DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
+ DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
+ DFS_FREQUENCY_MODE : string := "LOW";
+ DLL_FREQUENCY_MODE : string := "LOW";
+ DUTY_CYCLE_CORRECTION : boolean := TRUE;
+ FACTORY_JF : bit_vector := x"F0F0";
+ PHASE_SHIFT : integer := 0;
+ STARTUP_WAIT : boolean := FALSE;
+ SIM_DEVICE : string := "VIRTEX4");
+ port ( CLKIN : in std_logic;
+ CLKFB : in std_logic;
+ DADDR : in std_logic_vector (6 downto 0);
+ DI : in std_logic_vector (15 downto 0);
+ DWE : in std_logic;
+ DEN : in std_logic;
+ DCLK : in std_logic;
+ RST : in std_logic;
+ PSEN : in std_logic;
+ PSINCDEC : in std_logic;
+ PSCLK : in std_logic;
+ CLK0 : out std_logic;
+ CLK90 : out std_logic;
+ CLK180 : out std_logic;
+ CLK270 : out std_logic;
+ CLKDV : out std_logic;
+ CLK2X : out std_logic;
+ CLK2X180 : out std_logic;
+ CLKFX : out std_logic;
+ CLKFX180 : out std_logic;
+ DRDY : out std_logic;
+ DO : out std_logic_vector (15 downto 0);
+ LOCKED : out std_logic;
+ PSDONE : out std_logic);
+ end component;
+
+
+ signal tdc_ready : std_logic:='0';
+ signal write_eneble_and_tdc_ready : std_logic_vector(23 downto 0):=(others => '0');
+ signal write_address : std_logic_vector(14 downto 0):=(others => '0');
+ signal write_address_tdc_data : std_logic_vector(14 downto 0):=(others => '0');
+ signal read_address : std_logic_vector(14 downto 0):=(others => '0');
+ signal data_to_lvl1_fifo : std_logic_vector (31 downto 0):=(others => '0');
+ signal tdc_ready_or_add_word : std_logic:='0';
signal counter_a_i : std_logic_vector(31 downto 0);
signal counter_b_i : std_logic_vector(31 downto 0);
signal counter_c_i : std_logic_vector(31 downto 0);
signal counter_k_i : std_logic_vector(31 downto 0);
signal counter_l_i : std_logic_vector(31 downto 0);
signal counter_m_i : std_logic_vector(31 downto 0);
- signal add_data_counter : std_logic_vector(7 downto 0);
- signal add_data_pulse : std_logic;
- signal received_tdc_token_pulse : std_logic;
- signal data_selector : std_logic_vector(4 downto 0);
- signal saved_address : std_logic_vector(19 downto 0);
- signal first_header : std_logic_vector(31 downto 0);
- signal second_header : std_logic_vector(31 downto 0);
- signal words_in_event : std_logic_vector(15 downto 0);
- signal read_data_address_up : std_logic;
- signal not_how_many_words_in_ram: std_logic;
- signal next_kW_in_ram_pulse : std_logic;
- signal etrax_read_one_kW_pulse : std_logic;
- signal how_many_kW_in_ram : std_logic_vector(15 downto 0);
- signal word_count_up : std_logic;
- signal word_count_up_pulse : std_logic;
- signal how_many_words_in_fifo : std_logic_vector(15 downto 0);
- signal end_event_marker_in_i : std_logic;
- signal end_event_marker_out_i : std_logic;
- signal etrax_have_to_read_ram_i : std_logic;
- signal how_many_words_in_ram : std_logic_vector(9 downto 0);
- signal tdc_data_valid_i : std_logic;
+ signal add_data_counter : std_logic_vector(7 downto 0):=(others => '0');
+ signal add_data_pulse : std_logic:='0';
+ signal received_tdc_token_pulse : std_logic:='0';
+ signal data_selector : std_logic_vector(4 downto 0):=(others => '0');
+ signal saved_address : std_logic_vector(14 downto 0):=(others => '0');
+ signal first_header : std_logic_vector(31 downto 0):=(others => '0');
+ signal second_header : std_logic_vector(31 downto 0):=(others => '0');
+ signal words_in_event : std_logic_vector(15 downto 0):=(others => '0');
+ signal read_data_address_up : std_logic:='0';
+ signal word_count_up : std_logic:='0';
+ signal word_count_up_clk : std_logic := '0';
+ signal word_count_up_pulse : std_logic:='0';
+ signal how_many_words_in_fifo : std_logic_vector(15 downto 0):=(others => '0');
+ signal how_many_words_in_ram : std_logic_vector(9 downto 0):=(others => '0');
+ signal tdc_data_valid_i : std_logic:='0';
+ signal lvl2_trigger_pulse : std_logic;
+ signal how_many_words_in_event : std_logic_vector(19 downto 0);
+ signal lvl2_valid_saved : std_logic;
+ signal start_tdc_readout_pulse : std_logic;
+ signal start_tdc_readout_90_deg : std_logic;
+ signal word_count_up_synch : std_logic;
+ signal doutb_i : std_logic_vector(31 downto 0);
+ signal end_event_marker_in_i : std_logic;
+ signal first_trigger : std_logic;
+ signal clkfx_i : std_logic;
+ signal clkfx_bufg_i : std_logic;
+ signal clk0_i : std_logic;
+ signal clkfb_i : std_logic;
+ signal word_count_down_clk: std_logic;
+ signal word_count_down_pulse: std_logic;
+ signal locked_i : std_logic;
+ signal word_ram_counter_up : std_logic_vector(15 downto 0);
+ signal word_ram_counter_down : std_logic_vector(15 downto 0);
begin
- SEND_TDC_TOKEN <= START_TDC_READOUT;
+ TDC_REGISTER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ TDC_REGISTER_00 <= (others => '0');
+ else
+ TDC_REGISTER_00(0) <= A_TDC_ERROR;
+ TDC_REGISTER_00(1) <= B_TDC_ERROR;
+ TDC_REGISTER_00(2) <= C_TDC_ERROR;
+ TDC_REGISTER_00(3) <= D_TDC_ERROR;
+ TDC_REGISTER_00(19 downto 4) <= how_many_words_in_fifo;
+ TDC_REGISTER_00(20) <= clkfx_bufg_i;
+ TDC_REGISTER_00(30 downto 21) <= (others => '0');
+ TDC_REGISTER_00(31) <= locked_i;
+ end if;
+ end if;
+ end process TDC_REGISTER;
+ A_TDC_POWERUP <= '1';
+ B_TDC_POWERUP <= '1';
+ C_TDC_POWERUP <= '1';
+ D_TDC_POWERUP <= '1';
+ SEND_TDC_TOKEN <= start_tdc_readout_90_deg;
tdc_ready <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
GET_TDC_DATA <= '1';
- LVL1_FIFO_16k_WORD : lvl1_fifo
- port map (
- RESET => RESET,
- WRITE_ADDRESS => write_address,
- READ_ADDRESS => read_address,
- DATA_IN => data_to_lvl1_fifo,
- DATA_OUT => TDC_DATA_OUT,
- CLK_IN => TDC_CLK,
- CLK_OUT => CLK,
- TDC_DATA_VALID => tdc_ready_or_add_word,
- END_EVENT_MARKER_IN => end_event_marker_in_i,
- END_EVENT_MARKER_OUT => end_event_marker_out_i );
+ LVL1_MEMORY_32kW: lvl1_memory
+ port map (
+ addra => write_address,--addra_i,
+ addrb => read_address,--addrb_i,
+ clka => TDC_CLK,--clka_i,
+ clkb => CLK,--clkb_i,
+ dina => data_to_lvl1_fifo,
+ doutb => doutb_i,--TDC_DATA_OUT,
+ wea => tdc_ready_or_add_word);
+ BUNCH_RESET_90deg_shift: process (TDC_CLK, RESET)
+ begin
+ if falling_edge(TDC_CLK) then
+ if RESET = '1' then
+ BUNCH_RESET <= '1';
+ EVENT_RESET <= '1';
+ else
+ EVENT_RESET <= '0';
+ BUNCH_RESET <= received_tdc_token_pulse;
+ end if;
+ end if;
+ end process BUNCH_RESET_90deg_shift;
+
+ TDC_DATA_OUT <= doutb_i;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- LVL1 logic only TDC_CLK domain
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
- WRITE_ADDRESS_CHANGE : process (TDC_CLK, RESET)
+ WRITE_ADDRESS_CHANGE : process (TDC_CLK, RESET,tdc_ready,add_data_pulse)
begin
if rising_edge(TDC_CLK) then
if RESET = '1' then
- write_address_tdc_data <= "000000000000" & HOW_MANY_ADD_DATA + 1; --+1_beacause_data_selector_count_to_0_!
+ write_address_tdc_data <= "0000000" & HOW_MANY_ADD_DATA + 1; --+1_beacause_data_selector_count_to_0_!
elsif tdc_ready = '1' or add_data_pulse = '1' then
write_address_tdc_data <= write_address_tdc_data + 1;
else
end if;
end if;
end process WRITE_ADDRESS_CHANGE;
- SAVE_DATA : process (CLK, RESET)
+ SAVE_DATA : process (CLK, RESET,START_TDC_READOUT )
begin
if rising_edge(CLK) then
if RESET = '1' then
end if;
end if;
end process SAVE_DATA;
-
TOKEN_PULSE : edge_to_pulse
port map (
clock => TDC_CLK,
en_clk => '1',
signal_in => RECEIVED_TDC_TOKEN,
pulse => received_tdc_token_pulse);
- ADD_DATA_PULSE_MAKE : process (TDC_CLK, RESET)
+ ADD_DATA_PULSE_MAKE : process (TDC_CLK, RESET,received_tdc_token_pulse,add_data_counter)
begin
if rising_edge(TDC_CLK) then
if RESET = '1' or add_data_counter = x"0" then
end case;
-- end if;
end process CHOOSE_DATA;
- end_event_marker_in_i <= '1' when data_selector = "10001" else '0';
+ end_event_marker_in_i <= '1' when data_selector = "10000" else '0';
TDC_READOUT_COMPLETED <= end_event_marker_in_i;
- ADD_DATA_COUNTER_CONTROL : process (TDC_CLK, RESET)
+ LVL1_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => TDC_CLK,
+ en_clk => '1',
+ signal_in => START_TDC_READOUT,
+ pulse => start_tdc_readout_pulse);
+ process (TDC_CLK, RESET)
+ begin
+ if falling_edge(TDC_CLK) then
+ if RESET = '1' then
+ start_tdc_readout_90_deg <= start_tdc_readout_90_deg;
+ else
+ start_tdc_readout_90_deg <= start_tdc_readout_pulse;
+ end if;
+ end if;
+ end process;
+ ADD_DATA_COUNTER_CONTROL : process (TDC_CLK, RESET,START_TDC_READOUT,add_data_pulse, start_tdc_readout_pulse)
begin
if rising_edge(TDC_CLK) then
- if RESET = '1' or START_TDC_READOUT = '1' then
+ if RESET = '1' or start_tdc_readout_pulse = '1' then
add_data_counter <= HOW_MANY_ADD_DATA + 1;
saved_address <= write_address_tdc_data;
elsif add_data_pulse = '1' then
end if;
end process ADD_DATA_COUNTER_CONTROL;
tdc_ready_or_add_word <= tdc_ready or add_data_pulse;
-
- COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET)
+ COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET, tdc_ready_or_add_word,start_tdc_readout_pulse)
begin
if rising_edge(TDC_CLK) then
- if RESET = '1' or START_TDC_READOUT = '1' then
+ if RESET = '1' or start_tdc_readout_pulse = '1' then
words_in_event <= x"0000";
elsif tdc_ready_or_add_word = '1' then
words_in_event <= words_in_event +1;
end if;
end if;
end process COUNT_WORDS_IN_EVENT;
- first_header <= x"f" & LVL1_TAG & LVL1_CODE & words_in_event;
- second_header <= x"00" & x"00" & x"00" & HOW_MANY_ADD_DATA;
+ first_header <= x"0" & LVL1_CODE & LVL1_TAG & words_in_event;
+ second_header <= x"02" & x"00" & x"00" & HOW_MANY_ADD_DATA;
write_address <= write_address_tdc_data when add_data_pulse = '0' else saved_address;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- LVL2 logic (only CLK domain)
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
+ SAVE_LVL2_VALID: process (CLK, RESET,lvl2_trigger_pulse)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_valid_saved <= '0';
+ elsif lvl2_trigger_pulse = '1' then
+ lvl2_valid_saved <= LVL2_TRIGGER(1);
+ end if;
+ end if;
+ end process SAVE_LVL2_VALID;
+ LVL2_TRIGGER_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL2_TRIGGER(0),
+ pulse => lvl2_trigger_pulse);
+ COUNT_DOWN_READOUT: process (CLK, RESET,lvl2_trigger_pulse,how_many_words_in_event)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ how_many_words_in_event <= (others => '0');
+ elsif lvl2_trigger_pulse = '1' then
+ how_many_words_in_event <= x"1" & doutb_i(15 downto 0);
+ elsif lvl2_trigger_pulse = '0' and how_many_words_in_event > x"0ffff" then
+ how_many_words_in_event <= how_many_words_in_event - 1;
+ end if;
+ end if;
+ end process COUNT_DOWN_READOUT;
- MAKE_LVL2_PULSE : process (CLK, RESET)
+ MAKE_LVL2_PULSE : process (CLK, RESET, how_many_words_in_event )
begin
if rising_edge(CLK) then
- if RESET = '1' or end_event_marker_out_i = '1' then
+ if RESET = '1' then
tdc_data_valid_i <= '0';
read_data_address_up <= '0';
- elsif LVL2_TRIGGER = "11" and tdc_data_valid_i = '0' then
- tdc_data_valid_i <= '1';
+ elsif how_many_words_in_event > x"10000" then
+ tdc_data_valid_i <= lvl2_valid_saved;
read_data_address_up <= '1';
- elsif LVL2_TRIGGER = "10" and tdc_data_valid_i = '0' then
- tdc_data_valid_i <= '0';
+ elsif how_many_words_in_event = x"10000" then
+ tdc_data_valid_i <= '0';--lvl2_valid_saved;
read_data_address_up <= '1';
else
- tdc_data_valid_i <= tdc_data_valid_i;
- read_data_address_up <= read_data_address_up;
+ tdc_data_valid_i <= '0';--tdc_data_valid_i;
+ read_data_address_up <= '0';--read_data_address_up;
end if;
end if;
end process MAKE_LVL2_PULSE;
- TDC_DATA_VALID <= tdc_data_valid_i;
- READ_ADDRESS_CHANGE : process (CLK, RESET)
+ SYNCH_DATA_VALID: process (CLK, RESET)
+ begin
+ if falling_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
+ if RESET = '1' then
+ TDC_DATA_VALID <= '0';
+ else
+ TDC_DATA_VALID <= tdc_data_valid_i;
+ end if;
+ end if;
+ end process SYNCH_DATA_VALID;
+ TDC_LVL2_BUSY <= tdc_data_valid_i;
+ READ_ADDRESS_CHANGE : process (CLK, RESET, read_data_address_up)
begin
if rising_edge(CLK) then
if RESET = '1' then
end if;
end if;
end process READ_ADDRESS_CHANGE;
- not_how_many_words_in_ram <= not how_many_words_in_ram(9);
- COUNT_WORDS_IN_RAM: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- how_many_words_in_ram <= (others => '0');
- elsif tdc_data_valid_i = '1' then
- how_many_words_in_ram <= how_many_words_in_ram +1;
- end if;
- end if;
- end process COUNT_WORDS_IN_RAM;
- NEXT_ONE_kW_IN_RAM_PULSE : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => not_how_many_words_in_ram,
- pulse => next_kW_in_ram_pulse);
- ETRAX_HAS_READ_kW : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ETRAX_READ_ONE_kW,
- pulse => etrax_read_one_kW_pulse);
- DIFF_kW_WRITE_READ : up_down_counter_16_bit
- port map (
- QOUT => how_many_kW_in_ram,
- UP => next_kW_in_ram_pulse,
- DOWN => etrax_read_one_kW_pulse,
- CLK => CLK,
- CLR => RESET);
- etrax_have_to_read_ram_i <= '1' when how_many_kW_in_ram /= x"0000" and ETRAX_IS_READY_TO_READ = '1' and read_data_address_up = '0' else '0';
- ETRAX_HAS_TO_READ_EVENT <= etrax_have_to_read_ram_i;
- TDC_LVL2_BUSY_ETRAX_ACCESS : process (CLK, RESET) --create lvl2 fifo trigg
- --if there is no lvl2 fifo
- --!!! ??
- begin
- if rising_edge(CLK) then
- if RESET = '1' or etrax_read_one_kW_pulse = '1' then
- TDC_LVL2_BUSY <= '0';
- elsif etrax_have_to_read_ram_i = '1' then
- TDC_LVL2_BUSY <= '1';
- end if;
- end if;
- end process TDC_LVL2_BUSY_ETRAX_ACCESS;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Mixed LVL1 and LVL2
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
- word_count_up <= TDC_CLK and tdc_ready_or_add_word;
- NEXT_ONE_WORD_IN_LVL1_FIFO : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => word_count_up,
- pulse => word_count_up_pulse);
- DIFF_WORD_WRITE_READ : up_down_counter_16_bit
- port map (
- QOUT => how_many_words_in_fifo,
- UP => word_count_up,
- DOWN => read_data_address_up,
- CLK => CLK,
- CLR => RESET);
+ WORD_ADD_TO_MEMORY: process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' then
+ word_ram_counter_up <= (others => '0');
+ elsif tdc_ready_or_add_word = '1' then
+ word_ram_counter_up <= word_ram_counter_up + 1;
+ end if;
+ end if;
+ end process WORD_ADD_TO_MEMORY;
+ WORD_SEND_FROM_MEMORY: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ word_ram_counter_down <= (others => '0');
+ elsif read_data_address_up = '1' then
+ word_ram_counter_down <= word_ram_counter_down + 1;
+ end if;
+ end if;
+ end process WORD_SEND_FROM_MEMORY;
+ how_many_words_in_fifo <= word_ram_counter_up - word_ram_counter_down;
TDC_LVL1_BUSY <= '1' when how_many_words_in_fifo > "0011111111111111" else '0';
--set
--to
-----------------------------------------------------------------------------
-- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
-----------------------------------------------------------------------------
-
-
end tdc_interface;
NET ADO_TTL<46> LOC = "B33"| IOSTANDARD = "LVTTL";
# NET A_CS1B LOC = P9;
# NET A_CS<1> LOC = P10;
-# NET A_DATA_READY LOC = "B12";
+ NET A_DATA_READY LOC = "B12"| IOSTANDARD = "LVTTL";
NET A_RESERVED LOC = "J11" | IOSTANDARD = "LVTTL";
# NET A_SCK LOC = H3;
# NET A_SCKB LOC = H2;
# NET A_SDIB LOC = G1;
# NET A_SDO LOC = J4;
# NET A_SDOB LOC = K4;
-# NET A_TDC_ERROR LOC = "F11";
-# NET A_TDC_POWERUP LOC = "H8";
+ NET A_TDC_ERROR LOC = "F11"| IOSTANDARD = "LVTTL";
+ NET A_TDC_POWERUP LOC = "H8"| IOSTANDARD = "LVTTL";
NET A_TEMP LOC = "B7" | IOSTANDARD = "LVTTL";
# NET A_TEST1B LOC = N7;
# NET A_TEST2B LOC = L4;
# NET A_TEST1 LOC = M7;
# NET A_TEST2 LOC = L5;
-# NET A_TRIGGER LOC = "J6";
-# NET A_TRIGGERB LOC = "J5";
+ NET A_TRIGGER LOC = "J6";
+ NET A_TRIGGERB LOC = "J5";
# NET B_CS1B LOC = G5;
# NET B_CS<1> LOC = F5;
-# NET B_DATA_READY LOC = "A8";
+ NET B_DATA_READY LOC = "A8"| IOSTANDARD = "LVTTL";
NET B_RESERVED LOC = "C7" | IOSTANDARD = "LVTTL";
# NET B_SCK LOC = C4;
# NET B_SCKB LOC = C3;
# NET B_SDIB LOC = T11;
# NET B_SDO LOC = J2;
# NET B_SDOB LOC = J1;
-# NET B_TDC_ERROR LOC = "A6";
-# NET B_TDC_POWERUP LOC = "H7";
+ NET B_TDC_ERROR LOC = "A6"| IOSTANDARD = "LVTTL";
+ NET B_TDC_POWERUP LOC = "H7"| IOSTANDARD = "LVTTL";
NET B_TEMP LOC = "A10" | IOSTANDARD = "LVTTL";
# NET B_TEST2B LOC = L9;
# NET B_TEST1B LOC = E4;
# NET B_TEST1 LOC = D4;
# NET B_TEST2 LOC = M10;
-# NET B_TRIGGER LOC = "H5";
-# NET B_TRIGGERB LOC = "H4";
+ NET B_TRIGGER LOC = "H5";
+ NET B_TRIGGERB LOC = "H4";
# NET C_CS1B LOC = R9;
# NET C_CS<1> LOC = T10;
-# NET C_DATA_READY LOC = "B8";
+ NET C_DATA_READY LOC = "B8" | IOSTANDARD = "LVTTL";
NET C_RESERVED LOC = "F8" | IOSTANDARD = "LVTTL";
# NET C_SCK LOC = P7;
# NET C_SCKB LOC = P6;
# NET C_SDIB LOC = E1;
# NET C_SDO LOC = F4;
# NET C_SDOB LOC = F3;
-# NET C_TDC_ERROR LOC = "B6";
-# NET C_TDC_POWERUP LOC = "K8";
+ NET C_TDC_ERROR LOC = "B6"| IOSTANDARD = "LVTTL";
+ NET C_TDC_POWERUP LOC = "K8"| IOSTANDARD = "LVTTL";
NET C_TEMP LOC = "A9" | IOSTANDARD = "LVTTL";
# NET C_TEST2B LOC = N12;
# NET C_TEST1B LOC = D2;
# NET C_TEST1 LOC = C2;
# NET C_TEST2 LOC = N13;
-# NET C_TOKEN_OUT_TTL LOC = "F6";
-# NET C_TRIGGER LOC = "N10";
-# NET C_TRIGGERB LOC = "N9";
+ NET C_TOKEN_OUT_TTL LOC = "F6"| IOSTANDARD = "LVTTL";
+ NET C_TRIGGER LOC = "N10";
+ NET C_TRIGGERB LOC = "N9";
NET DBAD LOC = "M28" | IOSTANDARD = "LVTTL";
NET DGOOD LOC = "H34" | IOSTANDARD = "LVTTL";
NET DINT LOC = "L31" | IOSTANDARD = "LVTTL";
NET DWAIT LOC = "H33" | IOSTANDARD = "LVTTL";
# NET D_CS1B LOC = M2;
# NET D_CS<1> LOC = M3;
-# NET D_DATA_READY LOC = "E11";
+ NET D_DATA_READY LOC = "E11"| IOSTANDARD = "LVTTL";
NET D_RESERVED LOC = "G8" | IOSTANDARD = "LVTTL";
# NET D_SCK LOC = M6;
# NET D_SCKB LOC = M5;
# NET D_SDIB LOC = L3;
# NET D_SDO LOC = K2;
# NET D_SDOB LOC = K1;
-# NET D_TDC_ERROR LOC = "H12";
-# NET D_TDC_POWERUP LOC = "J7";
+ NET D_TDC_ERROR LOC = "H12"| IOSTANDARD = "LVTTL";
+ NET D_TDC_POWERUP LOC = "J7"| IOSTANDARD = "LVTTL";
NET D_TEMP LOC = "C14" | IOSTANDARD = "LVTTL";
# NET D_TEST1B LOC = M1;
# NET D_TEST2B LOC = P5;
# NET D_TEST1 LOC = L1;
# NET D_TEST2 LOC = N5;
-# NET D_TRIGGER LOC = "P12";
-# NET D_TRIGGERB LOC = "P11";
+ NET D_TRIGGER LOC = "P12";
+ NET D_TRIGGERB LOC = "P11";
NET ETRAX_IRQ LOC = "AK12" | IOSTANDARD = "LVTTL";
NET FS_PB<0> LOC = "AL5" | IOSTANDARD = "LVTTL";
NET FS_PB<1> LOC = "AL4" | IOSTANDARD = "LVTTL";
# NET FS_PE<1> LOC = V13;
# NET FS_PE<2> LOC = V14;
# NET FS_PE<3> LOC = W17;
-# NET GET_DATA LOC = "B13";
+ NET GET_DATA LOC = "B13"| IOSTANDARD = "LVTTL";
# NET GND LOC = V22;
-# NET REF_TDC_CLK LOC = "F18";
-# NET REF_TDC_CLKB LOC = "G18";
- NET RESET_VIRT LOC = "AK16"| IOSTANDARD = "LVTTL";
+ NET REF_TDC_CLK LOC = "F18";
+ NET REF_TDC_CLKB LOC = "G18";
+ NET RESET_VIRT LOC = "AK16"| IOSTANDARD = "LVTTL";
# NET SFP_LOS LOC = M27;
# NET SFP_MOD<0> LOC = R23;
# NET SFP_MOD<1> LOC = K32;
# NET SFP_MOD<2> LOC = K33;
# NET SFP_RATE_SEL LOC = P27;
- NET SFP_TX_DIS LOC = "N27"| IOSTANDARD = "LVTTL";
+ NET SFP_TX_DIS LOC = "N27"| IOSTANDARD = "LVTTL";
# NET SFP_TX_FAULT LOC = J32;
-# NET TDC_BU_RESET LOC = "AK27";
-# NET TDC_BU_RESETB LOC = "AK28";
-# NET TDC_EV_RESET LOC = "K6";
-# NET TDC_EV_RESETB LOC = "L6";
-# NET TDC_OUT<0> LOC = "D12";
-# NET TDC_OUT<1> LOC = "C12";
-# NET TDC_OUT<2> LOC = "B10";
-# NET TDC_OUT<3> LOC = "C10";
-# NET TDC_OUT<4> LOC = "A11";
-# NET TDC_OUT<5> LOC = "B11";
-# NET TDC_OUT<6> LOC = "C9";
-# NET TDC_OUT<7> LOC = "C8";
-# NET TDC_OUT<8> LOC = "G12";
-# NET TDC_OUT<9> LOC = "G11";
-# NET TDC_OUT<10> LOC = "F10";
-# NET TDC_OUT<11> LOC = "G10";
-# NET TDC_OUT<12> LOC = "D11";
-# NET TDC_OUT<13> LOC = "D10";
-# NET TDC_OUT<14> LOC = "H10";
-# NET TDC_OUT<15> LOC = "H9";
-# NET TDC_OUT<16> LOC = "A14";
-# NET TDC_OUT<17> LOC = "A13";
-# NET TDC_OUT<18> LOC = "D7";
-# NET TDC_OUT<19> LOC = "D6";
-# NET TDC_OUT<20> LOC = "D9";
-# NET TDC_OUT<21> LOC = "E9";
-# NET TDC_OUT<22> LOC = "A4";
-# NET TDC_OUT<23> LOC = "A3";
-# NET TDC_OUT<24> LOC = "E13";
-# NET TDC_OUT<25> LOC = "E12";
-# NET TDC_OUT<26> LOC = "A5";
-# NET TDC_OUT<27> LOC = "B5";
-# NET TDC_OUT<28> LOC = "E8";
-# NET TDC_OUT<29> LOC = "E7";
-# NET TDC_OUT<30> LOC = "J9";
-# NET TDC_OUT<31> LOC = "K9";
+ NET TDC_BU_RESET LOC = "AK27";
+ NET TDC_BU_RESETB LOC = "AK28";
+ NET TDC_EV_RESET LOC = "K6";
+ NET TDC_EV_RESETB LOC = "L6";
+ NET TDC_OUT<0> LOC = "D12" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<1> LOC = "C12" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<2> LOC = "B10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<3> LOC = "C10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<4> LOC = "A11" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<5> LOC = "B11" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<6> LOC = "C9" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<7> LOC = "C8" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<8> LOC = "G12" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<9> LOC = "G11" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<10> LOC = "F10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<11> LOC = "G10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<12> LOC = "D11" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<13> LOC = "D10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<14> LOC = "H10" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<15> LOC = "H9" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<16> LOC = "A14" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<17> LOC = "A13" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<18> LOC = "D7" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<19> LOC = "D6" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<20> LOC = "D9" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<21> LOC = "E9" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<22> LOC = "A4" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<23> LOC = "A3" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<24> LOC = "E13" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<25> LOC = "E12" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<26> LOC = "A5" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<27> LOC = "B5" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<28> LOC = "E8" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<29> LOC = "E7" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<30> LOC = "J9" | IOSTANDARD = "LVTTL";
+ NET TDC_OUT<31> LOC = "K9" | IOSTANDARD = "LVTTL";
NET TDC_RESET LOC = "C5" | IOSTANDARD = "LVTTL";
NET TLK_CLK LOC = "R22" | IOSTANDARD = "LVTTL";
# NET "TLK_CLK" TNM_NET = "TLK_CLK";
NET TLK_TXD<15> LOC = "E34" | IOSTANDARD = "LVTTL";
NET TLK_TX_EN LOC = "L29" | IOSTANDARD = "LVTTL";
NET TLK_TX_ER LOC = "P24" | IOSTANDARD = "LVTTL";
-# NET TOKEN_IN LOC = "E6";
-# NET TOKEN_OUT LOC = "C13";
+ NET TOKEN_IN LOC = "E6"| IOSTANDARD = "LVTTL";
+ NET TOKEN_OUT LOC = "C13"| IOSTANDARD = "LVTTL";
NET VIRT_CLK LOC = "AF18";
NET VIRT_CLKB LOC = "AE18";
NET VIRT_TDO LOC = N30 | IOSTANDARD = "LVTTL";
NET VIRT_TMS LOC = J34 | IOSTANDARD = "LVTTL";
NET VIRT_TRST LOC = N29 | IOSTANDARD = "LVTTL";
- NET VIR_TRIG LOC = "E3"| IOSTANDARD = "LVDS_25";
- NET VIR_TRIGB LOC = "E2"| IOSTANDARD = "LVDS_25";
+ NET VIR_TRIG LOC = "E3";#| IOSTANDARD = "LVDS_25_DCI";
+ NET VIR_TRIGB LOC = "E2";#| IOSTANDARD = "LVDS_25_DCI";
# NET VSD_A<0> LOC = F23;
# NET VSD_A<1> LOC = E23;
# NET VSD_A<2> LOC = D26;
# NET VSD_RAS LOC = F29;
# NET VSD_WE LOC = K26;
+ OFFSET=OUT 17.0 ns AFTER "VIRT_CLK" HIGH;
+ OFFSET=IN 3.0 ns BEFORE "VIRT_CLK" HIGH;
+NET "VIRT_CLK" TNM_NET = VIRT_CLK;
+TIMESPEC TS_VIRT_CLK = PERIOD "VIRT_CLK" 10 ns;
\ No newline at end of file
-------------------------------------------------------------------------
-- TDC connections
-------------------------------------------------------------------------
--- A_TDC_ERROR : in std_logic;
--- B_TDC_ERROR : in std_logic;
--- C_TDC_ERROR : in std_logic;
--- D_TDC_ERROR : in std_logic;
--- A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
--- B_TDC_POWERUP : out std_logic;
--- C_TDC_POWERUP : out std_logic;
--- D_TDC_POWERUP : out std_logic;
--- TOKEN_IN : in std_logic;
--- TOKEN_OUT : out std_logic;
--- C_TOKEN_OUT_TTL : in std_logic;
--- GET_DATA : out std_logic;
--- A_DATA_READY : in std_logic;
--- B_DATA_READY : in std_logic;
--- C_DATA_READY : in std_logic;
--- D_DATA_READY : in std_logic;
--- REF_TDC_CLK : in std_logic;
--- REF_TDC_CLKB : in std_logic;
--- TDC_BU_RESET : out std_logic;
--- TDC_BU_RESETB : out std_logic;
--- TDC_EV_RESET : out std_logic;
--- TDC_EV_RESETB : out std_logic;
--- TDC_OUT : in std_logic_vector (31 downto 0);
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ TDC_BU_RESET : out std_logic;
+ TDC_BU_RESETB : out std_logic;
+ TDC_EV_RESET : out std_logic;
+ TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
TDC_RESET : out std_logic;
--- A_TRIGGER : out std_logic;
--- A_TRIGGERB : out std_logic;
--- B_TRIGGER : out std_logic;
--- B_TRIGGERB : out std_logic;
--- C_TRIGGER : out std_logic;
--- C_TRIGGERB : out std_logic;
--- D_TRIGGER : out std_logic;
--- D_TRIGGERB : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
-------------------------------------------------------------------------
-- ETRAX connections
-------------------------------------------------------------------------
B_TDC_READY : in std_logic;
C_TDC_READY : in std_logic;
D_TDC_READY : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
SEND_TDC_TOKEN : out std_logic;
RECEIVED_TDC_TOKEN : in std_logic;
GET_TDC_DATA : out std_logic;
LVL2_TRIGGER : in std_logic_vector(1 downto 0);
TDC_DATA_OUT : out std_logic_vector(31 downto 0);
TDC_DATA_VALID : out std_logic;
- ETRAX_READ_ONE_kW : in std_logic;
- ETRAX_HAS_TO_READ_EVENT : out std_logic;
ETRAX_IS_READY_TO_READ : in std_logic;
TDC_LVL1_BUSY : out std_logic;
- TDC_LVL2_BUSY : out std_logic);
+ TDC_LVL2_BUSY : out std_logic;
+ TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
+ BUNCH_RESET : out std_logic;
+ EVENT_RESET : out std_logic);
end component;
component lvl1_and_lvl2_busy
port (
LVL2_BUSY : out std_logic;
TDC_LVL1_BUSY : in std_logic;
TDC_LVL2_BUSY : in std_logic;
+ ETRAX_BUSY : in std_logic;
+ ETRAX_BUS_BUSY : in std_logic;
LVL1_TRIGG : in std_logic;
LVL2_TRIGG : in std_logic;
TRIGGER_CODE : in std_logic_vector(3 downto 0);
- TDC_READOUT_COMPLETED : in std_logic
+ TDC_READOUT_COMPLETED : in std_logic;
+ TRIGGER_WITHOUT_HADES : in std_logic
);
end component;
component trigger_logic
port (
CLK : in std_logic;
+ TDC_CLK : in std_logic;
RESET : in std_logic;
LVL1_TRIGGER_CODE : in std_logic_vector(3 downto 0);
LVL1_TRIGGER_TAG : in std_logic_vector(7 downto 0);
LVL1_BUSY : in std_logic;
LVL2_BUSY : in std_logic;
TRB_ACK_LVL1 : out std_logic;
- TRB_ACK_LVL2 : out std_logic);
+ TRB_ACK_LVL2 : out std_logic;
+ TRIGGER_TO_TDC : out std_logic
+ );
end component;
component etrax_interface
port (
RESET : in std_logic;
DATA_BUS : in std_logic_vector(31 downto 0);
ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
DATA_VALID : in std_logic;
ETRAX_BUS_BUSY : out std_logic;
- ETRAX_READ_ONE_kW : in std_logic;
- ETRAX_HAS_TO_READ_EVENT : in std_logic;
- ETRAX_IS_READY_TO_READ : in std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
TDC_TCK : out std_logic;
TDC_TDI : out std_logic;
TDC_TMS : out std_logic;
-- SPI --component !!!
-----------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- EDGE TO PULSE
+ -----------------------------------------------------------------------------
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------
signal lvl2_trigger_i : std_logic_vector(1 downto 0);
signal lvl1_trigger_i : std_logic;
signal trigg_without_hades_i : std_logic;
+ signal trigg_without_hades_t : std_logic;
signal tdc_control_register_i : std_logic_vector(7 downto 0);
signal delay_trigger_i : std_logic_vector(7 downto 0);
signal trb_ack_lvl1_i : std_logic;
signal etrax_bus_busy_i : std_logic; --should go to busy logic !?
signal tdc_lvl1_busy_i : std_logic;
signal tdc_lvl2_busy_i : std_logic;
- signal etrax_read_one_kw_i : std_logic;
- signal etrax_has_to_read_event_i : std_logic;
signal etrax_is_ready_to_read_i : std_logic;
signal tlk_rx_clk_io : std_logic;
signal tlk_clk_io : std_logic;
signal external_debug_i : std_logic;
signal DSP_WRL_i: std_logic;
signal DSP_RD_i: std_logic;
+ signal tdc_register_00_i : std_logic_vector(31 downto 0);
+ signal tdc_control_register_e : std_logic_vector(31 downto 0);
+ signal simulation_00 : std_logic_vector(3 downto 0);
+ signal bunch_reset_i : std_logic;
+ signal event_reset_i : std_logic;
+ signal trigger_to_tdc_i : std_logic;
+ signal trb_status_register_00 : std_logic_vector(31 downto 0);
+ signal token_out_i : std_logic;
+ signal test_en_tdc_clk : std_logic;
+ signal test_en : std_logic;
begin
-----------------------------------------------------------------------------
-- LVDS signals
-----------------------------------------------------------------------------
- IBUFGDS_CLK : IBUFGDS
+ IBUFGDS_CLK : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => CLK,--CLK,
+ I => VIRT_CLK,
+ IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port)
+ );
+ IBUFGDS_TDC_CLK : IBUFGDS
generic map (
- IOSTANDARD => "LVDS_25_DCI")
+ IOSTANDARD => "LVDS_25") --_DCI
port map (
- O => CLK,--CLK,
- I => VIRT_CLK,
- IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port)
+ O => tdc_clk,
+ I => REF_TDC_CLK,
+ IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port)
);
--- BUFG_CLK : BUFG
--- port map(
--- I => internal_clock,
--- O => CLK
--- );
-
-
--- CLK <= tlk_clk_r;
--- IBUFGDS_TDC_CLK : IBUFGDS
--- generic map (
--- IOSTANDARD => "LVDS_25")
--- port map (
--- O => tdc_clk,
--- I => REF_TDC_CLK,
--- IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port)
--- );
--- OBUFDS_TRIGG_A : OBUFDS
--- generic map (
--- -- DRIVE => 12,
--- IOSTANDARD => "LVDS_25"
--- -- SLEW => "SLOW"
--- )
--- port map (
--- O => A_TRIGGER,
--- OB => A_TRIGGERB,
--- I => a_trigg
--- );
--- OBUFDS_TRIGG_B : OBUFDS
--- generic map (
--- IOSTANDARD => "LVDS_25"
--- )
--- port map (
--- O => B_TRIGGER,
--- OB => B_TRIGGERB,
--- I => b_trigg
--- );
--- OBUFDS_TRIGG_C : OBUFDS
--- generic map (
--- IOSTANDARD => "LVDS_25"
--- )
--- port map (
--- O => C_TRIGGER,
--- OB => C_TRIGGERB,
--- I => c_trigg
--- );
--- OBUFDS_TRIGG_D : OBUFDS
--- generic map (
--- IOSTANDARD => "LVDS_25"
--- )
--- port map (
--- O => D_TRIGGER,
--- OB => D_TRIGGERB,
--- I => d_trigg
--- );
- IBUFDS_REFERENCE : IBUFGDS
- generic map (
- IOSTANDARD => "LVDS_25_DCI")
- port map (
- O => reference_signal,
- I => VIR_TRIG,
- IB => VIR_TRIGB
- );
- -----------------------------------------------------------------------------
- -- Component Instance
- -----------------------------------------------------------------------------
- reset_i <= not RESET_VIRT;
-
-
--- TDC_INT: tdc_interface
--- port map (
--- CLK => CLK,
--- TDC_CLK => tdc_clk,
--- RESET => not RESET_VIRT,
--- TDC_RESET => TDC_RESET
--- TDC_DATA_IN => TDC_OUT,
--- START_TDC_READOUT => lvl1_tdc_trigg_i,
--- A_TDC_READY => A_DATA_READY,
--- B_TDC_READY => B_DATA_READY,
--- C_TDC_READY => C_DATA_READY,
--- D_TDC_READY => D_DATA_READY,
--- SEND_TDC_TOKEN => TOKEN_OUT,
--- RECEIVED_TDC_TOKEN => TOKEN_IN,
--- GET_TDC_DATA => GET_DATA,
--- TO_MANY_TDC_DATA => to_many_tdc_data_i,
--- TDC_READOUT_COMPLETED => tdc_readout_completed_i,
--- LVL1_TAG => tdc_tag_i,
--- LVL1_CODE => tdc_code_i,
--- HOW_MANY_ADD_DATA => how_many_add_data_i,
--- COUNTER_a => x"12341234",
--- COUNTER_b => x"12341234",
--- COUNTER_c => x"12341234",
--- COUNTER_d => x"12341234",
--- COUNTER_e => x"12341234",
--- COUNTER_f => x"12341234",
--- COUNTER_g => x"12341234",
--- COUNTER_h => x"12341234",
--- COUNTER_i => x"12341234",
--- COUNTER_j => x"12341234",
--- COUNTER_k => x"12341234",
--- COUNTER_l => x"12341234",
--- COUNTER_m => x"12341234",
--- LVL2_TRIGGER => lvl2_tdc_trigg_i,
--- TDC_DATA_OUT => tdc_data_out_i,
--- TDC_DATA_VALID => tdc_data_valid_i,
--- ETRAX_READ_ONE_kW => etrax_read_one_kw_i,
--- ETRAX_HAS_TO_READ_EVENT => etrax_has_to_read_event_i,
--- ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
--- TDC_LVL1_BUSY => tdc_lvl1_busy_i,
--- TDC_LVL2_BUSY => tdc_lvl2_busy_i);
--- BUSY_LOGIC: lvl1_and_lvl2_busy
--- port map (
--- CLK => CLK,
--- RESET => reset_i,
--- LVL1_BUSY => lvl1_busy_i,
--- LVL2_BUSY => lvl2_busy_i,
--- TDC_LVL1_BUSY => tdc_lvl1_busy_i,
--- TDC_LVL2_BUSY => tdc_lvl2_busy_i,
--- LVL1_TRIGG => lvl1_trigger_i,
--- LVL2_TRIGG => lvl2_trigger_i(0),
--- TRIGGER_CODE => lvl1_trigger_code_i,
--- TDC_READOUT_COMPLETED => tdc_readout_completed_i);
--- TRIGG_LOGIC: trigger_logic
--- port map (
--- CLK => CLK,
--- RESET => reset_i,
--- LVL1_TRIGGER_CODE => lvl1_trigger_code_i,
--- LVL1_TRIGGER_TAG => lvl1_trigger_tag_i,
--- TDC_CODE => tdc_code_i,
--- TDC_TAG => tdc_tag_i,
--- LVL2_TRIGGER => lvl2_trigger_i,
--- LVL1_TRIGGER => lvl1_trigger_i,
--- LVL1_TDC_TRIGG => lvl1_tdc_trigg_i,
--- LVL2_TDC_TRIGG => lvl2_tdc_trigg_i,
--- TRIGG_WITHOUT_HADES => trigg_without_hades_i,
--- TDC_CONTROL_REGISTER => tdc_control_register_i,
--- DELAY_TRIGGER => x"00",--delay_trigger_i,
--- LVL1_BUSY => lvl1_busy_i,
--- LVL2_BUSY => lvl2_busy_i,
--- TRB_ACK_LVL1 => trb_ack_lvl1_i,
--- TRB_ACK_LVL2 => trb_ack_lvl2_i);
- external_valid_i <= dsp_external_valid_i;
- ETRAX_INTERFACE_LOGIC : etrax_interface
- port map (
- CLK => CLK,
- RESET => reset_i,
- DATA_BUS => tdc_data_out_i,
- ETRAX_DATA_BUS_B => FS_PB,
- ETRAX_DATA_BUS_C => FS_PC,
- DATA_VALID => '0',--tdc_data_valid_i,
- ETRAX_BUS_BUSY => etrax_bus_busy_i,
- ETRAX_READ_ONE_kW => etrax_read_one_kw_i,
- ETRAX_HAS_TO_READ_EVENT => etrax_has_to_read_event_i,
- ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
- TDC_TCK => VIRT_TCK,
- TDC_TDI => VIRT_TDI,
- TDC_TMS => VIRT_TMS,
- TDC_TRST => VIRT_TRST,
- TDC_TDO => VIRT_TDO,
- TDC_RESET => TDC_RESET,
- EXTERNAL_ADDRESS => external_address_i,
- EXTERNAL_DATA_OUT => external_data_out_i,
- EXTERNAL_DATA_IN => external_data_in_i,
- EXTERNAL_ACK => external_ack_i,
- EXTERNAL_VALID => external_valid_i,
- EXTERNAL_MODE => external_mode_i,
- FPGA_REGISTER_00 => x"00000000",
- FPGA_REGISTER_01 => tlk_register_00_i,
- FPGA_REGISTER_02 => tlk_register_01_i,
- FPGA_REGISTER_03 => x"abbaab02",
- FPGA_REGISTER_04 => x"abbaab03",
- FPGA_REGISTER_05 => x"abbaab04",
- FPGA_REGISTER_06 => x"abbaab05",
- FPGA_REGISTER_07 => fpga_register_07_i,
- FPGA_REGISTER_08 => x"abbaab07",
- FPGA_REGISTER_09 => x"abbaab08",
- FPGA_REGISTER_10 => x"abbaab09",
- FPGA_REGISTER_11 => x"abbaab10",
- FPGA_REGISTER_12 => x"abbaab11",
- FPGA_REGISTER_13 => x"abbaab12",
- FPGA_REGISTER_14 => x"abbaab13",
- FPGA_REGISTER_15 => dsp_register_00_i,
- FPGA_REGISTER_16 => open,
- FPGA_REGISTER_17 => open,
- FPGA_REGISTER_18 => fpga_register_18_i,
- FPGA_REGISTER_19 => fpga_register_19_i,
- FPGA_REGISTER_20 => fpga_register_20_i,
- FPGA_REGISTER_21 => open,
- FPGA_REGISTER_22 => open,
- FPGA_REGISTER_23 => open,
- FPGA_REGISTER_24 => open,
- FPGA_REGISTER_25 => open,
- FPGA_REGISTER_26 => open,
- FPGA_REGISTER_27 => open,
- FPGA_REGISTER_28 => open,
- FPGA_REGISTER_29 => open,
- FPGA_REGISTER_30 => open,
- FPGA_REGISTER_31 => open,
- EXTERNAL_RESET => external_reset_i);
- TLK_RX_CLK_BUFR: BUFR
- port map(
- CE => '1',
- CLR => '0',
- I => TLK_RX_CLK,
- O => tlk_rx_clk_r
+ IBUFDS_TRIGG_A : OBUFDS
+ port map (
+ O => A_TRIGGER,
+ OB => A_TRIGGERB,
+ I => a_trigg
);
-
+ IBUFDS_TRIGG_B : OBUFDS
+ port map (
+ O => B_TRIGGER,
+ OB => B_TRIGGERB,
+ I => b_trigg
+ );
+ IBUFDS_TRIGG_C : OBUFDS
+ port map (
+ O => C_TRIGGER,
+ OB => C_TRIGGERB,
+ I => c_trigg
+ );
+ IBUFDS_TRIGG_D : OBUFDS
+ port map (
+ O => D_TRIGGER,
+ OB => D_TRIGGERB,
+ I => d_trigg
+ );
+ IBUFDS_REFERENCE : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => reference_signal,
+ I => VIR_TRIG,
+ IB => VIR_TRIGB
+ );
+ OBUFDS_BUNCH_RESET : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => TDC_BU_RESET,
+ OB =>TDC_BU_RESETB ,
+ I => bunch_reset_i
+ );
+ OBUFDS_EVENT_RESET : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => TDC_EV_RESET,
+ OB =>TDC_EV_RESETB ,
+ I => event_reset_i
+ );
+-- A_TRIGGER <= a_trigg;
+-- B_TRIGGER <= a_trigg;
+-- C_TRIGGER <= a_trigg;
+-- D_TRIGGER <= a_trigg;
+
+-- TDC_EV_RESET <= event_reset_i;
+-- TDC_BU_RESET <= bunch_reset_i;
+ -----------------------------------------------------------------------------
+ -- Component Instance
+ -----------------------------------------------------------------------------
+ reset_i <= not RESET_VIRT;
+ TOKEN_OUT <= token_out_i or trigger_to_tdc_i;
+ -- LONG_TOKEN: process (TDC_CLK, external_reset_i)
+ -- begin -- process LONG_TOKEN
+ -- if rising_edge(TDC_CLK) then -- rising clock edge
+ -- if external_reset_i = '1' or A_DATA_READY = '1' then -- asynchronous reset (active low)
+ -- TOKEN_OUT <= '0';
+ -- trigger_to_tdc_i <= '0';
+ -- elsif token_out_i = '1' then
+ -- TOKEN_OUT <= '1';
+ -- trigger_to_tdc_i <= '1';
+
+ -- end if;
+ -- end if;
+ -- end process LONG_TOKEN;
+
+ TDC_INT: tdc_interface
+ port map (
+ CLK => CLK,
+ TDC_CLK => tdc_clk,
+ RESET => external_reset_i,--not RESET_VIRT,
+ -- TDC_RESET => TDC_RESET,
+ TDC_DATA_IN => TDC_OUT,
+ START_TDC_READOUT => lvl1_tdc_trigg_i,
+ A_TDC_ERROR => A_TDC_ERROR,
+ B_TDC_ERROR => B_TDC_ERROR,
+ C_TDC_ERROR => C_TDC_ERROR,
+ D_TDC_ERROR => D_TDC_ERROR,
+ A_TDC_POWERUP => open, --A_TDC_POWERUP,
+ B_TDC_POWERUP => open, --B_TDC_POWERUP,
+ C_TDC_POWERUP => open, --C_TDC_POWERUP,
+ D_TDC_POWERUP => open, --D_TDC_POWERUP,
+ A_TDC_READY => A_DATA_READY,
+ B_TDC_READY => B_DATA_READY,
+ C_TDC_READY => C_DATA_READY,
+ D_TDC_READY => D_DATA_READY,
+ SEND_TDC_TOKEN => token_out_i,
+ RECEIVED_TDC_TOKEN => TOKEN_IN,
+ GET_TDC_DATA => GET_DATA,
+ TO_MANY_TDC_DATA => to_many_tdc_data_i,
+ TDC_READOUT_COMPLETED => tdc_readout_completed_i,
+ LVL1_TAG => tdc_tag_i,
+ LVL1_CODE => tdc_code_i,
+ HOW_MANY_ADD_DATA => how_many_add_data_i,
+ COUNTER_a => x"12311231",
+ COUNTER_b => x"12321232",
+ COUNTER_c => x"12331233",
+ COUNTER_d => x"12341234",
+ COUNTER_e => x"12351235",
+ COUNTER_f => x"12361236",
+ COUNTER_g => x"12371237",
+ COUNTER_h => x"12381238",
+ COUNTER_i => x"12391239",
+ COUNTER_j => x"123a123a",
+ COUNTER_k => x"123b123b",
+ COUNTER_l => x"123c123c",
+ COUNTER_m => x"123d123d",
+ LVL2_TRIGGER => lvl2_tdc_trigg_i,
+ TDC_DATA_OUT => tdc_data_out_i,
+ TDC_DATA_VALID => tdc_data_valid_i,
+ ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+ TDC_LVL1_BUSY => tdc_lvl1_busy_i,
+ TDC_LVL2_BUSY => tdc_lvl2_busy_i,
+ TDC_REGISTER_00 => tdc_register_00_i,
+ BUNCH_RESET => bunch_reset_i,
+ EVENT_RESET => event_reset_i);
+-- -------------------------------------------------------------------------------
+-- -- sim
+-- -------------------------------------------------------------------------------
+ how_many_add_data_i <= x"05"; --put this to etrax register !!!!
+ lvl1_trigger_i <= A_TEMP;
+ simulation_00 <= A_RESERVED & B_RESERVED & C_RESERVED & D_RESERVED;
+ lvl2_trigger_i <= B_TEMP & C_TEMP;
+ tdc_tag_i <= x"ab";
+ tdc_code_i <= simulation_00;
+-- -------------------------------------------------------------------------------
+-- -- end sim
+-- -------------------------------------------------------------------------------
+ BUSY_LOGIC: lvl1_and_lvl2_busy
+ port map (
+ CLK => CLK,
+ RESET => external_reset_i,
+ LVL1_BUSY => lvl1_busy_i,
+ LVL2_BUSY => lvl2_busy_i,
+ TDC_LVL1_BUSY => tdc_lvl1_busy_i,
+ TDC_LVL2_BUSY => tdc_lvl2_busy_i,
+ ETRAX_BUS_BUSY => etrax_bus_busy_i,
+ ETRAX_BUSY => FS_PC(17),
+ LVL1_TRIGG => lvl1_trigger_i,
+ LVL2_TRIGG => lvl2_trigger_i(0),
+ TRIGGER_CODE => lvl1_trigger_code_i,
+ TDC_READOUT_COMPLETED => tdc_readout_completed_i,
+ TRIGGER_WITHOUT_HADES => trigg_without_hades_i
+ );
+-- trigg_without_hades_i <= TDC_CLK;
+ SYNCH_EXT_TRIGG: process (CLK, external_reset_i)
+ begin -- process SYNCH_EXT_TRIGG
+ if rising_edge(CLK) then -- rising clock edge
+ if external_reset_i = '1' then -- asynchronous reset (active low)
+ trigg_without_hades_i <= '0';
+ else
+ trigg_without_hades_i <= TDC_CLK and tdc_control_register_e(0) and (not lvl1_busy_i);
+ end if;
+ end if;
+ end process SYNCH_EXT_TRIGG;
+
+ TRIGG_LOGIC : trigger_logic
+ port map (
+ CLK => CLK,
+ TDC_CLK => TDC_CLK,
+ RESET => external_reset_i,
+ LVL1_TRIGGER_CODE => lvl1_trigger_code_i,
+ LVL1_TRIGGER_TAG => lvl1_trigger_tag_i,
+ TDC_CODE => tdc_code_i,
+ TDC_TAG => tdc_tag_i,
+ LVL2_TRIGGER => lvl2_trigger_i,
+ LVL1_TRIGGER => lvl1_trigger_i,
+ LVL1_TDC_TRIGG => lvl1_tdc_trigg_i,
+ LVL2_TDC_TRIGG => lvl2_tdc_trigg_i,
+ TRIGG_WITHOUT_HADES => trigg_without_hades_i,
+ TDC_CONTROL_REGISTER => tdc_control_register_i,
+ DELAY_TRIGGER => x"00", --delay_trigger_i,
+ LVL1_BUSY => lvl1_busy_i,
+ LVL2_BUSY => lvl2_busy_i,
+ TRB_ACK_LVL1 => trb_ack_lvl1_i,
+ TRB_ACK_LVL2 => trb_ack_lvl2_i,
+ TRIGGER_TO_TDC => trigger_to_tdc_i
+ );
+
+ a_trigg <= trigger_to_tdc_i;
+ b_trigg <= trigger_to_tdc_i;
+ c_trigg <= trigger_to_tdc_i;
+ d_trigg <= trigger_to_tdc_i;
+-- external_valid_i <= dsp_external_valid_i;
+ tdc_control_register_i <= tdc_control_register_e(7 downto 0);
- TLK_CLK_BUFR: BUFR
+ ETRAX_INTERFACE_LOGIC : etrax_interface
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+ DATA_BUS => tdc_data_out_i,
+ ETRAX_DATA_BUS_B => FS_PB,
+ ETRAX_DATA_BUS_C => FS_PC,
+ DATA_VALID => tdc_data_valid_i,
+ ETRAX_BUS_BUSY => etrax_bus_busy_i,
+ ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+ TDC_TCK => VIRT_TCK,
+ TDC_TDI => VIRT_TDI,
+ TDC_TMS => VIRT_TMS,
+ TDC_TRST => open, --VIRT_TRST,
+ TDC_TDO => VIRT_TDO,
+ TDC_RESET => open, --TDC_RESET,
+ EXTERNAL_ADDRESS => external_address_i,
+ EXTERNAL_DATA_OUT => external_data_out_i,
+ EXTERNAL_DATA_IN => external_data_in_i,
+ EXTERNAL_ACK => external_ack_i,
+ EXTERNAL_VALID => external_valid_i,
+ EXTERNAL_MODE => external_mode_i,
+ FPGA_REGISTER_00 => x"00000000",
+ FPGA_REGISTER_01 => tlk_register_00_i,
+ FPGA_REGISTER_02 => tlk_register_01_i,
+ FPGA_REGISTER_03 => tdc_register_00_i,--x"abbaab02",
+ FPGA_REGISTER_04 => x"abbaab03",
+ FPGA_REGISTER_05 => x"abbaab04",
+ FPGA_REGISTER_06 => x"abbaab05",
+ FPGA_REGISTER_07 => fpga_register_07_i,
+ FPGA_REGISTER_08 => x"abbaab07",
+ FPGA_REGISTER_09 => x"abbaab08",
+ FPGA_REGISTER_10 => x"abbaab09",
+ FPGA_REGISTER_11 => x"abbaab10",
+ FPGA_REGISTER_12 => x"abbaab11",
+ FPGA_REGISTER_13 => x"abbaab12",
+ FPGA_REGISTER_14 => x"abbaab13",
+ FPGA_REGISTER_15 => dsp_register_00_i,
+ FPGA_REGISTER_16 => open, --used in etrax int
+ FPGA_REGISTER_17 => open, --used in etrax int
+ FPGA_REGISTER_18 => fpga_register_18_i,
+ FPGA_REGISTER_19 => fpga_register_19_i,
+ FPGA_REGISTER_20 => fpga_register_20_i,
+ FPGA_REGISTER_21 => tdc_control_register_e,
+ FPGA_REGISTER_22 => open,
+ FPGA_REGISTER_23 => open,
+ FPGA_REGISTER_24 => open,
+ FPGA_REGISTER_25 => open,
+ FPGA_REGISTER_26 => open,
+ FPGA_REGISTER_27 => open,
+ FPGA_REGISTER_28 => open,
+ FPGA_REGISTER_29 => open,
+ FPGA_REGISTER_30 => open,
+ FPGA_REGISTER_31 => open,
+ EXTERNAL_RESET => external_reset_i);
+ TLK_RX_CLK_BUFR: BUFR
port map(
CE => '1',
CLR => '0',
- I => TLK_CLK,
- O => tlk_clk_r
- );
- tlk_interface_logic: tlk_interface
- port map (
- VIRT_CLK => CLK,
- ENABLE => TLK_ENABLE,
- LCKREFN => TLK_LCKREFN,
- LOOPEN => TLK_LOOPEN,
- PRBSEN => TLK_PRBSEN,
- RX_CLK => tlk_rx_clk_r,
- RX_DV => TLK_RX_DV,
- RX_ER => TLK_RX_ER,
- TLK_CLK => tlk_clk_r,
- TLK_RXD => TLK_RXD,
- TLK_TXD => TLK_TXD,
- TX_EN => TLK_TX_EN,
- TX_ER => TLK_TX_ER,
- RESET_VIRT => reset_i,
- TLK_REGISTER_00 => tlk_register_00_i,
- TLK_REGISTER_01 => tlk_register_01_i
- );
- dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
+ I => TLK_RX_CLK,
+ O => tlk_rx_clk_r
+ );
+ TLK_CLK_BUFR: BUFR
+ port map(
+ CE => '1',
+ CLR => '0',
+ I => TLK_CLK,
+ O => tlk_clk_r
+ );
+ tlk_interface_logic: tlk_interface
+ port map (
+ VIRT_CLK => CLK,
+ ENABLE => TLK_ENABLE,
+ LCKREFN => TLK_LCKREFN,
+ LOOPEN => TLK_LOOPEN,
+ PRBSEN => TLK_PRBSEN,
+ RX_CLK => tlk_rx_clk_r,
+ RX_DV => TLK_RX_DV,
+ RX_ER => TLK_RX_ER,
+ TLK_CLK => tlk_clk_r,
+ TLK_RXD => TLK_RXD,
+ TLK_TXD => TLK_TXD,
+ TX_EN => TLK_TX_EN,
+ TX_ER => TLK_TX_ER,
+ RESET_VIRT => external_reset_i,
+ TLK_REGISTER_00 => tlk_register_00_i,
+ TLK_REGISTER_01 => tlk_register_01_i
+ );
+ dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
- DSP_INTERFACE_LOGIC: dsp_interface
- port map (
- HBR_OUT => dsp_hbr_i,
- HBG_IN => DSP_HBG,
- RD_OUT => DSP_RD_i,
- DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP,
- DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA,
- ADDRESS_DSP => dspaddr_i,--DSPADDR,
- WRL => DSP_WRL_i,
- WRH => DSP_WRH,
- BM_IN => DSP_BM,
- DSP_RESET => open,
- BRST => DSP_BRST,
- ACK => DSP_ACK,
- CLK => CLK,
- RESET => external_reset_i,
- R_W_ENABLE => external_mode_i(15),
- TRIGGER => dsp_strobe_i,
- INTERNAL_DATA_IN => external_data_out_i,
- INTERNAL_DATA_OUT => external_data_in_i,
- INTERNAL_ADDRESS => external_address_i,
- VALID_DATA_SENT => dsp_external_valid_i,
- ACKNOWLEDGE => dsp_strobe_i,
- DEBUGSTATE_MACHINE => dsp_register_00_i);
+ DSP_INTERFACE_LOGIC: dsp_interface
+ port map (
+ HBR_OUT => dsp_hbr_i,
+ HBG_IN => DSP_HBG,
+ RD_OUT => DSP_RD_i,
+ DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP,
+ DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA,
+ ADDRESS_DSP => dspaddr_i,--DSPADDR,
+ WRL => DSP_WRL_i,
+ WRH => DSP_WRH,
+ BM_IN => DSP_BM,
+ DSP_RESET => open,
+ BRST => DSP_BRST,
+ ACK => DSP_ACK,
+ CLK => CLK,
+ RESET => external_reset_i,
+ R_W_ENABLE => external_mode_i(15),
+ TRIGGER => dsp_strobe_i,
+ INTERNAL_DATA_IN => external_data_out_i,
+ INTERNAL_DATA_OUT => external_data_in_i,
+ INTERNAL_ADDRESS => external_address_i,
+ VALID_DATA_SENT => dsp_external_valid_i,
+ ACKNOWLEDGE => dsp_strobe_i,
+ DEBUGSTATE_MACHINE => dsp_register_00_i);
- SFP_TX_DIS <= '0';
- ETRAX_IRQ <= '1';
- DBAD <= '0';
- DGOOD <= '1';
- DINT <= '1';
- DWAIT <= fpga_register_20_i(0); --'0'enable clock for TDC
+ SFP_TX_DIS <= '0';
+ ETRAX_IRQ <= '1';
+ DBAD <= lvl1_busy_i;
+ DGOOD <= lvl2_busy_i;
+ --DINT <= '1';
+ DINT <= etrax_bus_busy_i;
+ DWAIT <= fpga_register_20_i(0); --'0'enable clock for TDC
- DSP_RESET <= fpga_register_19_i(1);
- DSP_HBR <= dsp_hbr_i;
- DSPDAT <= dspdat_out_i;
- dspdat_in_i <= DSPDAT;
- DSP_WRL <= DSP_WRL_i;
- DSP_RD <= DSP_RD_i;
--- DSP_HBR <= '1';
- fpga_register_07_i <= x"000000" &"0"& DSP_ACK & dsp_register_00_i(2 downto 0)& DSP_HBG & dsp_hbr_i&dsp_strobe_i;
- --ADO_TTL <= dspdat_i(15 downto 0) & DSPADDR(15 downto 0) &
- --CLK & fpga_register_07_i(6 downto 0);
- DSPADDR <= dspaddr_i;
- DSP_BOFF <= '1';
- ADO_TTL <= "000" & x"0000000" & DSP_WRL_i & DSP_RD_i & "0" &
- dspdat_in_i(4 downto 0) & dspdat_out_i(4 downto 0)
- & CLK & fpga_register_07_i(2 downto 1);
+ DSP_RESET <= fpga_register_19_i(1);
+ DSP_HBR <= dsp_hbr_i;
+ DSPDAT <= dspdat_out_i;
+ dspdat_in_i <= DSPDAT;
+ DSP_WRL <= DSP_WRL_i;
+ DSP_RD <= DSP_RD_i;
+ -- DSP_HBR <= '1';
+ fpga_register_07_i <= x"000000" &"0"& DSP_ACK & dsp_register_00_i(2 downto 0)& DSP_HBG & dsp_hbr_i&dsp_strobe_i;
+ --ADO_TTL <= dspdat_i(15 downto 0) & DSPADDR(15 downto 0) &
+ --CLK & fpga_register_07_i(6 downto 0);
+ DSPADDR <= dspaddr_i;
+ DSP_BOFF <= '1';
+ -- ADO_TTL <= "000" & x"0000000" & DSP_WRL_i & DSP_RD_i & "0" &
+ -- dspdat_in_i(4 downto 0) & dspdat_out_i(4 downto 0)
+ -- & CLK & fpga_register_07_i(2 downto 1);
+ ADO_TTL <= "000" & x"0000000" & tdc_register_00_i(20) & clk & bunch_reset_i & TOKEN_IN & trigger_to_tdc_i & token_out_i & lvl1_tdc_trigg_i & A_DATA_READY & B_DATA_READY & C_DATA_READY & D_DATA_READY & etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i;
+ -- trb_status_register_00 <= etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i;
+ -- clk & tdc_clk & event_reset_i no & bunch_reset_i no & trigger_to_tdc_i yes & TOKEN_
+ -- OUT '1' & lvl1_tdc_trigg_i yes & A_DATA_READY no & B_DATA_READY no & C_DATA_
+ -- READY no & D_DATA_READY no & etrax_bus_busy_i yes & tdc_lvl2_busy_i no & tdc_lvl1_busy_i & lvl2_busy_
+ -- i constant 1 & lvl1_busy_i constatn 1;
+ TDC_RESET <= '0';
+ VIRT_TRST <= '1';
+ A_TDC_POWERUP <= '1';
+ B_TDC_POWERUP <= '1';
+ C_TDC_POWERUP <= '1';
+ D_TDC_POWERUP <= '1';
+-- FS_PB <= (others => 'Z');
end trb_v2a_fpga;
add_file -vhdl -lib work "simpleupcounter_10bit.vhd"
add_file -vhdl -lib work "simpleupcounter_16bit.vhd"
add_file -vhdl -lib work "dsp_interface.vhd"
+#add_file -vhdl -lib work "lvl1_memory.vhd"
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
-#add_file -vhdl -lib work ""
-add_file -constraint "trb_v2a_fpga_syn.sdc"
+#add_file -constraint "trb_v2a_fpga_syn.sdc"
#implementation: "workdir"
#
# Clocks
#
-define_clock -name {CLK} -freq 100.000 -clockgroup default_clkgroup_0
+define_clock -name {clk} -freq 100.000 -clockgroup
+#default_clkgroup_0
+#define_clock -name {tdc_clk} -freq 40.000 -clockgroup
define_clock -name {tlk_rx_clk_r} -freq 100.000 -clockgroup default_clkgroup_2
define_clock -name {tlk_clk_r} -freq 100.000 -clockgroup default_clkgroup_3
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
-ENTITY rpc_trb_v2_fpga_tb_vhd IS
-END rpc_trb_v2_fpga_tb_vhd;
+ENTITY trb_v2_fpga_tb_vhd IS
+END trb_v2_fpga_tb_vhd;
-ARCHITECTURE behavior OF rpc_trb_v2_fpga_tb_vhd IS
+ARCHITECTURE behavior OF trb_v2_fpga_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
- COMPONENT rpc_trb_v2_fpga
+ COMPONENT trb_v2a_fpga
PORT(
VIRT_CLK : IN std_logic;
VIRT_CLKB : IN std_logic;
DGOOD : OUT std_logic;
DINT : OUT std_logic;
DWAIT : OUT std_logic;
- TDC_RESET : OUT std_logic;
+
FS_PB : OUT std_logic_vector(17 downto 0);
ETRAX_IRQ : OUT std_logic;
DSPADDR : OUT std_logic_vector(31 downto 0);
DSP_BRST : inout std_logic;
DSP_ACK : in std_logic;
DSP_BM : in std_logic;
- ADO_TTL : out std_logic_vector(46 downto 0)
- );
+ ADO_TTL : out std_logic_vector(46 downto 0);
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ TDC_BU_RESET : out std_logic;
+ TDC_BU_RESETB : out std_logic;
+ TDC_EV_RESET : out std_logic;
+ TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic
+ );
END COMPONENT;
--Inputs
SIGNAL DGOOD : std_logic;
SIGNAL DINT : std_logic;
SIGNAL DWAIT : std_logic;
- SIGNAL TDC_RESET : std_logic;
SIGNAL FS_PB : std_logic_vector(17 downto 0);
SIGNAL ETRAX_IRQ : std_logic;
SIGNAL DSPADDR : std_logic_vector(31 downto 0);
SIGNAL DSP_RESET : std_logic;
SIGNAL DSP_BRST : std_logic;
SIGNAL DSP_ACK : std_logic;
- SIGNAL DSP_BM : std_logic;
+ SIGNAL DSP_BM : std_logic;
+ SIGNAL A_TDC_ERROR : std_logic;
+ SIGNAL B_TDC_ERROR : std_logic;
+ SIGNAL C_TDC_ERROR : std_logic;
+ SIGNAL D_TDC_ERROR : std_logic;
+ SIGNAL A_TDC_POWERUP : std_logic; --turn on TDC -should be one ?!
+ SIGNAL B_TDC_POWERUP : std_logic;
+ SIGNAL C_TDC_POWERUP : std_logic;
+ SIGNAL D_TDC_POWERUP : std_logic;
+ SIGNAL TOKEN_IN : std_logic;
+ SIGNAL TOKEN_OUT : std_logic;
+ SIGNAL C_TOKEN_OUT_TTL : std_logic;
+ SIGNAL GET_DATA : std_logic;
+ SIGNAL A_DATA_READY : std_logic;
+ SIGNAL B_DATA_READY : std_logic;
+ SIGNAL C_DATA_READY : std_logic;
+ SIGNAL D_DATA_READY : std_logic;
+ SIGNAL REF_TDC_CLK : std_logic;
+ SIGNAL REF_TDC_CLKB : std_logic;
+ SIGNAL TDC_BU_RESET : std_logic;
+ SIGNAL TDC_BU_RESETB : std_logic;
+ SIGNAL TDC_EV_RESET : std_logic;
+ SIGNAL TDC_EV_RESETB : std_logic;
+ SIGNAL TDC_OUT : std_logic_vector (31 downto 0);
+ SIGNAL TDC_RESET : std_logic;
+ SIGNAL A_TRIGGER : std_logic;
+ SIGNAL A_TRIGGERB : std_logic;
+ SIGNAL B_TRIGGER : std_logic;
+ SIGNAL B_TRIGGERB : std_logic;
+ SIGNAL C_TRIGGER : std_logic;
+ SIGNAL C_TRIGGERB : std_logic;
+ SIGNAL D_TRIGGER : std_logic;
+ SIGNAL D_TRIGGERB : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
- uut: rpc_trb_v2_fpga PORT MAP(
+ uut: trb_v2a_fpga PORT MAP(
VIRT_CLK => VIRT_CLK,
VIRT_CLKB => VIRT_CLKB,
RESET_VIRT => RESET_VIRT,
D_TEMP => D_TEMP,
VIR_TRIG => VIR_TRIG,
VIR_TRIGB => VIR_TRIGB,
- TDC_RESET => TDC_RESET,
FS_PB => FS_PB,
FS_PC => FS_PC,
ETRAX_IRQ => ETRAX_IRQ,
DSP_WRL => DSP_WRL,
DSP_BRST => DSP_BRST,
DSP_ACK => DSP_ACK,
- DSP_BM => DSP_BM
+ DSP_BM => DSP_BM,
+ A_TDC_ERROR => A_TDC_ERROR ,
+ B_TDC_ERROR => B_TDC_ERROR ,
+ C_TDC_ERROR => C_TDC_ERROR ,
+ D_TDC_ERROR => D_TDC_ERROR ,
+ A_TDC_POWERUP => A_TDC_POWERUP , --turn on TDC -should be one ?!
+ B_TDC_POWERUP => B_TDC_POWERUP ,
+ C_TDC_POWERUP => C_TDC_POWERUP ,
+ D_TDC_POWERUP => D_TDC_POWERUP ,
+ TOKEN_IN => TOKEN_IN ,
+ TOKEN_OUT => TOKEN_OUT ,
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL ,
+ GET_DATA => GET_DATA ,
+ A_DATA_READY => A_DATA_READY ,
+ B_DATA_READY => B_DATA_READY ,
+ C_DATA_READY => C_DATA_READY ,
+ D_DATA_READY => D_DATA_READY ,
+ REF_TDC_CLK => REF_TDC_CLK ,
+ REF_TDC_CLKB => REF_TDC_CLKB ,
+ TDC_BU_RESET => TDC_BU_RESET ,
+ TDC_BU_RESETB => TDC_BU_RESETB ,
+ TDC_EV_RESET => TDC_EV_RESET ,
+ TDC_EV_RESETB => TDC_EV_RESETB ,
+ TDC_OUT => TDC_OUT ,
+ TDC_RESET => TDC_RESET ,
+ A_TRIGGER => A_TRIGGER ,
+ A_TRIGGERB => A_TRIGGERB ,
+ B_TRIGGER => B_TRIGGER ,
+ B_TRIGGERB => B_TRIGGERB ,
+ C_TRIGGER => C_TRIGGER ,
+ C_TRIGGERB => C_TRIGGERB ,
+ D_TRIGGER => D_TRIGGER ,
+ D_TRIGGERB => D_TRIGGERB
);
etrax_intf : PROCESS
--reading DSP(dev number 1)
wait for 10 ns;
RESET_VIRT <= '0';
+
wait for 10 ns;
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '1';
RESET_VIRT <= '1';
wait for 10 ns;
+
+ wait for 30 ns;
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait for 10 ns;
FS_PC(15 downto 0) <= x"0000";
FS_PC(16) <= '0';
FS_PC(17) <= '0';
+ wait on VIRT_CLK until FS_PB(16) = '0';
wait for 20 ns;
FS_PC(16) <= '1';
wait for 20 ns;
FS_PC(15) <= '1'; --read mode
FS_PC(14 downto 8) <= (others => '0');
- FS_PC(7 downto 0) <= x"01"; --device
+ FS_PC(7 downto 0) <= x"00"; --device
FS_PC(16) <= '0';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
FS_PC(16) <= '1';
- FS_PC(15 downto 0) <= x"0005"; --adrees lower part
+ FS_PC(15 downto 0) <= x"0025"; --adrees lower part
FS_PC(16) <= '1';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
- wait until FS_PB(16)= '1';
+ wait on VIRT_CLK until FS_PB(16)= '1';
FS_PC(16) <= '1';
wait for 20 ns;
FS_PC(16) <= '0';
- wait until FS_PB(16) = '0';
+ wait on VIRT_CLK until FS_PB(16) = '0';
FS_PC(16) <= '1';
wait for 20 ns;
FS_PC(16) <= '0';
- wait until FS_PB(16)= '1';
+ wait on VIRT_CLK until FS_PB(16)= '1';
FS_PC(16) <= '1';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
FS_PC(15) <= '0'; --write mode
FS_PC(14 downto 8) <= (others => '0');
- FS_PC(7 downto 0) <= x"01"; --device
+ FS_PC(7 downto 0) <= x"00"; --device
FS_PC(16) <= '0';
FS_PC(17) <= '0';
wait for 20 ns;
- FS_PC(15 downto 0) <= x"6754"; --address upper part
+ FS_PC(15 downto 0) <= x"0000"; --address upper part
FS_PC(16) <= '1';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
FS_PC(16) <= '1';
- FS_PC(15 downto 0) <= x"ad05"; --adrees lower part
+ FS_PC(15 downto 0) <= x"0021"; --adrees lower part
FS_PC(16) <= '1';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
- FS_PC(15 downto 0) <= x"dada"; --data upper part
+ FS_PC(15 downto 0) <= x"0000"; --data upper part
FS_PC(16) <= '1';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
- FS_PC(15 downto 0) <= x"baca"; --data upper part
+ FS_PC(15 downto 0) <= x"0001"; --data upper part
FS_PC(16) <= '1';
FS_PC(17) <= '0';
wait for 20 ns;
FS_PC(16) <= '0';
wait for 20 ns;
test_synch_00 <= '0';
- wait until FS_PB(16)= '1';
FS_PC(16) <= '1';
wait for 20 ns;
FS_PC(16) <= '0';
-
--- process
--- begin
--- VIRT_CLK <= '0';
--- VIRT_CLKB <= '1';
--- wait for 10 ns;
--- VIRT_CLKB <= '0';
--- VIRT_CLK <= '1';
--- wait for 10 ns;
--- end process;
- -- Place stimulus here
-
+ wait on VIRT_CLK until FS_PB(16)= '1';
wait; -- will wait forever
end process;
DSP_HBG <= '1';
wait for 20 ns;
DSPDAT <= (others => 'Z');
- wait until DSP_HBR = '0';
+ wait on VIRT_CLK until DSP_HBR = '0';
wait for 8 ns;
DSP_HBG <= '0';
DSPDAT <= x"babeface";
wait for 10 ns;
DSP_ACK <= '1';
- wait until DSP_HBR = '1';
+ wait on VIRT_CLK until DSP_HBR = '1';
DSP_ACK <= '0';
DSP_HBG <= '1';
DSPDAT <= (others => 'Z');
- wait until test_synch_00 = '1';
- wait until DSP_HBR = '0';
+ wait on VIRT_CLK until test_synch_00 = '1';
+ wait on VIRT_CLK until DSP_HBR = '0';
wait for 8 ns;
DSP_HBG <= '0';
wait until DSP_HBR = '1';
TLK_RXD <= TLK_TXD;
--TLK_RX_ER <= '0';
TLK_RX_DV <= '1';
-
+ -----------------------------------------------------------------------
+ -- TDC
+ -----------------------------------------------------------------------
+ clock_tdcclk : process
+ begin
+ REF_TDC_CLK <= '0';
+ REF_TDC_CLKB <= '1';
+ wait for 12.5 ns;
+ REF_TDC_CLK <= '1';
+ REF_TDC_CLKB <= '0';
+ wait for 12.5 ns;
+ end process;
+ trigger_lvl1 : process
+ begin
+ A_DATA_READY <= '0';
+ B_DATA_READY <= '0';
+ C_DATA_READY <= '0';
+ D_DATA_READY <= '0';
+ TOKEN_IN <= '0';
+ TDC_OUT <= x"bedebabe";
+-- A_TEMP <= '0';
+-- wait for 50 ns;
+-- A_TEMP <= '1';
+-- wait for 10 ns;
+-- A_TEMP <= '0';
+-- wait for 10 ns;
+ wait on REF_TDC_CLK until TOKEN_OUT = '1';
+ wait on REF_TDC_CLK until TOKEN_OUT = '0';
+ wait for 10 ns;
+ A_DATA_READY <= '1';
+ wait for 50 ns;
+ A_DATA_READY <= '0';
+ B_DATA_READY <= '1';
+ wait for 50 ns;
+ B_DATA_READY <= '0';
+ C_DATA_READY <= '1';
+ wait for 50 ns;
+ C_DATA_READY <= '0';
+ D_DATA_READY <= '1';
+ wait for 50 ns;
+ D_DATA_READY <= '0';
+ wait for 50 ns;
+ TOKEN_IN <= '1';
+ wait for 25 ns;
+ TOKEN_IN <= '0';
+ wait on REF_TDC_CLK until DBAD = '0';
+ end process;
+-- trigger_lvl2 : process
+-- begin
+-- B_TEMP <= '0';
+-- C_TEMP <= '0';
+-- wait until DBAD = '1';
+-- wait until DBAD = '0';
+-- wait for 30 ns;
+-- wait on VIRT_CLK until DGOOD = '0';
+-- B_TEMP <= '0';
+-- C_TEMP <= '1';
+-- wait for 30 ns;
+-- end process;
END;
port (
CLK : in std_logic;
+ TDC_CLK : in std_logic;
RESET : in std_logic;
LVL1_TRIGGER_CODE : in std_logic_vector(3 downto 0);
LVL1_TRIGGER_TAG : in std_logic_vector(7 downto 0);
LVL1_BUSY : in std_logic;
LVL2_BUSY : in std_logic;
TRB_ACK_LVL1 : out std_logic;
- TRB_ACK_LVL2 : out std_logic
+ TRB_ACK_LVL2 : out std_logic;
+ TRIGGER_TO_TDC : out std_logic
);
end trigger_logic;
signal delay_qout : std_logic_vector(16 downto 0);
signal lvl1_trigger_pulse_start : std_logic;
signal lvl1_trigger_pulse_delay : std_logic;
+ signal lvl1_tdc_trigg_i : std_logic;
+ signal not_tdc_clk : std_logic;
begin
end if;
end process DELAY_FSM_CLOCK;
-- purpose: delay trigger whitch is sending to TDC
- TO_DELAY_TRIGG : process (CLK)
+ TO_DELAY_TRIGG : process (CLK,lvl1_trigger_pulse,delay_qout,DELAY_TRIGGER)
begin -- process TO_DELAY_TRIGG
case (delay_fsm_currentstate) is
when IDLE =>
end case;
end process TO_DELAY_TRIGG;
lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
- SAVE_LVL1_TRIGG_VALUES : process (CLK, RESET)
+ SAVE_LVL1_TRIGG_VALUES : process (CLK, RESET,lvl1_trigger_pulse)
begin
if rising_edge(CLK) then
if RESET = '1' then
end if;
end if;
end process LVL1_START;
- LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, CLK,lvl1_trigger_pulse_start)
+ LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, CLK,lvl1_trigger_pulse_start,ACK_LVL1_STATE,TRIGG_WITHOUT_HADES,TDC_CONTROL_REGISTER,LVL1_BUSY,LVL2_BUSY)
begin
case (LVL1_START_fsm_currentstate) is
when IDLE =>
- LVL1_TDC_TRIGG <= '0';
+ lvl1_tdc_trigg_i <= '0';
if (lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE /= x"d") or
(TRIGG_WITHOUT_HADES ='1' and TDC_CONTROL_REGISTER(0) = '1') then
LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
LVL1_START_fsm_nextstate <= IDLE;
end if;
when SEND_LVL1_TRIGG_1 => --4 clock of 100MHz - to generate token
- LVL1_TDC_TRIGG <= '1';
+ lvl1_tdc_trigg_i <= '1';
LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_2;
when SEND_LVL1_TRIGG_2 =>
- LVL1_TDC_TRIGG <= '1';
+ lvl1_tdc_trigg_i <= '1';
LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_3;
when SEND_LVL1_TRIGG_3 =>
- LVL1_TDC_TRIGG <= '1';
+ lvl1_tdc_trigg_i <= '1';
LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_4;
when SEND_LVL1_TRIGG_4 =>
- LVL1_TDC_TRIGG <= '1';
+ lvl1_tdc_trigg_i <= '0';
LVL1_START_fsm_nextstate <= WAIT_FOR_ACK;
when WAIT_FOR_ACK =>
- LVL1_TDC_TRIGG <= '0';
+ lvl1_tdc_trigg_i <= '0';
if ACK_LVL1_STATE = ACK_LVL1_pulse_1 then
LVL1_START_fsm_nextstate <= IDLE;
else
end if;
when others =>
LVL1_START_fsm_nextstate <= IDLE;
- LVL1_TDC_TRIGG <= '0';
+ lvl1_tdc_trigg_i <= '0';
end case;
end process LVL1_START_FSM_PROC;
- ACK_LVL1_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL1_STATE)
+ LVL1_TDC_TRIGG <= lvl1_tdc_trigg_i;
+ ACK_LVL1_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL1_STATE,LVL1_BUSY,lvl1_trigger_pulse_start)
begin
if rising_edge(CLK) then
if RESET = '1' then
end if;
end if;
end process;
+ not_tdc_clk <= not TDC_CLK;
+ SEND_TDC_TRIGGER : edge_to_pulse
+ port map (
+ clock => not_tdc_clk,
+ en_clk => '1',
+ signal_in => lvl1_tdc_trigg_i,
+ pulse => TRIGGER_TO_TDC);
-----------------------------------------------------------------------------
-- LVL2 trigger logic
-----------------------------------------------------------------------------
end if;
end if;
end process LVL2_START;
- LVL2_START_FSM_PROC : process (LVL2_START_fsm_currentstate,CLK)
+ LVL2_START_FSM_PROC : process (LVL2_START_fsm_currentstate,CLK,lvl2_trigger_pulse,ACK_LVL1_STATE,TDC_CONTROL_REGISTER(0),ACK_LVL2_STATE)
begin
case (LVL2_START_fsm_currentstate) is
when IDLE =>
LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2;
when SEND_LVL2_TRIGG_2 =>
- LVL2_TDC_TRIGG <= "00";
+ LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
LVL2_START_fsm_nextstate <= WAIT_FOR_ACK;
when WAIT_FOR_ACK =>
- LVL2_TDC_TRIGG <= "00";
+ LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
if ACK_LVL2_STATE = ACK_LVL2_PULSE_1 then
LVL2_START_fsm_nextstate <= IDLE;
else
LVL2_TDC_TRIGG <= "00";
end case;
end process LVL2_START_FSM_PROC;
- ACK_LVL2_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL2_STATE)
+ ACK_LVL2_NEXT_STATE_DECODE : process (CLK, RESET, LVL2_BUSY, ACK_LVL2_STATE,LVL2_START_fsm_currentstate)
begin
if rising_edge(CLK) then
if RESET = '1' then
else
case (ACK_LVL2_STATE) is
when IDLE =>
- if LVL2_BUSY = '1' then
+ if LVL2_BUSY = '1' and LVL2_START_fsm_currentstate /= IDLE then
ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
else
ACK_LVL2_STATE <= IDLE;
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