# Bitgen
workdir/$(TARGET).bit: workdir/$(TARGET).ncd
+ @$(MAKE) report
+
@echo ""
@echo "----------------------------------------------------------------------"
@echo "-------------- Bitgen ------------------------------------------------"
cd workdir && \
bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \
$(TARGET).bit $(TARGET).prf
- @$(MAKE) report
+
@$(MAKE) error
# Place and Route (multipar)
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
FREQUENCY PORT NX1_ADC_DCLK_IN 187.5 MHz;
-FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c" 93.750000 MHz;
+FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK" 93.750000 MHz;
USE PRIMARY NET "CLK_PCLK_RIGHT_c";
-USE PRIMARY NET "clk_100_i_c";
-USE PRIMARY NET "nx_main_clk_c";
-USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c";
+USE PRIMARY NET "clk_100_i";
+USE PRIMARY NET "nx_main_clk";
+USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK";
#################################################################
# Reset Nets
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
REGION "MEDIA_UPLINK" "R102C95D" 13 25;
LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns;
-MULTICYCLE to CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns;
# Bitgen
workdir/$(TARGET).bit: workdir/$(TARGET).ncd
+ @$(MAKE) report
+
@echo ""
@echo "----------------------------------------------------------------------"
@echo "-------------- Bitgen ------------------------------------------------"
cd workdir && \
bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \
$(TARGET).bit $(TARGET).prf
- @$(MAKE) report
+
@$(MAKE) error
# Place and Route (multipar)
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="adc_ddr_generic" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 10 16 12:18:43.132" version="5.6" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="adc_ddr_generic.lpc" type="lpc" modified="2014 10 16 12:18:36.000"/>
- <File name="adc_ddr_generic.vhd" type="top_level_vhdl" modified="2014 10 16 12:18:37.000"/>
- <File name="adc_ddr_generic_tmpl.vhd" type="template_vhdl" modified="2014 10 16 12:18:37.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=DDR_GENERIC
-CoreRevision=5.6
-ModuleName=adc_ddr_generic
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/16/2014
-Time=12:18:36
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-mode=Receive
-trioddr=0
-io_type=LVDS25
-num_int=1
-width=5
-freq_in=187.5
-bandwidth=1875.0
-aligned=Centered
-pre-configuration=DISABLED
-mode2=Receive
-trioddr2=0
-io_type2=LVDS25
-freq_in2=187.5
-gear=2x
-aligned2=Centered
-num_int2=1
-width2=5
-Interface=GDDRX2_RX.ECLK.Centered
-Delay=Fixed
-Number=
-dqs1=
-dqs2=
-dqs3=
-dqs4=
-dqs5=
-dqs6=
-dqs7=
-dqs8=
-val=
-Phase=TRDLLB/DLLDELB
-Divider=CLKDIVB
-Multiplier=2
-PllFreq=94
-
-[Command]
-cmd_line= -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk eclk
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
--- Module Version: 5.6
---/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk eclk
-
--- Thu Oct 16 12:18:37 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity adc_ddr_generic is
- port (
- clk: in std_logic;
- clkdiv_reset: in std_logic;
- eclk: out std_logic;
- sclk: out std_logic;
- datain: in std_logic_vector(4 downto 0);
- q: out std_logic_vector(19 downto 0));
- attribute dont_touch : boolean;
- attribute dont_touch of adc_ddr_generic : entity is true;
-end adc_ddr_generic;
-
-architecture Structure of adc_ddr_generic is
-
- -- internal signal declarations
- signal qb14: std_logic;
- signal qa14: std_logic;
- signal qb04: std_logic;
- signal qa04: std_logic;
- signal qb13: std_logic;
- signal qa13: std_logic;
- signal qb03: std_logic;
- signal qa03: std_logic;
- signal qb12: std_logic;
- signal qa12: std_logic;
- signal qb02: std_logic;
- signal qa02: std_logic;
- signal qb11: std_logic;
- signal qa11: std_logic;
- signal qb01: std_logic;
- signal qa01: std_logic;
- signal qb10: std_logic;
- signal qa10: std_logic;
- signal qb00: std_logic;
- signal qa00: std_logic;
- signal cdiv8: std_logic;
- signal cdiv4: std_logic;
- signal cdiv1: std_logic;
- signal scuba_vhi: std_logic;
- signal eclk_t: std_logic;
- signal dataini_t4: std_logic;
- signal dataini_t3: std_logic;
- signal dataini_t2: std_logic;
- signal dataini_t1: std_logic;
- signal dataini_t0: std_logic;
- signal buf_clk: std_logic;
- signal buf_dataini4: std_logic;
- signal buf_dataini3: std_logic;
- signal buf_dataini2: std_logic;
- signal buf_dataini1: std_logic;
- signal buf_dataini0: std_logic;
- signal sclk_t: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component IB
- port (I: in std_logic; O: out std_logic);
- end component;
- component CLKDIVB
- port (CLKI: in std_logic; RST: in std_logic;
- RELEASE: in std_logic; CDIV1: out std_logic;
- CDIV2: out std_logic; CDIV4: out std_logic;
- CDIV8: out std_logic);
- end component;
- component IDDRX2D1
- generic (DR_CONFIG : in String);
- port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic;
- QA0: out std_logic; QB0: out std_logic;
- QA1: out std_logic; QB1: out std_logic);
- end component;
- component DELAYC
- port (A: in std_logic; Z: out std_logic);
- end component;
- attribute IDDRAPPS : string;
- attribute IO_TYPE : string;
- attribute IDDRAPPS of Inst_IDDRX2D1_0_4 : label is "ECLK_CENTERED";
- attribute IDDRAPPS of Inst_IDDRX2D1_0_3 : label is "ECLK_CENTERED";
- attribute IDDRAPPS of Inst_IDDRX2D1_0_2 : label is "ECLK_CENTERED";
- attribute IDDRAPPS of Inst_IDDRX2D1_0_1 : label is "ECLK_CENTERED";
- attribute IDDRAPPS of Inst_IDDRX2D1_0_0 : label is "ECLK_CENTERED";
- attribute IO_TYPE of Inst2_IB : label is "LVDS25";
- attribute IO_TYPE of Inst1_IB4 : label is "LVDS25";
- attribute IO_TYPE of Inst1_IB3 : label is "LVDS25";
- attribute IO_TYPE of Inst1_IB2 : label is "LVDS25";
- attribute IO_TYPE of Inst1_IB1 : label is "LVDS25";
- attribute IO_TYPE of Inst1_IB0 : label is "LVDS25";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- Inst_IDDRX2D1_0_4: IDDRX2D1
- generic map (DR_CONFIG=> "DISABLED")
- port map (D=>dataini_t4, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa04,
- QB0=>qb04, QA1=>qa14, QB1=>qb14);
-
- Inst_IDDRX2D1_0_3: IDDRX2D1
- generic map (DR_CONFIG=> "DISABLED")
- port map (D=>dataini_t3, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa03,
- QB0=>qb03, QA1=>qa13, QB1=>qb13);
-
- Inst_IDDRX2D1_0_2: IDDRX2D1
- generic map (DR_CONFIG=> "DISABLED")
- port map (D=>dataini_t2, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa02,
- QB0=>qb02, QA1=>qa12, QB1=>qb12);
-
- Inst_IDDRX2D1_0_1: IDDRX2D1
- generic map (DR_CONFIG=> "DISABLED")
- port map (D=>dataini_t1, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa01,
- QB0=>qb01, QA1=>qa11, QB1=>qb11);
-
- Inst_IDDRX2D1_0_0: IDDRX2D1
- generic map (DR_CONFIG=> "DISABLED")
- port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa00,
- QB0=>qb00, QA1=>qa10, QB1=>qb10);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- Inst3_CLKDIVB: CLKDIVB
- port map (CLKI=>eclk_t, RST=>clkdiv_reset, RELEASE=>scuba_vhi,
- CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8);
-
- udel_dataini4: DELAYC
- port map (A=>buf_dataini4, Z=>dataini_t4);
-
- udel_dataini3: DELAYC
- port map (A=>buf_dataini3, Z=>dataini_t3);
-
- udel_dataini2: DELAYC
- port map (A=>buf_dataini2, Z=>dataini_t2);
-
- udel_dataini1: DELAYC
- port map (A=>buf_dataini1, Z=>dataini_t1);
-
- udel_dataini0: DELAYC
- port map (A=>buf_dataini0, Z=>dataini_t0);
-
- Inst2_IB: IB
- port map (I=>clk, O=>buf_clk);
-
- Inst1_IB4: IB
- port map (I=>datain(4), O=>buf_dataini4);
-
- Inst1_IB3: IB
- port map (I=>datain(3), O=>buf_dataini3);
-
- Inst1_IB2: IB
- port map (I=>datain(2), O=>buf_dataini2);
-
- Inst1_IB1: IB
- port map (I=>datain(1), O=>buf_dataini1);
-
- Inst1_IB0: IB
- port map (I=>datain(0), O=>buf_dataini0);
-
- eclk <= eclk_t;
- q(19) <= qb14;
- q(18) <= qb13;
- q(17) <= qb12;
- q(16) <= qb11;
- q(15) <= qb10;
- q(14) <= qa14;
- q(13) <= qa13;
- q(12) <= qa12;
- q(11) <= qa11;
- q(10) <= qa10;
- q(9) <= qb04;
- q(8) <= qb03;
- q(7) <= qb02;
- q(6) <= qb01;
- q(5) <= qb00;
- q(4) <= qa04;
- q(3) <= qa03;
- q(2) <= qa02;
- q(1) <= qa01;
- q(0) <= qa00;
- eclk_t <= buf_clk;
- sclk <= sclk_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of adc_ddr_generic is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:IB use entity ecp3.IB(V); end for;
- for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
- for all:IDDRX2D1 use entity ecp3.IDDRX2D1(V); end for;
- for all:DELAYC use entity ecp3.DELAYC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="dynamic_shift_register33x64" module="RAM_Based_Shift_Register" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 09 14:16:24.965" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2014 08 09 14:16:24.000"/>
- <File name="dynamic_shift_register33x64.lpc" type="lpc" modified="2014 08 09 14:16:23.000"/>
- <File name="dynamic_shift_register33x64.vhd" type="top_level_vhdl" modified="2014 08 09 14:16:23.000"/>
- <File name="dynamic_shift_register33x64_tmpl.vhd" type="template_vhdl" modified="2014 08 09 14:16:23.000"/>
- <File name="tb_dynamic_shift_register33x64_tmpl.vhd" type="testbench_vhdl" modified="2014 08 09 14:16:23.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_Based_Shift_Register
-CoreRevision=5.1
-ModuleName=dynamic_shift_register33x64
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/09/2014
-Time=14:16:23
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-DataWidth=33
-Type=VarLossless
-NoOfShifts=16
-MaxLossyShifts=16
-MaxLosslessShifts=64
-EOR=1
-MemFile=
-MemFormat=orca
-RamType=bram
-
-[FilesGenerated]
-=mem
-
-[Command]
-cmd_line= -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
--- Module Version: 5.1
---/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output
-
--- Sat Aug 9 14:16:23 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity dynamic_shift_register33x64 is
- port (
- Din: in std_logic_vector(32 downto 0);
- Addr: in std_logic_vector(5 downto 0);
- Clock: in std_logic;
- ClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(32 downto 0));
-end dynamic_shift_register33x64;
-
-architecture Structure of dynamic_shift_register33x64 is
-
- -- internal signal declarations
- signal Reset_inv: std_logic;
- signal ishreg_addr_w0: std_logic;
- signal ishreg_addr_w1: std_logic;
- signal sreg_0_ctr_1_ci: std_logic;
- signal ishreg_addr_w2: std_logic;
- signal ishreg_addr_w3: std_logic;
- signal co0: std_logic;
- signal ishreg_addr_w4: std_logic;
- signal ishreg_addr_w5: std_logic;
- signal co2: std_logic;
- signal co1: std_logic;
- signal shreg_addr_r0: std_logic;
- signal precin: std_logic;
- signal high_inv: std_logic;
- signal scuba_vhi: std_logic;
- signal shreg_addr_w0: std_logic;
- signal shreg_addr_r1: std_logic;
- signal shreg_addr_r2: std_logic;
- signal co0_1: std_logic;
- signal shreg_addr_w1: std_logic;
- signal shreg_addr_w2: std_logic;
- signal shreg_addr_r3: std_logic;
- signal shreg_addr_r4: std_logic;
- signal co1_1: std_logic;
- signal shreg_addr_w3: std_logic;
- signal shreg_addr_w4: std_logic;
- signal shreg_addr_r5: std_logic;
- signal co2_1: std_logic;
- signal shreg_addr_w5: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of sram_1_0_0_0 : label is "dynamic_shift_register33x64.lpc";
- attribute MEM_INIT_FILE of sram_1_0_0_0 : label is "";
- attribute RESETMODE of sram_1_0_0_0 : label is "SYNC";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- INV_1: INV
- port map (A=>Reset, Z=>Reset_inv);
-
- INV_0: INV
- port map (A=>scuba_vhi, Z=>high_inv);
-
- sram_1_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3),
- DI4=>Din(4), DI5=>Din(5), DI6=>Din(6), DI7=>Din(7),
- DI8=>Din(8), DI9=>Din(9), DI10=>Din(10), DI11=>Din(11),
- DI12=>Din(12), DI13=>Din(13), DI14=>Din(14), DI15=>Din(15),
- DI16=>Din(16), DI17=>Din(17), DI18=>Din(18), DI19=>Din(19),
- DI20=>Din(20), DI21=>Din(21), DI22=>Din(22), DI23=>Din(23),
- DI24=>Din(24), DI25=>Din(25), DI26=>Din(26), DI27=>Din(27),
- DI28=>Din(28), DI29=>Din(29), DI30=>Din(30), DI31=>Din(31),
- DI32=>Din(32), DI33=>scuba_vlo, DI34=>scuba_vlo,
- DI35=>scuba_vlo, ADW0=>shreg_addr_w0, ADW1=>shreg_addr_w1,
- ADW2=>shreg_addr_w2, ADW3=>shreg_addr_w3,
- ADW4=>shreg_addr_w4, ADW5=>shreg_addr_w5, ADW6=>scuba_vlo,
- ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>ClockEn,
- CLKW=>Clock, CSW0=>Reset_inv, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>shreg_addr_r0, ADR6=>shreg_addr_r1,
- ADR7=>shreg_addr_r2, ADR8=>shreg_addr_r3,
- ADR9=>shreg_addr_r4, ADR10=>shreg_addr_r5, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>ClockEn,
- CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>open,
- DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- FF_5: FD1P3DX
- port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w0);
-
- FF_4: FD1P3DX
- port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w1);
-
- FF_3: FD1P3DX
- port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w2);
-
- FF_2: FD1P3DX
- port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w3);
-
- FF_1: FD1P3DX
- port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w4);
-
- FF_0: FD1P3DX
- port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>shreg_addr_w5);
-
- sreg_0_ctr_1_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci,
- S0=>open, S1=>open);
-
- sreg_0_ctr_1_0: CU2
- port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0,
- PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0,
- NC1=>ishreg_addr_w1);
-
- sreg_0_ctr_1_1: CU2
- port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3,
- CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3);
-
- sreg_0_ctr_1_2: CU2
- port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5,
- CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5);
-
- precin_inst101: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open,
- S1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- raddr_sub_1_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>shreg_addr_w0, B0=>high_inv,
- B1=>Addr(0), BI=>precin, BOUT=>co0_1, S0=>open,
- S1=>shreg_addr_r0);
-
- raddr_sub_1_1: FSUB2B
- port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1),
- B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1,
- S1=>shreg_addr_r2);
-
- raddr_sub_1_2: FSUB2B
- port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3),
- B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3,
- S1=>shreg_addr_r4);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- raddr_sub_1_3: FSUB2B
- port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5),
- B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5,
- S1=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of dynamic_shift_register33x64 is
- for Structure
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_32_data" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 03 06 20:19:44.509" version="4.8" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_32_data.lpc" type="lpc" modified="2014 03 06 20:19:42.000"/>
- <File name="fifo_32_data.vhd" type="top_level_vhdl" modified="2014 03 06 20:19:42.000"/>
- <File name="fifo_32_data_tmpl.vhd" type="template_vhdl" modified="2014 03 06 20:19:42.000"/>
- <File name="tb_fifo_32_data_tmpl.vhd" type="testbench_vhdl" modified="2014 03 06 20:19:42.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO
-CoreRevision=4.8
-ModuleName=fifo_32_data
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=03/06/2014
-Time=20:19:42
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2048
-Width=32
-regout=1
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Single Threshold
-PeAssert=1
-PeDeassert=12
-FullFlg=1
-PfMode=Dynamic - Single Threshold
-PfAssert=1020
-PfDeassert=506
-RDataCount=0
-EnECC=0
-EnFWFT=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 32 -depth 2048 -regout -no_enable -pe -1 -pf 0 -e
-
--- Thu Mar 6 20:19:42 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_32_data is
- port (
- Data: in std_logic_vector(31 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmFullThresh: in std_logic_vector(10 downto 0);
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostFull: out std_logic);
-end fifo_32_data;
-
-architecture Structure of fifo_32_data is
-
- -- internal signal declarations
- signal invout_2: std_logic;
- signal invout_1: std_logic;
- signal rden_i_inv: std_logic;
- signal invout_0: std_logic;
- signal r_nw: std_logic;
- signal fcnt_en: std_logic;
- signal empty_i: std_logic;
- signal empty_d: std_logic;
- signal full_i: std_logic;
- signal full_d: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal rptr_11: std_logic;
- signal ifcount_0: std_logic;
- signal ifcount_1: std_logic;
- signal bdcnt_bctr_ci: std_logic;
- signal ifcount_2: std_logic;
- signal ifcount_3: std_logic;
- signal co0: std_logic;
- signal ifcount_4: std_logic;
- signal ifcount_5: std_logic;
- signal co1: std_logic;
- signal ifcount_6: std_logic;
- signal ifcount_7: std_logic;
- signal co2: std_logic;
- signal ifcount_8: std_logic;
- signal ifcount_9: std_logic;
- signal co3: std_logic;
- signal ifcount_10: std_logic;
- signal ifcount_11: std_logic;
- signal co5: std_logic;
- signal co4: std_logic;
- signal cmp_ci: std_logic;
- signal rden_i: std_logic;
- signal co0_1: std_logic;
- signal co1_1: std_logic;
- signal co2_1: std_logic;
- signal co3_1: std_logic;
- signal co4_1: std_logic;
- signal cmp_le_1: std_logic;
- signal cmp_le_1_c: std_logic;
- signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
- signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
- signal co1_2: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
- signal co2_2: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
- signal co3_2: std_logic;
- signal fcount_8: std_logic;
- signal fcount_9: std_logic;
- signal co4_2: std_logic;
- signal wren_i_inv: std_logic;
- signal fcount_10: std_logic;
- signal fcount_11: std_logic;
- signal cmp_ge_d1: std_logic;
- signal cmp_ge_d1_c: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_ctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0_3: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1_3: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2_3: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3_3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5_1: std_logic;
- signal wcount_11: std_logic;
- signal co4_3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal r_ctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co0_4: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co1_4: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co2_4: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co3_4: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5_2: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co4_4: std_logic;
- signal wcnt_sub_0: std_logic;
- signal cnt_con_inv: std_logic;
- signal rptr_0: std_logic;
- signal cnt_con: std_logic;
- signal wcount_0: std_logic;
- signal wcnt_sub_1: std_logic;
- signal wcnt_sub_2: std_logic;
- signal co0_5: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal wcount_1: std_logic;
- signal wcount_2: std_logic;
- signal wcnt_sub_3: std_logic;
- signal wcnt_sub_4: std_logic;
- signal co1_5: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal wcount_3: std_logic;
- signal wcount_4: std_logic;
- signal wcnt_sub_5: std_logic;
- signal wcnt_sub_6: std_logic;
- signal co2_5: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal wcount_5: std_logic;
- signal wcount_6: std_logic;
- signal wcnt_sub_7: std_logic;
- signal wcnt_sub_8: std_logic;
- signal co3_5: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal wcount_7: std_logic;
- signal wcount_8: std_logic;
- signal wcnt_sub_9: std_logic;
- signal wcnt_sub_10: std_logic;
- signal co4_5: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal wcount_9: std_logic;
- signal wcount_10: std_logic;
- signal wcnt_sub_11: std_logic;
- signal co5_3: std_logic;
- signal wcnt_sub_msb: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_2: std_logic;
- signal wcnt_reg_0: std_logic;
- signal wcnt_reg_1: std_logic;
- signal co0_6: std_logic;
- signal wcnt_reg_2: std_logic;
- signal wcnt_reg_3: std_logic;
- signal co1_6: std_logic;
- signal wcnt_reg_4: std_logic;
- signal wcnt_reg_5: std_logic;
- signal co2_6: std_logic;
- signal wcnt_reg_6: std_logic;
- signal wcnt_reg_7: std_logic;
- signal co3_6: std_logic;
- signal wcnt_reg_8: std_logic;
- signal wcnt_reg_9: std_logic;
- signal co4_6: std_logic;
- signal wcnt_reg_10: std_logic;
- signal wcnt_reg_11: std_logic;
- signal af_set: std_logic;
- signal af_set_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; LE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
- NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_32_data.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is "";
- attribute RESETMODE of pdp_ram_0_0_3 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_2 : label is "fifo_32_data.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_2 : label is "";
- attribute RESETMODE of pdp_ram_0_1_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_1 : label is "fifo_32_data.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_2_1 : label is "";
- attribute RESETMODE of pdp_ram_0_2_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_3_0 : label is "fifo_32_data.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_3_0 : label is "";
- attribute RESETMODE of pdp_ram_0_3_0 : label is "SYNC";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t5: AND2
- port map (A=>WrEn, B=>invout_2, Z=>wren_i);
-
- INV_5: INV
- port map (A=>full_i, Z=>invout_2);
-
- AND2_t4: AND2
- port map (A=>RdEn, B=>invout_1, Z=>rden_i);
-
- INV_4: INV
- port map (A=>empty_i, Z=>invout_1);
-
- AND2_t3: AND2
- port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
-
- XOR2_t2: XOR2
- port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
-
- INV_3: INV
- port map (A=>rden_i, Z=>rden_i_inv);
-
- INV_2: INV
- port map (A=>wren_i, Z=>wren_i_inv);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"3232")
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
- AD0=>empty_i, DO0=>empty_d);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"3232")
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
- AD0=>full_i, DO0=>full_d);
-
- AND2_t1: AND2
- port map (A=>rden_i, B=>invout_0, Z=>r_nw);
-
- INV_1: INV
- port map (A=>wren_i, Z=>invout_0);
-
- XOR2_t0: XOR2
- port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb);
-
- INV_0: INV
- port map (A=>cnt_con, Z=>cnt_con_inv);
-
- pdp_ram_0_0_3: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i,
- WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
- DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
- DOB8=>Q(8), DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_2: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(9), DOB1=>Q(10), DOB2=>Q(11),
- DOB3=>Q(12), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15),
- DOB7=>Q(16), DOB8=>Q(17), DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_2_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(18), DOB1=>Q(19), DOB2=>Q(20),
- DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23), DOB6=>Q(24),
- DOB7=>Q(25), DOB8=>Q(26), DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_3_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(27), DOB1=>Q(28), DOB2=>Q(29),
- DOB3=>Q(30), DOB4=>Q(31), DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_74: FD1P3DX
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_0);
-
- FF_73: FD1P3DX
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_1);
-
- FF_72: FD1P3DX
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_2);
-
- FF_71: FD1P3DX
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_3);
-
- FF_70: FD1P3DX
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_4);
-
- FF_69: FD1P3DX
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_5);
-
- FF_68: FD1P3DX
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_6);
-
- FF_67: FD1P3DX
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_7);
-
- FF_66: FD1P3DX
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_8);
-
- FF_65: FD1P3DX
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_9);
-
- FF_64: FD1P3DX
- port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_10);
-
- FF_63: FD1P3DX
- port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_11);
-
- FF_62: FD1S3BX
- port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
-
- FF_61: FD1S3DX
- port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
-
- FF_60: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
- Q=>wcount_0);
-
- FF_59: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_1);
-
- FF_58: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_2);
-
- FF_57: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_3);
-
- FF_56: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_4);
-
- FF_55: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_5);
-
- FF_54: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_6);
-
- FF_53: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_7);
-
- FF_52: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_8);
-
- FF_51: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_9);
-
- FF_50: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_10);
-
- FF_49: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_11);
-
- FF_48: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
- Q=>rcount_0);
-
- FF_47: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_1);
-
- FF_46: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_2);
-
- FF_45: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_3);
-
- FF_44: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_4);
-
- FF_43: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_5);
-
- FF_42: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_6);
-
- FF_41: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_7);
-
- FF_40: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_8);
-
- FF_39: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_9);
-
- FF_38: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_10);
-
- FF_37: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_11);
-
- FF_36: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_0);
-
- FF_35: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_1);
-
- FF_34: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_2);
-
- FF_33: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_3);
-
- FF_32: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_4);
-
- FF_31: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_5);
-
- FF_30: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_6);
-
- FF_29: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_7);
-
- FF_28: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_8);
-
- FF_27: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_9);
-
- FF_26: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_10);
-
- FF_25: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wptr_11);
-
- FF_24: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_0);
-
- FF_23: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_1);
-
- FF_22: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_2);
-
- FF_21: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_3);
-
- FF_20: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_4);
-
- FF_19: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_5);
-
- FF_18: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_6);
-
- FF_17: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_7);
-
- FF_16: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_8);
-
- FF_15: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_9);
-
- FF_14: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_10);
-
- FF_13: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rptr_11);
-
- FF_12: FD1S3DX
- port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
-
- FF_11: FD1S3DX
- port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
-
- FF_10: FD1S3DX
- port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
-
- FF_9: FD1S3DX
- port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
-
- FF_8: FD1S3DX
- port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
-
- FF_7: FD1S3DX
- port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
-
- FF_6: FD1S3DX
- port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
-
- FF_5: FD1S3DX
- port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
-
- FF_4: FD1S3DX
- port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
-
- FF_3: FD1S3DX
- port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
-
- FF_2: FD1S3DX
- port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
-
- FF_1: FD1S3DX
- port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
-
- FF_0: FD1S3DX
- port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
-
- bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
- CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
-
- bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
- CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
-
- bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
- CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
-
- bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
- CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
-
- bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
- CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
-
- bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
- CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
-
- bdcnt_bctr_5: CB2
- port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
- CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
-
- e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
- S1=>open);
-
- e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
- CI=>cmp_ci, LE=>co0_1);
-
- e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
-
- e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
-
- e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
-
- e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
-
- e_cmp_5: ALEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
- S1=>open);
-
- g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
- S1=>open);
-
- g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
- CI=>cmp_ci_1, GE=>co0_2);
-
- g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
- CI=>co0_2, GE=>co1_2);
-
- g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
- CI=>co1_2, GE=>co2_2);
-
- g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
- CI=>co2_2, GE=>co3_2);
-
- g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
- CI=>co3_2, GE=>co4_2);
-
- g_cmp_5: AGEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i,
- B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
- S1=>open);
-
- w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
- S1=>open);
-
- w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_ctr_5: CU2
- port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
- S1=>open);
-
- r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_ctr_5: CU2
- port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2,
- NC0=>ircount_10, NC1=>ircount_11);
-
- wcnt_0: FSUB2B
- port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
- BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
-
- wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
- BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
-
- wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
- BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
-
- wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
- BI=>co2_5, BOUT=>co3_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
-
- wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
- BI=>co3_5, BOUT=>co4_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
-
- wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
- BI=>co4_5, BOUT=>co5_3, S0=>wcnt_sub_9, S1=>wcnt_sub_10);
-
- wcnt_6: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co5_3, BOUT=>open, S0=>wcnt_sub_11,
- S1=>open);
-
- af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
-
- af_set_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
- B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
-
- af_set_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
- B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
-
- af_set_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
- B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6);
-
- af_set_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
- B1=>AmFullThresh(7), CI=>co2_6, GE=>co3_6);
-
- af_set_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
- B1=>AmFullThresh(9), CI=>co3_6, GE=>co4_6);
-
- af_set_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
- B1=>scuba_vlo, CI=>co4_6, GE=>af_set_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_32_data is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:ALEB2 use entity ecp3.ALEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:CB2 use entity ecp3.CB2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_adc_48to48_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 11 26 10:38:46.213" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_adc_48to48_dc.lpc" type="lpc" modified="2013 11 26 10:38:44.000"/>
- <File name="fifo_adc_48to48_dc.vhd" type="top_level_vhdl" modified="2013 11 26 10:38:44.000"/>
- <File name="fifo_adc_48to48_dc_tmpl.vhd" type="template_vhdl" modified="2013 11 26 10:38:44.000"/>
- <File name="tb_fifo_adc_48to48_dc_tmpl.vhd" type="testbench_vhdl" modified="2013 11 26 10:38:44.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_adc_48to48_dc
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=11/26/2013
-Time=10:38:44
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4
-Width=48
-RDepth=4
-RWidth=48
-regout=1
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 48 -depth 4 -rdata_width 48 -regout -no_enable -pe -1 -pf -1 -e
-
--- Tue Nov 26 10:38:44 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_adc_48to48_dc is
- port (
- Data: in std_logic_vector(47 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(47 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_adc_48to48_dc;
-
-architecture Structure of fifo_adc_48to48_dc is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal co1: std_logic;
- signal wcount_2: std_logic;
- signal co0: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal co1_1: std_logic;
- signal rcount_2: std_logic;
- signal co0_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_adc_48to48_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_adc_48to48_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t6: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t5: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t4: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t3: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t2: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t1: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t0: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo,
- ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
- ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
- CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo,
- ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
- CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
- DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>scuba_vlo, DI13=>scuba_vlo,
- DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
- DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
- DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
- DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
- DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
- DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
- DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
- DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo,
- ADW3=>scuba_vlo, ADW4=>scuba_vlo, ADW5=>scuba_vlo,
- ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo,
- ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo,
- ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo,
- CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open,
- DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
- DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
- DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39),
- DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), DO25=>Q(43),
- DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), DO29=>Q(47),
- DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
- DO35=>open);
-
- FF_31: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_30: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_29: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_28: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_27: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_26: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_25: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_24: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_23: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_22: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_21: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_20: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_19: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_18: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_17: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_16: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_15: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_14: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_11: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_7: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_6: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_5: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1,
- NC0=>iwcount_2, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1,
- NC0=>ircount_2, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_adc_48to48_dc is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_adc_status_4to4_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 25 02:08:30.818" version="5.7" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_adc_status_4to4_dc.lpc" type="lpc" modified="2014 08 25 02:08:24.000"/>
- <File name="fifo_adc_status_4to4_dc.vhd" type="top_level_vhdl" modified="2014 08 25 02:08:25.000"/>
- <File name="fifo_adc_status_4to4_dc_tmpl.vhd" type="template_vhdl" modified="2014 08 25 02:08:25.000"/>
- <File name="tb_fifo_adc_status_4to4_dc_tmpl.vhd" type="testbench_vhdl" modified="2014 08 25 02:08:25.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.7
-ModuleName=fifo_adc_status_4to4_dc
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/25/2014
-Time=02:08:24
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=2
-Width=4
-RDepth=2
-RWidth=4
-regout=1
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
-
-[Command]
-cmd_line= -w -n fifo_adc_status_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 1 -data_width 4 -num_words 2 -rdata_width 4 -outdata REGISTERED -no_enable -pe -1 -pf -1
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
--- Module Version: 5.7
---/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n fifo_adc_status_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2 -width 4 -depth 2 -rdata_width 4 -regout -no_enable -pe -1 -pf -1
-
--- Mon Aug 25 02:08:25 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_adc_status_4to4_dc is
- port (
- Data: in std_logic_vector(3 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(3 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_adc_status_4to4_dc;
-
-architecture Structure of fifo_adc_status_4to4_dc is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal r_gdata_0: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal co0: std_logic;
- signal w_gctr_ci: std_logic;
- signal wcount_1: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal co0_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal rcount_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_0: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_0: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_adc_status_4to4_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t4: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t3: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t2: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t1: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t0: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0,
- ADA3=>scuba_vlo, ADA4=>scuba_vlo, ADA5=>scuba_vlo,
- ADA6=>scuba_vlo, ADA7=>scuba_vlo, ADA8=>scuba_vlo,
- ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i,
- CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0,
- ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo,
- ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo,
- ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo,
- ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>rden_i,
- CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
- DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
- DOB17=>open);
-
- FF_21: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_20: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_19: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_18: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_17: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_16: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_15: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_14: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_13: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_12: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_11: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_10: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_9: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_8: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_5: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_4: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>empty_cmp_set, B0=>wcount_r0,
- B1=>empty_cmp_clr, CI=>cmp_ci, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>full_cmp_set, B0=>rcount_w0,
- B1=>full_cmp_clr, CI=>cmp_ci_1, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_adc_status_4to4_dc is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_data_stream_44to44_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 15 22:11:19.583" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="fifo_data_stream_44to44_dc.lpc" type="lpc" modified="2014 04 15 22:11:13.000"/>
- <File name="fifo_data_stream_44to44_dc.vhd" type="top_level_vhdl" modified="2014 04 15 22:11:13.000"/>
- <File name="fifo_data_stream_44to44_dc_tmpl.vhd" type="template_vhdl" modified="2014 04 15 22:11:13.000"/>
- <File name="tb_fifo_data_stream_44to44_dc_tmpl.vhd" type="testbench_vhdl" modified="2014 04 15 22:11:13.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_data_stream_44to44_dc
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/15/2014
-Time=22:11:13
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Based
-Depth=4
-Width=44
-RDepth=4
-RWidth=44
-regout=1
-CtrlByRdEn=0
-EmpFlg=0
-PeMode=Static - Dual Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
-PfDeassert=506
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 44 -depth 4 -rdata_width 44 -regout -no_enable -pe -1 -pf -1 -e
-
--- Tue Apr 15 22:11:13 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_data_stream_44to44_dc is
- port (
- Data: in std_logic_vector(43 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(43 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_data_stream_44to44_dc;
-
-architecture Structure of fifo_data_stream_44to44_dc is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal co1: std_logic;
- signal wcount_2: std_logic;
- signal co0: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal co1_1: std_logic;
- signal rcount_2: std_logic;
- signal co0_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_data_stream_44to44_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_data_stream_44to44_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t6: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t5: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t4: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t3: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t2: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t1: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t0: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo,
- ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
- ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
- CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo,
- ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
- CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
- DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
- DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
- DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
- DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
- DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
- DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
- DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
- DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
- DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
- DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1,
- ADW2=>scuba_vlo, ADW3=>scuba_vlo, ADW4=>scuba_vlo,
- ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo,
- ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>scuba_vlo, ADR8=>scuba_vlo, ADR9=>scuba_vlo,
- ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo,
- ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>RdClock,
- CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
- DO0=>open, DO1=>open, DO2=>open, DO3=>open, DO4=>open,
- DO5=>open, DO6=>open, DO7=>open, DO8=>open, DO9=>open,
- DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
- DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
- DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
- DO34=>open, DO35=>open);
-
- FF_31: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_30: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_29: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_28: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_27: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_26: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_25: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_24: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_23: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_22: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_21: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_20: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_19: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_18: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_17: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_16: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_15: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_14: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_11: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_7: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_6: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_5: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1,
- NC0=>iwcount_2, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1,
- NC0=>ircount_2, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_data_stream_44to44_dc is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_sampling_clk" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 19 21:30:32.016" version="5.3" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_adc_sampling_clk.lpc" type="lpc" modified="2013 10 19 21:30:28.000"/>
- <File name="pll_adc_sampling_clk.vhd" type="top_level_vhdl" modified="2013 10 19 21:30:29.000"/>
- <File name="pll_adc_sampling_clk_tmpl.vhd" type="template_vhdl" modified="2013 10 19 21:30:29.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_sampling_clk
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/19/2013
-Time=21:31:09
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=31.25
-Div=1
-ClkOPBp=0
-Post=32
-U_OFrq=31.25
-OP_Tol=0.0
-OFrq=31.250000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=Internal
-Mult=1
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Dynamic
-CLKOK_INPUT=CLKOS
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=1
-FINDELA=0
-VcoRate=
-Bandwidth=3.424318
-;DelayControl=No
-EnCLKOS=1
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_sampling_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 31.25 -phase_cntl DYNAMIC -fclkop 31.25 -fclkop_tol 0.0 -fb_mode INTERNAL -duty50 -noclkok -use_rst -noclkok2 -bw -e
-
--- Sat Oct 19 21:31:09 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_sampling_clk is
- port (
- CLK: in std_logic;
- RESET: in std_logic;
- FINEDELB0: in std_logic;
- FINEDELB1: in std_logic;
- FINEDELB2: in std_logic;
- FINEDELB3: in std_logic;
- DPHASE0: in std_logic;
- DPHASE1: in std_logic;
- DPHASE2: in std_logic;
- DPHASE3: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_sampling_clk : entity is true;
-end pll_adc_sampling_clk;
-
-architecture Structure of pll_adc_sampling_clk is
-
- -- internal signal declarations
- signal CLKOS_t: std_logic;
- signal CLKOP_t: std_logic;
- signal DPHASE3_inv: std_logic;
- signal CLKFB_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKOS : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "31.250000";
- attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "31.250000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "31.250000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- INV_0: INV
- port map (A=>DPHASE3, Z=>DPHASE3_inv);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "DYNAMIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 32, CLKFB_DIV=> 1, CLKI_DIV=> 1,
- FIN=> "31.250000")
- port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo,
- WRDEL=>scuba_vlo, DRPAI3=>DPHASE3, DRPAI2=>DPHASE2,
- DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, DFPAI3=>DPHASE3_inv,
- DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, DFPAI0=>DPHASE0,
- FDA3=>FINEDELB3, FDA2=>FINEDELB2, FDA1=>FINEDELB1,
- FDA0=>FINEDELB0, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, CLKOK=>open,
- CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t);
-
- CLKOS <= CLKOS_t;
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_sampling_clk is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 08 23:14:15.031" version="5.3" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_nx_clk250.lpc" type="lpc" modified="2014 04 08 23:14:13.000"/>
- <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2014 04 08 23:14:13.000"/>
- <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2014 04 08 23:14:13.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_nx_clk250
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/08/2014
-Time=23:14:13
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=200
-Div=4
-ClkOPBp=0
-Post=4
-U_OFrq=250
-OP_Tol=0.0
-OFrq=250.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=5
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=125
-OK_Tol=0.0
-KFrq=125.000000
-ClkRst=0
-PCDR=1
-FINDELA=0
-VcoRate=
-Bandwidth=1.753251
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e
-
--- Tue Apr 8 23:14:13 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_nx_clk250 is
- port (
- CLK: in std_logic;
- RESET: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_nx_clk250 : entity is true;
-end pll_nx_clk250;
-
-architecture Structure of pll_nx_clk250 is
-
- -- internal signal declarations
- signal CLKOP_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 4,
- FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo,
- WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo,
- DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo,
- DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo,
- FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo,
- FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
- CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
-
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_nx_clk250 is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_dp_128x32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 15 15:23:00.769" version="6.1" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2013 12 15 15:23:00.000"/>
- <File name="ram_dp_128x32.lpc" type="lpc" modified="2013 12 15 15:22:59.000"/>
- <File name="ram_dp_128x32.vhd" type="top_level_vhdl" modified="2013 12 15 15:22:59.000"/>
- <File name="ram_dp_128x32_tmpl.vhd" type="template_vhdl" modified="2013 12 15 15:22:59.000"/>
- <File name="tb_ram_dp_128x32_tmpl.vhd" type="testbench_vhdl" modified="2013 12 15 15:22:59.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=ram_dp_128x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/15/2013
-Time=15:22:59
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=128
-RData=32
-WAddress=128
-WData=32
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=1
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 128 -outdata REGISTERED -cascade -1 -e
-
--- Sun Dec 15 15:22:59 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ram_dp_128x32 is
- port (
- WrAddress: in std_logic_vector(6 downto 0);
- RdAddress: in std_logic_vector(6 downto 0);
- Data: in std_logic_vector(31 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(31 downto 0));
-end ram_dp_128x32;
-
-architecture Structure of ram_dp_128x32 is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ram_dp_128x32_0_0_0 : label is "ram_dp_128x32.lpc";
- attribute MEM_INIT_FILE of ram_dp_128x32_0_0_0 : label is "";
- attribute RESETMODE of ram_dp_128x32_0_0_0 : label is "SYNC";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ram_dp_128x32_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
- ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
- DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
- DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
- DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ram_dp_128x32 is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_dp_128x40" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 15 14:15:58.011" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2013 12 15 14:15:58.000"/>
- <File name="ram_dp_128x40.lpc" type="lpc" modified="2013 12 15 14:15:56.000"/>
- <File name="ram_dp_128x40.vhd" type="top_level_vhdl" modified="2013 12 15 14:15:56.000"/>
- <File name="ram_dp_128x40_tmpl.vhd" type="template_vhdl" modified="2013 12 15 14:15:56.000"/>
- <File name="tb_ram_dp_128x40_tmpl.vhd" type="testbench_vhdl" modified="2013 12 15 14:15:56.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=ram_dp_128x40
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/15/2013
-Time=14:15:56
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=128
-RData=40
-WAddress=128
-WData=40
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=0
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 40 -data_width 40 -num_rows 128 -cascade -1 -e
-
--- Sun Dec 15 14:15:56 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ram_dp_128x40 is
- port (
- WrAddress: in std_logic_vector(6 downto 0);
- RdAddress: in std_logic_vector(6 downto 0);
- Data: in std_logic_vector(39 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(39 downto 0));
-end ram_dp_128x40;
-
-architecture Structure of ram_dp_128x40 is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ram_dp_128x40_0_0_1 : label is "ram_dp_128x40.lpc";
- attribute MEM_INIT_FILE of ram_dp_128x40_0_0_1 : label is "";
- attribute RESETMODE of ram_dp_128x40_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of ram_dp_128x40_0_1_0 : label is "ram_dp_128x40.lpc";
- attribute MEM_INIT_FILE of ram_dp_128x40_0_1_0 : label is "";
- attribute RESETMODE of ram_dp_128x40_0_1_0 : label is "SYNC";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- ram_dp_128x40_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
- ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
- DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
- DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
- DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
- DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ram_dp_128x40_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>scuba_vlo, DI5=>scuba_vlo,
- DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
- DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo,
- DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
- DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
- ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
- DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
- DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
- DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36),
- DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>open,
- DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
- DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
- DO33=>open, DO34=>open, DO35=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ram_dp_128x40 is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_dp_512x32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 20 16:10:11.922" version="6.1" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2014 05 20 16:10:11.000"/>
- <File name="ram_dp_512x32.lpc" type="lpc" modified="2014 05 20 16:10:09.000"/>
- <File name="ram_dp_512x32.vhd" type="top_level_vhdl" modified="2014 05 20 16:10:10.000"/>
- <File name="ram_dp_512x32_tmpl.vhd" type="template_vhdl" modified="2014 05 20 16:10:10.000"/>
- <File name="tb_ram_dp_512x32_tmpl.vhd" type="testbench_vhdl" modified="2014 05 20 16:10:10.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=ram_dp_512x32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/20/2014
-Time=16:10:09
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=512
-RData=32
-WAddress=512
-WData=32
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=1
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -outdata REGISTERED -cascade -1 -e
-
--- Tue May 20 16:10:10 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ram_dp_512x32 is
- port (
- WrAddress: in std_logic_vector(8 downto 0);
- RdAddress: in std_logic_vector(8 downto 0);
- Data: in std_logic_vector(31 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(31 downto 0));
-end ram_dp_512x32;
-
-architecture Structure of ram_dp_512x32 is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ram_dp_512x32_0_0_0 : label is "ram_dp_512x32.lpc";
- attribute MEM_INIT_FILE of ram_dp_512x32_0_0_0 : label is "";
- attribute RESETMODE of ram_dp_512x32_0_0_0 : label is "SYNC";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ram_dp_512x32_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8),
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6),
- ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open,
- DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ram_dp_512x32 is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_dp_512x40" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 20 16:10:46.289" version="6.1" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2014 05 20 16:10:46.000"/>
- <File name="ram_dp_512x40.lpc" type="lpc" modified="2014 05 20 16:10:44.000"/>
- <File name="ram_dp_512x40.vhd" type="top_level_vhdl" modified="2014 05 20 16:10:44.000"/>
- <File name="ram_dp_512x40_tmpl.vhd" type="template_vhdl" modified="2014 05 20 16:10:44.000"/>
- <File name="tb_ram_dp_512x40_tmpl.vhd" type="testbench_vhdl" modified="2014 05 20 16:10:44.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=ram_dp_512x40
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/20/2014
-Time=16:10:44
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=512
-RData=40
-WAddress=512
-WData=40
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=0
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 40 -data_width 40 -num_rows 512 -cascade -1 -e
-
--- Tue May 20 16:10:44 2014
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ram_dp_512x40 is
- port (
- WrAddress: in std_logic_vector(8 downto 0);
- RdAddress: in std_logic_vector(8 downto 0);
- Data: in std_logic_vector(39 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(39 downto 0));
-end ram_dp_512x40;
-
-architecture Structure of ram_dp_512x40 is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ram_dp_512x40_0_0_1 : label is "ram_dp_512x40.lpc";
- attribute MEM_INIT_FILE of ram_dp_512x40_0_0_1 : label is "";
- attribute RESETMODE of ram_dp_512x40_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of ram_dp_512x40_0_1_0 : label is "ram_dp_512x40.lpc";
- attribute MEM_INIT_FILE of ram_dp_512x40_0_1_0 : label is "";
- attribute RESETMODE of ram_dp_512x40_0_1_0 : label is "SYNC";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- ram_dp_512x40_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8),
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6),
- ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
- DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ram_dp_512x40_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>scuba_vlo, DI5=>scuba_vlo,
- DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
- DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo,
- DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
- DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
- DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
- DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
- DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
- DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
- DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8),
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6),
- ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open,
- DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
- DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
- DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
- DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39),
- DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
- DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
- DO32=>open, DO33=>open, DO34=>open, DO35=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ram_dp_512x40 is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_fifo_delay_256x44" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 01 16:38:04.085" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2013 12 01 16:38:04.000"/>
- <File name="ram_fifo_delay_256x44.lpc" type="lpc" modified="2013 12 01 16:38:02.000"/>
- <File name="ram_fifo_delay_256x44.vhd" type="top_level_vhdl" modified="2013 12 01 16:38:02.000"/>
- <File name="ram_fifo_delay_256x44_tmpl.vhd" type="template_vhdl" modified="2013 12 01 16:38:02.000"/>
- <File name="tb_ram_fifo_delay_256x44_tmpl.vhd" type="testbench_vhdl" modified="2013 12 01 16:38:02.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP
-CoreRevision=6.1
-ModuleName=ram_fifo_delay_256x44
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/01/2013
-Time=16:38:02
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=256
-RData=44
-WAddress=256
-WData=44
-enByte=0
-ByteSize=9
-adPipeline=0
-inPipeline=0
-outPipeline=1
-MOR=0
-InData=Registered
-AdControl=Registered
-MemFile=
-MemFormat=bin
-Reset=Sync
-GSR=Enabled
-Pad=0
-EnECC=0
-Optimization=Speed
-EnSleep=ENABLED
-Pipeline=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 44 -data_width 44 -num_rows 256 -outdata REGISTERED -cascade -1 -e
-
--- Sun Dec 1 16:38:02 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ram_fifo_delay_256x44 is
- port (
- WrAddress: in std_logic_vector(7 downto 0);
- RdAddress: in std_logic_vector(7 downto 0);
- Data: in std_logic_vector(43 downto 0);
- WE: in std_logic;
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- WrClock: in std_logic;
- WrClockEn: in std_logic;
- Q: out std_logic_vector(43 downto 0));
-end ram_fifo_delay_256x44;
-
-architecture Structure of ram_fifo_delay_256x44 is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ram_fifo_delay_256x44_0_0_1 : label is "ram_fifo_delay_256x44.lpc";
- attribute MEM_INIT_FILE of ram_fifo_delay_256x44_0_0_1 : label is "";
- attribute RESETMODE of ram_fifo_delay_256x44_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of ram_fifo_delay_256x44_0_1_0 : label is "ram_fifo_delay_256x44.lpc";
- attribute MEM_INIT_FILE of ram_fifo_delay_256x44_0_1_0 : label is "";
- attribute RESETMODE of ram_fifo_delay_256x44_0_1_0 : label is "SYNC";
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- ram_fifo_delay_256x44_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
- ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
- ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
- ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
- ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
- ADR10=>RdAddress(5), ADR11=>RdAddress(6),
- ADR12=>RdAddress(7), ADR13=>scuba_vlo, CER=>RdClockEn,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
- DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
- DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
- DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ram_fifo_delay_256x44_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
- DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
- DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
- DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
- DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
- DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
- DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
- DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
- DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
- DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>WrAddress(0),
- ADW1=>WrAddress(1), ADW2=>WrAddress(2), ADW3=>WrAddress(3),
- ADW4=>WrAddress(4), ADW5=>WrAddress(5), ADW6=>WrAddress(6),
- ADW7=>WrAddress(7), ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi,
- CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>RdAddress(0), ADR6=>RdAddress(1), ADR7=>RdAddress(2),
- ADR8=>RdAddress(3), ADR9=>RdAddress(4), ADR10=>RdAddress(5),
- ADR11=>RdAddress(6), ADR12=>RdAddress(7), ADR13=>scuba_vlo,
- CER=>RdClockEn, CLKR=>RdClock, CSR0=>scuba_vlo,
- CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
- DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
- DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
- DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
- DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
- DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
- DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
- DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
- DO34=>open, DO35=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ram_fifo_delay_256x44 is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
[pbs1]
system = linux
corenum = 2
-env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs2]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs3]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs4]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs5]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs6]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs7]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
+workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+
+[pbs8]
+system = linux
+corenum = 2
+env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env
workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.scaler_components.all;
-
-entity nx_trigger_handler is
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- NX_MAIN_CLK_IN : in std_logic;
- NXYTER_OFFLINE_IN : in std_logic;
-
- --Input Triggers
- TIMING_TRIGGER_IN : in std_logic; -- The raw timing Trigger Signal
- LVL1_TRG_DATA_VALID_IN : in std_logic; -- Data Trigger is valid
- LVL1_VALID_TIMING_TRG_IN : in std_logic; -- Timin Trigger is valid
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- calib trigger w/o ref time
- LVL1_INVALID_TRG_IN : in std_logic;
-
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
-
- --Response from FEE
- FEE_DATA_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_OUT : out std_logic;
- FEE_DATA_FINISHED_OUT : out std_logic;
- FEE_TRG_RELEASE_OUT : out std_logic;
- FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
-
- FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_0_IN : in std_logic;
- FEE_DATA_1_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_1_IN : in std_logic;
-
- -- Internal FPGA Trigger
- INTERNAL_TRIGGER_IN : in std_logic;
-
- -- Trigger FeedBack
- TRIGGER_VALIDATE_BUSY_IN : in std_logic;
- TRIGGER_BUSY_0_IN : in std_logic;
- TRIGGER_BUSY_1_IN : in std_logic;
-
- -- OUT
- VALID_TRIGGER_OUT : out std_logic;
- TIMESTAMP_TRIGGER_OUT : out std_logic;
- TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_STATUS_OUT : out std_logic;
- TRIGGER_CALIBRATION_OUT : out std_logic;
- FAST_CLEAR_OUT : out std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
-
- -- Pulser
- NX_TESTPULSE_OUT : out std_logic;
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- -- Debug Line
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end entity;
-
-architecture Behavioral of nx_trigger_handler is
-
- -- Timing Trigger Handler
- constant NUM_FF : integer := 10;
- signal timing_trigger_ff_p : std_logic_vector(1 downto 0);
- signal timing_trigger_ff : std_logic_vector(NUM_FF - 1 downto 0);
- signal timing_trigger_l : std_logic;
- signal timing_trigger : std_logic;
- signal timing_trigger_set : std_logic;
- signal timestamp_trigger_o : std_logic;
-
- signal invalid_timing_trigger_n : std_logic;
-
- signal invalid_timing_trigger_ff : std_logic;
- signal invalid_timing_trigger_f : std_logic;
- signal invalid_timing_trigger : std_logic;
- signal invalid_timing_trigger_ctr : unsigned(15 downto 0);
-
- signal trigger_busy_ff : std_logic;
- signal trigger_busy_f : std_logic;
- signal trigger_busy : std_logic;
-
- signal fast_clear_ff : std_logic;
- signal fast_clear_f : std_logic;
- signal fast_clear : std_logic;
-
- type TS_STATES is (TS_IDLE,
- TS_WAIT_VALID_TIMING_TRIGGER,
- TS_INVALID_TRIGGER,
- TS_WAIT_TRIGGER_END
- );
- signal TS_STATE : TS_STATES;
-
- signal ts_wait_timer_reset : std_logic;
- signal ts_wait_timer_start : std_logic;
- signal ts_wait_timer_done : std_logic;
-
- -- Trigger Handler
- signal valid_trigger_o : std_logic;
- signal timing_trigger_o : std_logic;
- signal status_trigger_o : std_logic;
- signal calibration_trigger_o : std_logic;
- signal calib_downscale_ctr : unsigned(15 downto 0);
- signal fast_clear_o : std_logic;
- signal trigger_busy_o : std_logic;
- signal fee_data_o : std_logic_vector(31 downto 0);
- signal fee_data_write_o : std_logic;
- signal fee_data_finished_o : std_logic;
- signal fee_trg_release_o : std_logic;
- signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal testpulse_trigger : std_logic;
-
- signal testpulse_enable : std_logic;
-
- signal timestamp_calib_trigger_c100 : std_logic;
- signal timestamp_calib_trigger_f : std_logic;
- signal timestamp_calib_trigger_o : std_logic;
-
- type STATES is (S_IDLE,
- S_IGNORE_TRIGGER,
- S_STATUS_TRIGGER,
- S_TIMING_TRIGGER,
- S_CALIBRATION_TRIGGER,
- S_WAIT_TRG_DATA_VALID,
- S_WAIT_TIMING_TRIGGER_DONE,
- S_FEE_TRIGGER_RELEASE,
- S_WAIT_FEE_TRIGGER_RELEASE_ACK,
- S_INTERNAL_TRIGGER,
- S_WAIT_TRIGGER_VALIDATE_ACK,
- S_WAIT_TRIGGER_VALIDATE_DONE
- );
- signal STATE : STATES;
-
- type TRIGGER_TYPES is (T_UNDEF,
- T_IGNORE,
- T_TIMING,
- T_STATUS,
- T_CALIBRATION
- );
- signal TRIGGER_TYPE : TRIGGER_TYPES;
-
-
- -- Testpulse Handler
- type T_STATES is (T_IDLE,
- T_WAIT_TESTPULE_DELAY,
- T_SET_TESTPULSE,
- T_WAIT_TESTPULE_END
- );
-
- signal T_STATE : T_STATES;
-
- signal start_testpulse : std_logic;
- signal testpulse_delay : unsigned(11 downto 0);
- signal testpulse_length : unsigned(11 downto 0);
- signal testpulse_o : std_logic;
- signal wait_timer_reset : std_logic;
- signal wait_timer_start : std_logic;
- signal wait_timer_done : std_logic;
- signal wait_timer_end : unsigned(11 downto 0);
- signal internal_trigger_f : std_logic;
- signal internal_trigger : std_logic;
-
- -- Rate Calculation
- signal start_testpulse_ff : std_logic;
- signal start_testpulse_f : std_logic;
-
- signal accepted_trigger_rate_t : unsigned(27 downto 0);
- signal start_testpulse_clk100 : std_logic;
- signal testpulse_rate_t : unsigned(27 downto 0);
- signal rate_timer : unsigned(27 downto 0);
-
- -- TRBNet Slave Bus
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
-
- signal reg_testpulse_delay : unsigned(11 downto 0);
- signal reg_testpulse_length : unsigned(11 downto 0);
- signal reg_testpulse_enable : std_logic;
- signal accepted_trigger_rate : unsigned(27 downto 0);
- signal testpulse_rate : unsigned(27 downto 0);
- signal invalid_t_trigger_ctr_clear : std_logic;
- signal bypass_all_trigger : std_logic;
- signal bypass_physics_trigger : std_logic;
- signal bypass_status_trigger : std_logic;
- signal bypass_calibration_trigger : std_logic;
- signal calibration_downscale : unsigned(15 downto 0);
- signal physics_trigger_type : std_logic_vector(3 downto 0);
- signal status_trigger_type : std_logic_vector(3 downto 0);
- signal calibration_trigger_type : std_logic_vector(3 downto 0);
-
- -- Reset
- signal reset_nx_main_clk_in_ff : std_logic;
- signal reset_nx_main_clk_in_f : std_logic;
- signal RESET_NX_MAIN_CLK_IN : std_logic;
-
- attribute syn_keep : boolean;
- attribute syn_keep of reset_nx_main_clk_in_ff : signal is true;
- attribute syn_keep of reset_nx_main_clk_in_f : signal is true;
-
- attribute syn_keep of trigger_busy_ff : signal is true;
- attribute syn_keep of trigger_busy_f : signal is true;
-
- attribute syn_keep of fast_clear_ff : signal is true;
- attribute syn_keep of fast_clear_f : signal is true;
-
- attribute syn_keep of internal_trigger_f : signal is true;
- attribute syn_keep of internal_trigger : signal is true;
-
- attribute syn_keep of start_testpulse_ff : signal is true;
- attribute syn_keep of start_testpulse_f : signal is true;
-
- attribute syn_keep of timestamp_calib_trigger_f : signal is true;
- attribute syn_keep of timestamp_calib_trigger_o : signal is true;
-
- attribute syn_preserve : boolean;
- attribute syn_preserve of reset_nx_main_clk_in_ff : signal is true;
- attribute syn_preserve of reset_nx_main_clk_in_f : signal is true;
-
- attribute syn_preserve of trigger_busy_ff : signal is true;
- attribute syn_preserve of trigger_busy_f : signal is true;
-
- attribute syn_preserve of fast_clear_ff : signal is true;
- attribute syn_preserve of fast_clear_f : signal is true;
-
- attribute syn_preserve of internal_trigger_f : signal is true;
- attribute syn_preserve of internal_trigger : signal is true;
-
- attribute syn_preserve of start_testpulse_ff : signal is true;
- attribute syn_preserve of start_testpulse_f : signal is true;
-
- attribute syn_preserve of timestamp_calib_trigger_f : signal is true;
- attribute syn_preserve of timestamp_calib_trigger_o : signal is true;
-
-begin
-
- -- Debug Line
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= TIMING_TRIGGER_IN;
- DEBUG_OUT(2) <= invalid_timing_trigger;
- DEBUG_OUT(3) <= LVL1_VALID_TIMING_TRG_IN;
- DEBUG_OUT(4) <= LVL1_TRG_DATA_VALID_IN;
- DEBUG_OUT(5) <= fee_data_write_o;
- DEBUG_OUT(6) <= TRIGGER_VALIDATE_BUSY_IN;
- DEBUG_OUT(7) <= TRIGGER_BUSY_0_IN;
- DEBUG_OUT(8) <= valid_trigger_o;
- DEBUG_OUT(9) <= timing_trigger_o;
- DEBUG_OUT(10) <= fee_data_finished_o;
- DEBUG_OUT(11) <= fee_trg_release_o;
- DEBUG_OUT(12) <= trigger_busy_o;
- DEBUG_OUT(13) <= timestamp_trigger_o;
- DEBUG_OUT(14) <= testpulse_trigger;
- DEBUG_OUT(15) <= testpulse_o;
-
- -----------------------------------------------------------------------------
- -- Reset Domain Transfer
- -----------------------------------------------------------------------------
- reset_nx_main_clk_in_ff <= RESET_IN when rising_edge(NX_MAIN_CLK_IN);
- reset_nx_main_clk_in_f <= reset_nx_main_clk_in_ff
- when rising_edge(NX_MAIN_CLK_IN);
- RESET_NX_MAIN_CLK_IN <= reset_nx_main_clk_in_f
- when rising_edge(NX_MAIN_CLK_IN);
-
-
- -----------------------------------------------------------------------------
- -- Trigger Handler
- -----------------------------------------------------------------------------
-
- PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN)
- constant pattern : std_logic_vector(NUM_FF - 1 downto 0)
- := (others => '1');
- begin
- if( rising_edge(NX_MAIN_CLK_IN) ) then
- timing_trigger_ff_p(1) <= TIMING_TRIGGER_IN;
- if (RESET_NX_MAIN_CLK_IN = '1') then
- timing_trigger_ff_p(0) <= '0';
- timing_trigger_ff(NUM_FF - 1 downto 0) <= (others => '0');
- timing_trigger_l <= '0';
- else
- timing_trigger_ff_p(0) <= timing_trigger_ff_p(1);
- timing_trigger_ff(NUM_FF - 1) <= timing_trigger_ff_p(0);
-
- for I in NUM_FF - 2 downto 0 loop
- timing_trigger_ff(I) <= timing_trigger_ff(I + 1);
- end loop;
-
- if (timing_trigger_ff = pattern) then
- timing_trigger_l <= '1';
- else
- timing_trigger_l <= '0';
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_HANDLER;
-
- level_to_pulse_1: level_to_pulse
- port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => RESET_NX_MAIN_CLK_IN,
- LEVEL_IN => timing_trigger_l,
- PULSE_OUT => timing_trigger
- );
-
- -- Timer
- timer_static_2: timer_static
- generic map (
- CTR_WIDTH => 8,
- CTR_END => 32 -- 128ns
- )
- port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => ts_wait_timer_reset,
- TIMER_START_IN => ts_wait_timer_start,
- TIMER_DONE_OUT => ts_wait_timer_done
- );
-
-
- -- Signal Domain Transfers to NX Clock
- trigger_busy_ff <= trigger_busy_o
- when rising_edge(NX_MAIN_CLK_IN);
- trigger_busy_f <= trigger_busy_ff
- when rising_edge(NX_MAIN_CLK_IN);
- trigger_busy <= trigger_busy_f
- when rising_edge(NX_MAIN_CLK_IN);
-
- fast_clear_ff <= fast_clear_o
- when rising_edge(NX_MAIN_CLK_IN);
- fast_clear_f <= fast_clear_ff
- when rising_edge(NX_MAIN_CLK_IN);
- fast_clear <= fast_clear_f
- when rising_edge(NX_MAIN_CLK_IN);
-
- testpulse_enable <= reg_testpulse_enable when rising_edge(NX_MAIN_CLK_IN);
-
- PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN)
- begin
- if( rising_edge(NX_MAIN_CLK_IN) ) then
- if (RESET_NX_MAIN_CLK_IN = '1') then
- invalid_timing_trigger_n <= '1';
- ts_wait_timer_start <= '0';
- ts_wait_timer_reset <= '1';
- testpulse_trigger <= '0';
- timestamp_trigger_o <= '0';
- TS_STATE <= TS_IDLE;
- else
- invalid_timing_trigger_n <= '0';
- ts_wait_timer_start <= '0';
- ts_wait_timer_reset <= '0';
- testpulse_trigger <= '0';
- timestamp_trigger_o <= '0';
-
- if (fast_clear = '1') then
- ts_wait_timer_reset <= '1';
- TS_STATE <= TS_IDLE;
- else
- case TS_STATE is
- when TS_IDLE =>
- -- Wait for Timing Trigger synced to NX_MAIN_CLK_DOMAIN
- if (timing_trigger = '1') then
- if (trigger_busy = '1') then
- -- If busy is set --> Error
- TS_STATE <= TS_INVALID_TRIGGER;
- else
- if (reg_testpulse_enable = '1') then
- testpulse_trigger <= '1';
- end if;
- timestamp_trigger_o <= '1';
- ts_wait_timer_start <= '1';
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
- end if;
- else
- TS_STATE <= TS_IDLE;
- end if;
-
- when TS_WAIT_VALID_TIMING_TRIGGER =>
- -- Wait and test if CLK_IN Trigger Handler does accepted Trigger
- if (trigger_busy = '1') then
- -- Trigger has been accepted, stop timer and wait trigger end
- ts_wait_timer_reset <= '1';
- TS_STATE <= TS_WAIT_TRIGGER_END;
- else
- if (ts_wait_timer_done = '1') then
- -- Timeout after 128ns --> Invalid Trigger Error
- TS_STATE <= TS_INVALID_TRIGGER;
- else
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
- end if;
- end if;
-
- when TS_INVALID_TRIGGER =>
- invalid_timing_trigger_n <= '1';
- TS_STATE <= TS_IDLE;
-
- when TS_WAIT_TRIGGER_END =>
- if (trigger_busy = '0') then
- TS_STATE <= TS_IDLE;
- else
- TS_STATE <= TS_WAIT_TRIGGER_END;
- end if;
-
- end case;
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_HANDLER;
-
- PROC_TIMING_TRIGGER_COUNTER: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- invalid_timing_trigger_ctr <= (others => '0');
- else
- if (invalid_t_trigger_ctr_clear = '1') then
- invalid_timing_trigger_ctr <= (others => '0');
- elsif (invalid_timing_trigger = '1') then
- invalid_timing_trigger_ctr <= invalid_timing_trigger_ctr + 1;
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_COUNTER;
-
- -- Relax Timing
- invalid_timing_trigger_ff <= invalid_timing_trigger_n
- when rising_edge(NX_MAIN_CLK_IN);
- invalid_timing_trigger_f <= invalid_timing_trigger_ff
- when rising_edge(NX_MAIN_CLK_IN);
-
- pulse_dtrans_INVALID_TIMING_TRIGGER: pulse_dtrans
- generic map (
- CLK_RATIO => 4
- )
- port map (
- CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_NX_MAIN_CLK_IN,
- PULSE_A_IN => invalid_timing_trigger_f,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => invalid_timing_trigger
- );
-
- -----------------------------------------------------------------------------
-
- PROC_TRIGGER_HANDLER: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- valid_trigger_o <= '0';
- timing_trigger_o <= '0';
- status_trigger_o <= '0';
- calibration_trigger_o <= '0';
- fee_data_finished_o <= '0';
- fee_trg_release_o <= '0';
- fee_trg_statusbits_o <= (others => '0');
- fast_clear_o <= '0';
- trigger_busy_o <= '0';
- timestamp_calib_trigger_c100 <= '0';
- calib_downscale_ctr <= (others => '0');
- TRIGGER_TYPE <= T_UNDEF;
- STATE <= S_IDLE;
- else
- valid_trigger_o <= '0';
- timing_trigger_o <= '0';
- status_trigger_o <= '0';
- calibration_trigger_o <= '0';
- fee_data_finished_o <= '0';
- fee_trg_release_o <= '0';
- fee_trg_statusbits_o <= (others => '0');
- fast_clear_o <= '0';
- trigger_busy_o <= '1';
- timestamp_calib_trigger_c100 <= '0';
-
- if (LVL1_INVALID_TRG_IN = '1') then
- -- There was no valid Timing Trigger at CTS, do a fast clear
- fast_clear_o <= '1';
- fee_trg_release_o <= '1';
- STATE <= S_IDLE;
- else
-
- case STATE is
-
- when S_IDLE =>
-
- if (LVL1_VALID_TIMING_TRG_IN = '1') then
- -- Timing Trigger IN
- if (NXYTER_OFFLINE_IN = '1' or
- bypass_all_trigger = '1') then
-
- -- Ignore Trigger for nxyter is or pretends to be offline
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- -- Check Trigger Type
- if (LVL1_TRG_TYPE_IN = physics_trigger_type) then
- -- Physiks Trigger
- if (bypass_physics_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- TRIGGER_TYPE <= T_TIMING;
- STATE <= S_TIMING_TRIGGER;
- end if;
- else
- -- Unknown Timing Trigger, ignore
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
- end if;
-
- elsif (LVL1_VALID_NOTIMING_TRG_IN = '1') then
- -- No Timing Trigger IN
- if (NXYTER_OFFLINE_IN = '1' or
- bypass_all_trigger = '1') then
-
- -- Ignore Trigger for nxyter is or pretends to be offline
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- -- Check Trigger Type
- if (LVL1_TRG_TYPE_IN = calibration_trigger_type) then
- -- Calibration Trigger
- if (bypass_calibration_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- if (calib_downscale_ctr >= calibration_downscale) then
- timestamp_calib_trigger_c100 <= '1';
- calib_downscale_ctr <= x"0001";
- TRIGGER_TYPE <= T_CALIBRATION;
- STATE <= S_CALIBRATION_TRIGGER;
- else
- calib_downscale_ctr <= calib_downscale_ctr + 1;
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
- end if;
-
- elsif (LVL1_TRG_TYPE_IN = status_trigger_type) then
- -- Status Trigger
- if (bypass_status_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- -- Status Trigger
- status_trigger_o <= '1';
- TRIGGER_TYPE <= T_STATUS;
- STATE <= S_STATUS_TRIGGER;
- end if;
-
- else
- -- Some other Trigger, ignore it
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
-
- end if;
-
- else
- -- No Trigger IN, Nothing to do, Sleep Well
- trigger_busy_o <= '0';
- TRIGGER_TYPE <= T_UNDEF;
- STATE <= S_IDLE;
- end if;
-
- when S_TIMING_TRIGGER =>
- valid_trigger_o <= '1';
- timing_trigger_o <= '1';
- STATE <= S_WAIT_TRG_DATA_VALID;
-
- when S_CALIBRATION_TRIGGER =>
- calibration_trigger_o <= '1';
- valid_trigger_o <= '1';
- timing_trigger_o <= '1';
- STATE <= S_WAIT_TRG_DATA_VALID;
-
- when S_WAIT_TRG_DATA_VALID | S_STATUS_TRIGGER | S_IGNORE_TRIGGER =>
- if (LVL1_TRG_DATA_VALID_IN = '0') then
- STATE <= S_WAIT_TRG_DATA_VALID;
- else
- STATE <= S_WAIT_TIMING_TRIGGER_DONE;
- end if;
-
- when S_WAIT_TIMING_TRIGGER_DONE =>
- if (((TRIGGER_TYPE = T_TIMING or
- TRIGGER_TYPE = T_CALIBRATION)
- and TRIGGER_BUSY_0_IN = '1')
- or
- (TRIGGER_TYPE = T_STATUS and
- TRIGGER_BUSY_1_IN = '1')
- ) then
- STATE <= S_WAIT_TIMING_TRIGGER_DONE;
- else
- fee_data_finished_o <= '1';
- STATE <= S_FEE_TRIGGER_RELEASE;
- end if;
-
- when S_FEE_TRIGGER_RELEASE =>
- fee_trg_release_o <= '1';
- STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;
-
- when S_WAIT_FEE_TRIGGER_RELEASE_ACK =>
- if (LVL1_TRG_DATA_VALID_IN = '1') then
- STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;
- else
- STATE <= S_IDLE;
- end if;
-
- -- Internal Trigger Handler
- when S_INTERNAL_TRIGGER =>
- valid_trigger_o <= '1';
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
-
- when S_WAIT_TRIGGER_VALIDATE_ACK =>
- if (TRIGGER_VALIDATE_BUSY_IN = '0') then
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
- else
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;
- end if;
-
- when S_WAIT_TRIGGER_VALIDATE_DONE =>
- if (TRIGGER_VALIDATE_BUSY_IN = '1') then
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;
- else
- STATE <= S_IDLE;
- end if;
-
- end case;
- end if;
- end if;
- end if;
- end process PROC_TRIGGER_HANDLER;
-
- PROC_EVENT_DATA_MULTIPLEXER: process(TRIGGER_TYPE)
- begin
- case TRIGGER_TYPE is
- when T_UNDEF | T_IGNORE =>
- fee_data_o <= (others => '0');
- fee_data_write_o <= '0';
-
- when T_TIMING | T_CALIBRATION =>
- fee_data_o <= FEE_DATA_0_IN;
- fee_data_write_o <= FEE_DATA_WRITE_0_IN;
-
- when T_STATUS =>
- fee_data_o <= FEE_DATA_1_IN;
- fee_data_write_o <= FEE_DATA_WRITE_1_IN;
-
- end case;
- end process PROC_EVENT_DATA_MULTIPLEXER;
-
- timer_1: timer
- generic map (
- CTR_WIDTH => 12
- )
- port map (
- CLK_IN => NX_MAIN_CLK_IN,
- RESET_IN => wait_timer_reset,
- TIMER_START_IN => wait_timer_start,
- TIMER_END_IN => wait_timer_end,
- TIMER_DONE_OUT => wait_timer_done
- );
-
- testpulse_delay <= reg_testpulse_delay when rising_edge(NX_MAIN_CLK_IN);
- testpulse_length <= reg_testpulse_length when rising_edge(NX_MAIN_CLK_IN);
-
- internal_trigger_f <= INTERNAL_TRIGGER_IN or
- calibration_trigger_o when rising_edge(NX_MAIN_CLK_IN);
- internal_trigger <= internal_trigger_f when rising_edge(NX_MAIN_CLK_IN);
-
- start_testpulse <= testpulse_trigger or
- internal_trigger;
-
- PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN)
- begin
- if( rising_edge(NX_MAIN_CLK_IN) ) then
- if (RESET_NX_MAIN_CLK_IN = '1') then
- wait_timer_start <= '0';
- wait_timer_reset <= '1';
- testpulse_o <= '0';
- T_STATE <= T_IDLE;
- else
- wait_timer_start <= '0';
- wait_timer_reset <= '0';
- testpulse_o <= '0';
-
- if (fast_clear = '1') then
- wait_timer_reset <= '1';
- T_STATE <= T_IDLE;
- else
- case T_STATE is
-
- when T_IDLE =>
- if (start_testpulse = '1') then
- if (reg_testpulse_delay > 0) then
- wait_timer_end <= testpulse_delay;
- wait_timer_start <= '1';
- T_STATE <= T_WAIT_TESTPULE_DELAY;
- else
- T_STATE <= T_SET_TESTPULSE;
- end if;
- else
- T_STATE <= T_IDLE;
- end if;
-
- when T_WAIT_TESTPULE_DELAY =>
- if (wait_timer_done = '0') then
- T_STATE <= T_WAIT_TESTPULE_DELAY;
- else
- T_STATE <= T_SET_TESTPULSE;
- end if;
-
- when T_SET_TESTPULSE =>
- testpulse_o <= '1';
- wait_timer_end <= testpulse_length;
- wait_timer_start <= '1';
- T_STATE <= T_WAIT_TESTPULE_END;
-
- when T_WAIT_TESTPULE_END =>
- if (wait_timer_done = '0') then
- testpulse_o <= '1';
- T_STATE <= T_WAIT_TESTPULE_END;
- else
- T_STATE <= T_IDLE;
- end if;
-
- end case;
- end if;
- end if;
- end if;
- end process PROC_TESTPULSE_HANDLER;
-
--- Relax Timing
- start_testpulse_ff <= start_testpulse when rising_edge(NX_MAIN_CLK_IN);
- start_testpulse_f <= start_testpulse_ff when rising_edge(NX_MAIN_CLK_IN);
-
- pulse_dtrans_TESTPULSE_RATE: pulse_dtrans
- generic map (
- CLK_RATIO => 4
- )
- port map (
- CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_NX_MAIN_CLK_IN,
- PULSE_A_IN => start_testpulse_f,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => start_testpulse_clk100
- );
-
- PROC_CAL_RATES: process (CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- accepted_trigger_rate_t <= (others => '0');
- accepted_trigger_rate <= (others => '0');
- testpulse_rate_t <= (others => '0');
- testpulse_rate <= (others => '0');
- rate_timer <= (others => '0');
- else
- if (rate_timer < x"5f5e100") then
- if (timing_trigger_o = '1') then
- accepted_trigger_rate_t <= accepted_trigger_rate_t + 1;
- end if;
-
- if (start_testpulse_clk100 = '1') then
- testpulse_rate_t <= testpulse_rate_t + 1;
- end if;
- rate_timer <= rate_timer + 1;
- else
- rate_timer <= (others => '0');
- accepted_trigger_rate <= accepted_trigger_rate_t;
- testpulse_rate <= testpulse_rate_t;
-
- accepted_trigger_rate_t <= (others => '0');
- testpulse_rate_t <= (others => '0');
- end if;
- end if;
- end if;
- end process PROC_CAL_RATES;
-
------------------------------------------------------------------------------
--- TRBNet Slave Bus
------------------------------------------------------------------------------
-
- PROC_SLAVE_BUS: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_ack_o <= '0';
- reg_testpulse_delay <= (others => '0');
- reg_testpulse_length <= x"064";
- reg_testpulse_enable <= '0';
- invalid_t_trigger_ctr_clear <= '1';
- bypass_all_trigger <= '0';
- bypass_physics_trigger <= '0';
- bypass_status_trigger <= '1';
- bypass_calibration_trigger <= '1';
- calibration_downscale <= x"0001";
- physics_trigger_type <= x"1";
- calibration_trigger_type <= x"9";
- status_trigger_type <= x"e";
- else
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
- invalid_t_trigger_ctr_clear <= '0';
-
- if (SLV_WRITE_IN = '1') then
- case SLV_ADDR_IN is
- when x"0000" =>
- reg_testpulse_enable <= SLV_DATA_IN(0);
- slv_ack_o <= '1';
-
- when x"0001" =>
- reg_testpulse_delay <=
- unsigned(SLV_DATA_IN(11 downto 0));
- slv_ack_o <= '1';
-
- when x"0002" =>
- reg_testpulse_length <=
- unsigned(SLV_DATA_IN(11 downto 0));
- slv_ack_o <= '1';
-
- when x"0003" =>
- invalid_t_trigger_ctr_clear <= '1';
- slv_ack_o <= '1';
-
- when x"0006" =>
- bypass_physics_trigger <= SLV_DATA_IN(0);
- bypass_status_trigger <= SLV_DATA_IN(1);
- bypass_calibration_trigger <= SLV_DATA_IN(2);
- bypass_all_trigger <= SLV_DATA_IN(3);
- slv_ack_o <= '1';
-
- when x"0007" =>
- if (unsigned(SLV_DATA_IN(15 downto 0)) > x"0000") then
- calibration_downscale <=
- unsigned(SLV_DATA_IN(15 downto 0));
- end if;
- slv_ack_o <= '1';
-
- when x"0008" =>
- physics_trigger_type <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
-
- when x"0009" =>
- status_trigger_type <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
-
- when x"000a" =>
- calibration_trigger_type <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
-
- end case;
-
- elsif (SLV_READ_IN = '1') then
- case SLV_ADDR_IN is
-
- when x"0000" =>
- slv_data_out_o(0) <= reg_testpulse_enable;
- slv_data_out_o(31 downto 1) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0001" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(reg_testpulse_delay);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0002" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(reg_testpulse_length);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0003" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(invalid_timing_trigger_ctr);
- slv_data_out_o(31 downto 26) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0004" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(accepted_trigger_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0005" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(testpulse_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0006" =>
- slv_data_out_o(0) <= bypass_physics_trigger;
- slv_data_out_o(1) <= bypass_status_trigger;
- slv_data_out_o(2) <= bypass_calibration_trigger;
- slv_data_out_o(3) <= bypass_all_trigger;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0007" =>
- slv_data_out_o(15 downto 0) <= calibration_downscale;
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0008" =>
- slv_data_out_o(3 downto 0) <= physics_trigger_type;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0009" =>
- slv_data_out_o(3 downto 0) <= status_trigger_type;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"000a" =>
- slv_data_out_o(3 downto 0) <= calibration_trigger_type;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
-
- end case;
-
- end if;
- end if;
- end if;
- end process PROC_SLAVE_BUS;
-
------------------------------------------------------------------------------
--- Output Signals
------------------------------------------------------------------------------
-
- timestamp_calib_trigger_f <= timestamp_calib_trigger_c100
- when rising_edge(NX_MAIN_CLK_IN);
-
- timestamp_calib_trigger_o <= timestamp_calib_trigger_f
- when rising_edge(NX_MAIN_CLK_IN);
-
--- Trigger Output
- VALID_TRIGGER_OUT <= valid_trigger_o;
- TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o or timestamp_calib_trigger_o;
- TRIGGER_TIMING_OUT <= timing_trigger_o;
- TRIGGER_STATUS_OUT <= status_trigger_o;
- TRIGGER_CALIBRATION_OUT <= calibration_trigger_o;
- FAST_CLEAR_OUT <= fast_clear_o;
- TRIGGER_BUSY_OUT <= trigger_busy_o;
-
- FEE_DATA_OUT <= fee_data_o;
- FEE_DATA_WRITE_OUT <= fee_data_write_o;
- FEE_DATA_FINISHED_OUT <= fee_data_finished_o;
- FEE_TRG_RELEASE_OUT <= fee_trg_release_o;
- FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;
-
- NX_TESTPULSE_OUT <= testpulse_o;
-
--- Slave Bus
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
-
-end Behavioral;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- CLK_NX_MAIN_IN : in std_logic;
- PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_RESET_OUT : out std_logic;
+
+ CLK_D1_IN : in std_logic;
+
TRIGGER_OUT : out std_logic;
-- Scaler Channels
- SCALER_LATCH_IN : in std_logic;
- SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0);
+ LATCH_IN : in std_logic;
+ CHANNELS_IN : in std_logic_vector (7 downto 0);
-- Input Triggers
TIMING_TRIGGER_IN : in std_logic;
-------------------------------------------------------------------------------
-- Bus Handler
- constant NUM_PORTS : integer := 2;
+ constant NUM_PORTS : integer := 3;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal error_event_buffer : std_logic;
-- Debug Handler
- constant DEBUG_NUM_PORTS : integer := 1; -- 14
+ constant DEBUG_NUM_PORTS : integer := 2; -- 14
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
----------------------------------------------------------------------
signal clock_div : unsigned(11 downto 0);
signal clk_pulse : std_logic;
+ signal pulse : std_logic;
+ signal latch_i : std_logic;
+ signal latch : std_logic;
signal scaler_counter : unsigned(11 downto 0);
signal input_pulse : std_logic;
----------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------
- signal reset_scaler_clk_in_ff : std_logic;
- signal reset_scaler_clk_in_f : std_logic;
- signal RESET_SCALER_CLK_IN : std_logic;
-
- attribute syn_keep : boolean;
- attribute syn_keep of reset_scaler_clk_in_ff : signal is true;
- attribute syn_keep of reset_scaler_clk_in_f : signal is true;
-
- attribute syn_preserve : boolean;
- attribute syn_preserve of reset_scaler_clk_in_ff : signal is true;
- attribute syn_preserve of reset_scaler_clk_in_f : signal is true;
+ signal RESET_SCALER_CLK_IN : std_logic;
+
begin
- -----------------------------------------------------------------------------
- -- Reset Domain Transfer
- -----------------------------------------------------------------------------
- reset_scaler_clk_in_ff <= RESET_IN when rising_edge(CLK_NX_MAIN_IN);
- reset_scaler_clk_in_f <= reset_scaler_clk_in_ff
- when rising_edge(CLK_NX_MAIN_IN);
- RESET_SCALER_CLK_IN <= reset_scaler_clk_in_f
- when rising_edge(CLK_NX_MAIN_IN);
+
+ RESET_SCALER_CLK_IN <= RESET_IN;
-------------------------------------------------------------------------------
-- Port Maps
generic map(
PORT_NUMBER => NUM_PORTS,
- PORT_ADDRESSES => (0 => x"0020", -- Debug Handler
- 1 => x"0040", -- Scaler Channel 0
+ PORT_ADDRESSES => (0 => x"0200", -- Debug Multiplexer
+ 1 => x"0000", -- Scaler Channel 0
+ 2 => x"0160", -- Trigger Handler
+ --2 => x"0040", -- Scaler Channel 2
+ --3 => x"0060", -- Scaler Channel 3
+ --4 => x"0080", -- Scaler Channel 4
+ --5 => x"00a0", -- Scaler Channel 5
+ --6 => x"00c0", -- Scaler Channel 6
+ --7 => x"00e0", -- Scaler Channel 7
+
others => x"0000"
),
- PORT_ADDR_MASK => (0 => 0, -- Debug Handler
- 1 => 2, -- Scaler Channel 0
+ PORT_ADDR_MASK => (0 => 0, -- Debug Multiplexer
+ 1 => 2, -- Scaler Channel 0
+ 7 => 4, -- Trigger Handler
+ --2 => 2, -- Scaler Channel 2
+ --3 => 2, -- Scaler Channel 3
+ --4 => 2, -- Scaler Channel 4
+ --5 => 2, -- Scaler Channel 5
+ --6 => 2, -- Scaler Channel 6
+ --7 => 2, -- Scaler Channel 7
+
others => 0
),
clock_div <= (others => '0');
clk_pulse <= '0';
else
- if (clock_div < x"3e8") then
- clk_pulse <= '0';
+ if (clock_div < x"00f") then -- x"3e8"
+ clk_pulse <= '0';
clock_div <= clock_div + 1;
else
clk_pulse <= '1';
end if;
end process PROC_CLOCK_DIVIDER;
+ latch_i <= clk_pulse;
+ pulse <= CLK_IN;
- scaler_channel_1: scaler_channel
+ scaler_channel_0: scaler_channel
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- CLK_SCALER_IN => CLK_NX_MAIN_IN,
+ CLK_D1_IN => CLK_D1_IN,
RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- LATCH_IN => clk_pulse,
- PULSE_IN => clk_pulse,
+ LATCH_IN => latch_i, --LATCH_IN,
+ PULSE_IN => CHANNELS_IN(0),
+ PULSE_INTERNAL_IN => pulse,
INHIBIT_IN => '0',
SLV_READ_IN => slv_read(1),
DEBUG_OUT => debug_line(0)
);
-
+
+
+ trigger_handler_1: trigger_handler
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_MAIN_CLK_IN => CLK_IN,
+ OFFLINE_IN => not nxyter_online,
+
+ TIMING_TRIGGER_IN => TIMING_TRIGGER_IN,
+ LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
+ LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN,
+ LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN,
+ LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN,
+
+ LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
+ LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,
+ LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN,
+ LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
+ LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN,
+
+ FEE_DATA_OUT => FEE_DATA_OUT,
+ FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
+ FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
+ FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT,
+ FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT,
+
+ FEE_DATA_0_IN => fee_data_o_0,
+ FEE_DATA_WRITE_0_IN => fee_data_write_o_0,
+ FEE_DATA_1_IN => fee_data_o_1,
+ FEE_DATA_WRITE_1_IN => fee_data_write_o_1,
+ INTERNAL_TRIGGER_IN => internal_trigger,
+
+ TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy,
+ TRIGGER_BUSY_0_IN => trigger_evt_busy_0,
+ TRIGGER_BUSY_1_IN => trigger_evt_busy_1,
+
+ VALID_TRIGGER_OUT => trigger,
+ TIMESTAMP_TRIGGER_OUT => timestamp_trigger,
+ TRIGGER_TIMING_OUT => trigger_timing,
+ TRIGGER_STATUS_OUT => trigger_status,
+ TRIGGER_CALIBRATION_OUT => trigger_calibration,
+ FAST_CLEAR_OUT => fast_clear,
+ TRIGGER_BUSY_OUT => trigger_busy,
+
+ TESTPULSE_OUT => open,
+
+ SLV_READ_IN => slv_read(2),
+ SLV_WRITE_IN => slv_write(2),
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
+ SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
+ SLV_ACK_OUT => slv_ack(2),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
+
+ DEBUG_OUT => debug_line(1)
+ );
+
+ -- scaler_channel_1: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(1),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(1),
+ -- SLV_WRITE_IN => slv_write(1),
+ -- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+ -- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ -- SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
+ -- SLV_ACK_OUT => slv_ack(1),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_2: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(2),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(2),
+ -- SLV_WRITE_IN => slv_write(2),
+ -- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
+ -- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
+ -- SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
+ -- SLV_ACK_OUT => slv_ack(2),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_3: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(3),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(3),
+ -- SLV_WRITE_IN => slv_write(3),
+ -- SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
+ -- SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
+ -- SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
+ -- SLV_ACK_OUT => slv_ack(3),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_4: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(4),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(4),
+ -- SLV_WRITE_IN => slv_write(4),
+ -- SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
+ -- SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
+ -- SLV_ADDR_IN => slv_addr(4*16+15 downto 4*16),
+ -- SLV_ACK_OUT => slv_ack(4),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_5: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(5),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(5),
+ -- SLV_WRITE_IN => slv_write(5),
+ -- SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
+ -- SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
+ -- SLV_ADDR_IN => slv_addr(5*16+15 downto 5*16),
+ -- SLV_ACK_OUT => slv_ack(5),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_6: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(6),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(6),
+ -- SLV_WRITE_IN => slv_write(6),
+ -- SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),
+ -- SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),
+ -- SLV_ADDR_IN => slv_addr(6*16+15 downto 6*16),
+ -- SLV_ACK_OUT => slv_ack(6),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
+ --
+ -- DEBUG_OUT => open
+ -- );
+ --
+ -- scaler_channel_7: scaler_channel
+ -- port map (
+ -- CLK_IN => CLK_IN,
+ -- RESET_IN => RESET_IN,
+ -- CLK_SCALER_IN => CLK_SCALER_1_IN,
+ -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
+ -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
+ -- PULSE_IN => SCALER_CHANNELS_IN(7),
+ -- PULSE_INTERNAL_IN => pulse,
+ -- INHIBIT_IN => '0',
+ --
+ -- SLV_READ_IN => slv_read(7),
+ -- SLV_WRITE_IN => slv_write(7),
+ -- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
+ -- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),
+ -- SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16),
+ -- SLV_ACK_OUT => slv_ack(7),
+ -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
+ -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
+ --
+ -- DEBUG_OUT => open
+ -- );
+
-------------------------------------------------------------------------------
-- DEBUG Line Select
-------------------------------------------------------------------------------
+
debug_multiplexer_1: debug_multiplexer
generic map (
NUM_PORTS => DEBUG_NUM_PORTS
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- CLK_NX_MAIN_IN : in std_logic;
- PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_RESET_OUT : out std_logic;
+
+ CLK_D1_IN : in std_logic;
+
TRIGGER_OUT : out std_logic;
- SCALER_LATCH_IN : in std_logic;
- SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0);
+ LATCH_IN : in std_logic;
+ CHANNELS_IN : in std_logic_vector (7 downto 0);
TIMING_TRIGGER_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
LVL1_VALID_TIMING_TRG_IN : in std_logic;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- CLK_SCALER_IN : in std_logic;
+ CLK_D1_IN : in std_logic;
RESET_SCALER_IN : in std_logic;
LATCH_IN : in std_logic;
PULSE_IN : in std_logic;
+ PULSE_INTERNAL_IN : in std_logic;
INHIBIT_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
);
end component;
+-------------------------------------------------------------------------------
+-- Trigger Handler
+-------------------------------------------------------------------------------
+
+ component trigger_handler
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NX_MAIN_CLK_IN : in std_logic;
+ OFFLINE_IN : in std_logic;
+ TIMING_TRIGGER_IN : in std_logic;
+ LVL1_TRG_DATA_VALID_IN : in std_logic;
+ LVL1_VALID_TIMING_TRG_IN : in std_logic;
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
+ LVL1_INVALID_TRG_IN : in std_logic;
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_TRG_RELEASE_OUT : out std_logic;
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_0_IN : in std_logic;
+ FEE_DATA_1_IN : in std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_1_IN : in std_logic;
+ INTERNAL_TRIGGER_IN : in std_logic;
+ TRIGGER_VALIDATE_BUSY_IN : in std_logic;
+ TRIGGER_BUSY_0_IN : in std_logic;
+ TRIGGER_BUSY_1_IN : in std_logic;
+ VALID_TRIGGER_OUT : out std_logic;
+ TIMESTAMP_TRIGGER_OUT : out std_logic;
+ TRIGGER_TIMING_OUT : out std_logic;
+ TRIGGER_STATUS_OUT : out std_logic;
+ TRIGGER_CALIBRATION_OUT : out std_logic;
+ FAST_CLEAR_OUT : out std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ TESTPULSE_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
-------------------------------------------------------------------------------
-- nXyter I2C Interface
-------------------------------------------------------------------------------
);
end component;
- component nx_trigger_handler
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- NX_MAIN_CLK_IN : in std_logic;
- NXYTER_OFFLINE_IN : in std_logic;
- TIMING_TRIGGER_IN : in std_logic;
- LVL1_TRG_DATA_VALID_IN : in std_logic;
- LVL1_VALID_TIMING_TRG_IN : in std_logic;
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
- LVL1_INVALID_TRG_IN : in std_logic;
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- FEE_DATA_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_OUT : out std_logic;
- FEE_DATA_FINISHED_OUT : out std_logic;
- FEE_TRG_RELEASE_OUT : out std_logic;
- FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_0_IN : in std_logic;
- FEE_DATA_1_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_1_IN : in std_logic;
- INTERNAL_TRIGGER_IN : in std_logic;
- TRIGGER_VALIDATE_BUSY_IN : in std_logic;
- TRIGGER_BUSY_0_IN : in std_logic;
- TRIGGER_BUSY_1_IN : in std_logic;
- VALID_TRIGGER_OUT : out std_logic;
- TIMESTAMP_TRIGGER_OUT : out std_logic;
- TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_STATUS_OUT : out std_logic;
- TRIGGER_CALIBRATION_OUT : out std_logic;
- FAST_CLEAR_OUT : out std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
- NX_TESTPULSE_OUT : out std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
component nx_trigger_generator
port (
#Trigger from fan-out
LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+
#################################################################
# Scaler
-LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
-LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
+#LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
+#LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
-LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
-LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
+#LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
+#LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
+#LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
LOCATE COMP "SCALER_LATCH_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
LOCATE COMP "SCALER_CHANNELS_IN_6" SITE "K3"; #DQUL3_2 #53
LOCATE COMP "SCALER_CHANNELS_IN_7" SITE "H1"; #DQUL3_4 #57
-LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
+#LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
-IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+#IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
+#
+#IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+#IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
+#IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
+#IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
+#
+#IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+#IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+#IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+#IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+#
+#IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+#IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+#IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
# Nxyter Debug Lines Addon Board
-LOCATE COMP "SCALER_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170
-LOCATE COMP "SCALER_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172
-LOCATE COMP "SCALER_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174
-LOCATE COMP "SCALER_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176
-LOCATE COMP "SCALER_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178
-LOCATE COMP "SCALER_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180
-LOCATE COMP "SCALER_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186
-LOCATE COMP "SCALER_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188
-LOCATE COMP "SCALER_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169
-LOCATE COMP "SCALER_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171
-LOCATE COMP "SCALER_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173
-LOCATE COMP "SCALER_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175
-LOCATE COMP "SCALER_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177
-LOCATE COMP "SCALER_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179
-LOCATE COMP "SCALER_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185
-LOCATE COMP "SCALER_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187
-
-DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ;
-IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
+#LOCATE COMP "SCALER_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170
+#LOCATE COMP "SCALER_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172
+#LOCATE COMP "SCALER_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174
+#LOCATE COMP "SCALER_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176
+#LOCATE COMP "SCALER_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178
+#LOCATE COMP "SCALER_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180
+#LOCATE COMP "SCALER_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186
+#LOCATE COMP "SCALER_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188
+#LOCATE COMP "SCALER_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169
+#LOCATE COMP "SCALER_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171
+#LOCATE COMP "SCALER_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173
+#LOCATE COMP "SCALER_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175
+#LOCATE COMP "SCALER_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177
+#LOCATE COMP "SCALER_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179
+#LOCATE COMP "SCALER_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185
+#LOCATE COMP "SCALER_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187
+
+#DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ;
+#IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
#################################################################
# Additional Lines to AddOn
-w
-i 2
-l 5
--n 1
--t 1
+-n 2
+-t 10
-s 1
-c 1
-e 2
# nXyter Files
add_file -vhdl -lib "work" "cores/pll_clk400.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd"
-add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd"
-add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd"
-add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd"
-add_file -vhdl -lib "work" "cores/ram_dp_512x40.vhd"
-add_file -vhdl -lib "work" "cores/ram_dp_512x32.vhd"
-add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd"
-add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd"
-add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd"
-add_file -vhdl -lib "work" "cores/fifo_adc_status_4to4_dc.vhd"
-add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
-add_file -vhdl -lib "work" "cores/dynamic_shift_register33x64.vhd"
+add_file -vhdl -lib "work" "cores/counter_45bit.vhd"
+add_file -vhdl -lib "work" "cores/fifo_5to5_dc.vhd"
add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
add_file -vhdl -lib "work" "trb3_periph_scaler.vhd"
add_file -vhdl -lib "work" "source/signal_async_trans.vhd"
add_file -vhdl -lib "work" "source/bus_async_trans.vhd"
add_file -vhdl -lib "work" "source/pulse_delay.vhd"
-add_file -vhdl -lib "work" "source/gray_decoder.vhd"
-add_file -vhdl -lib "work" "source/gray_encoder.vhd"
add_file -vhdl -lib "work" "source/timer.vhd"
add_file -vhdl -lib "work" "source/timer_static.vhd"
add_file -vhdl -lib "work" "source/debug_multiplexer.vhd"
-add_file -vhdl -lib "work" "source/fifo_44_data_delay_my.vhd"
add_file -vhdl -lib "work" "source/scaler.vhd"
add_file -vhdl -lib "work" "source/scaler_channel.vhd"
-add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
-add_file -vhdl -lib "work" "source/nx_data_delay.vhd"
-add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
-add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
-add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
-add_file -vhdl -lib "work" "source/nx_status_event.vhd"
-
-add_file -vhdl -lib "work" "source/nx_status.vhd"
-add_file -vhdl -lib "work" "source/nx_register_setup.vhd"
-add_file -vhdl -lib "work" "source/nx_histogram.vhd"
-add_file -vhdl -lib "work" "source/nx_histograms.vhd"
-
-add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
-add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd"
-add_file -vhdl -lib "work" "source/nx_i2c_sendbyte.vhd"
-add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd"
-
-add_file -vhdl -lib "work" "source/adc_spi_master.vhd"
-add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
-add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
-add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
-add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd"
-
-add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
-add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
-add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd"
-add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd"
+add_file -vhdl -lib "work" "source/trigger_handler.vhd"
+#add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
+#add_file -vhdl -lib "work" "source/nx_data_delay.vhd"
+#add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
+#add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
+#add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
+#add_file -vhdl -lib "work" "source/nx_status_event.vhd"
+
+#add_file -vhdl -lib "work" "source/nx_status.vhd"
+#add_file -vhdl -lib "work" "source/nx_register_setup.vhd"
+#add_file -vhdl -lib "work" "source/nx_histogram.vhd"
+#add_file -vhdl -lib "work" "source/nx_histograms.vhd"
+
+#add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
+#add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd"
+#add_file -vhdl -lib "work" "source/nx_i2c_sendbyte.vhd"
+#add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd"
+
+#add_file -vhdl -lib "work" "source/adc_spi_master.vhd"
+#add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
+#add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
+#add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
+#add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd"
+
+#add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
+#add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
+#add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd"
+#add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd"
signal bussed_tx : CTRLBUS_TX;
-- nXyter-FEB-Board Clocks
- signal nx_main_clk : std_logic;
- signal nx_pll_clk_lock : std_logic;
- signal nx_pll_reset : std_logic;
-
- signal nx1_adc_sample_clk : std_logic;
+ signal clk_scaler : std_logic;
+ signal clk_scaler_lock : std_logic;
+ signal clk_scaler_reset : std_logic;
-- nXyter 1 Regio Bus
signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
port map (
CLK_IN => clk_100_i,
RESET_IN => reset_i,
- CLK_NX_MAIN_IN => nx_main_clk,
- PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock,
- PLL_RESET_OUT => nx_pll_reset,
-
+
+ CLK_D1_IN => clk_scaler,
+
TRIGGER_OUT => fee1_trigger,
- SCALER_LATCH_IN => SCALER_LATCH_IN,
- SCALER_CHANNELS_IN => SCALER_CHANNELS_IN,
+ LATCH_IN => SCALER_LATCH_IN,
+ CHANNELS_IN => SCALER_CHANNELS_IN,
TIMING_TRIGGER_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
- --DEBUG_LINE_OUT => TEST_LINE
- DEBUG_LINE_OUT => open
+ DEBUG_LINE_OUT => TEST_LINE
+ --DEBUG_LINE_OUT => open
);
nx1_regio_addr_in(15 downto 12) <= (others => '0');
- TEST_LINE(0) <= clk_100_i;
- TEST_LINE(1) <= nx1_regio_read_enable_in;
- TEST_LINE(2) <= nx1_regio_write_enable_in;
- TEST_LINE(3) <= nx1_regio_dataready_out;
- TEST_LINE(4) <= nx1_regio_write_ack_out;
- TEST_LINE(5) <= nx1_regio_unknown_addr_out;
- TEST_LINE(15 downto 6) <= (others => '0');
+ -- TEST_LINE(0) <= clk_100_i;
+ -- TEST_LINE(1) <= nx1_regio_read_enable_in;
+ -- TEST_LINE(2) <= nx1_regio_write_enable_in;
+ -- TEST_LINE(3) <= nx1_regio_dataready_out;
+ -- TEST_LINE(4) <= nx1_regio_write_ack_out;
+ -- TEST_LINE(5) <= nx1_regio_unknown_addr_out;
+ -- TEST_LINE(6) <= LED_GREEN;
+ -- TEST_LINE(7) <= LED_ORANGE;
+ -- TEST_LINE(8) <= LED_RED;
+ -- TEST_LINE(9) <= LED_YELLOW;
+ -- TEST_LINE(15 downto 10) <= (others => '0');
---------------------------------------------------------------------------
-- SED Detection
---------------------------------------------------------------------------
-- nXyter Main and ADC Clocks
-----------------------------------------------------------------------------
- -- Scaler Domain Clock(400MHz)
- pll_clk400_1: entity work.pll_clk400
+ -- Scaler Domain Clock 500MHz
+ pll_scaler_1: entity work.pll_clk400
port map (
CLK => CLK_PCLK_RIGHT,
- RESET => nx_pll_reset,
- CLKOP => nx_main_clk,
- LOCK => nx_pll_clk_lock
+ RESET => clk_scaler_reset,
+ CLKOP => clk_scaler,
+ LOCK => clk_scaler_lock
);
end architecture;
USE PRIMARY NET "CLK_PCLK_RIGHT_c";
USE PRIMARY NET "clk_100_i";
-USE PRIMARY NET "nx_main_clk";
#################################################################
# Reset Nets
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
REGION "MEDIA_UPLINK" "R102C95D" 13 25;
LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
#################################################
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
+
+MULTICYCLE TO CELL "scaler_0/scaler_channel_*/reset_clk_d1_ff*" 30 ns;
+
+MULTICYCLE TO CELL "scaler_0/scaler_channel_*/PULSE_IN_to_pulse/pulse_ff*" 30 ns;
+MULTICYCLE TO CELL "scaler_0/scaler_channel_*/LATCH_IN_to_latch/pulse_ff*" 30 ns;
+MULTICYCLE FROM CELL "scaler_0/scaler_channel_*/internal_pulse*" 100 ns;
+
+MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
+
+#MULTICYCLE TO CELL "scaler_0/scaler_channel_1/INHIBIT_IN_to_inhibit/pulse_ff*" 30 ns;
+#MULTICYCLE TO CELL "scaler_0/scaler_channel_1/counter_latched*" 30 ns;
+
-# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns;
# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns;
# MULTICYCLE to CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns;
# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns;
# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns;
# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns;
#
-# MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
-# MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
-# MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
-# MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
+
#################################################################
# Constraints for nxyter inputs
jspc29 / trb3.git / commitdiff