# write strobe can be delayed due to A/D being stable after access
MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-# SCI write signal problem...
-#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
-#BLOCK INTERCLOCKDOMAIN PATHS;
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
NET_CLK_FULL_IN => med2int(4).clk_full,
NET_CLK_HALF_IN => med2int(4).clk_half,
- GLOBAL_RESET_IN => '0', --global_reset_i,
+ GLOBAL_RESET_IN => global_reset_i,
RESET_FROM_NET_IN => '0',
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
---------------------------------------------------------------------------
THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => open,
- MEDIA_MED2INT(1) => open,
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => med2int(4),
- MEDIA_INT2MED(0) => open,
- MEDIA_INT2MED(1) => open,
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => int2med(4),
+ MEDIA_MED2INT(0 to 2) => open,
+ MEDIA_MED2INT(3) => med2int(4),
+ MEDIA_INT2MED(0 to 2) => open,
+ MEDIA_INT2MED(3) => int2med(4),
-- komma operation
- RX_DLM_OUT(0) => open,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => rx_dlm_i,
+ RX_DLM_OUT(2 downto 0) => open,
+ RX_DLM_OUT(3) => rx_dlm_i,
RX_DLM_WORD_OUT(23 downto 0) => open,
RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => send_rst_i,
- RX_RST_WORD_OUT => send_rst_word_i,
- TX_RST_IN => '0',
- TX_RST_WORD_IN => x"00",
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => send_dlm_word_i,
+ RX_RST_OUT => send_rst_i,
+ RX_RST_WORD_OUT => send_rst_word_i,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
-- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => master_clk_i,
- QUAD_RST_IN => '0', --global_reset_i,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => global_reset_i,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
- WAP_REQUESTED_IN => x"0",
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => master_clk_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => global_reset_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
- SD_PRSNT_N_IN(0) => '1',
- SD_PRSNT_N_IN(1) => '1',
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(0) => '1',
- SD_LOS_IN(1) => '1',
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(0) => open,
- SD_TXDIS_OUT(1) => open,
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN(2 downto 0) => (others => '1'),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(2 downto 0) => (others => '1'),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(2 downto 0) => open,
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
-- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
);
---------------------------------------------------------------------------
THE_MAIN_TX_RST: main_tx_reset_RS
port map (
CLEAR => '0',
- CLK_REF => CLK_SUPPL_PCLK, --clk_full_osc,
+ CLK_REF => CLK_SUPPL_PCLK,
TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i,
TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
TX_PLL_LOL_QD_C_IN => '0',
---------------------------------------------------------------------------
THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
RESET => reset_i,
-- Media Interface TX/RX
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- QUAD_RST_IN => '0', --global_reset_i,
+ QUAD_RST_IN => '0',
LINK_TX_NULL_IN => global_reset_i,
LINK_RX_NULL_OUT => open,
TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i,
signal slave_active_fake : std_logic;
signal send_reset_i : std_logic;
--- attribute syn_keep : boolean;
--- attribute syn_preserve : boolean;
--- attribute syn_keep of tx_dlm_i : signal is true;
--- attribute syn_preserve of tx_dlm_i : signal is true;
--- attribute syn_keep of rx_dlm_i : signal is true;
--- attribute syn_preserve of rx_dlm_i : signal is true;
-
begin
-THE_TIME_COUNTER_PROC: process( clk_full_osc )
-begin
- if( rising_edge(clk_full_osc) ) then
- time_counter <= time_counter + 1;
- end if;
-end process THE_TIME_COUNTER_PROC;
+ THE_TIME_COUNTER_PROC: process( clk_full_osc )
+ begin
+ if( rising_edge(clk_full_osc) ) then
+ time_counter <= time_counter + 1;
+ end if;
+ end process THE_TIME_COUNTER_PROC;
---------------------------------------------------------------------------
-- Clock & Reset Handling
---------------------------------------------------------------------------
-THE_CLOCK_RESET : entity work.clock_reset_handler
+ THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
INT_CLK_IN => CLK_CORE_PCLK,
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
-- Reset by GbE: a minimum delay of 1us is kept before the reset
-- pulse is injected into the reset handler.
- proc_make_reset : process begin
+ PROC_MAKE_RESET : process
+ begin
wait until rising_edge(clk_sys);
if( reset_via_gbe = '1' ) then
reset_via_gbe_long <= '1';
end if;
last_reset_via_gbe_long <= reset_via_gbe_long;
make_reset_by_gbe <= last_reset_via_gbe_long and not reset_via_gbe_long; -- pulse, 1 clock cycle
- end process;
+ end process PROC_MAKE_RESET;
-- REMARK: this should be transfered to GbE part.
-- BUG: for some reasons, some TRB3sc refuse to work with this reset. Links are not destroyed reliably,
-- and strange things happen with WAP.
gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i, -- check
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => open,
- MEDIA_MED2INT(1) => open,
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => med2int(0),
- MEDIA_INT2MED(0) => open,
- MEDIA_INT2MED(1) => open,
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => int2med(0),
+ MEDIA_MED2INT(0 to 2) => open,
+ MEDIA_MED2INT(3) => med2int(0),
+ MEDIA_INT2MED(0 to 2) => open,
+ MEDIA_INT2MED(3) => int2med(0),
-- Sync operation
- RX_DLM_OUT(0) => open,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => rx_dlm_i,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => tx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => open,
- RX_RST_WORD_OUT => open,
- TX_RST_IN => tx_rst_i,
- TX_RST_WORD_IN => send_rst_word_i,
+ RX_DLM_OUT(2 downto 0) => open,
+ RX_DLM_OUT(3) => rx_dlm_i,
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => tx_dlm_i,
+ TX_DLM_WORD_IN => send_dlm_word_i,
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => tx_rst_i,
+ TX_RST_WORD_IN => send_rst_word_i,
-- sync operation
- WORD_SYNC_IN => '1',
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => open,
- QUAD_RST_IN => '0', -- check
- LINK_TX_NULL_IN => send_reset_i,
- LINK_RX_NULL_OUT => open,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
- TX_CLK_AVAIL_OUT => open,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN(0) => '0',
- DESTROY_LINK_IN(1) => '0',
- DESTROY_LINK_IN(2) => '0',
- DESTROY_LINK_IN(3) => destroy_link_i,
- WAP_REQUESTED_IN => wap_requested_i,
+ WORD_SYNC_IN => '1',
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => open,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => send_reset_i,
+ LINK_RX_NULL_OUT => open,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
+ TX_CLK_AVAIL_OUT => open,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN(2 downto 0) => (others => '0'),
+ DESTROY_LINK_IN(3) => destroy_link_i,
+ WAP_REQUESTED_IN => wap_requested_i,
--SFP Connection
- SD_PRSNT_N_IN(0) => '1',
- SD_LOS_IN(0) => '1',
- SD_TXDIS_OUT(0) => open,
- SD_PRSNT_N_IN(1) => '1',
- SD_LOS_IN(1) => '1',
- SD_TXDIS_OUT(1) => open,
- SD_PRSNT_N_IN(2) => '1',
- SD_LOS_IN(2) => '1',
- SD_TXDIS_OUT(2) => open,
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN(2 downto 0) => (others => '1'),
+ SD_LOS_IN(2 downto 0) => (others => '1'),
+ SD_TXDIS_OUT(2 downto 0) => open,
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
-- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
);
- master_clk_i <= CLK_SUPPL_PCLK; --clk_full_osc;
+ master_clk_i <= CLK_SUPPL_PCLK;
THE_MAIN_TX_RST: main_tx_reset_RS
port map (
- CLEAR => '0',
- CLK_REF => CLK_SUPPL_PCLK, --clk_full_osc,
+ CLEAR => '0', -- DO NOT USE
+ CLK_REF => CLK_SUPPL_PCLK,
TX_PLL_LOL_QD_A_IN => '0',
TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
TX_PLL_LOL_QD_C_IN => '0',
tx_dlm_i <= dlm_send_qq;
-- LED feedback
--- LED_WHITE(1) <= not send_rst_word_i(1);
LED_WHITE(1) <= not std_logic(dlm_tag_ctr(7));
LED_WHITE(0) <= not send_rst_word_i(0);
D_OUT(0) => rst_ctrs_mc
);
--- HDR_IO(10 downto 1) <= (others => '0');
--- TEST_LINE(15 downto 0) <= (others => '0');
-
-- RST send pulse generator
THE_RST_SEND_PROC: process( master_clk_i )
begin
-w
-l 5
-s 12
--t 66 # seed setting here! # 32
+-t 34 # seed setting here! # 32
-c 1
-e 2
-i 15
MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-MULTICYCLE FROM ASIC THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE TO ASIC THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
# SCI write signal problem...
FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz;
-
-MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns;
-MULTICYCLE FROM CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns;
-MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i";
-BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i";
-BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i";
-BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i";
-
-MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-MULTICYCLE FROM CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i";
-BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i";
-BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i";
-BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i";
-
-MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns;
-MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i";
-BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i";
-BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i";
-BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i";
-
-MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_4_PCSC/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_write_i";
-BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_read_i";
-
-MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns;
-MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns;
-MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i";
-BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i";
-BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
-BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
-
-MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
signal tx_pll_lol_qd_b_i : std_logic;
signal tx_pll_lol_qd_c_i : std_logic;
signal tx_pll_lol_qd_d_i : std_logic;
- signal tx_pll_lol_all_i : std_logic;
signal tx_clk_avail_i : std_logic;
signal tx_pcs_rst_i : std_logic;
signal sync_tx_quad_i : std_logic;
signal link_tx_ready_i : std_logic;
- signal slave_active_i : std_logic;
signal rx_dlm_i : std_logic;
signal tx_reset_state : std_logic_vector(3 downto 0);
signal debug_i : std_logic_vector(31 downto 0);
-- PCSA: Uplink when backplane is used
---------------------------------------------------------------------------
gen_PCSA : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => med2int(INTERFACE_NUM-1),
- MEDIA_MED2INT(1) => open,
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => open,
- MEDIA_INT2MED(0) => int2med(INTERFACE_NUM-1),
- MEDIA_INT2MED(1) => open,
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => open,
+ MEDIA_MED2INT(0) => med2int(INTERFACE_NUM-1),
+ MEDIA_MED2INT(1 to 3) => open,
+ MEDIA_INT2MED(0) => int2med(INTERFACE_NUM-1),
+ MEDIA_INT2MED(1 to 3) => open,
-- komma operation
- RX_DLM_OUT(0) => rx_dlm_i,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => open,
--- RX_DLM_WORD_OUT => open,
+ RX_DLM_OUT(3 downto 1) => open,
+ RX_DLM_OUT(0) => rx_dlm_i,
+ RX_DLM_WORD_OUT(31 downto 8) => open,
RX_DLM_WORD_OUT(7 downto 0) => send_dlm_word_i,
- RX_DLM_WORD_OUT(15 downto 8) => open,
- RX_DLM_WORD_OUT(23 downto 16) => open,
- RX_DLM_WORD_OUT(31 downto 24) => open,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => send_rst_i,
- RX_RST_WORD_OUT => send_rst_word_i,
- TX_RST_IN => '0',
- TX_RST_WORD_IN => x"00",
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => send_dlm_word_i,
+ RX_RST_OUT => send_rst_i,
+ RX_RST_WORD_OUT => send_rst_word_i,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
-- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => master_clk_i,
- QUAD_RST_IN => global_reset_i,
- GLOBAL_RESET_OUT => global_reset_i,
- SLAVE_ACTIVE_OUT => slave_active_i,
- SLAVE_ACTIVE_IN => slave_active_i,
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
- WAP_REQUESTED_IN => x"0",
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => master_clk_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => global_reset_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => (others => '0'),
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
- SD_PRSNT_N_IN(0) => BACK_GPIO(1),
- SD_PRSNT_N_IN(1) => '1',
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => '1',
- SD_LOS_IN(0) => BACK_GPIO(1),
- SD_LOS_IN(1) => '1',
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
- SD_TXDIS_OUT(0) => BACK_GPIO(0),
- SD_TXDIS_OUT(1) => open,
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
+ SD_PRSNT_N_IN(0) => BACK_GPIO(1),
+ SD_PRSNT_N_IN(3 downto 1) => (others => '1'),
+ SD_LOS_IN(0) => BACK_GPIO(1),
+ SD_LOS_IN(3 downto 1) => (others => '1'),
+ SD_TXDIS_OUT(0) => BACK_GPIO(0),
+ SD_TXDIS_OUT(3 downto 1) => open,
--Control Interface
- BUS_RX => bussci1_rx,
- BUS_TX => bussci1_tx,
+ BUS_RX => bussci1_rx,
+ BUS_TX => bussci1_tx,
-- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
);
end generate;
-- PCSB: TrbNet downlinks (backplane)
---------------------------------------------------------------------------
gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
RESET => reset_i,
-- Media Interface TX/RX
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- QUAD_RST_IN => global_reset_i,
- GLOBAL_RESET_OUT => open,
- SLAVE_ACTIVE_OUT => open,
- SLAVE_ACTIVE_IN => slave_active_i,
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => open,
TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
TX_CLK_AVAIL_OUT => open,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
+ DESTROY_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
-- PCSB: TrbNet one uplink and three downlinks (no backplane)
---------------------------------------------------------------------------
gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
RESET => reset_i,
-- Media Interface TX/RX
RX_DLM_OUT(1) => open,
RX_DLM_OUT(2) => open,
RX_DLM_OUT(3) => rx_dlm_i,
--- RX_DLM_WORD_OUT => open,
- RX_DLM_WORD_OUT(7 downto 0) => open,
- RX_DLM_WORD_OUT(15 downto 8) => open,
- RX_DLM_WORD_OUT(23 downto 16) => open,
+ RX_DLM_WORD_OUT(23 downto 0) => open,
RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
TX_DLM_IN => rx_dlm_i,
TX_DLM_WORD_IN => send_dlm_word_i,
WORD_SYNC_OUT => word_sync_i,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => master_clk_i,
- QUAD_RST_IN => global_reset_i,
- GLOBAL_RESET_OUT => global_reset_i,
- SLAVE_ACTIVE_OUT => slave_active_i,
- SLAVE_ACTIVE_IN => slave_active_i,
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => global_reset_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
+ DESTROY_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
-- Status and control port
STAT_DEBUG => open,
CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
+ DEBUG_OUT => open
);
tx_pll_lol_qd_a_i <= '0';
THE_MAIN_TX_RST: main_tx_reset_RS
port map (
CLEAR => '0',
- CLK_REF => clk_full_osc,
+ CLK_REF => CLK_SUPPL_PCLK,
TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i,
TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i,
TX_PLL_LOL_QD_D_IN => tx_pll_lol_qd_d_i,
- TX_PLL_LOL_OUT => tx_pll_lol_all_i,
TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
SYNC_TX_QUAD_OUT => sync_tx_quad_i,
LINK_TX_READY_OUT => link_tx_ready_i,
STATE_OUT => tx_reset_state
);
-
--- sync_tx_quad_i <= '1';
---------------------------------------------------------------------------
-- PCSC: 4 downlinks
---------------------------------------------------------------------------
- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
RESET => reset_i,
-- Media Interface TX/RX
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- QUAD_RST_IN => global_reset_i,
- GLOBAL_RESET_OUT => open,
- SLAVE_ACTIVE_OUT => open,
- SLAVE_ACTIVE_IN => slave_active_i,
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => open,
TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i,
TX_CLK_AVAIL_OUT => open,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
+ DESTROY_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
-- PCSD: 2 downlinks (no GbE)
---------------------------------------------------------------------------
gen_PCSD : if INCLUDE_GBE = c_NO generate
- THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
RESET => reset_i,
-- Media Interface TX/RX
WORD_SYNC_OUT => open,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => open,
- QUAD_RST_IN => global_reset_i,
- GLOBAL_RESET_OUT => open,
- SLAVE_ACTIVE_OUT => open,
- SLAVE_ACTIVE_IN => slave_active_i,
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ QUAD_RST_IN => '0',
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => open,
TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i,
TX_CLK_AVAIL_OUT => open,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => x"0",
+ DESTROY_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
-- LED
---------------------------------------------------------------------------
--LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
- LED_GREEN <= not debug_i(24 + 3); -- LFD --debug_clock_reset(0);
- LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1);
- LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i;
- LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2);
+ LED_GREEN <= not debug_i(0 + 3); -- LFD --debug_clock_reset(0);
+ LED_ORANGE <= not debug_i(0 + 2); -- LHD --debug_clock_reset(1);
+ LED_RED <= not debug_i(0 + 1); -- LRR --not sed_error_i;
+ LED_YELLOW <= not debug_i(0 + 0); -- LTR --debug_clock_reset(2);
gen_hub_leds : for i in 0 to 6 generate
LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9);
MULTICYCLE FROM ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
MULTICYCLE TO ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
-# SCI write signal problem...
-#BLOCK NET THE_MEDIA_INTERFACE/sci_write_i;
-#BLOCK INTERCLOCKDOMAIN PATHS;
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
attribute syn_preserve of bustc_rx : signal is true;
signal tx_pll_lol_qd_b_i : std_logic;
- signal tx_pll_lol_all_i : std_logic;
signal sync_tx_quad_i : std_logic;
signal tx_clk_avail_i : std_logic;
signal link_tx_ready_i : std_logic;
signal send_rst_word_i : std_logic_vector(7 downto 0);
signal send_dlm_word_i : std_logic_vector(7 downto 0);
+ signal kill_quad : std_logic;
+
begin
---------------------------------------------------------------------------
DEBUG_OUT => debug_clock_reset
);
+ kill_quad <= not GSR_N;
+
gen_cal125 : if (USE_CALIBRATION_200MHZ = c_NO) generate
pll_calibration : entity work.pll_in125_out33
port map (
---------------------------------------------------------------------------
-- TrbNet Uplink
---------------------------------------------------------------------------
- THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS
+ THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_125M_RS
generic map(
- IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE),
- IS_WAP_ZERO => 1
+ IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => CLK_SUPPL_PCLK,
SYSCLK => clk_sys,
+ CLEAR => kill_quad,
RESET => reset_i,
-- Media Interface TX/RX
MEDIA_MED2INT(0) => open,
RX_DLM_OUT(1) => open,
RX_DLM_OUT(2) => open,
RX_DLM_OUT(3) => rx_dlm_i,
--- RX_DLM_WORD_OUT => open,
- RX_DLM_WORD_OUT(7 downto 0) => open,
- RX_DLM_WORD_OUT(15 downto 8) => open,
- RX_DLM_WORD_OUT(23 downto 16) => open,
+ RX_DLM_WORD_OUT(23 downto 0) => open,
RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
TX_DLM_IN => rx_dlm_i,
TX_DLM_WORD_IN => send_dlm_word_i,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => master_clk_i,
QUAD_RST_IN => '0',
- GLOBAL_RESET_OUT => global_reset_i,
- SLAVE_ACTIVE_OUT => open,
- SLAVE_ACTIVE_IN => '0',
- TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => global_reset_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN(0) => '0',
- DESTROY_LINK_IN(1) => '0',
- DESTROY_LINK_IN(2) => '0',
- DESTROY_LINK_IN(3) => '0',
+ DESTROY_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => '1',
THE_MAIN_TX_RST: main_tx_reset_RS
port map (
- CLEAR => '0',
- CLK_REF => clk_full_osc,
+ CLEAR => kill_quad, --'0',
+ CLK_REF => CLK_SUPPL_PCLK,
TX_PLL_LOL_QD_A_IN => '0',
TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i,
TX_PLL_LOL_QD_C_IN => '0',
TX_PLL_LOL_QD_D_IN => '0',
- TX_PLL_LOL_OUT => tx_pll_lol_all_i,
TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
SYNC_TX_QUAD_OUT => sync_tx_quad_i,
-- RJ_IO(1 downto 0) <= trig_gen_out_i(3 downto 2);
RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);
- RJ_IO(1) <= debug_i(1);
- RJ_IO(0) <= debug_i(0);
+ RJ_IO(1) <= '0'; --debug_i(1);
+ RJ_IO(0) <= '0'; --debug_i(0);
BACK_GPIO(1 downto 0) <= (others => 'Z');
BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2);
LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX
+-- THE_TOGGLE_PROC: process( clk_sys )
+-- begin
+-- if( rising_edge(clk_sys) ) then
+-- toggler <= not toggler;
+-- end if;
+-- end process THE_TOGGLE_PROC;
+
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
jspc29 / trb3sc.git / commitdiff