signal fifo_data_width_dataout_i : std_logic_vector(g_datawidthfifo - 1 downto 0);
signal fifo_data_width_datain_i : std_logic_vector(g_datawidthfifo - 1 downto 0);
signal fifo_data_width_rd_i, fifo_data_width_wr_i : std_logic;
- signal fifo_data_width_cnt_i : std_logic_vector(9 downto 0);
+ signal fifo_data_width_cnt_i : std_logic_vector(9 downto 0);
signal start_readout_slow_to_buffer : std_logic := '0';
signal start_readout : std_logic := '0';
signal slow_read_busy : std_logic := '0';
signal slow_read_done : std_logic := '0';
+ signal SLV_READ_IN_i : std_logic;
+ signal SLV_WRITE_IN_i : std_logic;
+ signal SLV_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal SLV_ADDR_IN_i : std_logic_vector(15 downto 0);
+
begin
start_readout <= start_readout_slow_to_buffer or trb_trigger;
SLV_NO_MORE_DATA_OUT <= '0';
SLV_UNKNOWN_ADDR_OUT <= '0';
start_slow_read <= '0';
+ SLV_ADDR_IN_i <= (others => '0');
+ SLV_DATA_IN_i <= (others => '0');
+ SLV_READ_IN_i <= '0';
+ SLV_WRITE_IN_i <= '0';
else
SLV_DATA_OUT <= (others => '0');
SLV_ACK_OUT <= '0';
SLV_UNKNOWN_ADDR_OUT <= '0';
start_slow_read <= '0';
+ SLV_ADDR_IN_i <= SLV_ADDR_IN;
+ SLV_DATA_IN_i <= SLV_DATA_IN;
+ SLV_READ_IN_i <= SLV_READ_IN;
+ SLV_WRITE_IN_i <= SLV_WRITE_IN;
+
if slow_read_busy = '1' then
if slow_read_done = '1' then
SLV_DATA_OUT <= slow_data;
SLV_ACK_OUT <= '1';
end if;
- elsif SLV_WRITE_IN = '1' then
- case SLV_ADDR_IN is
+ elsif SLV_WRITE_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0100" =>
- readout_mode_i <= SLV_DATA_IN(1 downto 0);
+ readout_mode_i <= SLV_DATA_IN_i(1 downto 0);
SLV_ACK_OUT <= '1';
when x"0101" =>
- readout_writes_aft_trig <= SLV_DATA_IN(g_cyc_mem_address_width - 1 downto 0);
+ readout_writes_aft_trig <= SLV_DATA_IN_i(g_cyc_mem_address_width - 1 downto 0);
SLV_ACK_OUT <= '1';
when x"0102" =>
- readout_words <= SLV_DATA_IN(g_cyc_mem_address_width - 1 downto 0);
+ readout_words <= SLV_DATA_IN_i(g_cyc_mem_address_width - 1 downto 0);
SLV_ACK_OUT <= '1';
when x"0103" =>
- sensor_id <= SLV_DATA_IN;
+ sensor_id <= SLV_DATA_IN_i;
SLV_ACK_OUT <= '1';
when x"0105" =>
- multiplexer_mask <= SLV_DATA_IN(g_mupix_links - 1 downto 0);
+ multiplexer_mask <= SLV_DATA_IN_i(g_mupix_links - 1 downto 0);
SLV_ACK_OUT <= '1';
when x"0106" =>
- multiplexer_channel_sel <= to_integer(unsigned(SLV_DATA_IN));
+ multiplexer_channel_sel <= to_integer(unsigned(SLV_DATA_IN_i));
SLV_ACK_OUT <= '1';
when others =>
slv_unknown_addr_out <= '1';
end case;
- elsif SLV_READ_IN = '1' then
- case SLV_ADDR_IN is
+ elsif SLV_READ_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0100" =>
SLV_DATA_OUT(1 downto 0) <= readout_mode_i;
SLV_ACK_OUT <= '1';
signal wr_status_int : std_logic := '0';
signal wr_dummy_int : std_logic := '0';
+ signal SLV_READ_IN_i : std_logic;
+ signal SLV_WRITE_IN_i : std_logic;
+ signal SLV_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal SLV_ADDR_IN_i : std_logic_vector(15 downto 0);
+
begin
Signal_Edge_Detect : process(CLK_IN) is
trigger_handler_proc : process(clk_in) is
begin -- process trigger_handler_proc
if rising_edge(CLK_IN) then
- trigger_busy_int <= '1';
- fee_trg_release_int <= '0';
- wr_header_int <= '0';
- wr_data_int <= '0';
- wr_status_int <= '0';
- wr_dummy_int <= '0';
+ trigger_busy_int <= '1';
+ fee_trg_release_int <= '0';
+ wr_header_int <= '0';
+ wr_data_int <= '0';
+ wr_status_int <= '0';
+ wr_dummy_int <= '0';
valid_trigger_int <= '0';
fee_data_finished_int <= '0';
fee_trg_release_int <= '0';
slv_no_more_data_out <= '0';
slv_unknown_addr_out <= '0';
- if slv_write_in = '1' then
- case SLV_ADDR_IN is
+ SLV_ADDR_IN_i <= SLV_ADDR_IN;
+ SLV_DATA_IN_i <= SLV_DATA_IN;
+ SLV_READ_IN_i <= SLV_READ_IN;
+ SLV_WRITE_IN_i <= SLV_WRITE_IN;
+
+ if SLV_WRITE_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0125" =>
- reset_trigger_counters <= SLV_DATA_IN(0);
+ reset_trigger_counters <= SLV_DATA_IN_i(0);
slv_ack_out <= '1';
when x"0126" =>
- reset_trigger_state <= SLV_DATA_IN(0);
+ reset_trigger_state <= SLV_DATA_IN_i(0);
slv_ack_out <= '1';
when x"0127" =>
- bypass_trigger <= SLV_DATA_IN(0);
+ bypass_trigger <= SLV_DATA_IN_i(0);
slv_ack_out <= '1';
when others =>
slv_unknown_addr_out <= '1';
end case;
- elsif slv_read_in = '1' then
- case slv_addr_in is
+ elsif SLV_READ_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0120" =>
slv_data_out <= std_logic_vector(trigger_rate_acc);
slv_ack_out <= '1';
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
entity FrameGeneratorMux is
- generic(
- FIFODEPTH : positive := 256;
- DATAWIDTH : natural := 32
+ generic(
+ FIFODEPTH : positive := 256;
+ DATAWIDTH : natural := 32
);
- port(
- clk : in std_logic;
- reset : in std_logic;
- serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0);
- serdes_fifo_full : in std_logic_vector(3 downto 0);
- serdes_fifo_empty : in std_logic_vector(3 downto 0);
- in_rden : in std_logic_vector(3 downto 0);
- serdes_fifo_rden : out std_logic_vector(3 downto 0);
- out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0);
- out_fifo_full : out std_logic_vector(3 downto 0);
- out_fifo_empty : out std_logic_vector(3 downto 0);
- --TRB slow control
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0);
+ serdes_fifo_full : in std_logic_vector(3 downto 0);
+ serdes_fifo_empty : in std_logic_vector(3 downto 0);
+ in_rden : in std_logic_vector(3 downto 0);
+ serdes_fifo_rden : out std_logic_vector(3 downto 0);
+ out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0);
+ out_fifo_full : out std_logic_vector(3 downto 0);
+ out_fifo_empty : out std_logic_vector(3 downto 0);
+ --TRB slow control
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
);
end FrameGeneratorMux;
architecture Behavioral of FrameGeneratorMux is
-component Generator3
+ component Generator3
generic(
- constant iWIDTH : natural
- );
+ constant iWIDTH : natural
+ );
port(
- clk : in std_logic;
- reset : in std_logic;
- start_gen : in std_logic;
- data_num : in std_logic_vector(31 downto 0);
- data_pause : in std_logic_vector(31 downto 0);
- data_down : in std_logic_vector(31 downto 0);
- chan_sel : in std_logic_vector(1 downto 0);
- data_out : out std_logic_vector(iWIDTH - 1 downto 0);
- writeEn : out std_logic
- );
-end component Generator3;
+ clk : in std_logic;
+ reset : in std_logic;
+ start_gen : in std_logic;
+ data_num : in std_logic_vector(31 downto 0);
+ data_pause : in std_logic_vector(31 downto 0);
+ data_down : in std_logic_vector(31 downto 0);
+ chan_sel : in std_logic_vector(1 downto 0);
+ data_out : out std_logic_vector(iWIDTH - 1 downto 0);
+ writeEn : out std_logic
+ );
+ end component Generator3;
-component STD_FIFO
+ component STD_FIFO
generic (
- constant DATA_WIDTH : positive;
- constant FIFO_DEPTH : positive
- );
+ constant DATA_WIDTH : positive;
+ constant FIFO_DEPTH : positive
+ );
port (
- CLK : in std_logic;
- RST : in std_logic;
- WriteEn : in std_logic;
- DataIn : in std_logic_vector (DATA_WIDTH - 1 downto 0);
- ReadEn : in std_logic;
- DataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0);
- Empty : out std_logic;
- Full : out std_logic
- );
-end component STD_FIFO;
+ CLK : in std_logic;
+ RST : in std_logic;
+ WriteEn : in std_logic;
+ DataIn : in std_logic_vector (DATA_WIDTH - 1 downto 0);
+ ReadEn : in std_logic;
+ DataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+ );
+ end component STD_FIFO;
-component DataSourceSelector is
+ component DataSourceSelector is
generic(
- constant WIDTH : natural
- );
+ constant WIDTH : natural
+ );
port(
- -- FrameGen Data
- fg0in : in std_logic_vector(WIDTH - 1 downto 0);
- fg1in : in std_logic_vector(WIDTH - 1 downto 0);
- fg2in : in std_logic_vector(WIDTH - 1 downto 0);
- fg3in : in std_logic_vector(WIDTH - 1 downto 0);
- fg_full : in std_logic_vector(3 downto 0);
- fg_empty : in std_logic_vector(3 downto 0);
- fg_rden : out std_logic_vector(3 downto 0);
-
- -- SerDes Data
- serdes0 : in std_logic_vector(WIDTH - 1 downto 0);
- serdes1 : in std_logic_vector(WIDTH - 1 downto 0);
- serdes2 : in std_logic_vector(WIDTH - 1 downto 0);
- serdes3 : in std_logic_vector(WIDTH - 1 downto 0);
- sd_full : in std_logic_vector(3 downto 0);
- sd_empty : in std_logic_vector(3 downto 0);
- sd_rden : out std_logic_vector(3 downto 0);
-
- sel : in std_logic; -- Selects FrameGen
- rst : in std_logic;
-
- out_data0 : out std_logic_vector(WIDTH - 1 downto 0);
- out_data1 : out std_logic_vector(WIDTH - 1 downto 0);
- out_data2 : out std_logic_vector(WIDTH - 1 downto 0);
- out_data3 : out std_logic_vector(WIDTH - 1 downto 0);
- fifo_rdenx: in std_logic_vector(3 downto 0);
- fifo_full : out std_logic_vector(3 downto 0);
- fifo_empty: out std_logic_vector(3 downto 0)
- );
-end component DataSourceSelector;
+ -- FrameGen Data
+ fg0in : in std_logic_vector(WIDTH - 1 downto 0);
+ fg1in : in std_logic_vector(WIDTH - 1 downto 0);
+ fg2in : in std_logic_vector(WIDTH - 1 downto 0);
+ fg3in : in std_logic_vector(WIDTH - 1 downto 0);
+ fg_full : in std_logic_vector(3 downto 0);
+ fg_empty : in std_logic_vector(3 downto 0);
+ fg_rden : out std_logic_vector(3 downto 0);
+
+ -- SerDes Data
+ serdes0 : in std_logic_vector(WIDTH - 1 downto 0);
+ serdes1 : in std_logic_vector(WIDTH - 1 downto 0);
+ serdes2 : in std_logic_vector(WIDTH - 1 downto 0);
+ serdes3 : in std_logic_vector(WIDTH - 1 downto 0);
+ sd_full : in std_logic_vector(3 downto 0);
+ sd_empty : in std_logic_vector(3 downto 0);
+ sd_rden : out std_logic_vector(3 downto 0);
+
+ sel : in std_logic; -- Selects FrameGen
+ rst : in std_logic;
+
+ out_data0 : out std_logic_vector(WIDTH - 1 downto 0);
+ out_data1 : out std_logic_vector(WIDTH - 1 downto 0);
+ out_data2 : out std_logic_vector(WIDTH - 1 downto 0);
+ out_data3 : out std_logic_vector(WIDTH - 1 downto 0);
+ fifo_rdenx : in std_logic_vector(3 downto 0);
+ fifo_full : out std_logic_vector(3 downto 0);
+ fifo_empty : out std_logic_vector(3 downto 0)
+ );
+ end component DataSourceSelector;
-- signal types
-type chan_type is array (0 to 3) of std_logic_vector(1 downto 0);
-type data_type is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
+ type chan_type is array (0 to 3) of std_logic_vector(1 downto 0);
+ type data_type is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
-- Internal signals: Data Generator
-signal gen_start : std_logic := '0';
-signal gen_num : std_logic_vector(31 downto 0) := (others => '0');
-signal gen_pause : std_logic_vector(31 downto 0) := (others => '0');
-signal gen_down : std_logic_vector(31 downto 0) := (others => '0');
-signal gen_wren : std_logic_vector(3 downto 0) := (others => '0');
-signal gen_chansel : chan_type := ("00", "01", "10", "11");
-signal gen_data : data_type;
+ signal gen_start : std_logic := '0';
+ signal gen_num : std_logic_vector(31 downto 0) := (others => '0');
+ signal gen_pause : std_logic_vector(31 downto 0) := (others => '0');
+ signal gen_down : std_logic_vector(31 downto 0) := (others => '0');
+ signal gen_wren : std_logic_vector(3 downto 0) := (others => '0');
+ signal gen_chansel : chan_type := ("00", "01", "10", "11");
+ signal gen_data : data_type;
-- Internal signals: Fifo
-signal fifo_data : data_type;
-signal fifo_rden : std_logic_vector(3 downto 0);
-signal fifo_ff : std_logic_vector(3 downto 0);
-signal fifo_ef : std_logic_vector(3 downto 0);
+ signal fifo_data : data_type;
+ signal fifo_rden : std_logic_vector(3 downto 0);
+ signal fifo_ff : std_logic_vector(3 downto 0);
+ signal fifo_ef : std_logic_vector(3 downto 0);
-- Internal signals: Datasource Selector
-signal mux_sel : std_logic := '0';
+ signal mux_sel : std_logic := '0';
+
+ signal SLV_READ_IN_i : std_logic;
+ signal SLV_WRITE_IN_i : std_logic;
+ signal SLV_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal SLV_ADDR_IN_i : std_logic_vector(15 downto 0);
-begin -- Behavioral
+begin -- Behavioral
- Frame_Generator: for J in 0 to 3 generate
- Data_Gen_J: Generator3
- generic map(
- iWIDTH => DATAWIDTH
+ Frame_Generator : for J in 0 to 3 generate
+ Data_Gen_J : Generator3
+ generic map(
+ iWIDTH => DATAWIDTH
)
- port map(
- clk => clk,
- reset => reset,
- start_gen => gen_start,
- data_num => gen_num,
- data_pause => gen_pause,
- data_down => gen_down,
- chan_sel => gen_chansel(J),
- writeEn => gen_wren(J),
- data_out => gen_data(J)
+ port map(
+ clk => clk,
+ reset => reset,
+ start_gen => gen_start,
+ data_num => gen_num,
+ data_pause => gen_pause,
+ data_down => gen_down,
+ chan_sel => gen_chansel(J),
+ writeEn => gen_wren(J),
+ data_out => gen_data(J)
);
-
- FIFO_J: STD_FIFO
- generic map(
- DATA_WIDTH => DATAWIDTH,
- FIFO_DEPTH => FIFODEPTH
+
+ FIFO_J : STD_FIFO
+ generic map(
+ DATA_WIDTH => DATAWIDTH,
+ FIFO_DEPTH => FIFODEPTH
)
- port map(
- CLK => clk,
- RST => reset,
- WriteEn => gen_wren(J),
- ReadEn => fifo_rden(J),
- DataIn => gen_data(J),
- DataOut => fifo_data(J),
- Full => fifo_ff(J),
- Empty => fifo_ef(J)
+ port map(
+ CLK => clk,
+ RST => reset,
+ WriteEn => gen_wren(J),
+ ReadEn => fifo_rden(J),
+ DataIn => gen_data(J),
+ DataOut => fifo_data(J),
+ Full => fifo_ff(J),
+ Empty => fifo_ef(J)
);
- end generate Frame_Generator;
-
- Mux: DataSourceSelector
+ end generate Frame_Generator;
+
+ Mux : DataSourceSelector
generic map(
- WIDTH => DATAWIDTH
- )
+ WIDTH => DATAWIDTH
+ )
port map(
- rst => reset,
- sel => mux_sel,
- fg0in => fifo_data(0),
- fg1in => fifo_data(1),
- fg2in => fifo_data(2),
- fg3in => fifo_data(3),
- fg_full => fifo_ff,
- fg_empty => fifo_ef,
- fg_rden => fifo_rden,
- serdes0 => serdes_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH),
- serdes1 => serdes_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH),
- serdes2 => serdes_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH),
- serdes3 => serdes_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH),
- sd_full => serdes_fifo_full,
- sd_empty => serdes_fifo_empty,
- sd_rden => serdes_fifo_rden,
- out_data0 => out_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH),
- out_data1 => out_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH),
- out_data2 => out_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH),
- out_data3 => out_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH),
- fifo_full => out_fifo_full,
- fifo_empty => out_fifo_empty,
- fifo_rdenx => in_rden
- );
-
+ rst => reset,
+ sel => mux_sel,
+ fg0in => fifo_data(0),
+ fg1in => fifo_data(1),
+ fg2in => fifo_data(2),
+ fg3in => fifo_data(3),
+ fg_full => fifo_ff,
+ fg_empty => fifo_ef,
+ fg_rden => fifo_rden,
+ serdes0 => serdes_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH),
+ serdes1 => serdes_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH),
+ serdes2 => serdes_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH),
+ serdes3 => serdes_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH),
+ sd_full => serdes_fifo_full,
+ sd_empty => serdes_fifo_empty,
+ sd_rden => serdes_fifo_rden,
+ out_data0 => out_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH),
+ out_data1 => out_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH),
+ out_data2 => out_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH),
+ out_data3 => out_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH),
+ fifo_full => out_fifo_full,
+ fifo_empty => out_fifo_empty,
+ fifo_rdenx => in_rden
+ );
+
----------------------------------------------------------------------------------
-- TRB Slave Bus
-- 0x0140: start pseudo data generator (writes data to fifo)
-- 0x0144: select data source (0 for MuPix data, 1 for pseudo data)
----------------------------------------------------------------------------------
-SLV_BUS_HANDLER: process (clk)
- begin
- if rising_edge(clk) then
- SLV_DATA_OUT <= (others => '0');
- SLV_ACK_OUT <= '0';
- SLV_UNKNOWN_ADDR_OUT <= '0';
- SLV_NO_MORE_DATA_OUT <= '0';
- gen_start <= '0';
-
- if SLV_READ_IN = '1' then
- case SLV_ADDR_IN is
- when x"0141" =>
- SLV_DATA_OUT <= gen_num;
- SLV_ACK_OUT <= '1';
- when x"0142" =>
- SLV_DATA_OUT <= gen_pause;
- SLV_ACK_OUT <= '1';
- when x"0143" =>
- SLV_DATA_OUT <= gen_down;
- SLV_ACK_OUT <= '1';
- when x"0144" =>
- SLV_DATA_OUT(0) <= mux_sel;
- SLV_ACK_OUT <= '1';
- when others =>
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end case;
-
- elsif SLV_WRITE_IN = '1' then
- case SLV_ADDR_IN is
- when x"0140" =>
- gen_start <= SLV_DATA_IN(0);
- SLV_ACK_OUT <= '1';
- when x"0141" =>
- gen_num <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"0142" =>
- gen_pause <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"0143" =>
- gen_down <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"0144" =>
- mux_sel <= SLV_DATA_IN(0);
- SLV_ACK_OUT <= '1';
- when others =>
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end case;
- end if;
- end if;
- end process SLV_BUS_HANDLER;
+ SLV_BUS_HANDLER : process (clk)
+ begin
+ if rising_edge(clk) then
+ SLV_DATA_OUT <= (others => '0');
+ SLV_ACK_OUT <= '0';
+ SLV_UNKNOWN_ADDR_OUT <= '0';
+ SLV_NO_MORE_DATA_OUT <= '0';
+ gen_start <= '0';
+
+ SLV_ADDR_IN_i <= SLV_ADDR_IN;
+ SLV_DATA_IN_i <= SLV_DATA_IN;
+ SLV_READ_IN_i <= SLV_READ_IN;
+ SLV_WRITE_IN_i <= SLV_WRITE_IN;
+
+ if SLV_READ_IN_i = '1' then
+ case SLV_ADDR_IN_i is
+ when x"0141" =>
+ SLV_DATA_OUT <= gen_num;
+ SLV_ACK_OUT <= '1';
+ when x"0142" =>
+ SLV_DATA_OUT <= gen_pause;
+ SLV_ACK_OUT <= '1';
+ when x"0143" =>
+ SLV_DATA_OUT <= gen_down;
+ SLV_ACK_OUT <= '1';
+ when x"0144" =>
+ SLV_DATA_OUT(0) <= mux_sel;
+ SLV_ACK_OUT <= '1';
+ when others =>
+ SLV_UNKNOWN_ADDR_OUT <= '1';
+ end case;
+
+ elsif SLV_WRITE_IN_i = '1' then
+ case SLV_ADDR_IN_i is
+ when x"0140" =>
+ gen_start <= SLV_DATA_IN_i(0);
+ SLV_ACK_OUT <= '1';
+ when x"0141" =>
+ gen_num <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"0142" =>
+ gen_pause <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"0143" =>
+ gen_down <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"0144" =>
+ mux_sel <= SLV_DATA_IN_i(0);
+ SLV_ACK_OUT <= '1';
+ when others =>
+ SLV_UNKNOWN_ADDR_OUT <= '1';
+ end case;
+ end if;
+ end if;
+ end process SLV_BUS_HANDLER;
end Behavioral;
use ieee.numeric_std.all;
entity MupixBoardDAC is
- generic(
- fpga_clock_speed : integer := 1e8;
- spi_clock_speed : integer := 5e4);
- port(
- clk : in std_logic; --clock
- reset : in std_logic; --reset
- --DAC signals
- spi_dout_dac : in std_logic; --dac serial data from board
- dac4_dout : in std_logic; --serial data in from threshold dac
- spi_dout_adc : in std_logic; --adc serial data from board
- spi_clk : out std_logic; --serial clock
- spi_din : out std_logic; --serial data out
- spi_ld_tmp_dac : out std_logic; --load temperature dac
- spi_ld_thres : out std_logic; --load threshold and injection dac
- spi_cs_adc : out std_logic; --load adc
- injection_pulse : out std_logic; --injection pulse to board
- --TRB slow control
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic);
+ generic(
+ fpga_clock_speed : integer := 1e8;
+ spi_clock_speed : integer := 5e4);
+ port(
+ clk : in std_logic; --clock
+ reset : in std_logic; --reset
+ --DAC signals
+ spi_dout_dac : in std_logic; --dac serial data from board
+ dac4_dout : in std_logic; --serial data in from threshold dac
+ spi_dout_adc : in std_logic; --adc serial data from board
+ spi_clk : out std_logic; --serial clock
+ spi_din : out std_logic; --serial data out
+ spi_ld_tmp_dac : out std_logic; --load temperature dac
+ spi_ld_thres : out std_logic; --load threshold and injection dac
+ spi_cs_adc : out std_logic; --load adc
+ injection_pulse : out std_logic; --injection pulse to board
+ --TRB slow control
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic);
end entity MupixBoardDAC;
architecture RTL of MupixBoardDAC is
-
- component LTC1658SPI
- generic(
- data_length : integer;
- fpga_clock_speed : integer;
- spi_clock_speed : integer
- );
- port(
- clk : in std_logic;
- reset : in std_logic;
- start_write : in std_logic;
- spi_data_in : in std_logic_vector(data_length - 1 downto 0);
- spi_data_from_chip : in std_logic;
- spi_data_to_chip : out std_logic;
- spi_data_out : out std_logic_vector(data_length - 1 downto 0);
- spi_clk : out std_logic;
- spi_ld : out std_logic
- );
- end component LTC1658SPI;
-
- component ADS1018SPI
- generic(
- fpga_clock_speed : integer;
- spi_clock_speed : integer
- );
- port(
- clk : in std_logic;
- reset : in std_logic;
- start_write : in std_logic;
- config_in : in std_logic_vector(15 downto 0);
- spi_data_from_chip : in std_logic;
- spi_data_to_chip : out std_logic;
- spi_data_out : out std_logic_vector(31 downto 0);
- spi_clk : out std_logic;
- spi_cs : out std_logic
- );
- end component ADS1018SPI;
-
- component injection_generator
- port(
- rst : in std_logic;
- clk : in std_logic;
- pulse_length : in std_logic_vector(31 downto 0);
- pulse_pause : in std_logic_vector(31 downto 0);
- pulse_number : in std_logic_vector(31 downto 0);
- pulse_start : in std_logic;
- pulse_o : out std_logic
- );
- end component injection_generator;
-
- constant c_bits_threshold_dacs : integer := 64; --4*16 bit of the four DACs
- signal start_write_threshold : std_logic := '0';
- signal spi_data_in_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
- signal spi_data_to_chip_threshold : std_logic;
- signal spi_data_out_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
- signal spi_clk_threshold : std_logic;
- constant c_bits_temperature_dac : integer := 16;
- signal start_write_temperature : std_logic := '0';
- signal spi_data_in_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
- signal spi_data_to_chip_temperature : std_logic;
- signal spi_data_out_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
- signal spi_clk_temperature_temperature : std_logic;
+ component LTC1658SPI
+ generic(
+ data_length : integer;
+ fpga_clock_speed : integer;
+ spi_clock_speed : integer
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ start_write : in std_logic;
+ spi_data_in : in std_logic_vector(data_length - 1 downto 0);
+ spi_data_from_chip : in std_logic;
+ spi_data_to_chip : out std_logic;
+ spi_data_out : out std_logic_vector(data_length - 1 downto 0);
+ spi_clk : out std_logic;
+ spi_ld : out std_logic
+ );
+ end component LTC1658SPI;
- signal start_write_adc : std_logic := '0';
- signal config_adc : std_logic_vector(15 downto 0);
- signal spi_data_to_chip_adc : std_logic;
- signal spi_data_out_adc : std_logic_vector(31 downto 0);
- signal spi_clk_adc : std_logic;
+ component ADS1018SPI
+ generic(
+ fpga_clock_speed : integer;
+ spi_clock_speed : integer
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ start_write : in std_logic;
+ config_in : in std_logic_vector(15 downto 0);
+ spi_data_from_chip : in std_logic;
+ spi_data_to_chip : out std_logic;
+ spi_data_out : out std_logic_vector(31 downto 0);
+ spi_clk : out std_logic;
+ spi_cs : out std_logic
+ );
+ end component ADS1018SPI;
+
+ component injection_generator
+ port(
+ rst : in std_logic;
+ clk : in std_logic;
+ pulse_length : in std_logic_vector(31 downto 0);
+ pulse_pause : in std_logic_vector(31 downto 0);
+ pulse_number : in std_logic_vector(31 downto 0);
+ pulse_start : in std_logic;
+ pulse_o : out std_logic
+ );
+ end component injection_generator;
+
+ constant c_bits_threshold_dacs : integer := 64; --4*16 bit of the four DACs
+ signal start_write_threshold : std_logic := '0';
+ signal spi_data_in_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
+ signal spi_data_to_chip_threshold : std_logic;
+ signal spi_data_out_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
+ signal spi_clk_threshold : std_logic;
+
+ constant c_bits_temperature_dac : integer := 16;
+ signal start_write_temperature : std_logic := '0';
+ signal spi_data_in_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
+ signal spi_data_to_chip_temperature : std_logic;
+ signal spi_data_out_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
+ signal spi_clk_temperature_temperature : std_logic;
+
+ signal start_write_adc : std_logic := '0';
+ signal config_adc : std_logic_vector(15 downto 0);
+ signal spi_data_to_chip_adc : std_logic;
+ signal spi_data_out_adc : std_logic_vector(31 downto 0);
+ signal spi_clk_adc : std_logic;
+
+ signal pulse_start_i : std_logic := '0';
+ signal pulse_length_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal pulse_pause_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal number_pulses_i : std_logic_vector(31 downto 0) := (others => '0');
+
+ signal SLV_READ_IN_i : std_logic;
+ signal SLV_WRITE_IN_i : std_logic;
+ signal SLV_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal SLV_ADDR_IN_i : std_logic_vector(15 downto 0);
- signal pulse_start_i : std_logic := '0';
- signal pulse_length_i : std_logic_vector(31 downto 0) := (others => '0');
- signal pulse_pause_i : std_logic_vector(31 downto 0) := (others => '0');
- signal number_pulses_i : std_logic_vector(31 downto 0) := (others => '0');
-
begin
-
- spi_din <= spi_data_to_chip_threshold or spi_data_to_chip_temperature or spi_data_to_chip_adc;
- spi_clk <= spi_clk_threshold or spi_clk_temperature_temperature or spi_clk_adc;
-
- threshold_injection_dac : entity work.LTC1658SPI
- generic map(
- data_length => c_bits_threshold_dacs,
- fpga_clock_speed => fpga_clock_speed, --100 MHz
- spi_clock_speed => spi_clock_speed --50 kHz
- )
- port map(
- clk => clk,
- reset => reset,
- start_write => start_write_threshold,
- spi_data_in => spi_data_in_threshold,
- spi_data_from_chip => dac4_dout,
- spi_data_to_chip => spi_data_to_chip_threshold,
- spi_data_out => spi_data_out_threshold,
- spi_clk => spi_clk_threshold,
- spi_ld => spi_ld_thres
- );
-
- temperature_dac : entity work.LTC1658SPI
- generic map(
- data_length => c_bits_temperature_dac,
- fpga_clock_speed => fpga_clock_speed, --100 MHz
- spi_clock_speed => spi_clock_speed --50 kHz
- )
- port map(
- clk => clk,
- reset => reset,
- start_write => start_write_temperature,
- spi_data_in => spi_data_in_temperature,
- spi_data_from_chip => spi_dout_dac,
- spi_data_to_chip => spi_data_to_chip_temperature,
- spi_data_out => spi_data_out_temperature,
- spi_clk => spi_clk_temperature_temperature,
- spi_ld => spi_ld_tmp_dac
- );
-
-
- temperature_adc : component ADS1018SPI
- generic map(
- fpga_clock_speed => fpga_clock_speed,
- spi_clock_speed => spi_clock_speed
- )
- port map(
- clk => clk,
- reset => reset,
- start_write => start_write_adc,
- config_in => config_adc,
- spi_data_from_chip => spi_dout_adc,
- spi_data_to_chip => spi_data_to_chip_adc,
- spi_data_out => spi_data_out_adc,
- spi_clk => spi_clk_adc,
- spi_cs => spi_cs_adc
- );
-
- injection_gen_1 : component injection_generator
- port map(
- rst => reset,
- clk => clk,
- pulse_length => pulse_length_i,
- pulse_pause => pulse_pause_i,
- pulse_number => number_pulses_i,
- pulse_start => pulse_start_i,
- pulse_o => injection_pulse
- );
- -----------------------------------------------------------------------------
- --TRB Slave Bus
- --0x0090: threshold high and low dacs, 31:16 threshold high, 15:0 threshold low
- --0x0091: threshold pix dac and injection dac, 31:16 pix dac, 15:0 injection dac
- --0x0092: readback threshold high and low dacs, 31:16 threshold high, 15:0 threshold low
- --0x0093: readback threshold pix dac and injection dac, 31:16 pix dac, 15:0 injection dac
- --0x0094: temperature dac
- --0x0095: readback temperature dac
- --0x0096: start write threshold and injection dacs bit
- --0x0097: write config adc
- --0x0098: read adc data
- --0x0099: injection length
- --0x009a: injection pause
- --0x009b: start injection pulse
- --0x009c: number of injection pulses
- -----------------------------------------------------------------------------
- SLV_BUS_HANDLER : process(clk)
- begin -- process SLV_BUS_HANDLER
- if rising_edge(clk) then
- SLV_DATA_OUT <= (others => '0');
- SLV_ACK_OUT <= '0';
- SLV_UNKNOWN_ADDR_OUT <= '0';
- SLV_NO_MORE_DATA_OUT <= '0';
- start_write_threshold <= '0';
- start_write_temperature <= '0';
- start_write_adc <= '0';
- pulse_start_i <= '0';
- if SLV_READ_IN = '1' then
- case SLV_ADDR_IN is
- when x"0090" =>
- SLV_DATA_OUT <= spi_data_in_threshold(63 downto 32);
- SLV_ACK_OUT <= '1';
- when x"0091" =>
- SLV_DATA_OUT <= spi_data_in_threshold(31 downto 0);
- SLV_ACK_OUT <= '1';
- when x"0092" =>
- SLV_DATA_OUT <= spi_data_out_threshold(63 downto 32);
- SLV_ACK_OUT <= '1';
- when x"0093" =>
- SLV_DATA_OUT <= spi_data_out_threshold(31 downto 0);
- SLV_ACK_OUT <= '1';
- when x"0094" =>
- SLV_DATA_OUT(15 downto 0) <= spi_data_in_temperature;
- SLV_ACK_OUT <= '1';
- when x"0095" =>
- SLV_DATA_OUT(15 downto 0) <= spi_data_out_temperature;
- SLV_ACK_OUT <= '1';
- when x"0097" =>
- SLV_DATA_OUT(15 downto 0) <= config_adc;
- SLV_ACK_OUT <= '1';
- when x"0098" =>
- SLV_DATA_OUT <= spi_data_out_adc;
- SLV_ACK_OUT <= '1';
- when x"0099" =>
- SLV_DATA_OUT(31 downto 0) <= pulse_length_i;
- SLV_ACK_OUT <= '1';
- when x"009a" =>
- SLV_DATA_OUT(31 downto 0) <= pulse_pause_i;
- SLV_ACK_OUT <= '1';
- when x"009c" =>
- SLV_DATA_OUT(31 downto 0) <= number_pulses_i;
- SLV_ACK_OUT <= '1';
- when others =>
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end case;
+ spi_din <= spi_data_to_chip_threshold or spi_data_to_chip_temperature or spi_data_to_chip_adc;
+ spi_clk <= spi_clk_threshold or spi_clk_temperature_temperature or spi_clk_adc;
+
+ threshold_injection_dac : entity work.LTC1658SPI
+ generic map(
+ data_length => c_bits_threshold_dacs,
+ fpga_clock_speed => fpga_clock_speed, --100 MHz
+ spi_clock_speed => spi_clock_speed --50 kHz
+ )
+ port map(
+ clk => clk,
+ reset => reset,
+ start_write => start_write_threshold,
+ spi_data_in => spi_data_in_threshold,
+ spi_data_from_chip => dac4_dout,
+ spi_data_to_chip => spi_data_to_chip_threshold,
+ spi_data_out => spi_data_out_threshold,
+ spi_clk => spi_clk_threshold,
+ spi_ld => spi_ld_thres
+ );
+
+ temperature_dac : entity work.LTC1658SPI
+ generic map(
+ data_length => c_bits_temperature_dac,
+ fpga_clock_speed => fpga_clock_speed, --100 MHz
+ spi_clock_speed => spi_clock_speed --50 kHz
+ )
+ port map(
+ clk => clk,
+ reset => reset,
+ start_write => start_write_temperature,
+ spi_data_in => spi_data_in_temperature,
+ spi_data_from_chip => spi_dout_dac,
+ spi_data_to_chip => spi_data_to_chip_temperature,
+ spi_data_out => spi_data_out_temperature,
+ spi_clk => spi_clk_temperature_temperature,
+ spi_ld => spi_ld_tmp_dac
+ );
+
+
+ temperature_adc : component ADS1018SPI
+ generic map(
+ fpga_clock_speed => fpga_clock_speed,
+ spi_clock_speed => spi_clock_speed
+ )
+ port map(
+ clk => clk,
+ reset => reset,
+ start_write => start_write_adc,
+ config_in => config_adc,
+ spi_data_from_chip => spi_dout_adc,
+ spi_data_to_chip => spi_data_to_chip_adc,
+ spi_data_out => spi_data_out_adc,
+ spi_clk => spi_clk_adc,
+ spi_cs => spi_cs_adc
+ );
+
+ injection_gen_1 : component injection_generator
+ port map(
+ rst => reset,
+ clk => clk,
+ pulse_length => pulse_length_i,
+ pulse_pause => pulse_pause_i,
+ pulse_number => number_pulses_i,
+ pulse_start => pulse_start_i,
+ pulse_o => injection_pulse
+ );
+ -----------------------------------------------------------------------------
+ --TRB Slave Bus
+ --0x0090: threshold high and low dacs, 31:16 threshold high, 15:0 threshold low
+ --0x0091: threshold pix dac and injection dac, 31:16 pix dac, 15:0 injection dac
+ --0x0092: readback threshold high and low dacs, 31:16 threshold high, 15:0 threshold low
+ --0x0093: readback threshold pix dac and injection dac, 31:16 pix dac, 15:0 injection dac
+ --0x0094: temperature dac
+ --0x0095: readback temperature dac
+ --0x0096: start write threshold and injection dacs bit
+ --0x0097: write config adc
+ --0x0098: read adc data
+ --0x0099: injection length
+ --0x009a: injection pause
+ --0x009b: start injection pulse
+ --0x009c: number of injection pulses
+ -----------------------------------------------------------------------------
+ SLV_BUS_HANDLER : process(clk)
+ begin -- process SLV_BUS_HANDLER
+ if rising_edge(clk) then
+ SLV_DATA_OUT <= (others => '0');
+ SLV_ACK_OUT <= '0';
+ SLV_UNKNOWN_ADDR_OUT <= '0';
+ SLV_NO_MORE_DATA_OUT <= '0';
+ start_write_threshold <= '0';
+ start_write_temperature <= '0';
+ start_write_adc <= '0';
+ pulse_start_i <= '0';
+
+ -- slv pipeline
+ SLV_ADDR_IN_i <= SLV_ADDR_IN;
+ SLV_DATA_IN_i <= SLV_DATA_IN;
+ SLV_READ_IN_i <= SLV_READ_IN;
+ SLV_WRITE_IN_i <= SLV_WRITE_IN;
+
+ if SLV_READ_IN_i = '1' then
+ case SLV_ADDR_IN_i is
+ when x"0090" =>
+ SLV_DATA_OUT <= spi_data_in_threshold(63 downto 32);
+ SLV_ACK_OUT <= '1';
+ when x"0091" =>
+ SLV_DATA_OUT <= spi_data_in_threshold(31 downto 0);
+ SLV_ACK_OUT <= '1';
+ when x"0092" =>
+ SLV_DATA_OUT <= spi_data_out_threshold(63 downto 32);
+ SLV_ACK_OUT <= '1';
+ when x"0093" =>
+ SLV_DATA_OUT <= spi_data_out_threshold(31 downto 0);
+ SLV_ACK_OUT <= '1';
+ when x"0094" =>
+ SLV_DATA_OUT(15 downto 0) <= spi_data_in_temperature;
+ SLV_ACK_OUT <= '1';
+ when x"0095" =>
+ SLV_DATA_OUT(15 downto 0) <= spi_data_out_temperature;
+ SLV_ACK_OUT <= '1';
+ when x"0097" =>
+ SLV_DATA_OUT(15 downto 0) <= config_adc;
+ SLV_ACK_OUT <= '1';
+ when x"0098" =>
+ SLV_DATA_OUT <= spi_data_out_adc;
+ SLV_ACK_OUT <= '1';
+ when x"0099" =>
+ SLV_DATA_OUT(31 downto 0) <= pulse_length_i;
+ SLV_ACK_OUT <= '1';
+ when x"009a" =>
+ SLV_DATA_OUT(31 downto 0) <= pulse_pause_i;
+ SLV_ACK_OUT <= '1';
+ when x"009c" =>
+ SLV_DATA_OUT(31 downto 0) <= number_pulses_i;
+ SLV_ACK_OUT <= '1';
+ when others =>
+ SLV_UNKNOWN_ADDR_OUT <= '1';
+ end case;
- elsif SLV_WRITE_IN = '1' then
- case SLV_ADDR_IN is
- when x"0090" =>
- spi_data_in_threshold(63 downto 32) <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"0091" =>
- spi_data_in_threshold(31 downto 0) <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"0094" =>
- spi_data_in_temperature <= SLV_DATA_IN(15 downto 0);
- start_write_temperature <= '1';
- SLV_ACK_OUT <= '1';
- when x"0096" =>
- start_write_threshold <= SLV_DATA_IN(0);
- SLV_ACK_OUT <= '1';
- when x"0097" =>
- config_adc <= SLV_DATA_IN(15 downto 0);
- start_write_adc <= '1';
- SLV_ACK_OUT <= '1';
- when x"0099" =>
- pulse_length_i <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"009a" =>
- pulse_pause_i <= SLV_DATA_IN;
- SLV_ACK_OUT <= '1';
- when x"009b" =>
- pulse_start_i <= '1';
- SLV_ACK_OUT <= '1';
- when x"009c" =>
- number_pulses_i <= SLV_DATA_IN(31 downto 0);
- SLV_ACK_OUT <= '1';
- when others =>
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end case;
+ elsif SLV_WRITE_IN_i = '1' then
+ case SLV_ADDR_IN_i is
+ when x"0090" =>
+ spi_data_in_threshold(63 downto 32) <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"0091" =>
+ spi_data_in_threshold(31 downto 0) <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"0094" =>
+ spi_data_in_temperature <= SLV_DATA_IN_i(15 downto 0);
+ start_write_temperature <= '1';
+ SLV_ACK_OUT <= '1';
+ when x"0096" =>
+ start_write_threshold <= SLV_DATA_IN_i(0);
+ SLV_ACK_OUT <= '1';
+ when x"0097" =>
+ config_adc <= SLV_DATA_IN_i(15 downto 0);
+ start_write_adc <= '1';
+ SLV_ACK_OUT <= '1';
+ when x"0099" =>
+ pulse_length_i <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"009a" =>
+ pulse_pause_i <= SLV_DATA_IN_i;
+ SLV_ACK_OUT <= '1';
+ when x"009b" =>
+ pulse_start_i <= '1';
+ SLV_ACK_OUT <= '1';
+ when x"009c" =>
+ number_pulses_i <= SLV_DATA_IN_i(31 downto 0);
+ SLV_ACK_OUT <= '1';
+ when others =>
+ SLV_UNKNOWN_ADDR_OUT <= '1';
+ end case;
- end if;
- end if;
- end process SLV_BUS_HANDLER;
+ end if;
+ end if;
+ end process SLV_BUS_HANDLER;
end architecture RTL;
signal reset_fastcontrol_i : std_logic := '0';
signal configure_state, sendbits_state : std_logic_vector(3 downto 0) := (others => '0');
+ signal SLV_READ_IN_i : std_logic;
+ signal SLV_WRITE_IN_i : std_logic;
+ signal SLV_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal SLV_ADDR_IN_i : std_logic_vector(15 downto 0);
+
begin -- Behavioral
fifo_1 : entity work.STD_FIFO
SLV_UNKNOWN_ADDR_OUT <= '0';
SLV_NO_MORE_DATA_OUT <= '0';
SLV_ACK_OUT <= '0';
+ SLV_ADDR_IN_i <= SLV_ADDR_IN;
+ SLV_DATA_IN_i <= SLV_DATA_IN;
+ SLV_READ_IN_i <= SLV_READ_IN;
+ SLV_WRITE_IN_i <= SLV_WRITE_IN;
DataIn <= (others => '0');
WriteEn <= '0';
reset_readback_i <= '0';
reset_fastcontrol_i <= '0';
slv_data_out <= (others => '0');
- if SLV_WRITE_IN = '1' then
- case SLV_ADDR_IN is
+ if SLV_WRITE_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0080" =>
- DataIn <= SLV_DATA_IN;
+ DataIn <= SLV_DATA_IN_i;
WriteEn <= '1';
SLV_ACK_OUT <= '1';
when x"0083" =>
- mupix_ctrl_ext.sin <= SLV_DATA_IN(0);
- mupix_ctrl_ext.clk1 <= SLV_DATA_IN(1);
- mupix_ctrl_ext.clk2 <= SLV_DATA_IN(2);
- mupix_ctrl_ext.load <= SLV_DATA_IN(3);
- mupix_ctrcl_select <= SLV_DATA_IN(4);
- reset_crc_to_mupix_ext <= SLV_DATA_IN(5);
- reset_crc_from_mupix_ext <= SLV_DATA_IN(6);
- mupix_ctrl_ext.rb <= SLV_DATA_IN(7);
- reset_fastcontrol_i <= SLV_DATA_IN(8);
- bitstosend <= unsigned(SLV_DATA_IN(31 downto 16));
+ mupix_ctrl_ext.sin <= SLV_DATA_IN_i(0);
+ mupix_ctrl_ext.clk1 <= SLV_DATA_IN_i(1);
+ mupix_ctrl_ext.clk2 <= SLV_DATA_IN_i(2);
+ mupix_ctrl_ext.load <= SLV_DATA_IN_i(3);
+ mupix_ctrcl_select <= SLV_DATA_IN_i(4);
+ reset_crc_to_mupix_ext <= SLV_DATA_IN_i(5);
+ reset_crc_from_mupix_ext <= SLV_DATA_IN_i(6);
+ mupix_ctrl_ext.rb <= SLV_DATA_IN_i(7);
+ reset_fastcontrol_i <= SLV_DATA_IN_i(8);
+ bitstosend <= unsigned(SLV_DATA_IN_i(31 downto 16));
SLV_ACK_OUT <= '1';
when x"0084" =>
slv_ack_out <= '1';
when x"0085" =>
slv_ack_out <= '1';
if to_integer(unsigned(slv_data_in)) < c_config_words_max then
- readback_rd_addr <= slv_data_in(c_ram_address_width - 1 downto 0);
+ readback_rd_addr <= SLV_DATA_IN_i(c_ram_address_width - 1 downto 0);
else
readback_rd_addr <= (others => '0');
end if;
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
- elsif SLV_READ_IN = '1' then
- case SLV_ADDR_IN is
+ elsif SLV_READ_IN_i = '1' then
+ case SLV_ADDR_IN_i is
when x"0080" =>
SLV_DATA_OUT <= DataOut;
SLV_ACK_OUT <= '1';
jspc29 / trb3.git / commitdiff