-LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ;
+
REGION "MEDIA_DOWN1" "R102C40D" 13 100;
LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ;
+LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
-MULTICYCLE TO CELL "THE_MEDIA_4_DOWN/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_4_DOWN/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_MEDIA_4_DOWN/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "THE_MEDIA_4_DOWN/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_write_i";
-BLOCK PATH TO CLKNET "THE_MEDIA_4_DOWN/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_read_i";
-MULTICYCLE TO CLKNET "THE_MEDIA_4_DOWN/sci_read_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOWN/sci_read_i" 15 ns;
-MULTICYCLE TO CLKNET "THE_MEDIA_4_DOWN/sci_write_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOWN/sci_write_i" 15 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
+BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
+MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
+MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
-MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-MAXDELAY TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-
-# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
\ No newline at end of file
+MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
+MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
+
+#
+# #GbE Part
+# UGROUP "tsmac"
+# BLKNAME GBE/imp_gen.MAC
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS
+# BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER
+# BLKNAME GBE/FRAME_TRANSMITTER;
+# UGROUP "controllers"
+# BLKNAME GBE/main_gen.MAIN_CONTROL
+# BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER
+# BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER;
+# UGROUP "gbe_rx_tx"
+# BLKNAME GBE/FRAME_CONSTRUCTOR
+# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
+# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR
+# BLKNAME GBE/setup_imp_gen.SETUP;
+#
+# #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE;
+# #REGION "MED0" "R81C30D" 34 40 DEVSIZE;
+# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
+# #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE;
+# #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
+# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;
+#
+# UGROUP "sd_tx_to_pcs"
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
+# UGROUP "sd_rx_to_pcs"
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7]
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
+# UGROUP "pcs_tx_to_mac"
+# BLKNAME GBE/pcs_tx_en_q
+# BLKNAME GBE/pcs_tx_en_qq
+# BLKNAME GBE/pcs_tx_er_q
+# BLKNAME GBE/pcs_tx_er_qq
+# BLKNAME GBE/pcs_txd_q[0]
+# BLKNAME GBE/pcs_txd_q[1]
+# BLKNAME GBE/pcs_txd_q[2]
+# BLKNAME GBE/pcs_txd_q[3]
+# BLKNAME GBE/pcs_txd_q[4]
+# BLKNAME GBE/pcs_txd_q[5]
+# BLKNAME GBE/pcs_txd_q[6]
+# BLKNAME GBE/pcs_txd_q[7]
+# BLKNAME GBE/pcs_txd_qq[0]
+# BLKNAME GBE/pcs_txd_qq[1]
+# BLKNAME GBE/pcs_txd_qq[2]
+# BLKNAME GBE/pcs_txd_qq[3]
+# BLKNAME GBE/pcs_txd_qq[4]
+# BLKNAME GBE/pcs_txd_qq[5]
+# BLKNAME GBE/pcs_txd_qq[6]
+# BLKNAME GBE/pcs_txd_qq[7];
+# UGROUP "pcs_rx_to_mac"
+# BLKNAME GBE/pcs_rx_en_q
+# BLKNAME GBE/pcs_rx_en_qq
+# BLKNAME GBE/pcs_rx_er_q
+# BLKNAME GBE/pcs_rx_er_qq
+# BLKNAME GBE/pcs_rxd_q[0]
+# BLKNAME GBE/pcs_rxd_q[1]
+# BLKNAME GBE/pcs_rxd_q[2]
+# BLKNAME GBE/pcs_rxd_q[3]
+# BLKNAME GBE/pcs_rxd_q[4]
+# BLKNAME GBE/pcs_rxd_q[5]
+# BLKNAME GBE/pcs_rxd_q[6]
+# BLKNAME GBE/pcs_rxd_q[7]
+# BLKNAME GBE/pcs_rxd_qq[0]
+# BLKNAME GBE/pcs_rxd_qq[1]
+# BLKNAME GBE/pcs_rxd_qq[2]
+# BLKNAME GBE/pcs_rxd_qq[3]
+# BLKNAME GBE/pcs_rxd_qq[4]
+# BLKNAME GBE/pcs_rxd_qq[5]
+# BLKNAME GBE/pcs_rxd_qq[6]
+# BLKNAME GBE/pcs_rxd_qq[7];
+#
+# UGROUP "GBE_SERDES_group" BBOX 10 67
+# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES;
+# LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ;
+#
+# MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ;
+# MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ;
+#
+# DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
+# "GBE/pcs_rx_er_q"
+# "GBE/pcs_rxd_q*";
+# INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;
+#
+# PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ;
+# PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ;
+# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ;
\ No newline at end of file
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
#Basic Infrastructure
add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
#SlowControl files
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
#GbE
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd"
-#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v"
-#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v"
-#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v"
-#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v"
-#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd"
-
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
+ TRIG_LEFT : in std_logic;
--Additional IO
HDR_IO : inout std_logic_vector(10 downto 1);
-- RJ_IO : inout std_logic_vector( 3 downto 0);
-- SPARE_IN : in std_logic_vector( 1 downto 0);
- BACK_GPIO : inout std_logic_vector(15 downto 0);
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_3V3 : inout std_logic_vector( 3 downto 0);
+
+ --Lines to slaves
+ BACK_MASTER_READY : out std_logic_vector(8 downto 0);
+ BACK_SLAVE_READY : in std_logic_vector(8 downto 0);
+ BACK_SPARE1 : in std_logic_vector(8 downto 0);
+ BACK_SPARE2 : in std_logic_vector(8 downto 0);
--LED
LED_GREEN : out std_logic;
SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
--- LED_HUB_LINKOK : out std_logic_vector(6 downto 1);
--- LED_HUB_RX : out std_logic_vector(6 downto 1);
--- LED_HUB_TX : out std_logic_vector(6 downto 1);
--- HUB_MOD0 : in std_logic_vector(6 downto 1);
--- HUB_MOD1 : inout std_logic_vector(6 downto 1);
--- HUB_MOD2 : inout std_logic_vector(6 downto 1);
--- HUB_TXDIS : out std_logic_vector(6 downto 1);
--- HUB_LOS : in std_logic_vector(6 downto 1);
-
--Serdes switch
PCSSW_ENSMB : out std_logic;
PCSSW_EQ : out std_logic_vector( 3 downto 0);
signal debug_clock_reset : std_logic_vector(31 downto 0);
--Media Interface
- signal med2int : med2int_array_t(0 to 4);
- signal int2med : int2med_array_t(0 to 4);
+ signal med2int : med2int_array_t(0 to INTERFACE_NUM-1);
+ signal int2med : int2med_array_t(0 to INTERFACE_NUM-1);
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal ctrlbus_rx, bussci_rx, bussci2_rx, bustools_rx, bustc_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bussci_tx, bussci2_tx, bustools_tx, bustc_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx,
+ bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx,
+ bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
+
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
signal sed_error_i : std_logic;
+ signal bus_master_active : std_logic;
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
signal uart_tx, uart_rx : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
- attribute syn_keep of bussci_rx : signal is true;
- attribute syn_preserve of bussci_rx : signal is true;
+ attribute syn_keep of bussci1_rx : signal is true;
+ attribute syn_preserve of bussci1_rx : signal is true;
attribute syn_keep of bustools_rx : signal is true;
attribute syn_preserve of bustools_rx : signal is true;
attribute syn_keep of bustc_rx : signal is true;
port map(
INT_CLK_IN => CLK_CORE_PCLK,
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(4).clk_full,
- NET_CLK_HALF_IN => med2int(4).clk_half,
- RESET_FROM_NET => med2int(4).stat_op(13),
+ NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full,
+ NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half,
+ RESET_FROM_NET => med2int(INTERFACE_NUM-1).stat_op(13),
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
---------------------------------------------------------------------------
-- TrbNet Uplink
---------------------------------------------------------------------------
-THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB
generic map(
- SERDES_NUM => 3,
- IS_SYNC_SLAVE => c_YES
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
+ IS_USED => (c_YES, c_YES, c_YES ,c_YES)
)
port map(
- CLK => clk_full_osc,
+ CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(4),
- MEDIA_INT2MED => int2med(4),
+ MEDIA_MED2INT(0) => med2int(7),
+ MEDIA_MED2INT(1) => med2int(6),
+ MEDIA_MED2INT(2) => med2int(5),
+ MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
+ MEDIA_INT2MED(0) => int2med(7),
+ MEDIA_INT2MED(1) => int2med(6),
+ MEDIA_INT2MED(2) => int2med(5),
+ MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
--Sync operation
RX_DLM => open,
TX_DLM_WORD => open,
--SFP Connection
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN(0) => backplane_rx_present(7),
+ SD_LOS_IN(0) => backplane_rx_present(7),
+ SD_TXDIS_OUT(0) => backplane_tx_present(7),
+ SD_PRSNT_N_IN(1) => backplane_rx_present(6),
+ SD_LOS_IN(1) => backplane_rx_present(6),
+ SD_TXDIS_OUT(1) => backplane_tx_present(6),
+ SD_PRSNT_N_IN(2) => backplane_rx_present(5),
+ SD_LOS_IN(2) => backplane_rx_present(5),
+ SD_TXDIS_OUT(2) => backplane_tx_present(5),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--Control Interface
- BUS_RX => bussci_rx,
- BUS_TX => bussci_tx,
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
-- Status and control port
STAT_DEBUG => open,
CTRL_DEBUG => open
);
-SFP_TX_DIS(0) <= '1';
---------------------------------------------------------------------------
-- TrbNet Downlink
---------------------------------------------------------------------------
-THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
+THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4 --PCSA
generic map(
IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
)
port map(
- CLK => clk_full_osc,
+ CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
SD_TXDIS_OUT => backplane_tx_present(3 downto 0),
--Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
+ BUS_RX => bussci1_rx,
+ BUS_TX => bussci1_tx,
-- Status and control port
STAT_DEBUG => med_stat_debug(63 downto 0),
CTRL_DEBUG => open
);
-gen_ready_signals : for i in 0 to 3 generate
- backplane_rx_present(i) <= BACK_GPIO(i*4);
- BACK_GPIO(i*4+1) <= backplane_tx_present(i);
+THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
+ )
+ port map(
+ CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(8),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(8),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => backplane_rx_present(4),
+ SD_PRSNT_N_IN(1) => backplane_rx_present(8),
+ SD_PRSNT_N_IN(2) => '1',
+ SD_PRSNT_N_IN(3) => '1',
+
+ SD_LOS_IN(0) => backplane_rx_present(4),
+ SD_LOS_IN(1) => backplane_rx_present(8),
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+
+ SD_TXDIS_OUT(0) => backplane_tx_present(4),
+ SD_TXDIS_OUT(1) => backplane_tx_present(8),
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
+
+ --Control Interface
+ BUS_RX => bussci3_rx,
+ BUS_TX => bussci3_tx,
+
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+gen_ready_signals : for i in 0 to 8 generate
+ backplane_rx_present(i) <= BACK_SLAVE_READY(i);
+ BACK_MASTER_READY(i) <= backplane_tx_present(i);
end generate;
---------------------------------------------------------------------------
-- GbE
---------------------------------------------------------------------------
+gen_noGBE : if INCLUDE_GBE = 0 generate
+ gsc_reply_read <= '1';
+ gsc_init_dataready <= '0';
+ SFP_TX_DIS(0) <= '1';
+ busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write;
+ busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write;
+end generate;
+
+gen_GBE : if INCLUDE_GBE = 1 generate
+ GBE : entity work.gbe_wrapper
+ generic map(
+ DO_SIMULATION => 0,
+ INCLUDE_DEBUG => 0,
+ USE_INTERNAL_TRBNET_DUMMY => 0,
+ USE_EXTERNAL_TRBNET_DUMMY => 0,
+ RX_PATH_ENABLE => 1,
+ FIXED_SIZE_MODE => 1,
+ INCREMENTAL_MODE => 1,
+ FIXED_SIZE => 100,
+ FIXED_DELAY_MODE => 1,
+ UP_DOWN_MODE => 0,
+ UP_DOWN_LIMIT => 100,
+ FIXED_DELAY => 100,
+
+ NUMBER_OF_GBE_LINKS => 4,
+ LINKS_ACTIVE => "0001",
+
+ LINK_HAS_READOUT => "0001",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001",
+
+ NUMBER_OF_OUTPUT_LINKS => 1
+ )
+
+ port map(
+ CLK_SYS_IN => clk_sys,
+ CLK_125_IN => CLK_SUPPL_PCLK,
+ RESET => reset_i,
+ GSR_N => GSR_N,
+ TRIGGER_IN => TRIG_LEFT,
+
+ SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_LOS_IN(0) => SFP_LOS(0),
+ SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+
+ CTS_NUMBER_IN => cts_number,
+ CTS_CODE_IN => cts_code,
+ CTS_INFORMATION_IN => cts_information,
+ CTS_READOUT_TYPE_IN => cts_readout_type,
+ CTS_START_READOUT_IN => cts_start_readout,
+ CTS_DATA_OUT => cts_data,
+ CTS_DATAREADY_OUT => cts_dataready,
+ CTS_READOUT_FINISHED_OUT => cts_readout_finished,
+ CTS_READ_IN => cts_read,
+ CTS_LENGTH_OUT => cts_length,
+ CTS_ERROR_PATTERN_OUT => cts_status_bits,
+
+ FEE_DATA_IN => fee_data,
+ FEE_DATAREADY_IN => fee_dataready,
+ FEE_READ_OUT => fee_read,
+ FEE_STATUS_BITS_IN => fee_status_bits,
+ FEE_BUSY_IN => fee_busy,
+
+ MC_UNIQUE_ID_IN => mc_unique_id,
+
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+
+ MAKE_RESET_OUT => reset_via_gbe,
+
+ DEBUG_OUT => open
+ );
+end generate;
---------------------------------------------------------------------------
-- Hub
GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
GSC_REPLY_DATA_OUT => gsc_reply_data,
GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => '1', --gsc_reply_read,
+ GSC_REPLY_READ_IN => gsc_reply_read,
GSC_BUSY_OUT => gsc_busy,
--status and control ports
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"b200", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 9, others => 0),
+ PORT_NUMBER => 7,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
CLK => clk_sys,
RESET => reset_i,
- REGIO_RX => ctrlbus_rx,
+ REGIO_RX => handlerbus_rx,
REGIO_TX => ctrlbus_tx,
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bussci_rx, --SCI Serdes
- BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(1) => bustc_rx, --Clock switch
+ BUS_RX(2) => bussci1_rx, --SCI Serdes
BUS_RX(3) => bussci2_rx,
+ BUS_RX(4) => bussci3_rx,
+ BUS_RX(5) => busgbeip_rx,
+ BUS_RX(6) => busgbereg_rx,
BUS_TX(0) => bustools_tx,
- BUS_TX(1) => bussci_tx,
- BUS_TX(2) => bustc_tx,
+ BUS_TX(1) => bustc_tx,
+ BUS_TX(2) => bussci1_tx,
BUS_TX(3) => bussci2_tx,
+ BUS_TX(4) => bussci3_tx,
+ BUS_TX(5) => busgbeip_tx,
+ BUS_TX(6) => busgbereg_tx,
STAT_DEBUG => open
);
+ handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
+
---------------------------------------------------------------------------
-- Control Tools
---------------------------------------------------------------------------
--Slowcontrol
BUS_RX => bustools_rx,
BUS_TX => bustools_tx,
-
+ --Control master for default settings
+ BUS_MASTER_IN => ctrlbus_tx,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
DEBUG_OUT => open
);
-
+
---------------------------------------------------------------------------
-- Switches
LED_RED <= not sed_error_i;
LED_YELLOW <= debug_clock_reset(2);
LED_WHITE <= led;
- LED_SFP_GREEN <= not med2int(4).stat_op(9) & '1'; --SFP Link Status
- LED_SFP_RED <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)) & '1'; --SFP RX/TX
+ LED_SFP_GREEN <= not med2int(INTERFACE_NUM-1).stat_op(9) & '1'; --SFP Link Status
+ LED_SFP_RED <= not (med2int(INTERFACE_NUM-1).stat_op(10) or med2int(INTERFACE_NUM-1).stat_op(11)) & '1'; --SFP RX/TX
---------------------------------------------------------------------------
FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
-REGION "REGION_SPI" "R19C150D" 20 20 DEVSIZE;
-LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+# REGION "REGION_SPI" "R19C150D" 20 20 DEVSIZE;
+# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ;
LOCATE COMP "BACK_SPARE2_7" SITE "L7"; #DQUL1_3_N\r
LOCATE COMP "BACK_SPARE2_8" SITE "K1"; #DQUL1_1_N\r
\r
-LOCATE COMP "BACK_SLAVE_READY_0" SITE "D26";\r
-LOCATE COMP "BACK_SLAVE_READY_1" SITE "E27";\r
-LOCATE COMP "BACK_SLAVE_READY_2" SITE "A27";\r
-LOCATE COMP "BACK_SLAVE_READY_3" SITE "H25";\r
+LOCATE COMP "BACK_SLAVE_READY_0" SITE "C26";\r
+LOCATE COMP "BACK_SLAVE_READY_1" SITE "D27";\r
+LOCATE COMP "BACK_SLAVE_READY_2" SITE "A26";\r
+LOCATE COMP "BACK_SLAVE_READY_3" SITE "H26";\r
LOCATE COMP "BACK_SLAVE_READY_4" SITE "N32"; #was "DQUR1_2_P" 114\r
LOCATE COMP "BACK_SLAVE_READY_5" SITE "N26"; #was "DQUR1_1_P" 110\r
LOCATE COMP "BACK_SLAVE_READY_6" SITE "K6"; #was "DQUL0_2_P" 82\r
LOCATE COMP "BACK_SLAVE_READY_7" SITE "M4"; #was "DQUL0_1_P" 78\r
LOCATE COMP "BACK_SLAVE_READY_8" SITE "J3"; #was "DQUL2_4_P" 70\r
\r
-LOCATE COMP "BACK_MASTER_READY_0" SITE "C26";\r
-LOCATE COMP "BACK_MASTER_READY_1" SITE "D27";\r
-LOCATE COMP "BACK_MASTER_READY_2" SITE "A26";\r
-LOCATE COMP "BACK_MASTER_READY_3" SITE "H26";\r
+LOCATE COMP "BACK_MASTER_READY_0" SITE "D26";\r
+LOCATE COMP "BACK_MASTER_READY_1" SITE "E27";\r
+LOCATE COMP "BACK_MASTER_READY_2" SITE "A27";\r
+LOCATE COMP "BACK_MASTER_READY_3" SITE "H25";\r
LOCATE COMP "BACK_MASTER_READY_4" SITE "N31"; #DQUR1_2_N\r
LOCATE COMP "BACK_MASTER_READY_5" SITE "P26"; #DQUR1_1_N\r
LOCATE COMP "BACK_MASTER_READY_6" SITE "K5"; #DQUL0_2_N\r
jspc29 / trb3sc.git / commitdiff