*** empty log message ***

diff --git a/cts.tex b/cts.tex
index f5da192ae3c54efad4b2831592d5179b0545808c..5fa0410f109f5c6410618feb58810eec0eb28431 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -8,8 +8,8 @@
 
 Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \\
 Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \\
-
-Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicular stripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
+<<<<<<< cts.tex
+Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. For the first two the source is selected by 0xA0C2 register next 8 is START next 8 is also START but perpendicular stripes (the source of the start histograms is selected in 0xA0DA register). Next 8 is Veto.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{CTS Control Registers}
@@ -36,6 +36,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
     \end{description}
   \item [0xA0C1] LVL1/LVL2 trigger settings:
     \begin{description}
+     \item[Bit 3 -- 0] Set the delay for the sampling of the sector wise multiplicities. The sampling time is on $30\,ns + value * 5ns$. 
      \item[Bit 16 -- 12] Delay of MDCB (MDC 3/4) trigger = value * 20 ns 
      \item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns 
      \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns