signal tx_pcs_rst_i : std_logic;
signal debug_i : std_logic_vector(31 downto 0);
signal rx_dlm_i : std_logic;
+-- signal rx_dlm_iq : std_logic; -- ADDED
signal word_sync_i : std_logic;
+-- signal word_sync_iq : std_logic; -- ADDED
signal master_clk_i : std_logic;
-
+-- signal test_clk : std_logic; -- ADDED
+-- signal stat_debug_i : std_logic_vector(63 downto 0);
+
signal tx_reset_state : std_logic_vector(3 downto 0);
signal master_reset_i : std_logic;
DEBUG_OUT => debug_i
);
+-- test_clk <= stat_debug_i(7);
+--
+-- THE_TRANSFER_PROC: process(test_clk)
+-- begin
+-- if( rising_edge(test_clk) ) then
+-- word_sync_iq <= word_sync_i;
+-- rx_dlm_iq <= rx_dlm_i;
+-- end if;
+-- end process THE_TRANSFER_PROC;
+
THE_MAIN_TX_RST: main_tx_reset_RS
generic map(
SIM_MODE => 0
SFP_TX_DIS(0) <= '0' when USE_GBE = 1 else '1';
--HDR_IO(10 downto 1) <= (others => '0');
- HDR_IO(10) <= word_sync_i;
- HDR_IO(9) <= master_reset_i;
- HDR_IO(8) <= tx_clk_avail_i;
- HDR_IO(7) <= sync_tx_quad_i;
- HDR_IO(6) <= tx_pcs_rst_i;
+ HDR_IO(10) <= debug_i(17);
+ HDR_IO(9) <= debug_i(16);
+ HDR_IO(8) <= '0';
+ HDR_IO(7) <= '0';
+ HDR_IO(6) <= '0';
HDR_IO(5) <= '0';
HDR_IO(4) <= '0';
HDR_IO(3) <= '0';