mentioning additional modules like Uart, Spi, Lcd, Debug Interface

diff --git a/trb3/AdditionalModules.tex b/trb3/AdditionalModules.tex
new file mode 100644 (file)
index 0000000..d35cf43
--- /dev/null
+++ b/trb3/AdditionalModules.tex
@@ -0,0 +1,11 @@
+\subsection{DAC Programming}
+  \input{DacProgramming}
+\subsection{Forward inputs for trigger}
+  \input{TriggerModule}      
+\subsection{Interfaces}
+  \begin{description}
+    \item[SPI] The module used for DAC programming is a generic SPI interface that can be used for any purpose. (resources: 300 slices in FPGA)
+    \item[UART] A generic UART master implemented in FPGA  (resources: 300 slices in FPGA)
+    \item[LCD] Any numeric values can be shown on a graphic LCD  (resources: 800 slices in FPGA)
+    \item[Debug] For debugging, a UART can be used to access the internal data bus  (resources: 300 slices in FPGA)
+  \end{description}
\ No newline at end of file

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index 69bb6497316877c2b000025c49537a66daf33b60..4b9163c48005f8e4bd684abeac296228ba3c8fe4 100644 (file)
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -1,8 +1,8 @@
 \label{triggermodule}
 The trigger module can be used to forward any input of a peripheral FPGA via the central FPGA to 
-the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS.
+the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS.  (resources: 400 slices in FPGA for 32 inputs, 2 outputs)
 
-The VHDL code is available in \files{base/code/input\_to\_trigger\_logic.vhd}
+The VHDL code is available in \files{trb3/base/code/input\_to\_trigger\_logic\_record.vhd}
 
 \paragraph*{Setup}
 The trigger module can feature up to 32 input signals and up to 16 independent outputs.
@@ -21,9 +21,7 @@ to one of the RJ-45 sockets on the CTS-AddOn.
 \paragraph*{SlowControl}
 Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has two 
 configuration registers. The first one contains a bit mask to enable individual inputs, the second is unused. 
-In case of four outputs configured, registers 0xcf00, 0xcf02, 0xcf04 and 0xcf06 contain the enable 
-bit mask.
-Additionally, inputs can be inverted (0xcf24) and short signals can be stretched to at least 10 ns length (0xcf22).
+Additionally, inputs can be inverted and short signals can be stretched to at least 10 ns length.
 
 
 \paragraph*{Input Scalers}
@@ -32,25 +30,5 @@ be stored in a Fifo at an adjustable rate. The Fifos for all channels are contro
 logic and store their data synchronously. Filling of the Fifos has to be triggered and stops after
 1024 samples have been acquired.
 To save resources, it is also possible to use only one monitoring Fifo combined 
-with a multiplexer to select one of the inputs as source.
+with a multiplexer to select one of the inputs as source.  (resources: 1300 slices in FPGA for 32 inputs)
 
-\begin{description*}
- \item[cf00, cf02 .. cf1e] Input enable mask. Up to 16 times, according to number of outputs.
- \item[cf20] Status of all input signals
- \item[cf21] Status of all trigger output signals
- \item[cf22] Signal stretcher (at least 10 ns long) for each input
- \item[cf24] Invert of all input signals
- \item[cf80] Input enable for monitoring
- \item[cf81] Input invert for monitoring
- \item[cf82] Set the monitoring rate in units of 10 ns (FPGA clock frequency)
- \item[cf83] Debug: Current value of the timer register
- \item[cf84] Debug: Status register
- \item[cf8e] Status of all input signals
- \item[cf8f] Bit 0: Trigger recording of data. Fifo are cleared, then 1024 samples are acquired\\
-             Bit 1: Reset counters\\
-             Bit 20-16: Input select (if only a single Fifo is used)
- \item[cfa0 .. cfbf] One Fifo for each input. Up to 1024 values of 18 Bit are 
-stored. The uppermost
-bit is the Fifo empty signal (data invalid)
- \item[cfc0 .. cfdf] One counter for each input. The width is 24 Bit.
-\end{description*}

diff --git a/trb3/main.tex b/trb3/main.tex
index 0ddc2f34a2f703d853600918764487d9d08e3a52..f700e31f41b6d831af1e9228da0f9ec42454bc0d 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -209,10 +209,7 @@
       \input{TdcVersion}
   \clearpage
   \section{Additional Modules}
-    \subsection{DAC Programming}
-      \input{DacProgramming}
-    \subsection{Forward inputs for trigger}
-      \input{TriggerModule}      
+    \input{AdditionalModules}
 
   \clearpage
   \section{GbE Data Read-out}