Solved some timing error. But there is one timing error in SPI Master of trb3 ??

diff --git a/mupix/sources/HitbusHistogram.vhd b/mupix/sources/HitbusHistogram.vhd
index 53279635423df963737440e14d6289467054e1d8..38323b19574ffad14739593a5b74c4aca91b8d21 100644 (file)
--- a/mupix/sources/HitbusHistogram.vhd
+++ b/mupix/sources/HitbusHistogram.vhd
@@ -45,6 +45,7 @@ architecture Behavioral of HitbusHistogram is
 
 
   signal hitbus_i : std_logic_vector(1 downto 0);
+  signal hitbus_buffer : std_logic;
 
   --ToT Histogram
   type   hithisto_fsm_type is (idle, hitbus_high);
@@ -110,15 +111,21 @@ begin
       DataValid => open,
       BinHeight => latency_BinValue);
 
-
+  -- purpose: hitbus synchronize and  edge detect
+  hitbus_edge_proc: process (clk) is
+  begin  -- process hitbus_edge_proc
+    if rising_edge(clk) then
+      hitbus_buffer <= hitbus;
+      hitbus_i <= hitbus_i(0) & hitbus_buffer;
+    end if;
+  end process hitbus_edge_proc;
+  
   -----------------------------------------------------------------------------
   --Time over Threshold histogram
   -----------------------------------------------------------------------------
-  
   HitBusHisto : process(clk)
   begin  -- process HitBusHisto
     if rising_edge(clk) then
-      hitbus_i <= hitbus_i(0) & hitbus;
       case hithisto_fsm is
         when idle =>
           --hitbus_counter  <= (others => '0');

diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd
index 0ea59c7e419c4d43d4796bbbcda0528bb89d08da..bcc238b77b5b6d9c3ac42c594f520b0433f7de95 100644 (file)
--- a/mupix/sources/MuPix3_interface.vhd
+++ b/mupix/sources/MuPix3_interface.vhd
@@ -324,6 +324,7 @@ begin
           memwren      <= '0';
           ro_busy_int  <= '0';
           endofevent   <= '0';
+          delcounter   <= (others => '0');
           hitcounter   <= (others => '0');
           eventcounter <= eventcounter;
           if(reseteventcount = '1') then

diff --git a/mupix/sources/TimeWalk.vhd b/mupix/sources/TimeWalk.vhd
index 0a3a8665f60cff83670e35707e9203911f51a7a9..a8256cd280e5ab600f02928b654e7cd3a2fd6fc5 100644 (file)
--- a/mupix/sources/TimeWalk.vhd
+++ b/mupix/sources/TimeWalk.vhd
@@ -24,17 +24,28 @@ architecture TimeWalk_Arch of TimeWalk is
   signal hitbuscounter             : unsigned(15 downto 0)        := (others => '0');
   signal hitbus_edge               : std_logic_vector(1 downto 0) := (others => '0');
   signal szintillator_trigger_edge : std_logic_vector(1 downto 0) := (others => '0');
+  signal hitbusBuffer : std_logic := '0';
+  signal szintilatorTriggerBuffer : std_logic := '0';
   type TimeWalk_fsm_type is (idle, waitforhitbus, measurehitbus, measurement_done);
   signal timewalk_fsm              : TimeWalk_fsm_type            := idle;
 
   
 begin  -- architecture TimeWalk_Arch
 
+  -- purpose: synchronize signals and edge detection
+  signal_synchro: process (clk) is
+  begin  -- process clk
+    if rising_edge(clk) then
+      hitbusBuffer <= hitbus;
+      szintilatorTriggerBuffer <= szintillator_trigger;
+      hitbus_edge               <= hitbus_edge(0) & hitbusBuffer;
+      szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintilatorTriggerBuffer;  
+    end if;
+  end process signal_synchro;
+
   TimeWalk_Measurement : process (clk, reset) is
   begin  -- process TimeWalk_Measurement
     if rising_edge(clk) then
-      hitbus_edge               <= hitbus_edge(0) & hitbus;
-      szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger;
       measurementFinished  <= '0';
       measurementData      <= (others => '0');
       case timewalk_fsm is

diff --git a/mupix/sources/TimeWalkWithFiFo.vhd b/mupix/sources/TimeWalkWithFiFo.vhd
index 93c210fc19be7c1030bd6fd8274a685173d423df..bc196665f6f6da1847e5f5871abef6ce617fca01 100644 (file)
--- a/mupix/sources/TimeWalkWithFiFo.vhd
+++ b/mupix/sources/TimeWalkWithFiFo.vhd
@@ -38,6 +38,8 @@ architecture TimeWalk_arch of TimeWalkWithFiFo is
   signal szintilatorEdgeCounter : unsigned(31 downto 0) := (others => '0');
   signal hitbusRisingEdge : std_logic_vector(1 downto 0) := (others => '0');
   signal szintilatorRisingEdge : std_logic_vector(1 downto 0) := (others => '0');
+  signal hitbus_buffer : std_logic := '0';
+  signal szintilator_trigger_buffer : std_logic := '0';
   
   signal FiFo_Wren         : std_logic                     := '0';
   signal FiFo_Rden         : std_logic                     := '0';
@@ -107,8 +109,10 @@ begin  -- architecture TimeWalk_arch
   edge_counter: process (trb_slv_clock) is
   begin  -- process edge_counter
     if rising_edge(trb_slv_clock) then
-      hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus;
-      szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintillator_trigger;
+      hitbus_buffer <= hitbus;
+      szintilator_trigger_buffer <= szintillator_trigger;
+      hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus_buffer;
+      szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintilator_trigger_buffer;
       if szintilatorRisingEdge = "01" then
         szintilatorEdgeCounter <= szintilatorEdgeCounter + 1;
       end if;

diff --git a/mupix/sources/graycounter.vhd b/mupix/sources/graycounter.vhd
index c1625613591ce3e175bef48534ba8f8f6ae6214e..aaddd0722c66e9990680783a0cfe9380d3678a06 100644 (file)
--- a/mupix/sources/graycounter.vhd
+++ b/mupix/sources/graycounter.vhd
@@ -55,11 +55,11 @@ begin
 
   process(clk, reset)
   begin
-    if(reset = '1') then
-      counter_reg    <= (others => '0');
-      counter_reg(0) <= '1';
-      no_ones_below(0) <= '1';
-    elsif (clk'event and clk = '1') then
+    --if(reset = '1') then
+    --  counter_reg    <= (others => '0');
+    --  counter_reg(0) <= '1';
+    --  no_ones_below(0) <= '1';
+    if (clk'event and clk = '1') then
       if (sync_reset = '1') then
         no_ones_below(0) <= '1';
         counter_reg    <= (others => '0');