first try

diff --git a/nxyter/.cvsignore b/nxyter/.cvsignore
new file mode 100644 (file)
index 0000000..a459553
--- /dev/null
+++ b/nxyter/.cvsignore
@@ -0,0 +1,12 @@
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+

diff --git a/nxyter/compile_munich.pl b/nxyter/compile_munich.pl
index d1dafbc2982623c69c3cc17f07ca4d9a0f3da4b3..9bcb4d21049a0c9e361341eba83275324c44ff10 100755 (executable)
--- a/nxyter/compile_munich.pl
+++ b/nxyter/compile_munich.pl
@@ -9,8 +9,8 @@ use strict;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/1.4.2.105';
-my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lattice_path                 = '/usr/local/opt/lattice_diamond/diamond';
+my $synplify_path                = '/usr/local/opt/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################

diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd
index b1a2a1b2420fc33ac3f1ccca86c8b136e673c48e..6d239da066bc72d7e28e85d78cdde662b8662529 100644 (file)
--- a/nxyter/source/nxyter.vhd
+++ b/nxyter/source/nxyter.vhd
@@ -19,7 +19,6 @@ entity nXyter_FEE_board is
     -- I2C Ports
     I2C_SDA_INOUT      : inout std_logic;   -- nXyter I2C fdata line
     I2C_SCL_OUT        : out std_logic;     -- nXyter I2C Clock line
-
     I2C_SM_RESET_OUT   : out std_logic;     -- reset nXyter I2C StateMachine 
     I2C_REG_RESET_OUT  : out std_logic;     -- reset I2C registers to default
 
@@ -38,7 +37,7 @@ entity nXyter_FEE_board is
     -- ADC nXyter Pulse Hight Ports
     ADC_FCLK_IN        : in std_logic;
     ADC_DCLK_IN        : in std_logic;
-    ADC_SC_CLK32_IN    : in std_logic;
+    ADC_SC_CLK32_OUT   : out std_logic;
     ADC_A_IN           : in std_logic;
     ADC_B_IN           : in std_logic;
     ADC_NX_IN          : in std_logic;

diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd
index 2a64249d34b008f365316f207033389172fe7e3d..1e884bc64752568adcc4394945abbf5d3746d901 100644 (file)
--- a/nxyter/source/nxyter_components.vhd
+++ b/nxyter/source/nxyter_components.vhd
@@ -12,25 +12,30 @@ component nXyter_FEE_board
   port (
     CLK_IN                 : in    std_logic_vector;
     RESET_IN               : in    std_logic_vector;
+
     I2C_SDA_INOUT          : inout std_logic;
     I2C_SCL_OUT            : out   std_logic;
     I2C_SM_RESET_OUT       : out   std_logic;
     I2C_REG_RESET_OUT      : out   std_logic;
+
     SPI_SCLK_OUT           : out   std_logic;
     SPI_SDIO_INOUT         : in    std_logic;
     SPI_CSB_OUT            : out   std_logic;
+
     NX_CLK128_IN           : in    std_logic;
     NX_IN                  : in    std_logic_vector (7 downto 0);
     NX_RESET_OUT           : out   std_logic;
     NX_CLK256A_OUT         : out   std_logic;
     NX_TESTPULSE_OUT       : out   std_logic;
+
     ADC_FCLK_IN            : in    std_logic;
     ADC_DCLK_IN            : in    std_logic;
-    ADC_SC_CLK32_IN        : in    std_logic;
+    ADC_SC_CLK32_OUT       : out   std_logic;
     ADC_A_IN               : in    std_logic;
     ADC_B_IN               : in    std_logic;
     ADC_NX_IN              : in    std_logic;
     ADC_D_IN               : in    std_logic;
+
     REGIO_ADDR_IN          : in    std_logic_vector(15 downto 0);
     REGIO_DATA_IN          : in    std_logic_vector(31 downto 0);
     REGIO_DATA_OUT         : out   std_logic_vector(31 downto 0);
@@ -45,8 +50,6 @@ end component;
 
 
 
-
-
 component Gray_Decoder
   generic (
     WIDTH : integer);

diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj
index be648e66a2c98d212c5e21c0f82602f676799554..efb7ee495cbcaa1f6733a0daed1ce87698ebdb4a 100644 (file)
--- a/nxyter/trb3_periph.prj
+++ b/nxyter/trb3_periph.prj
@@ -140,6 +140,19 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 
 add_file -vhdl -lib "work" "trb3_periph.vhd"
 
+# nXyter Files
 
+add_file -vhdl -lib "work" "./source/adcmv3_components.vhd"
+add_file -vhdl -lib "work" "./source/nxyter_components.vhd"
 
+add_file -vhdl -lib "work" "./source/nxyter.vhd"
+add_file -vhdl -lib "work" "./source/slave_bus.vhd"
+add_file -vhdl -lib "work" "./source/slv_ped_thr_mem.vhd"
+add_file -vhdl -lib "work" "./source/slv_register.vhd"
+#add_file -vhdl -lib "work" "./source/gray_decoder.vhd"
+
+add_file -vhdl -lib "work" "./source/i2c_gstart.vhd"
+add_file -vhdl -lib "work" "./source/i2c_master.vhd"
+add_file -vhdl -lib "work" "./source/i2c_sendb.vhd"
+add_file -vhdl -lib "work" "./source/i2c_slim.vhd"
 

diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd
index 06f24a3a2f815b6bf2d66dac6a28d4afbff68b55..6970201fac14b327aeb30a366e82a997e8d1b676 100644 (file)
--- a/nxyter/trb3_periph.vhd
+++ b/nxyter/trb3_periph.vhd
@@ -7,6 +7,7 @@ use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
 use work.version.all;
+use work.nxyter_components.all;
 
 
 entity trb3_periph is
@@ -32,24 +33,38 @@ entity trb3_periph is
                                         --Bit 2/3 output, serial link TX active
 
 
-
-
+    
+    
     ---------------------------------------------------------------------------
-    -- ANFANG LUDWIG Addonstecker 
+    -- BEGIN AddonBoard nXyter
     ---------------------------------------------------------------------------
-
-    --Connection to ADA AddOn
-    SPARE_LINE           : inout std_logic_vector(3 downto 0);  --inputs only
-    INP                  : in    std_logic_vector(63 downto 0);
-    DAC_SDO              : in    std_logic;
-    DAC_SDI              : out   std_logic;
-    DAC_SCK              : out   std_logic;
-    DAC_CS               : out   std_logic_vector(3 downto 0);
-
+    --Connections to NXYTER-FEB
+
+    NX1_RESET_OUT              : out   std_logic;     
+    NX1_I2C_SDA_INOUT          : inout std_logic;
+    NX1_I2C_SCL_OUT            : out   std_logic;
+    NX1_I2C_SM_RESET_OUT       : out   std_logic;
+    NX1_I2C_REG_RESET_OUT      : out   std_logic;
+    NX1_SPI_SCLK_OUT           : out   std_logic;
+    NX1_SPI_SDIO_INOUT         : in    std_logic;
+    NX1_SPI_CSB_OUT            : out   std_logic;
+    NX1_CLK128_IN              : in    std_logic;
+    NX1_IN                     : in    std_logic_vector (7 downto 0);
+    NX1_RESET_OUT              : out   std_logic;
+    NX1_CLK256A_OUT            : out   std_logic;
+    NX1_TESTPULSE_OUT          : out   std_logic;
+    NX1_ADC_FCLK_IN            : in    std_logic;
+    NX1_ADC_DCLK_IN            : in    std_logic;
+    NX1_ADC_SC_CLK32_OUT       : out   std_logic;
+    NX1_ADC_A_IN               : in    std_logic;
+    NX1_ADC_B_IN               : in    std_logic;
+    NX1_ADC_NX_IN              : in    std_logic;
+    NX1_ADC_D_IN               : in    std_logic;
+     
     ---------------------------------------------------------------------------
-    -- ENDE LUDWIG
+    -- END AddonBoard nXyter
     ---------------------------------------------------------------------------
-
+    
 
     --Flash ROM & Reboot
     FLASH_CLK            : out   std_logic;
@@ -217,6 +232,8 @@ architecture trb3_periph_arch of trb3_periph is
   signal time_counter : unsigned(31 downto 0);
 
 
+  -- nXyter
+    
 
 begin
 ---------------------------------------------------------------------------
@@ -422,9 +439,13 @@ begin
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER    => 2,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"e000", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 4, others => 0)
+      PORT_NUMBER    => 3,
+      PORT_ADDRESSES => (0 => x"d000",
+                         1 => x"d100",
+                         others => x"0000"),
+      PORT_ADDR_MASK => (0 => 1,
+                         1 => 6,
+                         others => 0)
       )
     port map(
       CLK   => clk_100_i,
@@ -467,20 +488,10 @@ begin
       BUS_UNKNOWN_ADDR_IN(1)              => '0',
 
       -------------------------------------------------------------------------
-      -- HIer meine register.....
+      -- Hier meine register.....
+      -- Macht aber das nxyter entity
       -------------------------------------------------------------------------
-       --Bus Handler (SPI Memory)
---       BUS_READ_ENABLE_OUT(2)              => spimem_read_en,
---       BUS_WRITE_ENABLE_OUT(2)             => spimem_write_en,
---       BUS_DATA_OUT(2*32+31 downto 2*32)   => spimem_data_in,
---       BUS_ADDR_OUT(2*16+5 downto 2*16)    => spimem_addr,
---       BUS_ADDR_OUT(2*16+15 downto 2*16+6) => open,
---       BUS_TIMEOUT_OUT(2)                  => open,
---       BUS_DATA_IN(2*32+31 downto 2*32)    => spimem_data_out,
---       BUS_DATAREADY_IN(2)                 => spimem_ack,
---       BUS_WRITE_ACK_IN(2)                 => spimem_ack,
---       BUS_NO_MORE_DATA_IN(2)              => '0',
---       BUS_UNKNOWN_ADDR_IN(2)              => '0',
+      
 
       
       STAT_DEBUG => open
@@ -560,15 +571,53 @@ begin
 
 
   -----------------------------------------------------------------------------
-  -- HIER darf ich arbeiten!
+  -- The xXyter-FEB
   -----------------------------------------------------------------------------
 
+  nXyter_FEE_board_1: nXyter_FEE_board
+    port map (
+      CLK_IN                 => clk_100_i,
+      RESET_IN               => reset_i,
+
+      I2C_SDA_INOUT          => NX1_I2C_SDA_INOUT,
+      I2C_SCL_OUT            => NX1_I2C_SCL_OUT,
+      I2C_SM_RESET_OUT       => NX1_I2C_SM_RESET_OUT,
+      I2C_REG_RESET_OUT      => NX1_I2C_REG_RESET_OUT,
+
+      SPI_SCLK_OUT           => NX1_SPI_SCLK_OUT,
+      SPI_SDIO_INOUT         => NX1_SPI_SDIO_INOUT,
+      SPI_CSB_OUT            => NX1_SPI_CSB_OUT,
+
+      NX_CLK128_IN           => NX1_CLK128_IN,
+      NX_IN                  => NX1_IN,
+      NX_RESET_OUT           => NX1_RESET_OUT,
+      NX_CLK256A_OUT         => NX1_CLK256A_OUT,
+      NX_TESTPULSE_OUT       => NX1_TESTPULSE_OUT,
+
+      ADC_FCLK_IN            => NX1_ADC_FCLK_IN,
+      ADC_DCLK_IN            => NX1_ADC_DCLK_IN,
+      ADC_SC_CLK32_OUT       => NX1_ADC_SC_CLK32_OUT,
+      ADC_A_IN               => NX1_ADC_A_IN,
+      ADC_B_IN               => NX1_ADC_B_IN,
+      ADC_NX_IN              => NX1_ADC_NX_IN,
+      ADC_D_IN               => NX1_ADC_D_IN,
+
+      REGIO_ADDR_IN          => regio_addr_out,
+      REGIO_DATA_IN          => regio_data_out,
+      REGIO_DATA_OUT         => regio_data_in,
+      REGIO_READ_ENABLE_IN   => regio_read_enable_out,
+      REGIO_WRITE_ENABLE_IN  => regio_write_enable_out,
+      REGIO_TIMEOUT_IN       => regio_timeout_out,
+      REGIO_DATAREADY_OUT    => regio_dataready_in,
+      REGIO_WRITE_ACK_OUT    => regio_write_ack_in,
+      REGIO_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr_in
+      );
+  
 ---------------------------------------------------------------------------
 -- Test Connector - Logic Analyser
 ---------------------------------------------------------------------------
 
-
-
   
   TEST_LINE(15 downto 0) <= (others => '0');