Minor bug-fix to remove the errorous time-reference signal after reset

diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd
index c67ba888942368e0aa0617cfbddacaff556eea90..b5b8c9abbba3efed5598f0f1e6e64bfa5f23ca56 100755 (executable)
--- a/cts/source/cts.vhd
+++ b/cts/source/cts.vhd
@@ -578,7 +578,7 @@ begin
       if rising_edge(CLK) then
          TIME_REFERENCE_OUT <= '0';
          if RESET = '1' then
-            time_reference_counter_v := TIME_REFERENCE_COUNT;
+            time_reference_counter_v := TIME_REFERENCE_COUNT - 1;
          else
             if time_reference_start_i = '1' then
                -- start