architecture trigger_handle_trg_arch of trigger_handler is
- constant WAIT_AFTER_BEGRUN : unsigned(11 downto 0) := x"7D0";
+-- constant WAIT_AFTER_BEGRUN : unsigned(11 downto 0) := x"7D0";
type state_type is (IDLE, BEGRUN, DO_REINIT, DO_REINIT2, TIMING_TRIGGER, CALIB_TRIGGER,
DO_READOUT, RELEASE_LVL1, WAIT_FOR_FINISHED_STORING);
signal finished_cycle_i : std_logic;
signal lvl1_release_i : std_logic;
- signal timer : unsigned(11 downto 0);
+ signal timer : unsigned(3 downto 0);
signal timer_clear : std_logic;
signal state_bits : std_logic_vector(3 downto 0);
current_state <= BEGRUN;
when TIMING_TRIGGER =>
- if timer = x"02" then
+ if timer = x"2" then
current_state <= DO_READOUT;
start_readout_i <= '1';
end if;