--- /dev/null
+--------------------------------------------------------------------------------
+-- Company: GSI
+-- Engineer: Davide Leoni
+--
+-- Create Date: 9/3/07
+-- Design Name: vulom3
+-- Module Name: trig_box1 - Behavioral
+-- Project Name: triggerbox
+-- Target Device: XC4VLX25-10SF363
+-- Tool versions:
+-- Description: Triggerbox
+-- NOTE (1): To enable TOF/MDC part comment lines (a) and (b) and uncomment (c)
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity trig_box1 is
+ port (clk_50MHz : in std_logic;
+ clk_300MHz : in std_logic;
+ clk_100MHz : in std_logic;
+ ECL : in std_logic_vector(16 downto 1);
+ ECO : out std_logic_vector(16 downto 1);
+ IOO : in std_logic_vector(16 downto 1);
+ TIN : out std_logic_vector(16 downto 1);
+ LEMIN : in std_logic_vector(2 downto 1);
+ LEMOU : out std_logic_vector(2 downto 1);
+ INPUT_ENABLE : in std_logic_vector(7 downto 1);
+ DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_1 : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_2 : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_3 : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_4 : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_5 : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_TS : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0);
+ DELAY_REGISTER_VS : in std_logic_vector(3 downto 0);
+ WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0);
+ DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0);
+ BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value
+ WIDTH_OUTPUT : in std_logic_vector(3 downto 0);
+ MUX_SELECTOR_1 : in std_logic_vector(3 downto 0);
+ MUX_SELECTOR_2 : in std_logic_vector(3 downto 0);
+ OR_ON_OFF : in std_logic_vector(7 downto 0);
+ SCALER_PTI1 : out std_logic_vector(31 downto 0);
+ SCALER_PTI2 : out std_logic_vector(31 downto 0);
+ SCALER_PTI3 : out std_logic_vector(31 downto 0);
+ SCALER_PTI4 : out std_logic_vector(31 downto 0);
+ SCALER_PTI5 : out std_logic_vector(31 downto 0);
+ SCALER_TS : out std_logic_vector(31 downto 0);
+ SCALER_VS : out std_logic_vector(31 downto 0);
+ SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select
+ SCALER_MDC : out std_logic_vector(31 downto 0);
+ SCALER_TOF : out std_logic_vector(31 downto 0);
+ SCALER_RESET : in std_logic_vector(7 downto 0);
+ PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0);
+ DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0);
+ WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0);
+ WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0);
+ SCALER_DEAD : out std_logic_vector(31 downto 0);
+ TS_GATING_DISABLE : in std_logic_vector(7 downto 1);
+ SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0);
+ SCALER_MUX1 : out std_logic_vector(31 downto 0);
+ SCALER_MUX2 : out std_logic_vector(31 downto 0);
+ CAL_TRIGGER_DISABLE : in std_logic;
+ COM_RUN : in std_logic;
+ DTU_ERROR : inout std_logic;
+ hpv : inout std_logic_vector(15 downto 0);
+ hpw : inout std_logic_vector(15 downto 0)
+ );
+end trig_box1;
+architecture RTL of trig_box1 is
+ component one_clock_long port (
+ clk : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component delay port (
+ clk : in std_logic;
+ to_be_delayed : in std_logic;
+ delay_value : in std_logic_vector(3 downto 0);
+ delayed_pulse : out std_logic);
+ end component;
+ component downscale port (
+ clk : in std_logic;
+ disable : in std_logic;
+ to_be_downscaled : in std_logic;
+ downscale_value : in std_logic_vector(3 downto 0);
+ downscaled : out std_logic);
+ end component;
+ component set_width port (
+ clk : in std_logic;
+ to_be_set : in std_logic;
+ width_value : in std_logic_vector(3 downto 0);
+ width_adjusted_pulse : out std_logic);
+ end component;
+ component set_width_special port (
+ clk : in std_logic;
+ to_be_set : in std_logic;
+ width_value : in std_logic_vector(3 downto 0);
+ width_adjusted_pulse : out std_logic);
+ end component;
+ component scaler port (
+ clk : in std_logic;
+ input_pulse : in std_logic;
+ scaler_reset : in std_logic;
+ scaler_value : out std_logic_vector(19 downto 0));
+ end component;
+ component scaler_s port (
+ clk_300mhz : in std_logic;
+ clk_100mhz : in std_logic;
+ input_pulse : in std_logic;
+ scaler_reset : in std_logic;
+ scaler_value : out std_logic_vector(31 downto 0));
+ end component;
+ component eco_delay port (
+ clk : in std_logic;
+ signal_in : in std_logic;
+ signal_out : out std_logic);
+ end component;
+ component new_downscale_ck
+ port(
+ downscale_value : in std_logic_vector(3 downto 0);
+ clk : in std_logic;
+ downscaled : out std_logic;
+ output_disable : in std_logic;
+ scaler_reset : out std_logic;
+ cal_inhibit : out std_logic;
+ cal_trigger : out std_logic
+ );
+ end component;
+ component beam_ramp
+ port(
+ clk_300mhz : in std_logic;
+ clk_50mhz : in std_logic;
+ input : in std_logic;
+ delay_value : in std_logic_vector(7 downto 0);
+ width_value_inhibit : in std_logic_vector(7 downto 0);
+ width_value_external : in std_logic_vector(7 downto 0);
+ output_inhibit : out std_logic;
+ output_external : out std_logic
+ );
+ end component;
+ component bus_data_com5
+ port(
+ clk_300mhz : in std_logic;
+ clk_100mhz : in std_logic;
+ gts_pulse : in std_logic;
+ cal_trigger : in std_logic;
+ bus_busy : in std_logic; --not used
+ bus_ack : in std_logic;
+ bus_retx : in std_logic;
+ latch : in std_logic_vector(6 downto 0);
+ latch_dsc : in std_logic_vector(6 downto 0);
+ scaler_pti1 : in std_logic_vector(31 downto 0);
+ scaler_pti2 : in std_logic_vector(31 downto 0);
+ scaler_pti3 : in std_logic_vector(31 downto 0);
+ scaler_pti4 : in std_logic_vector(31 downto 0);
+ scaler_pti5 : in std_logic_vector(31 downto 0);
+ scaler_ts : in std_logic_vector(31 downto 0);
+ scaler_vs : in std_logic_vector(31 downto 0);
+ scaler_dead : in std_logic_vector(31 downto 0);
+ bus_inhibit : out std_logic;
+ dtu_inhibit : out std_logic;
+ ecl_bus_data : out std_logic_vector(1 downto 0);
+ ecl_bus_clk : out std_logic;
+ com_run : in std_logic;
+ dtu_bus_t : out std_logic;
+ dtu_bus_ts : out std_logic;
+ dtu_bus_td : out std_logic_vector (3 downto 0);
+ out_inhibit : in std_logic
+ );
+ end component;
+ signal pti1_one_clock, pti1_delayed, pti1_ready, pti1_downscaled, pti1_self_coin : std_logic;
+ signal pti2_one_clock, pti2_delayed, pti2_ready, pti2_downscaled, pti2_self_coin : std_logic;
+ signal pti3_one_clock, pti3_delayed, pti3_ready, pti3_downscaled, pti3_self_coin : std_logic;
+ signal pti4_one_clock, pti4_delayed, pti4_ready, pti4_downscaled, pti4_self_coin : std_logic;
+ signal pti5_one_clock, pti5_delayed, pti5_ready, pti5_downscaled, pti5_self_coin : std_logic;
+ signal ts_one_clock, ts_delayed, ts_ready, dead, ts_self_coin : std_logic;
+ signal vs_one_clocks, vs_delayed, vs_ready, vs_width_set, vs_self_coin : std_logic;
+ signal clock_downscaled, clock_ready : std_logic;
+ signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic;
+ signal global_timing_signal_out, or_out : std_logic;
+ signal pti1_and_gts, pti2_and_gts, pti3_and_gts, pti4_and_gts, pti5_and_gts : std_logic;
+ signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0);
+ signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic;
+ signal eco_s, eco_out : std_logic_vector(16 downto 1);
+ signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0);
+ signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic;
+ signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count, scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0);
+signal self_coin_delay_1, self_coin_delay_2, self_coin_delay_3, self_coin_delay_4, self_coin_delay_5 : std_logic_vector(3 downto 0);
+ signal scaler_reset_internal : std_logic;
+ signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic;
+ signal dtu_bus_td : std_logic_vector(3 downto 0);
+ signal gts_to_databus, cal_to_databus : std_logic;
+begin
+
+-------------------------------------------------------------one clock long
+ one1 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(1),
+ signal_in => ioo(1),
+ pulse => pti1_one_clock);
+ one2 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(2),
+ signal_in => ioo(2),
+ pulse => pti2_one_clock);
+ one3 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(3),
+ signal_in => ioo(3),
+ pulse => pti3_one_clock);
+ one4 : one_clock_long port map ( --directly connected to the or of tof, so ecl input n°4 is unused
+ clk => clk_300mhz,
+ en_clk => input_enable(4),
+ signal_in => tof_or,
+ pulse => pti4_one_clock);
+ one5 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(5),
+ signal_in => ioo(5),
+ pulse => pti5_one_clock);
+ one6 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(6),
+ signal_in => ioo(6),
+ pulse => ts_one_clock);
+ one7 : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => input_enable(7),
+ signal_in => ioo(7),
+ pulse => vs_one_clocks);
+ one_mdc : one_clock_long port map ( --used only for scaler
+ clk => clk_300mhz,
+ en_clk => '1',
+ signal_in => mdc_mux,
+ pulse => mdc_one_clock);
+ tof_generate_oneclock : for i in 9 to 14 generate
+ one_tof : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => '1', --tof always enabled
+ signal_in => ecl(i),
+ pulse => tof_one_clock(i-9));
+ end generate;
+---------------------------------------------\r
+ multiplicity : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => '1',
+ signal_in => tof_mult_2,
+ pulse => tof_mult_2_one); \r
+---------------------------------------------
+ one_ck : one_clock_long port map (
+ clk => clk_300mhz,
+ en_clk => '1',
+ signal_in => clock_downscaled,
+ pulse => clock_ready);
+
+-------------------------------------------------------------------------delay
+ del1 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti1_one_clock,
+ delay_value => delay_register_1(3 downto 0),
+ delayed_pulse => pti1_delayed);
+
+ del2 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti2_one_clock,
+ delay_value => delay_register_2(3 downto 0),
+ delayed_pulse => pti2_delayed);
+
+ del3 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti3_one_clock,
+ delay_value => delay_register_3(3 downto 0),
+ delayed_pulse => pti3_delayed);
+
+ del4 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti4_one_clock,
+ delay_value => delay_register_4(3 downto 0),
+ delayed_pulse => pti4_delayed);
+
+ del5 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti5_mux,
+ delay_value => delay_register_5(3 downto 0),
+ delayed_pulse => pti5_delayed);
+
+ del6 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => ts_mux,
+ delay_value => delay_register_ts(3 downto 0),
+ delayed_pulse => ts_delayed);
+
+ del7 : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => vs_one_clocks,
+ delay_value => delay_register_vs(3 downto 0),
+ delayed_pulse => vs_delayed);
+
+ self_coin_delay_1 <= '0' & width_register_1(3 downto 1); --automatic delay = width / 2
+ self_coin_delay_2 <= '0' & width_register_2(3 downto 1);
+ self_coin_delay_3 <= '0' & width_register_3(3 downto 1);
+ self_coin_delay_4 <= '0' & width_register_4(3 downto 1);
+ self_coin_delay_5 <= '0' & width_register_5(3 downto 1);
+
+ del1_self : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti1_downscaled,
+ delay_value => self_coin_delay_1,
+ delayed_pulse => pti1_self_coin);
+
+ del2_self : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti2_downscaled,
+ delay_value => self_coin_delay_2,
+ delayed_pulse => pti2_self_coin);
+
+ del3_self : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti3_downscaled,
+ delay_value => self_coin_delay_3,
+ delayed_pulse => pti3_self_coin);
+
+ del4_self : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti4_downscaled,
+ delay_value => self_coin_delay_4,
+ delayed_pulse => pti4_self_coin);
+
+ del5_self : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => pti5_downscaled,
+ delay_value => self_coin_delay_5,
+ delayed_pulse => pti5_self_coin);
+
+ tof_generate_delay : for t in 0 to 5 generate
+ del_tof : delay port map (
+ clk => clk_300mhz,
+ to_be_delayed => tof_one_clock(t),
+ delay_value => delay_register_4(3 downto 0),
+ delayed_pulse => tof_del(t));
+ end generate;
+
+-------------------------------------------------------------------------scaler
+ scal1 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz, --pti1÷5 before inhibit
+ input_pulse => pti1_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti1_count);
+
+ scal2 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => pti2_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti2_count);
+
+ scal3 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => pti3_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti3_count);
+
+ scal4 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => pti4_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti4_count);
+
+ scal5 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => pti5_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti5_count);
+
+ scal1a : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz, --pti1÷5 after inhibit
+ input_pulse => eco_s(9),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti1_accepted);
+
+ scal2a : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => eco_s(10),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti2_accepted);
+
+ scal3a : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => eco_s(11),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti3_accepted);
+
+ scal4a : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => eco_s(12),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti4_accepted);
+
+ scal5a : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => eco_s(13),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_pti5_accepted);
+
+ scalts : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz, --ts, vs and dead
+ input_pulse => ts_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_ts_count);
+
+ scalvs : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => vs_delayed,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_vs_count);
+
+ scaldead : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => dead,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_dead_count);
+
+ scalmdc : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz, --mdc and tof
+ input_pulse => mdc_one_clock,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_mdc);
+
+ scaltof : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => tof_mux,
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_tof);
+
+ scalmux1 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => mux_out(0),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_mux1);
+
+ scalmux2 : scaler_s port map (
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ input_pulse => mux_out(1),
+ scaler_reset => scaler_reset_internal,
+ scaler_value => scaler_mux2);
+
+---------------------------------------------------------------------------downscale
+ dwsc1 : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => pti1_delayed,
+ downscale_value => downscale_register_1(3 downto 0),
+ downscaled => pti1_downscaled);
+
+ dwsc2 : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => pti2_delayed,
+ downscale_value => downscale_register_2(3 downto 0),
+ downscaled => pti2_downscaled);
+
+ dwsc3 : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => pti3_delayed,
+ downscale_value => downscale_register_3(3 downto 0),
+ downscaled => pti3_downscaled);
+
+ dwsc4 : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => pti4_delayed,
+ downscale_value => downscale_register_4(3 downto 0),
+ downscaled => pti4_downscaled);
+
+ dwsc5 : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => pti5_delayed,
+ downscale_value => downscale_register_5(3 downto 0),
+ downscaled => pti5_downscaled);
+
+ dwscts : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => ts_delayed,
+ downscale_value => downscale_register_ts(3 downto 0),
+ downscaled => ts_ready);
+
+ dwscvs : downscale port map (
+ clk => clk_300mhz,
+ disable => out_inhibit,
+ to_be_downscaled => vs_delayed,
+ downscale_value => downscale_register_vs(3 downto 0),
+ downscaled => vs_ready);
+
+-------------------------------------------------------------------------------width
+ setw1 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => pti1_downscaled,
+ width_value => width_register_1(3 downto 0),
+ width_adjusted_pulse => pti1_ready);
+
+ setw2 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => pti2_downscaled,
+ width_value => width_register_2(3 downto 0),
+ width_adjusted_pulse => pti2_ready);
+
+ setw3 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => pti3_downscaled,
+ width_value => width_register_3(3 downto 0),
+ width_adjusted_pulse => pti3_ready);
+
+ setw4 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => pti4_downscaled,
+ width_value => width_register_4(3 downto 0),
+ width_adjusted_pulse => pti4_ready);
+
+ setw5 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => pti5_downscaled,
+ width_value => width_register_5(3 downto 0),
+ width_adjusted_pulse => pti5_ready);
+
+ setw7 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => vs_delayed,
+ width_value => width_register_vs(3 downto 0),
+ width_adjusted_pulse => vs_width_set);
+
+--*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --read note 1)
+ mdc_tof_trigger_width_set <= '1'; --(a)
+--*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*
+
+ setw_mdc_tof_trigger : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => mdc_tof_or,
+ width_value => branch_en_with_mdc_tof_width(3 downto 0),
+-- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c)
+ width_adjusted_pulse => open); --(b)
+
+ setwout : set_width_special port map (
+ clk => clk_300mhz,
+ to_be_set => global_timing_signal_out,
+ width_value => x"6", -- fixed to 20 ns
+ width_adjusted_pulse => lemou(1));
+
+------------------------------------------------------------------------------------------output
+ delaygen1 : for i in 1 to 7 generate
+ delay_out : eco_delay port map (
+ clk => clk_300mhz,
+ signal_in => eco_s(i),
+ signal_out => eco_out(i));
+ end generate;
+
+ eco(7 downto 1) <= eco_out(7 downto 1);
+
+ setmux1 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => mux_out(0),
+ width_value => "0010",
+ width_adjusted_pulse => eco(8));
+
+ delaygen2 : for i in 9 to 15 generate
+ delay_out : eco_delay port map (
+ clk => clk_300mhz,
+ signal_in => eco_s(i),
+ signal_out => eco_out(i));
+ end generate;
+
+ eco(15 downto 9) <= eco_out(15 downto 9);
+
+ setmux2 : set_width port map (
+ clk => clk_300mhz,
+ to_be_set => mux_out(1),
+ width_value => "0010",
+ width_adjusted_pulse => eco(16));
+
+ inst_new_downscale_ck : new_downscale_ck port map(
+ downscale_value => downscale_register_clock(3 downto 0),
+ clk => clk_300mhz,
+ output_disable => cal_trigger_disable,
+ scaler_reset => scaler_reset_internal,
+ downscaled => clock_downscaled,
+ cal_inhibit => cal_inhibit,
+ cal_trigger => cal_trigger);
+
+
+ lemou(2) <= '0'; --now calib pulse is coming out from lemo n°1, this output is unused
+
+ inst_beam_ramp : beam_ramp port map(
+ clk_300mhz => clk_300mhz,
+ clk_50mhz => clk_50mhz,
+ input => lemin_s(1),
+ output_inhibit => beam_inhibit,
+ output_external => tin(12),
+ delay_value => delay_register_beam,
+ width_value_inhibit => width_inhibit_register_beam,
+ width_value_external => width_external_register_beam);
+
+--------------bus communication
+
+ inst_bus_data_com5 : bus_data_com5 port map(
+ clk_300mhz => clk_300mhz,
+ clk_100mhz => clk_100mhz,
+ gts_pulse => gts_to_databus,
+ cal_trigger => cal_trigger,
+ bus_busy => ioo(16), --not used
+ bus_ack => ioo(15),
+ bus_retx => ioo(14),
+ latch => eco_out(7 downto 1),
+ latch_dsc => eco_out(15 downto 9),
+ scaler_pti1 => scaler_pti1_count,
+ scaler_pti2 => scaler_pti2_count,
+ scaler_pti3 => scaler_pti3_count,
+ scaler_pti4 => scaler_pti4_count,
+ scaler_pti5 => scaler_pti5_count,
+ scaler_ts => scaler_ts_count,
+ scaler_vs => scaler_vs_count,
+ scaler_dead => scaler_dead_count,
+ bus_inhibit => bus_inhibit,
+ dtu_inhibit => dtu_inhibit,
+ ecl_bus_data => tin(11 downto 10),
+ ecl_bus_clk => tin(9),
+ com_run => com_run,
+ dtu_bus_t => dtu_bus_t,
+ dtu_bus_ts => dtu_bus_ts,
+ dtu_bus_td => dtu_bus_td,
+ out_inhibit => out_inhibit
+ );
+
+ --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
+ hpv(14) <= not dtu_bus_t; --this is a "firmware patch": the vme connector
+ hpw(14) <= not dtu_bus_ts; --for dtu is reversed (mistake in pcb layout) so
+ hpw(10) <= not dtu_bus_td(3); --all the i/os must be inverted
+ hpv(10) <= not dtu_bus_td(2);
+ hpw(12) <= not dtu_bus_td(1);
+ hpv(12) <= not dtu_bus_td(0);
+ hpw(8) <= 'Z';
+ ----------------------
+ hpv(15) <= dtu_bus_ts; --with this connections all the dtu signals are
+ hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently
+ hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. be aware though, some signals
+ hpv(9) <= '0'; --are inverted
+ hpv(7 downto 0) <= x"00"; --unused
+
+ hpw(15) <= dtu_bus_t;
+ hpw(11) <= dtu_bus_td(2);
+ hpw(13) <= dtu_bus_td(0);
+ hpw(9) <= '0';
+ hpw(7 downto 0) <= x"00"; --unused
+ --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
+
+ scaler_pti1 <= scaler_pti1_count;
+ scaler_pti2 <= scaler_pti2_count;
+ scaler_pti3 <= scaler_pti3_count;
+ scaler_pti4 <= scaler_pti4_count;
+ scaler_pti5 <= scaler_pti5_count;
+ scaler_ts <= scaler_ts_count;
+ scaler_vs <= scaler_vs_count;
+ scaler_dead <= scaler_dead_count;
+
+ tin(16 downto 13) <= "0000";
+
+--------------pti5 & ts mux
+
+ mdc_tof_mux : process(clk_300mhz)
+ begin
+ if rising_edge(clk_300mhz) then
+
+-- case tof_one_clock is --multiplicity 2 detector
+ case ecl(14 downto 9) is --multiplicity 2 detector
+ when "000011" => tof_mult_2 <= '1';
+ when "000101" => tof_mult_2 <= '1';
+ when "001001" => tof_mult_2 <= '1';
+ when "010001" => tof_mult_2 <= '1';
+ when "100001" => tof_mult_2 <= '1';
+ when "000110" => tof_mult_2 <= '1';
+ when "001010" => tof_mult_2 <= '1';
+ when "010010" => tof_mult_2 <= '1';
+ when "100010" => tof_mult_2 <= '1';
+ when "001100" => tof_mult_2 <= '1';
+ when "010100" => tof_mult_2 <= '1';
+ when "100100" => tof_mult_2 <= '1';
+ when "011000" => tof_mult_2 <= '1';
+ when "101000" => tof_mult_2 <= '1';
+ when "110000" => tof_mult_2 <= '1';
+ when others => tof_mult_2 <= '0';
+ end case;
+
+ case pti5_ts_alternative(4) is
+ when '0' => pti5_mux <= pti5_one_clock;
+ when '1' => pti5_mux <= tof_mult_2_one;
+ when others => pti5_mux <= 'X';
+ end case;
+
+ case pti5_ts_alternative(0) is
+ when '0' => ts_mux <= ts_one_clock;
+ when '1' => ts_mux <= tof_or;
+ when others => ts_mux <= 'X';
+ end case;
+ end if;
+ end process mdc_tof_mux;
+
+--------------mdc & tof scaler mux
+
+ pti5_ts_mux : process(clk_300mhz)
+ begin
+ if rising_edge(clk_300mhz) then
+ case scaler_mdc_tof_select(7 downto 4) is
+ when x"0" => mdc_mux <= mdc_s1(0);
+ when x"1" => mdc_mux <= mdc_s1(1);
+ when x"2" => mdc_mux <= mdc_s1(2);
+ when x"3" => mdc_mux <= mdc_s1(3);
+ when x"4" => mdc_mux <= mdc_s1(4);
+ when x"5" => mdc_mux <= mdc_s1(5);
+ when others => mdc_mux <= '0';
+ end case;
+
+ case scaler_mdc_tof_select(3 downto 0) is
+ when x"0" => tof_mux <= tof_one_clock(0);
+ when x"1" => tof_mux <= tof_one_clock(1);
+ when x"2" => tof_mux <= tof_one_clock(2);
+ when x"3" => tof_mux <= tof_one_clock(3);
+ when x"4" => tof_mux <= tof_one_clock(4);
+ when x"5" => tof_mux <= tof_one_clock(5);
+ when others => tof_mux <= '0';
+ end case;
+ end if;
+ end process pti5_ts_mux;
+
+-------------- tof & mdc logic
+
+ tof_mdc_logic : process(clk_300mhz)
+ begin
+ if rising_edge(clk_300mhz) then
+
+ mdc_s <= ecl(6 downto 1);
+ tof_s <= ecl(14 downto 9);
+ mdc_s1 <= mdc_s;
+ tof_s1 <= tof_s;
+
+ mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or
+ (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or
+ (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5)))
+ and branch_en_with_mdc_tof_width(4));
+ tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14));
+ end if;
+ end process tof_mdc_logic;
+-------------- final and-or logic function
+ logic : process(clk_300mhz)
+ begin
+ if rising_edge(clk_300mhz) then
+
+ -------------------------------------- gate select single
+
+ pti1_and_gts <= ((pti1_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(1))
+ or (pti1_self_coin and ts_gating_disable(1)));
+ pti2_and_gts <= ((pti2_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(2))
+ or (pti2_self_coin and ts_gating_disable(2)));
+ pti3_and_gts <= ((pti3_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(3))
+ or (pti3_self_coin and ts_gating_disable(3)));
+ pti4_and_gts <= ((pti4_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(4))
+ or (pti4_self_coin and ts_gating_disable(4)));
+ pti5_and_gts <= ((pti5_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(5))
+ or (pti5_self_coin and ts_gating_disable(5)));
+ or_out <= (pti1_and_gts and or_on_off(0)) or
+ (pti2_and_gts and or_on_off(1)) or
+ (pti3_and_gts and or_on_off(2)) or
+ (pti4_and_gts and or_on_off(3)) or
+ (pti5_and_gts and or_on_off(4)) or
+ (ts_ready and or_on_off(5)) or
+ (vs_ready and or_on_off(6)) or
+ (clock_ready and or_on_off(7));
+ lemin_s <= lemin;
+ lemin_s1 <= lemin_s;
+ dtu_bus_tb_s <= not hpv(8); --dtu trigger busy
+ dead <= ts_delayed and (not out_inhibit);
+ out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit or dtu_bus_tb_s;
+ global_timing_signal_out <= (cal_trigger and not out_inhibit) or (or_out and not out_inhibit and not cal_inhibit);
+ gts_to_databus <= or_out and not out_inhibit and not cal_inhibit;
+ end if;
+ end process logic;
+---------------- outputs
+
+ assign : process(clk_300mhz)
+ begin
+ if rising_edge(clk_300mhz) then
+ eco_s(1) <= pti1_delayed; -- latches before downscale
+ eco_s(2) <= pti2_delayed;
+ eco_s(3) <= pti3_delayed;
+ eco_s(4) <= pti4_delayed;
+ eco_s(5) <= pti5_delayed;
+ eco_s(6) <= ts_delayed;
+ eco_s(7) <= vs_delayed;
+-- eco(8) is mux 0
+ eco_s(9) <= (or_on_off(0) and ((pti1_downscaled and ts_gating_disable(1))
+ or (pti1_and_gts and not ts_gating_disable(1))));
+ eco_s(10) <= (or_on_off(1) and ((pti2_downscaled and ts_gating_disable(2))
+ or (pti2_and_gts and not ts_gating_disable(2))));
+ eco_s(11) <= (or_on_off(2) and ((pti3_downscaled and ts_gating_disable(3))
+ or (pti3_and_gts and not ts_gating_disable(3))));
+ eco_s(12) <= (or_on_off(3) and ((pti4_downscaled and ts_gating_disable(4))
+ or (pti4_and_gts and not ts_gating_disable(4))));
+ eco_s(13) <= (or_on_off(4) and ((pti5_downscaled and ts_gating_disable(5))
+ or (pti5_and_gts and not ts_gating_disable(5))));
+ eco_s(14) <= ts_ready and or_on_off(5);
+ eco_s(15) <= vs_ready and or_on_off(6);
+-- eco(16) is mux 1
+
+----------------- multiplexers
+ case mux_selector_1 is --0x5c
+ when "0000" => mux_out(0) <= pti1_delayed; --0
+ when "0001" => mux_out(0) <= pti2_delayed;
+ when "0010" => mux_out(0) <= pti3_delayed; --2
+ when "0011" => mux_out(0) <= pti4_delayed;
+ when "0100" => mux_out(0) <= pti5_delayed; --4
+ when "0101" => mux_out(0) <= ts_delayed;
+ when "0110" => mux_out(0) <= vs_delayed; --6
+ when "0111" => mux_out(0) <= pti1_and_gts;
+ when "1000" => mux_out(0) <= pti2_and_gts; --8
+ when "1001" => mux_out(0) <= pti3_and_gts;
+ when "1010" => mux_out(0) <= pti4_and_gts; --a
+ when "1011" => mux_out(0) <= pti5_and_gts;
+ when "1100" => mux_out(0) <= ts_ready; --c
+ when "1101" => mux_out(0) <= vs_ready;
+ when "1110" => mux_out(0) <= or_out; --e
+ when "1111" => mux_out(0) <= global_timing_signal_out;
+ when others => mux_out(0) <= 'X';
+ end case;
+ case mux_selector_2 is --0x60
+ when "0000" => mux_out(1) <= pti1_delayed; --0
+ when "0001" => mux_out(1) <= pti2_delayed;
+ when "0010" => mux_out(1) <= pti3_delayed; --2
+ when "0011" => mux_out(1) <= pti4_delayed;
+ when "0100" => mux_out(1) <= pti5_delayed; --4
+ when "0101" => mux_out(1) <= ts_delayed;
+ when "0110" => mux_out(1) <= vs_delayed; --6
+ when "0111" => mux_out(1) <=tof_mux; --pti1_ready;
+ when "1000" => mux_out(1) <='0'; --pti2_ready; --8
+ when "1001" => mux_out(1) <='0'; --pti3_ready;
+ when "1010" => mux_out(1) <='0'; --pti4_ready; --a
+ when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--pti5_ready;
+ when "1100" => mux_out(1) <= ts_ready; --c
+ when "1101" => mux_out(1) <= vs_ready;
+ when "1110" => mux_out(1) <= clock_ready; --e
+ when "1111" => mux_out(1) <=mdc_mux; --vs_width_set;
+ when others => mux_out(1) <= 'X';
+ end case;
+ end if;
+ end process assign;
+end rtl;
--- /dev/null
+NOTE "CREATOR" "Xilinx iMPACT Software";
+NOTE "DATE" "2008/04/28";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "ALG_VERSION" "1";
+NOTE "DEVICE" "UNSPECIFIED";
+NOTE "CHECKSUM" "UNSPECIFIED";
+NOTE "IDCODE" "UNSPECIFIED";
+NOTE "USERCODE" "UNSPECIFIED";
+NOTE "TARGET" "UNSPECIFIED";
+NOTE "STACK_DEPTH" "4";
+NOTE "MAX_FREQ" "1000000";
+ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC;
+DATA MAINDATA;
+INTEGER I = 0;
+INTEGER D = 0;
+ENDDATA;
+PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA;
+BOOLEAN X = 0;
+IRSTOP IDLE;
+DRSTOP IDLE;
+STATE RESET IDLE;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f167c093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f167c093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' // Loading device with a `jprogram` instruction.
+IRSCAN 10, $03cb
+ ;
+D = 1;
+WAIT D CYCLES;
+' // Loading device with a `bypass` instruction.
+IRSCAN 10, $03ff
+ ;
+D = 21000;
+WAIT D CYCLES;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+ ;
+D = 100000;
+WAIT D CYCLES;
+' // Check init_complete in ircapture.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0010
+, $0010
+, X;
+IF (!X) THEN GOTO F;
+' STATE RESET;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+, COMPARE $0000
+, $0000
+, X;
+IF (!X) THEN GOTO F;
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@l4600
+00wojIsF60G0020000K40000WXC0C0m40000WW4088204210YW009G0W280m04QCcX4IQWXO
+0C0040800O22m0020G0000WcuW160G00000W10A82030000QqtloCC0W0040000ivEy30_@V
+ ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 12;
+WAIT D CYCLES;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 12;
+WAIT D CYCLES;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+ ;
+DRSCAN 224, $0000000000000000200000008001000c0000000466aa9955ffffffff
+ ;
+' //Checking done pin status.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0021
+, $0020
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+IRSCAN 10, $03ff
+ ;
+DRSCAN 1, $00
+ ;
+
+SUCCESS:
+PRINT "Successful File Execution.";
+EXIT 0;
+
+F:
+PRINT "File Execution Failure.";
+EXIT 16;
+
+ENDPROC;
+
+DATA TMPDATA;
+INTEGER TMP_DELAY;
+ENDDATA;
+
+PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D / 100;
+TMP_DELAY = TMP_DELAY * 25;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D * 25;
+TMP_DELAY = TMP_DELAY / 100;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY;
+IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
+IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
+ENDPROC;
+
+CRC 324E;
jspc29 / trbnet.git / commitdiff