ADC: Add 65MHz PLL to project

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index cac1d077741259f7f22b120a7a22c416e8da8dfb..62fcb0119e19f757f91ad76d753c4dfb139ae6ee 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -142,6 +142,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out65.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"